1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* mapping from nir_register to defining instruction: */
78 struct hash_table
*def_ht
;
82 /* a common pattern for indirect addressing is to request the
83 * same address register multiple times. To avoid generating
84 * duplicate instruction sequences (which our backend does not
85 * try to clean up, since that should be done as the NIR stage)
86 * we cache the address value generated for a given src value:
88 * Note that we have to cache these per alignment, since same
89 * src used for an array of vec1 cannot be also used for an
92 struct hash_table
*addr_ht
[4];
94 /* last dst array, for indirect we need to insert a var-store.
96 struct ir3_instruction
**last_dst
;
99 /* maps nir_block to ir3_block, mostly for the purposes of
100 * figuring out the blocks successors
102 struct hash_table
*block_ht
;
104 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
105 * so we need to use ldlv.u32 to load the varying directly:
109 /* on a3xx, we need to add one to # of array levels:
113 /* on a3xx, we need to scale up integer coords for isaml based
116 bool unminify_coords
;
118 /* on a4xx, for array textures we need to add 0.5 to the array
121 bool array_index_add_half
;
123 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
126 unsigned max_texture_index
;
128 /* set if we encounter something we can't handle yet, so we
129 * can bail cleanly and fallback to TGSI compiler f/e
134 /* gpu pointer size in units of 32bit registers/slots */
135 static unsigned pointer_size(struct ir3_context
*ctx
)
137 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
140 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
141 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
144 static struct ir3_context
*
145 compile_init(struct ir3_compiler
*compiler
,
146 struct ir3_shader_variant
*so
)
148 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
150 if (compiler
->gpu_id
>= 400) {
151 /* need special handling for "flat" */
152 ctx
->flat_bypass
= true;
153 ctx
->levels_add_one
= false;
154 ctx
->unminify_coords
= false;
155 ctx
->array_index_add_half
= true;
157 if (so
->type
== SHADER_VERTEX
)
158 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
159 else if (so
->type
== SHADER_FRAGMENT
)
160 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
163 /* no special handling for "flat" */
164 ctx
->flat_bypass
= false;
165 ctx
->levels_add_one
= true;
166 ctx
->unminify_coords
= true;
167 ctx
->array_index_add_half
= false;
170 ctx
->compiler
= compiler
;
173 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
174 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
175 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
176 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
178 /* TODO: maybe generate some sort of bitmask of what key
179 * lowers vs what shader has (ie. no need to lower
180 * texture clamp lowering if no texture sample instrs)..
181 * although should be done further up the stack to avoid
182 * creating duplicate variants..
185 if (ir3_key_lowers_nir(&so
->key
)) {
186 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
187 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
189 /* fast-path for shader key that lowers nothing in NIR: */
190 ctx
->s
= so
->shader
->nir
;
193 /* this needs to be the last pass run, so do this here instead of
194 * in ir3_optimize_nir():
196 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
197 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
199 if (fd_mesa_debug
& FD_DBG_DISASM
) {
200 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
201 so
->shader
->id
, so
->id
, so
->type
,
202 so
->key
.binning_pass
, so
->key
.color_two_side
,
203 so
->key
.half_precision
);
204 nir_print_shader(ctx
->s
, stdout
);
207 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
209 so
->num_uniforms
= ctx
->s
->num_uniforms
;
210 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
212 /* Layout of constant registers, each section aligned to vec4. Note
213 * that pointer size (ubo, etc) changes depending on generation.
218 * if (vertex shader) {
219 * driver params (IR3_DP_*)
220 * if (stream_output.num_outputs > 0)
221 * stream-out addresses
225 * Immediates go last mostly because they are inserted in the CP pass
226 * after the nir -> ir3 frontend.
228 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
229 unsigned ptrsz
= pointer_size(ctx
);
231 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
233 if (so
->num_ubos
> 0) {
234 so
->constbase
.ubo
= constoff
;
235 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
238 if (so
->const_layout
.ssbo_size
.count
> 0) {
239 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
240 so
->constbase
.ssbo_sizes
= constoff
;
241 constoff
+= align(cnt
, 4) / 4;
244 if (so
->const_layout
.image_dims
.count
> 0) {
245 unsigned cnt
= so
->const_layout
.image_dims
.count
;
246 so
->constbase
.image_dims
= constoff
;
247 constoff
+= align(cnt
, 4) / 4;
250 unsigned num_driver_params
= 0;
251 if (so
->type
== SHADER_VERTEX
) {
252 num_driver_params
= IR3_DP_VS_COUNT
;
253 } else if (so
->type
== SHADER_COMPUTE
) {
254 num_driver_params
= IR3_DP_CS_COUNT
;
257 so
->constbase
.driver_param
= constoff
;
258 constoff
+= align(num_driver_params
, 4) / 4;
260 if ((so
->type
== SHADER_VERTEX
) &&
261 (compiler
->gpu_id
< 500) &&
262 so
->shader
->stream_output
.num_outputs
> 0) {
263 so
->constbase
.tfbo
= constoff
;
264 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
267 so
->constbase
.immediate
= constoff
;
273 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
276 va_start(ap
, format
);
277 _debug_vprintf(format
, ap
);
279 nir_print_shader(ctx
->s
, stdout
);
284 #define compile_assert(ctx, cond) do { \
285 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
289 compile_free(struct ir3_context
*ctx
)
295 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
297 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
298 arr
->id
= ++ctx
->num_arrays
;
299 /* NOTE: sometimes we get non array regs, for example for arrays of
300 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
301 * treat a non-array as if it was an array of length 1.
303 * It would be nice if there was a nir pass to convert arrays of
306 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
307 compile_assert(ctx
, arr
->length
> 0);
309 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
312 static struct ir3_array
*
313 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
315 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
319 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
323 /* relative (indirect) if address!=NULL */
324 static struct ir3_instruction
*
325 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
326 struct ir3_instruction
*address
)
328 struct ir3_block
*block
= ctx
->block
;
329 struct ir3_instruction
*mov
;
330 struct ir3_register
*src
;
332 mov
= ir3_instr_create(block
, OPC_MOV
);
333 mov
->cat1
.src_type
= TYPE_U32
;
334 mov
->cat1
.dst_type
= TYPE_U32
;
335 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
336 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
337 ir3_reg_create(mov
, 0, 0);
338 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
339 COND(address
, IR3_REG_RELATIV
));
340 src
->instr
= arr
->last_write
;
341 src
->size
= arr
->length
;
342 src
->array
.id
= arr
->id
;
343 src
->array
.offset
= n
;
346 ir3_instr_set_address(mov
, address
);
351 /* relative (indirect) if address!=NULL */
353 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
354 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
356 struct ir3_block
*block
= ctx
->block
;
357 struct ir3_instruction
*mov
;
358 struct ir3_register
*dst
;
360 /* if not relative store, don't create an extra mov, since that
361 * ends up being difficult for cp to remove.
366 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
367 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
369 dst
->flags
|= IR3_REG_ARRAY
;
370 dst
->instr
= arr
->last_write
;
371 dst
->size
= arr
->length
;
372 dst
->array
.id
= arr
->id
;
373 dst
->array
.offset
= n
;
375 arr
->last_write
= src
;
377 array_insert(block
, block
->keeps
, src
);
382 mov
= ir3_instr_create(block
, OPC_MOV
);
383 mov
->cat1
.src_type
= TYPE_U32
;
384 mov
->cat1
.dst_type
= TYPE_U32
;
385 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
386 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
387 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
388 COND(address
, IR3_REG_RELATIV
));
389 dst
->instr
= arr
->last_write
;
390 dst
->size
= arr
->length
;
391 dst
->array
.id
= arr
->id
;
392 dst
->array
.offset
= n
;
393 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
396 ir3_instr_set_address(mov
, address
);
398 arr
->last_write
= mov
;
400 /* the array store may only matter to something in an earlier
401 * block (ie. loops), but since arrays are not in SSA, depth
402 * pass won't know this.. so keep all array stores:
404 array_insert(block
, block
->keeps
, mov
);
407 /* allocate a n element value array (to be populated by caller) and
410 static struct ir3_instruction
**
411 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
413 struct ir3_instruction
**value
=
414 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
415 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
419 static struct ir3_instruction
**
420 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
422 struct ir3_instruction
**value
;
425 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
427 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
430 /* NOTE: in non-ssa case, we don't really need to store last_dst
431 * but this helps us catch cases where put_dst() call is forgotten
433 compile_assert(ctx
, !ctx
->last_dst
);
434 ctx
->last_dst
= value
;
440 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
442 static struct ir3_instruction
* const *
443 get_src(struct ir3_context
*ctx
, nir_src
*src
)
446 struct hash_entry
*entry
;
447 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
448 compile_assert(ctx
, entry
);
451 nir_register
*reg
= src
->reg
.reg
;
452 struct ir3_array
*arr
= get_array(ctx
, reg
);
453 unsigned num_components
= arr
->r
->num_components
;
454 struct ir3_instruction
*addr
= NULL
;
455 struct ir3_instruction
**value
=
456 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
458 if (src
->reg
.indirect
)
459 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
460 reg
->num_components
);
462 for (unsigned i
= 0; i
< num_components
; i
++) {
463 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
464 compile_assert(ctx
, n
< arr
->length
);
465 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
473 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
475 unsigned bit_size
= nir_dest_bit_size(*dst
);
478 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
479 ctx
->last_dst
[i
]->regs
[0]->flags
|= IR3_REG_HALF
;
484 nir_register
*reg
= dst
->reg
.reg
;
485 struct ir3_array
*arr
= get_array(ctx
, reg
);
486 unsigned num_components
= ctx
->last_dst_n
;
487 struct ir3_instruction
*addr
= NULL
;
489 if (dst
->reg
.indirect
)
490 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
491 reg
->num_components
);
493 for (unsigned i
= 0; i
< num_components
; i
++) {
494 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
495 compile_assert(ctx
, n
< arr
->length
);
496 if (!ctx
->last_dst
[i
])
498 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
501 ralloc_free(ctx
->last_dst
);
503 ctx
->last_dst
= NULL
;
507 static struct ir3_instruction
*
508 create_immed(struct ir3_block
*block
, uint32_t val
)
510 struct ir3_instruction
*mov
;
512 mov
= ir3_instr_create(block
, OPC_MOV
);
513 mov
->cat1
.src_type
= TYPE_U32
;
514 mov
->cat1
.dst_type
= TYPE_U32
;
515 ir3_reg_create(mov
, 0, 0);
516 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
521 static struct ir3_instruction
*
522 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
524 struct ir3_instruction
*instr
, *immed
;
526 /* TODO in at least some cases, the backend could probably be
527 * made clever enough to propagate IR3_REG_HALF..
529 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
530 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
537 /* src *= 2 => src <<= 1: */
538 immed
= create_immed(block
, 1);
539 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
541 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
542 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
543 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
547 immed
= create_immed(block
, 3);
548 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
550 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
551 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
552 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
555 /* src *= 4 => src <<= 2: */
556 immed
= create_immed(block
, 2);
557 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
559 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
560 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
561 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
564 unreachable("bad align");
568 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
569 instr
->regs
[0]->num
= regid(REG_A0
, 0);
570 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
571 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
576 /* caches addr values to avoid generating multiple cov/shl/mova
577 * sequences for each use of a given NIR level src as address
579 static struct ir3_instruction
*
580 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
582 struct ir3_instruction
*addr
;
583 unsigned idx
= align
- 1;
585 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
587 if (!ctx
->addr_ht
[idx
]) {
588 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
589 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
591 struct hash_entry
*entry
;
592 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
597 addr
= create_addr(ctx
->block
, src
, align
);
598 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
603 static struct ir3_instruction
*
604 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
606 struct ir3_block
*b
= ctx
->block
;
607 struct ir3_instruction
*cond
;
609 /* NOTE: only cmps.*.* can write p0.x: */
610 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
611 cond
->cat2
.condition
= IR3_COND_NE
;
613 /* condition always goes in predicate register: */
614 cond
->regs
[0]->num
= regid(REG_P0
, 0);
619 static struct ir3_instruction
*
620 create_uniform(struct ir3_context
*ctx
, unsigned n
)
622 struct ir3_instruction
*mov
;
624 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
625 /* TODO get types right? */
626 mov
->cat1
.src_type
= TYPE_F32
;
627 mov
->cat1
.dst_type
= TYPE_F32
;
628 ir3_reg_create(mov
, 0, 0);
629 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
634 static struct ir3_instruction
*
635 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
636 struct ir3_instruction
*address
)
638 struct ir3_instruction
*mov
;
640 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
641 mov
->cat1
.src_type
= TYPE_U32
;
642 mov
->cat1
.dst_type
= TYPE_U32
;
643 ir3_reg_create(mov
, 0, 0);
644 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
646 ir3_instr_set_address(mov
, address
);
651 static struct ir3_instruction
*
652 create_collect(struct ir3_block
*block
, struct ir3_instruction
*const *arr
,
655 struct ir3_instruction
*collect
;
660 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
661 ir3_reg_create(collect
, 0, 0); /* dst */
662 for (unsigned i
= 0; i
< arrsz
; i
++)
663 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
668 static struct ir3_instruction
*
669 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
670 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
672 struct ir3_block
*block
= ctx
->block
;
673 struct ir3_instruction
*mov
;
674 struct ir3_register
*src
;
676 mov
= ir3_instr_create(block
, OPC_MOV
);
677 mov
->cat1
.src_type
= TYPE_U32
;
678 mov
->cat1
.dst_type
= TYPE_U32
;
679 ir3_reg_create(mov
, 0, 0);
680 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
681 src
->instr
= collect
;
683 src
->array
.offset
= n
;
685 ir3_instr_set_address(mov
, address
);
690 static struct ir3_instruction
*
691 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
693 struct ir3_instruction
*in
;
695 in
= ir3_instr_create(block
, OPC_META_INPUT
);
696 in
->inout
.block
= block
;
697 ir3_reg_create(in
, n
, 0);
699 in
->regs
[0]->wrmask
= compmask
;
704 static struct ir3_instruction
*
705 create_input(struct ir3_block
*block
, unsigned n
)
707 return create_input_compmask(block
, n
, 0x1);
710 static struct ir3_instruction
*
711 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
713 struct ir3_block
*block
= ctx
->block
;
714 struct ir3_instruction
*instr
;
715 /* actual inloc is assigned and fixed up later: */
716 struct ir3_instruction
*inloc
= create_immed(block
, 0);
719 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
720 instr
->cat6
.type
= TYPE_U32
;
721 instr
->cat6
.iim_val
= 1;
723 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
724 instr
->regs
[2]->wrmask
= 0x3;
730 static struct ir3_instruction
*
731 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
733 struct ir3_block
*block
= ctx
->block
;
734 struct ir3_instruction
*instr
;
736 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
738 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
743 /* for frag_coord, we get unsigned values.. we need
744 * to subtract (integer) 8 and divide by 16 (right-
745 * shift by 4) then convert to float:
749 * mov.u32f32 dst, tmp
752 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
753 create_immed(block
, 8), 0);
754 instr
= ir3_SHR_B(block
, instr
, 0,
755 create_immed(block
, 4), 0);
756 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
762 /* seems that we can use these as-is: */
763 return ctx
->frag_coord
[comp
];
767 static struct ir3_instruction
*
768 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
770 /* first four vec4 sysval's reserved for UBOs: */
771 /* NOTE: dp is in scalar, but there can be >4 dp components: */
772 unsigned n
= ctx
->so
->constbase
.driver_param
;
773 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
774 return create_uniform(ctx
, r
);
777 /* helper for instructions that produce multiple consecutive scalar
778 * outputs which need to have a split/fanout meta instruction inserted
781 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
782 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
784 struct ir3_instruction
*prev
= NULL
;
786 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
791 for (int i
= 0, j
= 0; i
< n
; i
++) {
792 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
793 ir3_reg_create(split
, 0, IR3_REG_SSA
);
794 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
795 split
->fo
.off
= i
+ base
;
798 split
->cp
.left
= prev
;
799 split
->cp
.left_cnt
++;
800 prev
->cp
.right
= split
;
801 prev
->cp
.right_cnt
++;
805 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
811 * Adreno uses uint rather than having dedicated bool type,
812 * which (potentially) requires some conversion, in particular
813 * when using output of an bool instr to int input, or visa
817 * -------+---------+-------+-
821 * To convert from an adreno bool (uint) to nir, use:
823 * absneg.s dst, (neg)src
825 * To convert back in the other direction:
827 * absneg.s dst, (abs)arc
829 * The CP step can clean up the absneg.s that cancel each other
830 * out, and with a slight bit of extra cleverness (to recognize
831 * the instructions which produce either a 0 or 1) can eliminate
832 * the absneg.s's completely when an instruction that wants
833 * 0/1 consumes the result. For example, when a nir 'bcsel'
834 * consumes the result of 'feq'. So we should be able to get by
835 * without a boolean resolve step, and without incuring any
836 * extra penalty in instruction count.
839 /* NIR bool -> native (adreno): */
840 static struct ir3_instruction
*
841 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
843 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
846 /* native (adreno) -> NIR bool: */
847 static struct ir3_instruction
*
848 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
850 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
854 * alu/sfu instructions:
858 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
860 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
861 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
862 struct ir3_block
*b
= ctx
->block
;
863 unsigned dst_sz
, wrmask
;
865 if (alu
->dest
.dest
.is_ssa
) {
866 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
867 wrmask
= (1 << dst_sz
) - 1;
869 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
870 wrmask
= alu
->dest
.write_mask
;
873 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
875 /* Vectors are special in that they have non-scalarized writemasks,
876 * and just take the first swizzle channel for each argument in
877 * order into each writemask channel.
879 if ((alu
->op
== nir_op_vec2
) ||
880 (alu
->op
== nir_op_vec3
) ||
881 (alu
->op
== nir_op_vec4
)) {
883 for (int i
= 0; i
< info
->num_inputs
; i
++) {
884 nir_alu_src
*asrc
= &alu
->src
[i
];
886 compile_assert(ctx
, !asrc
->abs
);
887 compile_assert(ctx
, !asrc
->negate
);
889 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
891 src
[i
] = create_immed(ctx
->block
, 0);
892 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
895 put_dst(ctx
, &alu
->dest
.dest
);
899 /* We also get mov's with more than one component for mov's so
900 * handle those specially:
902 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
903 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
904 nir_alu_src
*asrc
= &alu
->src
[0];
905 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
907 for (unsigned i
= 0; i
< dst_sz
; i
++) {
908 if (wrmask
& (1 << i
)) {
909 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
915 put_dst(ctx
, &alu
->dest
.dest
);
919 /* General case: We can just grab the one used channel per src. */
920 for (int i
= 0; i
< info
->num_inputs
; i
++) {
921 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
922 nir_alu_src
*asrc
= &alu
->src
[i
];
924 compile_assert(ctx
, !asrc
->abs
);
925 compile_assert(ctx
, !asrc
->negate
);
927 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
929 compile_assert(ctx
, src
[i
]);
934 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
937 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
940 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
943 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
946 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
947 dst
[0]->cat2
.condition
= IR3_COND_NE
;
948 dst
[0] = ir3_n2b(b
, dst
[0]);
951 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
954 dst
[0] = ir3_b2n(b
, src
[0]);
957 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
958 dst
[0]->cat2
.condition
= IR3_COND_NE
;
959 dst
[0] = ir3_n2b(b
, dst
[0]);
963 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
966 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
969 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
972 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
975 /* if there is just a single use of the src, and it supports
976 * (sat) bit, we can just fold the (sat) flag back to the
977 * src instruction and create a mov. This is easier for cp
980 * TODO probably opc_cat==4 is ok too
982 if (alu
->src
[0].src
.is_ssa
&&
983 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
984 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
985 src
[0]->flags
|= IR3_INSTR_SAT
;
986 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
988 /* otherwise generate a max.f that saturates.. blob does
989 * similar (generating a cat2 mov using max.f)
991 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
992 dst
[0]->flags
|= IR3_INSTR_SAT
;
996 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
999 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1002 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1005 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1008 dst
[0] = ir3_DSX(b
, src
[0], 0);
1009 dst
[0]->cat5
.type
= TYPE_F32
;
1012 dst
[0] = ir3_DSY(b
, src
[0], 0);
1013 dst
[0]->cat5
.type
= TYPE_F32
;
1017 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1018 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1019 dst
[0] = ir3_n2b(b
, dst
[0]);
1022 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1023 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1024 dst
[0] = ir3_n2b(b
, dst
[0]);
1027 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1028 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1029 dst
[0] = ir3_n2b(b
, dst
[0]);
1032 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1033 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1034 dst
[0] = ir3_n2b(b
, dst
[0]);
1037 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1040 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1043 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1045 case nir_op_fround_even
:
1046 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1049 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1053 dst
[0] = ir3_SIN(b
, src
[0], 0);
1056 dst
[0] = ir3_COS(b
, src
[0], 0);
1059 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1062 dst
[0] = ir3_RCP(b
, src
[0], 0);
1065 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1068 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1071 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1075 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1078 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1081 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1084 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1087 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1090 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1093 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1097 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1098 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1099 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1100 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1102 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1103 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1104 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1107 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1110 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1113 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1116 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1119 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1121 case nir_op_isign
: {
1122 /* maybe this would be sane to lower in nir.. */
1123 struct ir3_instruction
*neg
, *pos
;
1125 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1126 neg
->cat2
.condition
= IR3_COND_LT
;
1128 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1129 pos
->cat2
.condition
= IR3_COND_GT
;
1131 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1136 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1139 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1142 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1145 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1146 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1147 dst
[0] = ir3_n2b(b
, dst
[0]);
1150 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1151 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1152 dst
[0] = ir3_n2b(b
, dst
[0]);
1155 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1156 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1157 dst
[0] = ir3_n2b(b
, dst
[0]);
1160 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1161 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1162 dst
[0] = ir3_n2b(b
, dst
[0]);
1165 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1166 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1167 dst
[0] = ir3_n2b(b
, dst
[0]);
1170 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1171 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1172 dst
[0] = ir3_n2b(b
, dst
[0]);
1176 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1179 case nir_op_bit_count
:
1180 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1182 case nir_op_ifind_msb
: {
1183 struct ir3_instruction
*cmp
;
1184 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1185 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1186 cmp
->cat2
.condition
= IR3_COND_GE
;
1187 dst
[0] = ir3_SEL_B32(b
,
1188 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1192 case nir_op_ufind_msb
:
1193 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1194 dst
[0] = ir3_SEL_B32(b
,
1195 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1196 src
[0], 0, dst
[0], 0);
1198 case nir_op_find_lsb
:
1199 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1200 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1202 case nir_op_bitfield_reverse
:
1203 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1207 compile_error(ctx
, "Unhandled ALU op: %s\n",
1208 nir_op_infos
[alu
->op
].name
);
1212 put_dst(ctx
, &alu
->dest
.dest
);
1215 /* handles direct/indirect UBO reads: */
1217 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1218 struct ir3_instruction
**dst
)
1220 struct ir3_block
*b
= ctx
->block
;
1221 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1222 nir_const_value
*const_offset
;
1223 /* UBO addresses are the first driver params: */
1224 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1225 const unsigned ptrsz
= pointer_size(ctx
);
1229 /* First src is ubo index, which could either be an immed or not: */
1230 src0
= get_src(ctx
, &intr
->src
[0])[0];
1231 if (is_same_type_mov(src0
) &&
1232 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1233 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1234 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1236 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1237 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1240 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1243 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1245 off
+= const_offset
->u32
[0];
1247 /* For load_ubo_indirect, second src is indirect offset: */
1248 src1
= get_src(ctx
, &intr
->src
[1])[0];
1250 /* and add offset to addr: */
1251 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1254 /* if offset is to large to encode in the ldg, split it out: */
1255 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1256 /* split out the minimal amount to improve the odds that
1257 * cp can fit the immediate in the add.s instruction:
1259 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1260 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1265 struct ir3_instruction
*carry
;
1267 /* handle 32b rollover, ie:
1268 * if (addr < base_lo)
1271 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1272 carry
->cat2
.condition
= IR3_COND_LT
;
1273 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1275 addr
= create_collect(b
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1278 for (int i
= 0; i
< intr
->num_components
; i
++) {
1279 struct ir3_instruction
*load
=
1280 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1281 load
->cat6
.type
= TYPE_U32
;
1282 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1287 /* src[] = { buffer_index, offset }. No const_index */
1289 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1290 struct ir3_instruction
**dst
)
1292 struct ir3_block
*b
= ctx
->block
;
1293 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1294 nir_const_value
*const_offset
;
1296 /* can this be non-const buffer_index? how do we handle that? */
1297 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1298 compile_assert(ctx
, const_offset
);
1300 offset
= get_src(ctx
, &intr
->src
[1])[0];
1302 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1303 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1307 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1309 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1311 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1312 ldgb
->cat6
.iim_val
= intr
->num_components
;
1314 ldgb
->cat6
.type
= TYPE_U32
;
1315 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1316 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1318 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1321 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1323 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1325 struct ir3_block
*b
= ctx
->block
;
1326 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1327 nir_const_value
*const_offset
;
1328 /* TODO handle wrmask properly, see _store_shared().. but I think
1329 * it is more a PITA than that, since blob ends up loading the
1330 * masked components and writing them back out.
1332 unsigned wrmask
= intr
->const_index
[0];
1333 unsigned ncomp
= ffs(~wrmask
) - 1;
1335 /* can this be non-const buffer_index? how do we handle that? */
1336 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1337 compile_assert(ctx
, const_offset
);
1339 offset
= get_src(ctx
, &intr
->src
[2])[0];
1341 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1344 src0
= create_collect(b
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1345 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1346 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1351 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1352 src0
, 0, src1
, 0, src2
, 0);
1353 stgb
->cat6
.iim_val
= ncomp
;
1355 stgb
->cat6
.type
= TYPE_U32
;
1356 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1357 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1359 array_insert(b
, b
->keeps
, stgb
);
1362 /* src[] = { block_index } */
1364 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1365 struct ir3_instruction
**dst
)
1367 /* SSBO size stored as a const starting at ssbo_sizes: */
1368 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1369 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1370 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1372 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1374 dst
[0] = create_uniform(ctx
, idx
);
1378 * SSBO atomic intrinsics
1380 * All of the SSBO atomic memory operations read a value from memory,
1381 * compute a new value using one of the operations below, write the new
1382 * value to memory, and return the original value read.
1384 * All operations take 3 sources except CompSwap that takes 4. These
1385 * sources represent:
1387 * 0: The SSBO buffer index.
1388 * 1: The offset into the SSBO buffer of the variable that the atomic
1389 * operation will operate on.
1390 * 2: The data parameter to the atomic function (i.e. the value to add
1391 * in ssbo_atomic_add, etc).
1392 * 3: For CompSwap only: the second data parameter.
1394 static struct ir3_instruction
*
1395 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1397 struct ir3_block
*b
= ctx
->block
;
1398 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1399 nir_const_value
*const_offset
;
1400 type_t type
= TYPE_U32
;
1402 /* can this be non-const buffer_index? how do we handle that? */
1403 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1404 compile_assert(ctx
, const_offset
);
1405 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1407 offset
= get_src(ctx
, &intr
->src
[1])[0];
1409 /* src0 is data (or uvec2(data, compare))
1411 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1413 * Note that nir already multiplies the offset by four
1415 src0
= get_src(ctx
, &intr
->src
[2])[0];
1416 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1417 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1422 switch (intr
->intrinsic
) {
1423 case nir_intrinsic_ssbo_atomic_add
:
1424 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1426 case nir_intrinsic_ssbo_atomic_imin
:
1427 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1430 case nir_intrinsic_ssbo_atomic_umin
:
1431 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1433 case nir_intrinsic_ssbo_atomic_imax
:
1434 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1437 case nir_intrinsic_ssbo_atomic_umax
:
1438 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1440 case nir_intrinsic_ssbo_atomic_and
:
1441 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1443 case nir_intrinsic_ssbo_atomic_or
:
1444 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1446 case nir_intrinsic_ssbo_atomic_xor
:
1447 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1449 case nir_intrinsic_ssbo_atomic_exchange
:
1450 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1452 case nir_intrinsic_ssbo_atomic_comp_swap
:
1453 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1454 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1456 get_src(ctx
, &intr
->src
[3])[0],
1458 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1464 atomic
->cat6
.iim_val
= 1;
1466 atomic
->cat6
.type
= type
;
1467 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1468 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1470 /* even if nothing consume the result, we can't DCE the instruction: */
1471 array_insert(b
, b
->keeps
, atomic
);
1476 /* src[] = { offset }. const_index[] = { base } */
1478 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1479 struct ir3_instruction
**dst
)
1481 struct ir3_block
*b
= ctx
->block
;
1482 struct ir3_instruction
*ldl
, *offset
;
1485 offset
= get_src(ctx
, &intr
->src
[0])[0];
1486 base
= nir_intrinsic_base(intr
);
1488 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1489 ldl
->cat6
.src_offset
= base
;
1490 ldl
->cat6
.type
= TYPE_U32
;
1491 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1493 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1494 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1496 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1499 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1501 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1503 struct ir3_block
*b
= ctx
->block
;
1504 struct ir3_instruction
*stl
, *offset
;
1505 struct ir3_instruction
* const *value
;
1506 unsigned base
, wrmask
;
1508 value
= get_src(ctx
, &intr
->src
[0]);
1509 offset
= get_src(ctx
, &intr
->src
[1])[0];
1511 base
= nir_intrinsic_base(intr
);
1512 wrmask
= nir_intrinsic_write_mask(intr
);
1514 /* Combine groups of consecutive enabled channels in one write
1515 * message. We use ffs to find the first enabled channel and then ffs on
1516 * the bit-inverse, down-shifted writemask to determine the length of
1517 * the block of enabled bits.
1519 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1522 unsigned first_component
= ffs(wrmask
) - 1;
1523 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1525 stl
= ir3_STL(b
, offset
, 0,
1526 create_collect(b
, &value
[first_component
], length
), 0,
1527 create_immed(b
, length
), 0);
1528 stl
->cat6
.dst_offset
= first_component
+ base
;
1529 stl
->cat6
.type
= TYPE_U32
;
1530 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1531 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1533 array_insert(b
, b
->keeps
, stl
);
1535 /* Clear the bits in the writemask that we just wrote, then try
1536 * again to see if more channels are left.
1538 wrmask
&= (15 << (first_component
+ length
));
1543 * CS shared variable atomic intrinsics
1545 * All of the shared variable atomic memory operations read a value from
1546 * memory, compute a new value using one of the operations below, write the
1547 * new value to memory, and return the original value read.
1549 * All operations take 2 sources except CompSwap that takes 3. These
1550 * sources represent:
1552 * 0: The offset into the shared variable storage region that the atomic
1553 * operation will operate on.
1554 * 1: The data parameter to the atomic function (i.e. the value to add
1555 * in shared_atomic_add, etc).
1556 * 2: For CompSwap only: the second data parameter.
1558 static struct ir3_instruction
*
1559 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1561 struct ir3_block
*b
= ctx
->block
;
1562 struct ir3_instruction
*atomic
, *src0
, *src1
;
1563 type_t type
= TYPE_U32
;
1565 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1566 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1568 switch (intr
->intrinsic
) {
1569 case nir_intrinsic_shared_atomic_add
:
1570 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1572 case nir_intrinsic_shared_atomic_imin
:
1573 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1576 case nir_intrinsic_shared_atomic_umin
:
1577 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1579 case nir_intrinsic_shared_atomic_imax
:
1580 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1583 case nir_intrinsic_shared_atomic_umax
:
1584 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1586 case nir_intrinsic_shared_atomic_and
:
1587 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1589 case nir_intrinsic_shared_atomic_or
:
1590 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1592 case nir_intrinsic_shared_atomic_xor
:
1593 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1595 case nir_intrinsic_shared_atomic_exchange
:
1596 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1598 case nir_intrinsic_shared_atomic_comp_swap
:
1599 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1600 src1
= create_collect(b
, (struct ir3_instruction
*[]){
1601 get_src(ctx
, &intr
->src
[2])[0],
1604 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1610 atomic
->cat6
.iim_val
= 1;
1612 atomic
->cat6
.type
= type
;
1613 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1614 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1616 /* even if nothing consume the result, we can't DCE the instruction: */
1617 array_insert(b
, b
->keeps
, atomic
);
1622 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1623 * state block (for load). To simplify things, invert the image id and
1624 * map it from end of state block, ie. image 0 becomes num-1, image 1
1625 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1626 * state when switching shaders.
1628 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1629 * coded. Also, since all the gl shader stages (ie. everything but CS)
1630 * share the same SSBO/image state block, this might require some more
1631 * logic if we supported images in anything other than FS..
1634 get_image_slot(struct ir3_context
*ctx
, const nir_variable
*var
)
1636 /* TODO figure out real limit per generation, and don't hardcode: */
1637 const unsigned max_samplers
= 16;
1638 return max_samplers
- var
->data
.driver_location
- 1;
1642 get_image_coords(const nir_variable
*var
)
1644 switch (glsl_get_sampler_dim(glsl_without_array(var
->type
))) {
1645 case GLSL_SAMPLER_DIM_1D
:
1646 case GLSL_SAMPLER_DIM_BUF
:
1649 case GLSL_SAMPLER_DIM_2D
:
1650 case GLSL_SAMPLER_DIM_RECT
:
1651 case GLSL_SAMPLER_DIM_EXTERNAL
:
1652 case GLSL_SAMPLER_DIM_MS
:
1654 case GLSL_SAMPLER_DIM_3D
:
1655 case GLSL_SAMPLER_DIM_CUBE
:
1658 unreachable("bad sampler dim");
1664 get_image_type(const nir_variable
*var
)
1666 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1667 case GLSL_TYPE_UINT
:
1671 case GLSL_TYPE_FLOAT
:
1674 unreachable("bad sampler type.");
1679 static struct ir3_instruction
*
1680 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1681 struct ir3_instruction
* const *coords
, bool byteoff
)
1683 struct ir3_block
*b
= ctx
->block
;
1684 struct ir3_instruction
*offset
;
1685 unsigned ncoords
= get_image_coords(var
);
1687 /* to calculate the byte offset (yes, uggg) we need (up to) three
1688 * const values to know the bytes per pixel, and y and z stride:
1690 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1691 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1693 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1694 (1 << var
->data
.driver_location
));
1696 /* offset = coords.x * bytes_per_pixel: */
1697 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1699 /* offset += coords.y * y_pitch: */
1700 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1701 coords
[1], 0, offset
, 0);
1704 /* offset += coords.z * z_pitch: */
1705 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1706 coords
[2], 0, offset
, 0);
1710 /* Some cases, like atomics, seem to use dword offset instead
1711 * of byte offsets.. blob just puts an extra shr.b in there
1714 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1717 return create_collect(b
, (struct ir3_instruction
*[]){
1723 /* src[] = { coord, sample_index }. const_index[] = {} */
1725 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1726 struct ir3_instruction
**dst
)
1728 struct ir3_block
*b
= ctx
->block
;
1729 const nir_variable
*var
= intr
->variables
[0]->var
;
1730 struct ir3_instruction
*sam
;
1731 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1732 unsigned ncoords
= get_image_coords(var
);
1733 unsigned tex_idx
= get_image_slot(ctx
, var
);
1734 type_t type
= get_image_type(var
);
1738 flags
|= IR3_INSTR_3D
;
1740 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1741 tex_idx
, tex_idx
, create_collect(b
, coords
, ncoords
), NULL
);
1743 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1744 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1746 split_dest(b
, dst
, sam
, 0, 4);
1749 /* src[] = { coord, sample_index, value }. const_index[] = {} */
1751 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1753 struct ir3_block
*b
= ctx
->block
;
1754 const nir_variable
*var
= intr
->variables
[0]->var
;
1755 struct ir3_instruction
*stib
, *offset
;
1756 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
1757 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1758 unsigned ncoords
= get_image_coords(var
);
1759 unsigned tex_idx
= get_image_slot(ctx
, var
);
1763 * src2 is 64b byte offset
1766 offset
= get_image_offset(ctx
, var
, coords
, true);
1768 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1769 * too and takes a dword offset.. not quite sure yet why blob uses
1770 * one over the other in various cases.
1773 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
1774 create_collect(b
, value
, 4), 0,
1775 create_collect(b
, coords
, ncoords
), 0,
1777 stib
->cat6
.iim_val
= 4;
1778 stib
->cat6
.d
= ncoords
;
1779 stib
->cat6
.type
= get_image_type(var
);
1780 stib
->cat6
.typed
= true;
1781 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1782 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1784 array_insert(b
, b
->keeps
, stib
);
1788 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1789 struct ir3_instruction
**dst
)
1791 struct ir3_block
*b
= ctx
->block
;
1792 const nir_variable
*var
= intr
->variables
[0]->var
;
1793 unsigned ncoords
= get_image_coords(var
);
1794 unsigned tex_idx
= get_image_slot(ctx
, var
);
1795 struct ir3_instruction
*sam
, *lod
;
1799 flags
= IR3_INSTR_3D
;
1801 lod
= create_immed(b
, 0);
1802 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1803 tex_idx
, tex_idx
, lod
, NULL
);
1805 split_dest(b
, dst
, sam
, 0, ncoords
);
1808 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
1809 static struct ir3_instruction
*
1810 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1812 struct ir3_block
*b
= ctx
->block
;
1813 const nir_variable
*var
= intr
->variables
[0]->var
;
1814 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
1815 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1816 unsigned ncoords
= get_image_coords(var
);
1818 image
= create_immed(b
, get_image_slot(ctx
, var
));
1820 /* src0 is value (or uvec2(value, compare))
1822 * src2 is 64b byte offset
1824 src0
= get_src(ctx
, &intr
->src
[2])[0];
1825 src1
= create_collect(b
, coords
, ncoords
);
1826 src2
= get_image_offset(ctx
, var
, coords
, false);
1828 switch (intr
->intrinsic
) {
1829 case nir_intrinsic_image_var_atomic_add
:
1830 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1832 case nir_intrinsic_image_var_atomic_min
:
1833 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1835 case nir_intrinsic_image_var_atomic_max
:
1836 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1838 case nir_intrinsic_image_var_atomic_and
:
1839 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1841 case nir_intrinsic_image_var_atomic_or
:
1842 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1844 case nir_intrinsic_image_var_atomic_xor
:
1845 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1847 case nir_intrinsic_image_var_atomic_exchange
:
1848 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1850 case nir_intrinsic_image_var_atomic_comp_swap
:
1851 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1852 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1854 get_src(ctx
, &intr
->src
[3])[0],
1856 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1862 atomic
->cat6
.iim_val
= 1;
1863 atomic
->cat6
.d
= ncoords
;
1864 atomic
->cat6
.type
= get_image_type(var
);
1865 atomic
->cat6
.typed
= true;
1866 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1867 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1869 /* even if nothing consume the result, we can't DCE the instruction: */
1870 array_insert(b
, b
->keeps
, atomic
);
1876 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1878 struct ir3_block
*b
= ctx
->block
;
1879 struct ir3_instruction
*barrier
;
1881 switch (intr
->intrinsic
) {
1882 case nir_intrinsic_barrier
:
1883 barrier
= ir3_BAR(b
);
1884 barrier
->cat7
.g
= true;
1885 barrier
->cat7
.l
= true;
1886 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1887 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1889 case nir_intrinsic_memory_barrier
:
1890 barrier
= ir3_FENCE(b
);
1891 barrier
->cat7
.g
= true;
1892 barrier
->cat7
.r
= true;
1893 barrier
->cat7
.w
= true;
1894 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1895 IR3_BARRIER_BUFFER_W
;
1896 barrier
->barrier_conflict
=
1897 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1898 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1900 case nir_intrinsic_memory_barrier_atomic_counter
:
1901 case nir_intrinsic_memory_barrier_buffer
:
1902 barrier
= ir3_FENCE(b
);
1903 barrier
->cat7
.g
= true;
1904 barrier
->cat7
.r
= true;
1905 barrier
->cat7
.w
= true;
1906 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1907 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1908 IR3_BARRIER_BUFFER_W
;
1910 case nir_intrinsic_memory_barrier_image
:
1911 // TODO double check if this should have .g set
1912 barrier
= ir3_FENCE(b
);
1913 barrier
->cat7
.g
= true;
1914 barrier
->cat7
.r
= true;
1915 barrier
->cat7
.w
= true;
1916 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1917 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1918 IR3_BARRIER_IMAGE_W
;
1920 case nir_intrinsic_memory_barrier_shared
:
1921 barrier
= ir3_FENCE(b
);
1922 barrier
->cat7
.g
= true;
1923 barrier
->cat7
.l
= true;
1924 barrier
->cat7
.r
= true;
1925 barrier
->cat7
.w
= true;
1926 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1927 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1928 IR3_BARRIER_SHARED_W
;
1930 case nir_intrinsic_group_memory_barrier
:
1931 barrier
= ir3_FENCE(b
);
1932 barrier
->cat7
.g
= true;
1933 barrier
->cat7
.l
= true;
1934 barrier
->cat7
.r
= true;
1935 barrier
->cat7
.w
= true;
1936 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1937 IR3_BARRIER_IMAGE_W
|
1938 IR3_BARRIER_BUFFER_W
;
1939 barrier
->barrier_conflict
=
1940 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1941 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1942 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1948 /* make sure barrier doesn't get DCE'd */
1949 array_insert(b
, b
->keeps
, barrier
);
1952 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1953 gl_system_value slot
, unsigned compmask
,
1954 struct ir3_instruction
*instr
)
1956 struct ir3_shader_variant
*so
= ctx
->so
;
1957 unsigned r
= regid(so
->inputs_count
, 0);
1958 unsigned n
= so
->inputs_count
++;
1960 so
->inputs
[n
].sysval
= true;
1961 so
->inputs
[n
].slot
= slot
;
1962 so
->inputs
[n
].compmask
= compmask
;
1963 so
->inputs
[n
].regid
= r
;
1964 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1967 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1968 ctx
->ir
->inputs
[r
] = instr
;
1971 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1972 struct ir3_instruction
*instr
)
1974 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1978 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1980 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1981 struct ir3_instruction
**dst
;
1982 struct ir3_instruction
* const *src
;
1983 struct ir3_block
*b
= ctx
->block
;
1984 nir_const_value
*const_offset
;
1987 if (info
->has_dest
) {
1989 if (info
->dest_components
)
1990 n
= info
->dest_components
;
1992 n
= intr
->num_components
;
1993 dst
= get_dst(ctx
, &intr
->dest
, n
);
1998 switch (intr
->intrinsic
) {
1999 case nir_intrinsic_load_uniform
:
2000 idx
= nir_intrinsic_base(intr
);
2001 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2003 idx
+= const_offset
->u32
[0];
2004 for (int i
= 0; i
< intr
->num_components
; i
++) {
2005 unsigned n
= idx
* 4 + i
;
2006 dst
[i
] = create_uniform(ctx
, n
);
2009 src
= get_src(ctx
, &intr
->src
[0]);
2010 for (int i
= 0; i
< intr
->num_components
; i
++) {
2011 int n
= idx
* 4 + i
;
2012 dst
[i
] = create_uniform_indirect(ctx
, n
,
2013 get_addr(ctx
, src
[0], 4));
2015 /* NOTE: if relative addressing is used, we set
2016 * constlen in the compiler (to worst-case value)
2017 * since we don't know in the assembler what the max
2018 * addr reg value can be:
2020 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2023 case nir_intrinsic_load_ubo
:
2024 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2026 case nir_intrinsic_load_input
:
2027 idx
= nir_intrinsic_base(intr
);
2028 comp
= nir_intrinsic_component(intr
);
2029 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2031 idx
+= const_offset
->u32
[0];
2032 for (int i
= 0; i
< intr
->num_components
; i
++) {
2033 unsigned n
= idx
* 4 + i
+ comp
;
2034 dst
[i
] = ctx
->ir
->inputs
[n
];
2037 src
= get_src(ctx
, &intr
->src
[0]);
2038 struct ir3_instruction
*collect
=
2039 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2040 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2041 for (int i
= 0; i
< intr
->num_components
; i
++) {
2042 unsigned n
= idx
* 4 + i
+ comp
;
2043 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2048 case nir_intrinsic_load_ssbo
:
2049 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2051 case nir_intrinsic_store_ssbo
:
2052 emit_intrinsic_store_ssbo(ctx
, intr
);
2054 case nir_intrinsic_get_buffer_size
:
2055 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2057 case nir_intrinsic_ssbo_atomic_add
:
2058 case nir_intrinsic_ssbo_atomic_imin
:
2059 case nir_intrinsic_ssbo_atomic_umin
:
2060 case nir_intrinsic_ssbo_atomic_imax
:
2061 case nir_intrinsic_ssbo_atomic_umax
:
2062 case nir_intrinsic_ssbo_atomic_and
:
2063 case nir_intrinsic_ssbo_atomic_or
:
2064 case nir_intrinsic_ssbo_atomic_xor
:
2065 case nir_intrinsic_ssbo_atomic_exchange
:
2066 case nir_intrinsic_ssbo_atomic_comp_swap
:
2067 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2069 case nir_intrinsic_load_shared
:
2070 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2072 case nir_intrinsic_store_shared
:
2073 emit_intrinsic_store_shared(ctx
, intr
);
2075 case nir_intrinsic_shared_atomic_add
:
2076 case nir_intrinsic_shared_atomic_imin
:
2077 case nir_intrinsic_shared_atomic_umin
:
2078 case nir_intrinsic_shared_atomic_imax
:
2079 case nir_intrinsic_shared_atomic_umax
:
2080 case nir_intrinsic_shared_atomic_and
:
2081 case nir_intrinsic_shared_atomic_or
:
2082 case nir_intrinsic_shared_atomic_xor
:
2083 case nir_intrinsic_shared_atomic_exchange
:
2084 case nir_intrinsic_shared_atomic_comp_swap
:
2085 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2087 case nir_intrinsic_image_var_load
:
2088 emit_intrinsic_load_image(ctx
, intr
, dst
);
2090 case nir_intrinsic_image_var_store
:
2091 emit_intrinsic_store_image(ctx
, intr
);
2093 case nir_intrinsic_image_var_size
:
2094 emit_intrinsic_image_size(ctx
, intr
, dst
);
2096 case nir_intrinsic_image_var_atomic_add
:
2097 case nir_intrinsic_image_var_atomic_min
:
2098 case nir_intrinsic_image_var_atomic_max
:
2099 case nir_intrinsic_image_var_atomic_and
:
2100 case nir_intrinsic_image_var_atomic_or
:
2101 case nir_intrinsic_image_var_atomic_xor
:
2102 case nir_intrinsic_image_var_atomic_exchange
:
2103 case nir_intrinsic_image_var_atomic_comp_swap
:
2104 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2106 case nir_intrinsic_barrier
:
2107 case nir_intrinsic_memory_barrier
:
2108 case nir_intrinsic_group_memory_barrier
:
2109 case nir_intrinsic_memory_barrier_atomic_counter
:
2110 case nir_intrinsic_memory_barrier_buffer
:
2111 case nir_intrinsic_memory_barrier_image
:
2112 case nir_intrinsic_memory_barrier_shared
:
2113 emit_intrinsic_barrier(ctx
, intr
);
2114 /* note that blk ptr no longer valid, make that obvious: */
2117 case nir_intrinsic_store_output
:
2118 idx
= nir_intrinsic_base(intr
);
2119 comp
= nir_intrinsic_component(intr
);
2120 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2121 compile_assert(ctx
, const_offset
!= NULL
);
2122 idx
+= const_offset
->u32
[0];
2124 src
= get_src(ctx
, &intr
->src
[0]);
2125 for (int i
= 0; i
< intr
->num_components
; i
++) {
2126 unsigned n
= idx
* 4 + i
+ comp
;
2127 ctx
->ir
->outputs
[n
] = src
[i
];
2130 case nir_intrinsic_load_base_vertex
:
2131 if (!ctx
->basevertex
) {
2132 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2133 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
2136 dst
[0] = ctx
->basevertex
;
2138 case nir_intrinsic_load_vertex_id_zero_base
:
2139 case nir_intrinsic_load_vertex_id
:
2140 if (!ctx
->vertex_id
) {
2141 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2142 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2143 ctx
->vertex_id
= create_input(b
, 0);
2144 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2146 dst
[0] = ctx
->vertex_id
;
2148 case nir_intrinsic_load_instance_id
:
2149 if (!ctx
->instance_id
) {
2150 ctx
->instance_id
= create_input(b
, 0);
2151 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2154 dst
[0] = ctx
->instance_id
;
2156 case nir_intrinsic_load_user_clip_plane
:
2157 idx
= nir_intrinsic_ucp_id(intr
);
2158 for (int i
= 0; i
< intr
->num_components
; i
++) {
2159 unsigned n
= idx
* 4 + i
;
2160 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2163 case nir_intrinsic_load_front_face
:
2164 if (!ctx
->frag_face
) {
2165 ctx
->so
->frag_face
= true;
2166 ctx
->frag_face
= create_input(b
, 0);
2167 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2169 /* for fragface, we get -1 for back and 0 for front. However this is
2170 * the inverse of what nir expects (where ~0 is true).
2172 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2173 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2175 case nir_intrinsic_load_local_invocation_id
:
2176 if (!ctx
->local_invocation_id
) {
2177 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2178 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2179 0x7, ctx
->local_invocation_id
);
2181 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2183 case nir_intrinsic_load_work_group_id
:
2184 if (!ctx
->work_group_id
) {
2185 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2186 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2187 0x7, ctx
->work_group_id
);
2188 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2190 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2192 case nir_intrinsic_load_num_work_groups
:
2193 for (int i
= 0; i
< intr
->num_components
; i
++) {
2194 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2197 case nir_intrinsic_load_local_group_size
:
2198 for (int i
= 0; i
< intr
->num_components
; i
++) {
2199 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2202 case nir_intrinsic_discard_if
:
2203 case nir_intrinsic_discard
: {
2204 struct ir3_instruction
*cond
, *kill
;
2206 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2207 /* conditional discard: */
2208 src
= get_src(ctx
, &intr
->src
[0]);
2209 cond
= ir3_b2n(b
, src
[0]);
2211 /* unconditional discard: */
2212 cond
= create_immed(b
, 1);
2215 /* NOTE: only cmps.*.* can write p0.x: */
2216 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2217 cond
->cat2
.condition
= IR3_COND_NE
;
2219 /* condition always goes in predicate register: */
2220 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2222 kill
= ir3_KILL(b
, cond
, 0);
2223 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2225 array_insert(b
, b
->keeps
, kill
);
2226 ctx
->so
->has_kill
= true;
2231 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2232 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2237 put_dst(ctx
, &intr
->dest
);
2241 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2243 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2244 instr
->def
.num_components
);
2245 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2246 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
2250 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2252 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2253 undef
->def
.num_components
);
2254 /* backend doesn't want undefined instructions, so just plug
2257 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2258 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
2262 * texture fetch/sample instructions:
2266 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2268 unsigned coords
, flags
= 0;
2270 /* note: would use tex->coord_components.. except txs.. also,
2271 * since array index goes after shadow ref, we don't want to
2274 switch (tex
->sampler_dim
) {
2275 case GLSL_SAMPLER_DIM_1D
:
2276 case GLSL_SAMPLER_DIM_BUF
:
2279 case GLSL_SAMPLER_DIM_2D
:
2280 case GLSL_SAMPLER_DIM_RECT
:
2281 case GLSL_SAMPLER_DIM_EXTERNAL
:
2282 case GLSL_SAMPLER_DIM_MS
:
2285 case GLSL_SAMPLER_DIM_3D
:
2286 case GLSL_SAMPLER_DIM_CUBE
:
2288 flags
|= IR3_INSTR_3D
;
2291 unreachable("bad sampler_dim");
2294 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2295 flags
|= IR3_INSTR_S
;
2297 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2298 flags
|= IR3_INSTR_A
;
2305 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2307 struct ir3_block
*b
= ctx
->block
;
2308 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2309 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2310 struct ir3_instruction
*lod
, *compare
, *proj
;
2311 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2312 unsigned i
, coords
, flags
;
2313 unsigned nsrc0
= 0, nsrc1
= 0;
2317 coord
= off
= ddx
= ddy
= NULL
;
2318 lod
= proj
= compare
= NULL
;
2320 /* TODO: might just be one component for gathers? */
2321 dst
= get_dst(ctx
, &tex
->dest
, 4);
2323 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2324 switch (tex
->src
[i
].src_type
) {
2325 case nir_tex_src_coord
:
2326 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2328 case nir_tex_src_bias
:
2329 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2332 case nir_tex_src_lod
:
2333 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2336 case nir_tex_src_comparator
: /* shadow comparator */
2337 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2339 case nir_tex_src_projector
:
2340 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2343 case nir_tex_src_offset
:
2344 off
= get_src(ctx
, &tex
->src
[i
].src
);
2347 case nir_tex_src_ddx
:
2348 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2350 case nir_tex_src_ddy
:
2351 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2354 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2355 tex
->src
[i
].src_type
);
2361 case nir_texop_tex
: opc
= OPC_SAM
; break;
2362 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2363 case nir_texop_txl
: opc
= OPC_SAML
; break;
2364 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2365 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2366 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2368 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2369 * what blob does, seems gather is broken?), and a3xx did
2370 * not support it (but probably could also emulate).
2372 switch (tex
->component
) {
2373 case 0: opc
= OPC_GATHER4R
; break;
2374 case 1: opc
= OPC_GATHER4G
; break;
2375 case 2: opc
= OPC_GATHER4B
; break;
2376 case 3: opc
= OPC_GATHER4A
; break;
2379 case nir_texop_txf_ms
:
2381 case nir_texop_query_levels
:
2382 case nir_texop_texture_samples
:
2383 case nir_texop_samples_identical
:
2384 case nir_texop_txf_ms_mcs
:
2385 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2389 tex_info(tex
, &flags
, &coords
);
2392 * lay out the first argument in the proper order:
2393 * - actual coordinates first
2394 * - shadow reference
2397 * - starting at offset 4, dpdx.xy, dpdy.xy
2399 * bias/lod go into the second arg
2402 /* insert tex coords: */
2403 for (i
= 0; i
< coords
; i
++)
2408 /* scale up integer coords for TXF based on the LOD */
2409 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2411 for (i
= 0; i
< coords
; i
++)
2412 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2416 /* hw doesn't do 1d, so we treat it as 2d with
2417 * height of 1, and patch up the y coord.
2418 * TODO: y coord should be (int)0 in some cases..
2420 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2423 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2424 src0
[nsrc0
++] = compare
;
2426 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2427 struct ir3_instruction
*idx
= coord
[coords
];
2429 /* the array coord for cube arrays needs 0.5 added to it */
2430 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2431 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2433 src0
[nsrc0
++] = idx
;
2437 src0
[nsrc0
++] = proj
;
2438 flags
|= IR3_INSTR_P
;
2441 /* pad to 4, then ddx/ddy: */
2442 if (tex
->op
== nir_texop_txd
) {
2444 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2445 for (i
= 0; i
< coords
; i
++)
2446 src0
[nsrc0
++] = ddx
[i
];
2448 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2449 for (i
= 0; i
< coords
; i
++)
2450 src0
[nsrc0
++] = ddy
[i
];
2452 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2456 * second argument (if applicable):
2461 if (has_off
| has_lod
| has_bias
) {
2463 unsigned off_coords
= coords
;
2464 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2466 for (i
= 0; i
< off_coords
; i
++)
2467 src1
[nsrc1
++] = off
[i
];
2469 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2470 flags
|= IR3_INSTR_O
;
2473 if (has_lod
| has_bias
)
2474 src1
[nsrc1
++] = lod
;
2477 switch (tex
->dest_type
) {
2478 case nir_type_invalid
:
2479 case nir_type_float
:
2490 unreachable("bad dest_type");
2493 if (opc
== OPC_GETLOD
)
2496 unsigned tex_idx
= tex
->texture_index
;
2498 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2500 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
2501 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
2503 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2504 tex_idx
, tex_idx
, col0
, col1
);
2506 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2507 /* only need first 3 components: */
2508 sam
->regs
[0]->wrmask
= 0x7;
2509 split_dest(b
, dst
, sam
, 0, 3);
2511 /* we need to sample the alpha separately with a non-ASTC
2514 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2515 tex_idx
, tex_idx
, col0
, col1
);
2517 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2519 /* fixup .w component: */
2520 split_dest(b
, &dst
[3], sam
, 3, 1);
2522 /* normal (non-workaround) case: */
2523 split_dest(b
, dst
, sam
, 0, 4);
2526 /* GETLOD returns results in 4.8 fixed point */
2527 if (opc
== OPC_GETLOD
) {
2528 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2530 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2531 for (i
= 0; i
< 2; i
++) {
2532 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2537 put_dst(ctx
, &tex
->dest
);
2541 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2543 struct ir3_block
*b
= ctx
->block
;
2544 struct ir3_instruction
**dst
, *sam
;
2546 dst
= get_dst(ctx
, &tex
->dest
, 1);
2548 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2549 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2551 /* even though there is only one component, since it ends
2552 * up in .z rather than .x, we need a split_dest()
2554 split_dest(b
, dst
, sam
, 0, 3);
2556 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2557 * the value in TEX_CONST_0 is zero-based.
2559 if (ctx
->levels_add_one
)
2560 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2562 put_dst(ctx
, &tex
->dest
);
2566 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2568 struct ir3_block
*b
= ctx
->block
;
2569 struct ir3_instruction
**dst
, *sam
;
2570 struct ir3_instruction
*lod
;
2571 unsigned flags
, coords
;
2573 tex_info(tex
, &flags
, &coords
);
2575 /* Actually we want the number of dimensions, not coordinates. This
2576 * distinction only matters for cubes.
2578 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2581 dst
= get_dst(ctx
, &tex
->dest
, 4);
2583 compile_assert(ctx
, tex
->num_srcs
== 1);
2584 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2586 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2588 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2589 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2591 split_dest(b
, dst
, sam
, 0, 4);
2593 /* Array size actually ends up in .w rather than .z. This doesn't
2594 * matter for miplevel 0, but for higher mips the value in z is
2595 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2596 * returned, which means that we have to add 1 to it for arrays.
2598 if (tex
->is_array
) {
2599 if (ctx
->levels_add_one
) {
2600 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2602 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2606 put_dst(ctx
, &tex
->dest
);
2610 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2612 switch (jump
->type
) {
2613 case nir_jump_break
:
2614 case nir_jump_continue
:
2615 case nir_jump_return
:
2616 /* I *think* we can simply just ignore this, and use the
2617 * successor block link to figure out where we need to
2618 * jump to for break/continue
2622 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2628 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2630 switch (instr
->type
) {
2631 case nir_instr_type_alu
:
2632 emit_alu(ctx
, nir_instr_as_alu(instr
));
2634 case nir_instr_type_intrinsic
:
2635 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2637 case nir_instr_type_load_const
:
2638 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2640 case nir_instr_type_ssa_undef
:
2641 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2643 case nir_instr_type_tex
: {
2644 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2645 /* couple tex instructions get special-cased:
2649 emit_tex_txs(ctx
, tex
);
2651 case nir_texop_query_levels
:
2652 emit_tex_query_levels(ctx
, tex
);
2660 case nir_instr_type_jump
:
2661 emit_jump(ctx
, nir_instr_as_jump(instr
));
2663 case nir_instr_type_phi
:
2664 /* we have converted phi webs to regs in NIR by now */
2665 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2667 case nir_instr_type_call
:
2668 case nir_instr_type_parallel_copy
:
2669 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2674 static struct ir3_block
*
2675 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2677 struct ir3_block
*block
;
2678 struct hash_entry
*hentry
;
2679 struct set_entry
*sentry
;
2682 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2684 return hentry
->data
;
2686 block
= ir3_block_create(ctx
->ir
);
2687 block
->nblock
= nblock
;
2688 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2690 block
->predecessors_count
= nblock
->predecessors
->entries
;
2691 block
->predecessors
= ralloc_array_size(block
,
2692 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
2694 set_foreach(nblock
->predecessors
, sentry
) {
2695 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
2702 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2704 struct ir3_block
*block
= get_block(ctx
, nblock
);
2706 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2707 if (nblock
->successors
[i
]) {
2708 block
->successors
[i
] =
2709 get_block(ctx
, nblock
->successors
[i
]);
2714 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2716 /* re-emit addr register in each block if needed: */
2717 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2718 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2719 ctx
->addr_ht
[i
] = NULL
;
2722 nir_foreach_instr(instr
, nblock
) {
2723 emit_instr(ctx
, instr
);
2729 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2732 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2734 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2736 ctx
->block
->condition
=
2737 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2739 emit_cf_list(ctx
, &nif
->then_list
);
2740 emit_cf_list(ctx
, &nif
->else_list
);
2744 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2746 emit_cf_list(ctx
, &nloop
->body
);
2750 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2752 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2753 switch (node
->type
) {
2754 case nir_cf_node_block
:
2755 emit_block(ctx
, nir_cf_node_as_block(node
));
2757 case nir_cf_node_if
:
2758 emit_if(ctx
, nir_cf_node_as_if(node
));
2760 case nir_cf_node_loop
:
2761 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2763 case nir_cf_node_function
:
2764 compile_error(ctx
, "TODO\n");
2770 /* emit stream-out code. At this point, the current block is the original
2771 * (nir) end block, and nir ensures that all flow control paths terminate
2772 * into the end block. We re-purpose the original end block to generate
2773 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2774 * block holding stream-out write instructions, followed by the new end
2778 * p0.x = (vtxcnt < maxvtxcnt)
2779 * // succs: blockStreamOut, blockNewEnd
2782 * ... stream-out instructions ...
2783 * // succs: blockNewEnd
2789 emit_stream_out(struct ir3_context
*ctx
)
2791 struct ir3_shader_variant
*v
= ctx
->so
;
2792 struct ir3
*ir
= ctx
->ir
;
2793 struct pipe_stream_output_info
*strmout
=
2794 &ctx
->so
->shader
->stream_output
;
2795 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2796 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2797 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2799 /* create vtxcnt input in input block at top of shader,
2800 * so that it is seen as live over the entire duration
2803 vtxcnt
= create_input(ctx
->in_block
, 0);
2804 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2806 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2808 /* at this point, we are at the original 'end' block,
2809 * re-purpose this block to stream-out condition, then
2810 * append stream-out block and new-end block
2812 orig_end_block
= ctx
->block
;
2814 // TODO these blocks need to update predecessors..
2815 // maybe w/ store_global intrinsic, we could do this
2816 // stuff in nir->nir pass
2818 stream_out_block
= ir3_block_create(ir
);
2819 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2821 new_end_block
= ir3_block_create(ir
);
2822 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2824 orig_end_block
->successors
[0] = stream_out_block
;
2825 orig_end_block
->successors
[1] = new_end_block
;
2826 stream_out_block
->successors
[0] = new_end_block
;
2828 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2829 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2830 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2831 cond
->cat2
.condition
= IR3_COND_LT
;
2833 /* condition goes on previous block to the conditional,
2834 * since it is used to pick which of the two successor
2837 orig_end_block
->condition
= cond
;
2839 /* switch to stream_out_block to generate the stream-out
2842 ctx
->block
= stream_out_block
;
2844 /* Calculate base addresses based on vtxcnt. Instructions
2845 * generated for bases not used in following loop will be
2846 * stripped out in the backend.
2848 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2849 unsigned stride
= strmout
->stride
[i
];
2850 struct ir3_instruction
*base
, *off
;
2852 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2854 /* 24-bit should be enough: */
2855 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2856 create_immed(ctx
->block
, stride
* 4), 0);
2858 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2861 /* Generate the per-output store instructions: */
2862 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2863 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2864 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2865 struct ir3_instruction
*base
, *out
, *stg
;
2867 base
= bases
[strmout
->output
[i
].output_buffer
];
2868 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2870 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2871 create_immed(ctx
->block
, 1), 0);
2872 stg
->cat6
.type
= TYPE_U32
;
2873 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2875 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2879 /* and finally switch to the new_end_block: */
2880 ctx
->block
= new_end_block
;
2884 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2886 nir_metadata_require(impl
, nir_metadata_block_index
);
2888 emit_cf_list(ctx
, &impl
->body
);
2889 emit_block(ctx
, impl
->end_block
);
2891 /* at this point, we should have a single empty block,
2892 * into which we emit the 'end' instruction.
2894 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2896 /* If stream-out (aka transform-feedback) enabled, emit the
2897 * stream-out instructions, followed by a new empty block (into
2898 * which the 'end' instruction lands).
2900 * NOTE: it is done in this order, rather than inserting before
2901 * we emit end_block, because NIR guarantees that all blocks
2902 * flow into end_block, and that end_block has no successors.
2903 * So by re-purposing end_block as the first block of stream-
2904 * out, we guarantee that all exit paths flow into the stream-
2907 if ((ctx
->compiler
->gpu_id
< 500) &&
2908 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2909 !ctx
->so
->key
.binning_pass
) {
2910 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2911 emit_stream_out(ctx
);
2914 ir3_END(ctx
->block
);
2918 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2920 struct ir3_shader_variant
*so
= ctx
->so
;
2921 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2922 unsigned ncomp
= glsl_get_components(in
->type
);
2923 unsigned n
= in
->data
.driver_location
;
2924 unsigned slot
= in
->data
.location
;
2926 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2927 slot
, array_len
, ncomp
, n
);
2929 /* let's pretend things other than vec4 don't exist: */
2930 ncomp
= MAX2(ncomp
, 4);
2931 compile_assert(ctx
, ncomp
== 4);
2933 so
->inputs
[n
].slot
= slot
;
2934 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2935 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2936 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2938 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2939 for (int i
= 0; i
< ncomp
; i
++) {
2940 struct ir3_instruction
*instr
= NULL
;
2941 unsigned idx
= (n
* 4) + i
;
2943 if (slot
== VARYING_SLOT_POS
) {
2944 so
->inputs
[n
].bary
= false;
2945 so
->frag_coord
= true;
2946 instr
= create_frag_coord(ctx
, i
);
2947 } else if (slot
== VARYING_SLOT_PNTC
) {
2948 /* see for example st_get_generic_varying_index().. this is
2949 * maybe a bit mesa/st specific. But we need things to line
2950 * up for this in fdN_program:
2951 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2952 * if (emit->sprite_coord_enable & texmask) {
2956 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2957 so
->inputs
[n
].bary
= true;
2958 instr
= create_frag_input(ctx
, false);
2960 bool use_ldlv
= false;
2962 /* detect the special case for front/back colors where
2963 * we need to do flat vs smooth shading depending on
2966 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2968 case VARYING_SLOT_COL0
:
2969 case VARYING_SLOT_COL1
:
2970 case VARYING_SLOT_BFC0
:
2971 case VARYING_SLOT_BFC1
:
2972 so
->inputs
[n
].rasterflat
= true;
2979 if (ctx
->flat_bypass
) {
2980 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2981 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2985 so
->inputs
[n
].bary
= true;
2987 instr
= create_frag_input(ctx
, use_ldlv
);
2990 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2992 ctx
->ir
->inputs
[idx
] = instr
;
2994 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2995 for (int i
= 0; i
< ncomp
; i
++) {
2996 unsigned idx
= (n
* 4) + i
;
2997 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2998 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
3001 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3004 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3005 so
->total_in
+= ncomp
;
3010 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3012 struct ir3_shader_variant
*so
= ctx
->so
;
3013 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3014 unsigned ncomp
= glsl_get_components(out
->type
);
3015 unsigned n
= out
->data
.driver_location
;
3016 unsigned slot
= out
->data
.location
;
3019 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3020 slot
, array_len
, ncomp
, n
);
3022 /* let's pretend things other than vec4 don't exist: */
3023 ncomp
= MAX2(ncomp
, 4);
3024 compile_assert(ctx
, ncomp
== 4);
3026 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3028 case FRAG_RESULT_DEPTH
:
3029 comp
= 2; /* tgsi will write to .z component */
3030 so
->writes_pos
= true;
3032 case FRAG_RESULT_COLOR
:
3036 if (slot
>= FRAG_RESULT_DATA0
)
3038 compile_error(ctx
, "unknown FS output name: %s\n",
3039 gl_frag_result_name(slot
));
3041 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3043 case VARYING_SLOT_POS
:
3044 so
->writes_pos
= true;
3046 case VARYING_SLOT_PSIZ
:
3047 so
->writes_psize
= true;
3049 case VARYING_SLOT_COL0
:
3050 case VARYING_SLOT_COL1
:
3051 case VARYING_SLOT_BFC0
:
3052 case VARYING_SLOT_BFC1
:
3053 case VARYING_SLOT_FOGC
:
3054 case VARYING_SLOT_CLIP_DIST0
:
3055 case VARYING_SLOT_CLIP_DIST1
:
3056 case VARYING_SLOT_CLIP_VERTEX
:
3059 if (slot
>= VARYING_SLOT_VAR0
)
3061 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3063 compile_error(ctx
, "unknown VS output name: %s\n",
3064 gl_varying_slot_name(slot
));
3067 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3070 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3072 so
->outputs
[n
].slot
= slot
;
3073 so
->outputs
[n
].regid
= regid(n
, comp
);
3074 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3076 for (int i
= 0; i
< ncomp
; i
++) {
3077 unsigned idx
= (n
* 4) + i
;
3078 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3079 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3084 max_drvloc(struct exec_list
*vars
)
3087 nir_foreach_variable(var
, vars
) {
3088 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3093 static const unsigned max_sysvals
[SHADER_MAX
] = {
3094 [SHADER_VERTEX
] = 16,
3095 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3099 emit_instructions(struct ir3_context
*ctx
)
3101 unsigned ninputs
, noutputs
;
3102 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3104 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3105 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3107 /* we need to leave room for sysvals:
3109 ninputs
+= max_sysvals
[ctx
->so
->type
];
3111 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3113 /* Create inputs in first block: */
3114 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3115 ctx
->in_block
= ctx
->block
;
3116 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3118 ninputs
-= max_sysvals
[ctx
->so
->type
];
3120 /* for fragment shader, we have a single input register (usually
3121 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3123 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3124 // TODO maybe a helper for fi since we need it a few places..
3125 struct ir3_instruction
*instr
;
3126 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3127 ir3_reg_create(instr
, 0, 0);
3128 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3129 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3130 ctx
->frag_pos
= instr
;
3134 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3135 setup_input(ctx
, var
);
3138 /* Setup outputs: */
3139 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3140 setup_output(ctx
, var
);
3143 /* Setup registers (which should only be arrays): */
3144 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3145 declare_array(ctx
, reg
);
3148 /* NOTE: need to do something more clever when we support >1 fxn */
3149 nir_foreach_register(reg
, &fxn
->registers
) {
3150 declare_array(ctx
, reg
);
3152 /* And emit the body: */
3154 emit_function(ctx
, fxn
);
3157 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3158 * for a fragment shader are just bary.f instructions. The *actual* inputs
3159 * from the hw perspective are the frag_pos and optionally frag_coord and
3163 fixup_frag_inputs(struct ir3_context
*ctx
)
3165 struct ir3_shader_variant
*so
= ctx
->so
;
3166 struct ir3
*ir
= ctx
->ir
;
3167 struct ir3_instruction
**inputs
;
3168 struct ir3_instruction
*instr
;
3173 n
= 4; /* always have frag_pos */
3174 n
+= COND(so
->frag_face
, 4);
3175 n
+= COND(so
->frag_coord
, 4);
3177 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3179 if (so
->frag_face
) {
3180 /* this ultimately gets assigned to hr0.x so doesn't conflict
3181 * with frag_coord/frag_pos..
3183 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3184 ctx
->frag_face
->regs
[0]->num
= 0;
3186 /* remaining channels not used, but let's avoid confusing
3187 * other parts that expect inputs to come in groups of vec4
3189 inputs
[ir
->ninputs
++] = NULL
;
3190 inputs
[ir
->ninputs
++] = NULL
;
3191 inputs
[ir
->ninputs
++] = NULL
;
3194 /* since we don't know where to set the regid for frag_coord,
3195 * we have to use r0.x for it. But we don't want to *always*
3196 * use r1.x for frag_pos as that could increase the register
3197 * footprint on simple shaders:
3199 if (so
->frag_coord
) {
3200 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3201 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3202 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3203 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3205 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3206 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3207 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3208 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3211 /* we always have frag_pos: */
3212 so
->pos_regid
= regid
;
3215 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3216 instr
->regs
[0]->num
= regid
++;
3217 inputs
[ir
->ninputs
++] = instr
;
3218 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3221 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3222 instr
->regs
[0]->num
= regid
++;
3223 inputs
[ir
->ninputs
++] = instr
;
3224 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3226 ir
->inputs
= inputs
;
3229 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3230 * need to assign the tex state indexes for these after we know the
3234 fixup_astc_srgb(struct ir3_context
*ctx
)
3236 struct ir3_shader_variant
*so
= ctx
->so
;
3237 /* indexed by original tex idx, value is newly assigned alpha sampler
3238 * state tex idx. Zero is invalid since there is at least one sampler
3241 unsigned alt_tex_state
[16] = {0};
3242 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3245 so
->astc_srgb
.base
= tex_idx
;
3247 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3248 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3250 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3252 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3253 /* assign new alternate/alpha tex state slot: */
3254 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3255 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3256 so
->astc_srgb
.count
++;
3259 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3264 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3265 struct ir3_shader_variant
*so
)
3267 struct ir3_context
*ctx
;
3269 struct ir3_instruction
**inputs
;
3270 unsigned i
, j
, actual_in
, inloc
;
3271 int ret
= 0, max_bary
;
3275 ctx
= compile_init(compiler
, so
);
3277 DBG("INIT failed!");
3282 emit_instructions(ctx
);
3285 DBG("EMIT failed!");
3290 ir
= so
->ir
= ctx
->ir
;
3292 /* keep track of the inputs from TGSI perspective.. */
3293 inputs
= ir
->inputs
;
3295 /* but fixup actual inputs for frag shader: */
3296 if (so
->type
== SHADER_FRAGMENT
)
3297 fixup_frag_inputs(ctx
);
3299 /* at this point, for binning pass, throw away unneeded outputs: */
3300 if (so
->key
.binning_pass
) {
3301 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3302 unsigned slot
= so
->outputs
[i
].slot
;
3304 /* throw away everything but first position/psize */
3305 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3307 so
->outputs
[j
] = so
->outputs
[i
];
3308 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3309 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3310 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3311 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3316 so
->outputs_count
= j
;
3317 ir
->noutputs
= j
* 4;
3320 /* if we want half-precision outputs, mark the output registers
3323 if (so
->key
.half_precision
) {
3324 for (i
= 0; i
< ir
->noutputs
; i
++) {
3325 struct ir3_instruction
*out
= ir
->outputs
[i
];
3330 /* if frag shader writes z, that needs to be full precision: */
3331 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3334 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3335 /* output could be a fanout (ie. texture fetch output)
3336 * in which case we need to propagate the half-reg flag
3337 * up to the definer so that RA sees it:
3339 if (out
->opc
== OPC_META_FO
) {
3340 out
= out
->regs
[1]->instr
;
3341 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3344 if (out
->opc
== OPC_MOV
) {
3345 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3350 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3351 printf("BEFORE CP:\n");
3357 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3358 printf("BEFORE GROUPING:\n");
3362 ir3_sched_add_deps(ir
);
3364 /* Group left/right neighbors, inserting mov's where needed to
3369 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3370 printf("AFTER GROUPING:\n");
3376 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3377 printf("AFTER DEPTH:\n");
3381 ret
= ir3_sched(ir
);
3383 DBG("SCHED failed!");
3387 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3388 printf("AFTER SCHED:\n");
3392 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3398 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3399 printf("AFTER RA:\n");
3403 /* fixup input/outputs: */
3404 for (i
= 0; i
< so
->outputs_count
; i
++) {
3405 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3408 /* Note that some or all channels of an input may be unused: */
3411 for (i
= 0; i
< so
->inputs_count
; i
++) {
3412 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3413 so
->inputs
[i
].ncomp
= 0;
3414 so
->inputs
[i
].inloc
= inloc
;
3415 for (j
= 0; j
< 4; j
++) {
3416 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3417 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3418 compmask
|= (1 << j
);
3419 regid
= in
->regs
[0]->num
- j
;
3421 so
->inputs
[i
].ncomp
++;
3422 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3424 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3425 in
->regs
[1]->iim_val
= inloc
+ j
;
3430 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3432 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3434 } else if (!so
->inputs
[i
].sysval
){
3435 so
->inputs
[i
].compmask
= compmask
;
3437 so
->inputs
[i
].regid
= regid
;
3441 fixup_astc_srgb(ctx
);
3443 /* We need to do legalize after (for frag shader's) the "bary.f"
3444 * offsets (inloc) have been assigned.
3446 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3448 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3449 printf("AFTER LEGALIZE:\n");
3453 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3454 if (so
->type
== SHADER_VERTEX
)
3455 so
->total_in
= actual_in
;
3457 so
->total_in
= max_bary
+ 1;
3462 ir3_destroy(so
->ir
);