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freedreno/ir3/nir: UBO support
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_compiler_nir.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include <stdarg.h>
30
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
37
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
40
41 #include "freedreno_util.h"
42
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
45
46 #include "instr-a3xx.h"
47 #include "ir3.h"
48
49
50 static struct ir3_instruction * create_immed(struct ir3_block *block, uint32_t val);
51
52 struct ir3_compile {
53 const struct tgsi_token *tokens;
54 struct nir_shader *s;
55
56 struct ir3 *ir;
57 struct ir3_shader_variant *so;
58
59 /* bitmask of which samplers are integer: */
60 uint16_t integer_s;
61
62 struct ir3_block *block;
63
64 /* For fragment shaders, from the hw perspective the only
65 * actual input is r0.xy position register passed to bary.f.
66 * But TGSI doesn't know that, it still declares things as
67 * IN[] registers. So we do all the input tracking normally
68 * and fix things up after compile_instructions()
69 *
70 * NOTE that frag_pos is the hardware position (possibly it
71 * is actually an index or tag or some such.. it is *not*
72 * values that can be directly used for gl_FragCoord..)
73 */
74 struct ir3_instruction *frag_pos, *frag_face, *frag_coord[4];
75
76 /* For vertex shaders, keep track of the system values sources */
77 struct ir3_instruction *vertex_id, *basevertex, *instance_id;
78
79 /* mapping from nir_register to defining instruction: */
80 struct hash_table *def_ht;
81
82 /* mapping from nir_variable to ir3_array: */
83 struct hash_table *var_ht;
84 unsigned num_arrays;
85
86 /* a common pattern for indirect addressing is to request the
87 * same address register multiple times. To avoid generating
88 * duplicate instruction sequences (which our backend does not
89 * try to clean up, since that should be done as the NIR stage)
90 * we cache the address value generated for a given src value:
91 */
92 struct hash_table *addr_ht;
93
94 /* for calculating input/output positions/linkages: */
95 unsigned next_inloc;
96
97 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
98 * so we need to use ldlv.u32 to load the varying directly:
99 */
100 bool flat_bypass;
101
102 /* on a3xx, we need to add one to # of array levels:
103 */
104 bool levels_add_one;
105
106 /* for looking up which system value is which */
107 unsigned sysval_semantics[8];
108
109 /* list of kill instructions: */
110 struct ir3_instruction *kill[16];
111 unsigned int kill_count;
112
113 /* set if we encounter something we can't handle yet, so we
114 * can bail cleanly and fallback to TGSI compiler f/e
115 */
116 bool error;
117 };
118
119
120 static struct nir_shader *to_nir(const struct tgsi_token *tokens)
121 {
122 struct nir_shader_compiler_options options = {
123 .lower_fpow = true,
124 .lower_fsat = true,
125 .lower_scmp = true,
126 .lower_flrp = true,
127 .native_integers = true,
128 };
129 bool progress;
130
131 struct nir_shader *s = tgsi_to_nir(tokens, &options);
132
133 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
134 debug_printf("----------------------\n");
135 nir_print_shader(s, stdout);
136 debug_printf("----------------------\n");
137 }
138
139 nir_opt_global_to_local(s);
140 nir_convert_to_ssa(s);
141 nir_lower_idiv(s);
142
143 do {
144 progress = false;
145
146 nir_lower_vars_to_ssa(s);
147 nir_lower_alu_to_scalar(s);
148
149 progress |= nir_copy_prop(s);
150 progress |= nir_opt_dce(s);
151 progress |= nir_opt_cse(s);
152 progress |= nir_opt_peephole_select(s);
153 progress |= nir_opt_algebraic(s);
154 progress |= nir_opt_constant_folding(s);
155
156 } while (progress);
157
158 nir_remove_dead_variables(s);
159 nir_validate_shader(s);
160
161 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
162 debug_printf("----------------------\n");
163 nir_print_shader(s, stdout);
164 debug_printf("----------------------\n");
165 }
166
167 return s;
168 }
169
170 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
171 static const struct tgsi_token *
172 lower_tgsi(const struct tgsi_token *tokens, struct ir3_shader_variant *so)
173 {
174 struct tgsi_shader_info info;
175 struct tgsi_lowering_config lconfig = {
176 .color_two_side = so->key.color_two_side,
177 .lower_FRC = true,
178 };
179
180 switch (so->type) {
181 case SHADER_FRAGMENT:
182 case SHADER_COMPUTE:
183 lconfig.saturate_s = so->key.fsaturate_s;
184 lconfig.saturate_t = so->key.fsaturate_t;
185 lconfig.saturate_r = so->key.fsaturate_r;
186 break;
187 case SHADER_VERTEX:
188 lconfig.saturate_s = so->key.vsaturate_s;
189 lconfig.saturate_t = so->key.vsaturate_t;
190 lconfig.saturate_r = so->key.vsaturate_r;
191 break;
192 }
193
194 if (!so->shader) {
195 /* hack for standalone compiler which does not have
196 * screen/context:
197 */
198 } else if (ir3_shader_gpuid(so->shader) >= 400) {
199 /* a4xx seems to have *no* sam.p */
200 lconfig.lower_TXP = ~0; /* lower all txp */
201 } else {
202 /* a3xx just needs to avoid sam.p for 3d tex */
203 lconfig.lower_TXP = (1 << TGSI_TEXTURE_3D);
204 }
205
206 return tgsi_transform_lowering(&lconfig, tokens, &info);
207 }
208
209 static struct ir3_compile *
210 compile_init(struct ir3_shader_variant *so,
211 const struct tgsi_token *tokens)
212 {
213 struct ir3_compile *ctx = rzalloc(NULL, struct ir3_compile);
214 const struct tgsi_token *lowered_tokens;
215
216 if (!so->shader) {
217 /* hack for standalone compiler which does not have
218 * screen/context:
219 */
220 } else if (ir3_shader_gpuid(so->shader) >= 400) {
221 /* need special handling for "flat" */
222 ctx->flat_bypass = true;
223 ctx->levels_add_one = false;
224 } else {
225 /* no special handling for "flat" */
226 ctx->flat_bypass = false;
227 ctx->levels_add_one = true;
228 }
229
230 switch (so->type) {
231 case SHADER_FRAGMENT:
232 case SHADER_COMPUTE:
233 ctx->integer_s = so->key.finteger_s;
234 break;
235 case SHADER_VERTEX:
236 ctx->integer_s = so->key.vinteger_s;
237 break;
238 }
239
240 ctx->ir = so->ir;
241 ctx->so = so;
242 ctx->next_inloc = 8;
243 ctx->def_ht = _mesa_hash_table_create(ctx,
244 _mesa_hash_pointer, _mesa_key_pointer_equal);
245 ctx->var_ht = _mesa_hash_table_create(ctx,
246 _mesa_hash_pointer, _mesa_key_pointer_equal);
247 ctx->addr_ht = _mesa_hash_table_create(ctx,
248 _mesa_hash_pointer, _mesa_key_pointer_equal);
249
250 lowered_tokens = lower_tgsi(tokens, so);
251 if (!lowered_tokens)
252 lowered_tokens = tokens;
253 ctx->s = to_nir(lowered_tokens);
254
255 if (lowered_tokens != tokens)
256 free((void *)lowered_tokens);
257
258 so->first_driver_param = so->first_immediate = ctx->s->num_uniforms;
259
260 /* one (vec4) slot for vertex id base: */
261 if (so->type == SHADER_VERTEX)
262 so->first_immediate++;
263
264 /* reserve 4 (vec4) slots for ubo base addresses: */
265 so->first_immediate += 4;
266
267 return ctx;
268 }
269
270 static void
271 compile_error(struct ir3_compile *ctx, const char *format, ...)
272 {
273 va_list ap;
274 va_start(ap, format);
275 _debug_vprintf(format, ap);
276 va_end(ap);
277 nir_print_shader(ctx->s, stdout);
278 ctx->error = true;
279 debug_assert(0);
280 }
281
282 #define compile_assert(ctx, cond) do { \
283 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
284 } while (0)
285
286 static void
287 compile_free(struct ir3_compile *ctx)
288 {
289 ralloc_free(ctx);
290 }
291
292
293 struct ir3_array {
294 unsigned length, aid;
295 struct ir3_instruction *arr[];
296 };
297
298 static void
299 declare_var(struct ir3_compile *ctx, nir_variable *var)
300 {
301 unsigned length = glsl_get_length(var->type) * 4; /* always vec4, at least with ttn */
302 struct ir3_array *arr = ralloc_size(ctx, sizeof(*arr) +
303 (length * sizeof(arr->arr[0])));
304 arr->length = length;
305 arr->aid = ++ctx->num_arrays;
306 /* Some shaders end up reading array elements without first writing..
307 * so initialize things to prevent null instr ptrs later:
308 */
309 for (unsigned i = 0; i < length; i++)
310 arr->arr[i] = create_immed(ctx->block, 0);
311 _mesa_hash_table_insert(ctx->var_ht, var, arr);
312 }
313
314 static struct ir3_array *
315 get_var(struct ir3_compile *ctx, nir_variable *var)
316 {
317 struct hash_entry *entry = _mesa_hash_table_search(ctx->var_ht, var);
318 return entry->data;
319 }
320
321 /* allocate a n element value array (to be populated by caller) and
322 * insert in def_ht
323 */
324 static struct ir3_instruction **
325 __get_dst(struct ir3_compile *ctx, void *key, unsigned n)
326 {
327 struct ir3_instruction **value =
328 ralloc_array(ctx->def_ht, struct ir3_instruction *, n);
329 _mesa_hash_table_insert(ctx->def_ht, key, value);
330 return value;
331 }
332
333 static struct ir3_instruction **
334 get_dst(struct ir3_compile *ctx, nir_dest *dst, unsigned n)
335 {
336 if (dst->is_ssa) {
337 return __get_dst(ctx, &dst->ssa, n);
338 } else {
339 return __get_dst(ctx, dst->reg.reg, n);
340 }
341 }
342
343 static struct ir3_instruction **
344 get_dst_ssa(struct ir3_compile *ctx, nir_ssa_def *dst, unsigned n)
345 {
346 return __get_dst(ctx, dst, n);
347 }
348
349 static struct ir3_instruction **
350 get_src(struct ir3_compile *ctx, nir_src *src)
351 {
352 struct hash_entry *entry;
353 if (src->is_ssa) {
354 entry = _mesa_hash_table_search(ctx->def_ht, src->ssa);
355 } else {
356 entry = _mesa_hash_table_search(ctx->def_ht, src->reg.reg);
357 }
358 compile_assert(ctx, entry);
359 return entry->data;
360 }
361
362 static struct ir3_instruction *
363 create_immed(struct ir3_block *block, uint32_t val)
364 {
365 struct ir3_instruction *mov;
366
367 mov = ir3_instr_create(block, 1, 0);
368 mov->cat1.src_type = TYPE_U32;
369 mov->cat1.dst_type = TYPE_U32;
370 ir3_reg_create(mov, 0, 0);
371 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
372
373 return mov;
374 }
375
376 static struct ir3_instruction *
377 create_addr(struct ir3_block *block, struct ir3_instruction *src)
378 {
379 struct ir3_instruction *instr, *immed;
380
381 /* TODO in at least some cases, the backend could probably be
382 * made clever enough to propagate IR3_REG_HALF..
383 */
384 instr = ir3_COV(block, src, TYPE_U32, TYPE_S16);
385 instr->regs[0]->flags |= IR3_REG_HALF;
386
387 immed = create_immed(block, 2);
388 immed->regs[0]->flags |= IR3_REG_HALF;
389
390 instr = ir3_SHL_B(block, instr, 0, immed, 0);
391 instr->regs[0]->flags |= IR3_REG_HALF;
392 instr->regs[1]->flags |= IR3_REG_HALF;
393
394 instr = ir3_MOV(block, instr, TYPE_S16);
395 instr->regs[0]->flags |= IR3_REG_ADDR | IR3_REG_HALF;
396 instr->regs[1]->flags |= IR3_REG_HALF;
397
398 return instr;
399 }
400
401 /* caches addr values to avoid generating multiple cov/shl/mova
402 * sequences for each use of a given NIR level src as address
403 */
404 static struct ir3_instruction *
405 get_addr(struct ir3_compile *ctx, struct ir3_instruction *src)
406 {
407 struct ir3_instruction *addr;
408 struct hash_entry *entry;
409 entry = _mesa_hash_table_search(ctx->addr_ht, src);
410 if (entry)
411 return entry->data;
412
413 /* TODO do we need to cache per block? */
414 addr = create_addr(ctx->block, src);
415 _mesa_hash_table_insert(ctx->addr_ht, src, addr);
416
417 return addr;
418 }
419
420 static struct ir3_instruction *
421 create_uniform(struct ir3_compile *ctx, unsigned n)
422 {
423 struct ir3_instruction *mov;
424
425 mov = ir3_instr_create(ctx->block, 1, 0);
426 /* TODO get types right? */
427 mov->cat1.src_type = TYPE_F32;
428 mov->cat1.dst_type = TYPE_F32;
429 ir3_reg_create(mov, 0, 0);
430 ir3_reg_create(mov, n, IR3_REG_CONST);
431
432 return mov;
433 }
434
435 static struct ir3_instruction *
436 create_uniform_indirect(struct ir3_compile *ctx, unsigned n,
437 struct ir3_instruction *address)
438 {
439 struct ir3_instruction *mov;
440
441 mov = ir3_instr_create(ctx->block, 1, 0);
442 mov->cat1.src_type = TYPE_U32;
443 mov->cat1.dst_type = TYPE_U32;
444 ir3_reg_create(mov, 0, 0);
445 ir3_reg_create(mov, n, IR3_REG_CONST | IR3_REG_RELATIV);
446 mov->address = address;
447
448 array_insert(ctx->ir->indirects, mov);
449
450 return mov;
451 }
452
453 static struct ir3_instruction *
454 create_collect(struct ir3_block *block, struct ir3_instruction **arr,
455 unsigned arrsz)
456 {
457 struct ir3_instruction *collect;
458
459 if (arrsz == 0)
460 return NULL;
461
462 collect = ir3_instr_create2(block, -1, OPC_META_FI, 1 + arrsz);
463 ir3_reg_create(collect, 0, 0);
464 for (unsigned i = 0; i < arrsz; i++)
465 ir3_reg_create(collect, 0, IR3_REG_SSA)->instr = arr[i];
466
467 return collect;
468 }
469
470 static struct ir3_instruction *
471 create_indirect_load(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
472 struct ir3_instruction *address, struct ir3_instruction *collect)
473 {
474 struct ir3_block *block = ctx->block;
475 struct ir3_instruction *mov;
476 struct ir3_register *src;
477
478 mov = ir3_instr_create(block, 1, 0);
479 mov->cat1.src_type = TYPE_U32;
480 mov->cat1.dst_type = TYPE_U32;
481 ir3_reg_create(mov, 0, 0);
482 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
483 src->instr = collect;
484 src->size = arrsz;
485 src->offset = n;
486 mov->address = address;
487
488 array_insert(ctx->ir->indirects, mov);
489
490 return mov;
491 }
492
493 static struct ir3_instruction *
494 create_indirect_store(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
495 struct ir3_instruction *src, struct ir3_instruction *address,
496 struct ir3_instruction *collect)
497 {
498 struct ir3_block *block = ctx->block;
499 struct ir3_instruction *mov;
500 struct ir3_register *dst;
501
502 mov = ir3_instr_create(block, 1, 0);
503 mov->cat1.src_type = TYPE_U32;
504 mov->cat1.dst_type = TYPE_U32;
505 dst = ir3_reg_create(mov, 0, IR3_REG_RELATIV);
506 dst->size = arrsz;
507 dst->offset = n;
508 ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src;
509 mov->address = address;
510 mov->fanin = collect;
511
512 array_insert(ctx->ir->indirects, mov);
513
514 return mov;
515 }
516
517 static struct ir3_instruction *
518 create_input(struct ir3_block *block, struct ir3_instruction *instr,
519 unsigned n)
520 {
521 struct ir3_instruction *in;
522
523 in = ir3_instr_create(block, -1, OPC_META_INPUT);
524 in->inout.block = block;
525 ir3_reg_create(in, n, 0);
526 if (instr)
527 ir3_reg_create(in, 0, IR3_REG_SSA)->instr = instr;
528
529 return in;
530 }
531
532 static struct ir3_instruction *
533 create_frag_input(struct ir3_compile *ctx, unsigned n, bool use_ldlv)
534 {
535 struct ir3_block *block = ctx->block;
536 struct ir3_instruction *instr;
537 struct ir3_instruction *inloc = create_immed(block, n);
538
539 if (use_ldlv) {
540 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
541 instr->cat6.type = TYPE_U32;
542 instr->cat6.iim_val = 1;
543 } else {
544 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_pos, 0);
545 instr->regs[2]->wrmask = 0x3;
546 }
547
548 return instr;
549 }
550
551 static struct ir3_instruction *
552 create_frag_coord(struct ir3_compile *ctx, unsigned comp)
553 {
554 struct ir3_block *block = ctx->block;
555 struct ir3_instruction *instr;
556
557 compile_assert(ctx, !ctx->frag_coord[comp]);
558
559 ctx->frag_coord[comp] = create_input(ctx->block, NULL, 0);
560
561 switch (comp) {
562 case 0: /* .x */
563 case 1: /* .y */
564 /* for frag_coord, we get unsigned values.. we need
565 * to subtract (integer) 8 and divide by 16 (right-
566 * shift by 4) then convert to float:
567 *
568 * add.s tmp, src, -8
569 * shr.b tmp, tmp, 4
570 * mov.u32f32 dst, tmp
571 *
572 */
573 instr = ir3_ADD_S(block, ctx->frag_coord[comp], 0,
574 create_immed(block, -8), 0);
575 instr = ir3_SHR_B(block, instr, 0,
576 create_immed(block, 4), 0);
577 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
578
579 return instr;
580 case 2: /* .z */
581 case 3: /* .w */
582 default:
583 /* seems that we can use these as-is: */
584 return ctx->frag_coord[comp];
585 }
586 }
587
588 static struct ir3_instruction *
589 create_frag_face(struct ir3_compile *ctx, unsigned comp)
590 {
591 struct ir3_block *block = ctx->block;
592 struct ir3_instruction *instr;
593
594 switch (comp) {
595 case 0: /* .x */
596 compile_assert(ctx, !ctx->frag_face);
597
598 ctx->frag_face = create_input(block, NULL, 0);
599
600 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
601 * positive vs negative float.. and piglit further seems to
602 * expect -1.0 or 1.0:
603 *
604 * mul.s tmp, hr0.x, 2
605 * add.s tmp, tmp, 1
606 * mov.s32f32, dst, tmp
607 *
608 */
609 instr = ir3_MUL_S(block, ctx->frag_face, 0,
610 create_immed(block, 2), 0);
611 instr = ir3_ADD_S(block, instr, 0,
612 create_immed(block, 1), 0);
613 instr = ir3_COV(block, instr, TYPE_S32, TYPE_F32);
614
615 return instr;
616 case 1: /* .y */
617 case 2: /* .z */
618 return create_immed(block, fui(0.0));
619 default:
620 case 3: /* .w */
621 return create_immed(block, fui(1.0));
622 }
623 }
624
625 /* helper for instructions that produce multiple consecutive scalar
626 * outputs which need to have a split/fanout meta instruction inserted
627 */
628 static void
629 split_dest(struct ir3_block *block, struct ir3_instruction **dst,
630 struct ir3_instruction *src)
631 {
632 struct ir3_instruction *prev = NULL;
633 for (int i = 0, j = 0; i < 4; i++) {
634 struct ir3_instruction *split =
635 ir3_instr_create(block, -1, OPC_META_FO);
636 ir3_reg_create(split, 0, IR3_REG_SSA);
637 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = src;
638 split->fo.off = i;
639
640 if (prev) {
641 split->cp.left = prev;
642 split->cp.left_cnt++;
643 prev->cp.right = split;
644 prev->cp.right_cnt++;
645 }
646 prev = split;
647
648 if (src->regs[0]->wrmask & (1 << i))
649 dst[j++] = split;
650 }
651 }
652
653 /*
654 * Adreno uses uint rather than having dedicated bool type,
655 * which (potentially) requires some conversion, in particular
656 * when using output of an bool instr to int input, or visa
657 * versa.
658 *
659 * | Adreno | NIR |
660 * -------+---------+-------+-
661 * true | 1 | ~0 |
662 * false | 0 | 0 |
663 *
664 * To convert from an adreno bool (uint) to nir, use:
665 *
666 * absneg.s dst, (neg)src
667 *
668 * To convert back in the other direction:
669 *
670 * absneg.s dst, (abs)arc
671 *
672 * The CP step can clean up the absneg.s that cancel each other
673 * out, and with a slight bit of extra cleverness (to recognize
674 * the instructions which produce either a 0 or 1) can eliminate
675 * the absneg.s's completely when an instruction that wants
676 * 0/1 consumes the result. For example, when a nir 'bcsel'
677 * consumes the result of 'feq'. So we should be able to get by
678 * without a boolean resolve step, and without incuring any
679 * extra penalty in instruction count.
680 */
681
682 /* NIR bool -> native (adreno): */
683 static struct ir3_instruction *
684 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
685 {
686 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
687 }
688
689 /* native (adreno) -> NIR bool: */
690 static struct ir3_instruction *
691 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
692 {
693 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
694 }
695
696 /*
697 * alu/sfu instructions:
698 */
699
700 static void
701 emit_alu(struct ir3_compile *ctx, nir_alu_instr *alu)
702 {
703 const nir_op_info *info = &nir_op_infos[alu->op];
704 struct ir3_instruction **dst, *src[info->num_inputs];
705 struct ir3_block *b = ctx->block;
706
707 dst = get_dst(ctx, &alu->dest.dest, MAX2(info->output_size, 1));
708
709 /* Vectors are special in that they have non-scalarized writemasks,
710 * and just take the first swizzle channel for each argument in
711 * order into each writemask channel.
712 */
713 if ((alu->op == nir_op_vec2) ||
714 (alu->op == nir_op_vec3) ||
715 (alu->op == nir_op_vec4)) {
716
717 for (int i = 0; i < info->num_inputs; i++) {
718 nir_alu_src *asrc = &alu->src[i];
719
720 compile_assert(ctx, !asrc->abs);
721 compile_assert(ctx, !asrc->negate);
722
723 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[0]];
724 if (!src[i])
725 src[i] = create_immed(ctx->block, 0);
726 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
727 }
728
729 return;
730 }
731
732 /* General case: We can just grab the one used channel per src. */
733 for (int i = 0; i < info->num_inputs; i++) {
734 unsigned chan = ffs(alu->dest.write_mask) - 1;
735 nir_alu_src *asrc = &alu->src[i];
736
737 compile_assert(ctx, !asrc->abs);
738 compile_assert(ctx, !asrc->negate);
739
740 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
741
742 compile_assert(ctx, src[i]);
743 }
744
745 switch (alu->op) {
746 case nir_op_f2i:
747 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_S32);
748 break;
749 case nir_op_f2u:
750 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_U32);
751 break;
752 case nir_op_i2f:
753 dst[0] = ir3_COV(b, src[0], TYPE_S32, TYPE_F32);
754 break;
755 case nir_op_u2f:
756 dst[0] = ir3_COV(b, src[0], TYPE_U32, TYPE_F32);
757 break;
758 case nir_op_imov:
759 dst[0] = ir3_MOV(b, src[0], TYPE_S32);
760 break;
761 case nir_op_fmov:
762 dst[0] = ir3_MOV(b, src[0], TYPE_F32);
763 break;
764 case nir_op_f2b:
765 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
766 dst[0]->cat2.condition = IR3_COND_NE;
767 dst[0] = ir3_n2b(b, dst[0]);
768 break;
769 case nir_op_b2f:
770 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
771 break;
772 case nir_op_b2i:
773 dst[0] = ir3_b2n(b, src[0]);
774 break;
775 case nir_op_i2b:
776 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
777 dst[0]->cat2.condition = IR3_COND_NE;
778 dst[0] = ir3_n2b(b, dst[0]);
779 break;
780
781 case nir_op_fneg:
782 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
783 break;
784 case nir_op_fabs:
785 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
786 break;
787 case nir_op_fmax:
788 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
789 break;
790 case nir_op_fmin:
791 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
792 break;
793 case nir_op_fmul:
794 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
795 break;
796 case nir_op_fadd:
797 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
798 break;
799 case nir_op_fsub:
800 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
801 break;
802 case nir_op_ffma:
803 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
804 break;
805 case nir_op_fddx:
806 dst[0] = ir3_DSX(b, src[0], 0);
807 dst[0]->cat5.type = TYPE_F32;
808 break;
809 case nir_op_fddy:
810 dst[0] = ir3_DSY(b, src[0], 0);
811 dst[0]->cat5.type = TYPE_F32;
812 break;
813 break;
814 case nir_op_flt:
815 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
816 dst[0]->cat2.condition = IR3_COND_LT;
817 dst[0] = ir3_n2b(b, dst[0]);
818 break;
819 case nir_op_fge:
820 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
821 dst[0]->cat2.condition = IR3_COND_GE;
822 dst[0] = ir3_n2b(b, dst[0]);
823 break;
824 case nir_op_feq:
825 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
826 dst[0]->cat2.condition = IR3_COND_EQ;
827 dst[0] = ir3_n2b(b, dst[0]);
828 break;
829 case nir_op_fne:
830 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
831 dst[0]->cat2.condition = IR3_COND_NE;
832 dst[0] = ir3_n2b(b, dst[0]);
833 break;
834 case nir_op_fceil:
835 dst[0] = ir3_CEIL_F(b, src[0], 0);
836 break;
837 case nir_op_ffloor:
838 dst[0] = ir3_FLOOR_F(b, src[0], 0);
839 break;
840 case nir_op_ftrunc:
841 dst[0] = ir3_TRUNC_F(b, src[0], 0);
842 break;
843 case nir_op_fround_even:
844 dst[0] = ir3_RNDNE_F(b, src[0], 0);
845 break;
846 case nir_op_fsign:
847 dst[0] = ir3_SIGN_F(b, src[0], 0);
848 break;
849
850 case nir_op_fsin:
851 dst[0] = ir3_SIN(b, src[0], 0);
852 break;
853 case nir_op_fcos:
854 dst[0] = ir3_COS(b, src[0], 0);
855 break;
856 case nir_op_frsq:
857 dst[0] = ir3_RSQ(b, src[0], 0);
858 break;
859 case nir_op_frcp:
860 dst[0] = ir3_RCP(b, src[0], 0);
861 break;
862 case nir_op_flog2:
863 dst[0] = ir3_LOG2(b, src[0], 0);
864 break;
865 case nir_op_fexp2:
866 dst[0] = ir3_EXP2(b, src[0], 0);
867 break;
868 case nir_op_fsqrt:
869 dst[0] = ir3_SQRT(b, src[0], 0);
870 break;
871
872 case nir_op_iabs:
873 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
874 break;
875 case nir_op_iadd:
876 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
877 break;
878 case nir_op_iand:
879 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
880 break;
881 case nir_op_imax:
882 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
883 break;
884 case nir_op_imin:
885 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
886 break;
887 case nir_op_imul:
888 /*
889 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
890 * mull.u tmp0, a, b ; mul low, i.e. al * bl
891 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
892 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
893 */
894 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
895 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
896 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
897 break;
898 case nir_op_ineg:
899 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
900 break;
901 case nir_op_inot:
902 dst[0] = ir3_NOT_B(b, src[0], 0);
903 break;
904 case nir_op_ior:
905 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
906 break;
907 case nir_op_ishl:
908 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
909 break;
910 case nir_op_ishr:
911 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
912 break;
913 case nir_op_isign: {
914 /* maybe this would be sane to lower in nir.. */
915 struct ir3_instruction *neg, *pos;
916
917 neg = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
918 neg->cat2.condition = IR3_COND_LT;
919
920 pos = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
921 pos->cat2.condition = IR3_COND_GT;
922
923 dst[0] = ir3_SUB_U(b, pos, 0, neg, 0);
924
925 break;
926 }
927 case nir_op_isub:
928 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
929 break;
930 case nir_op_ixor:
931 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
932 break;
933 case nir_op_ushr:
934 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
935 break;
936 case nir_op_ilt:
937 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
938 dst[0]->cat2.condition = IR3_COND_LT;
939 dst[0] = ir3_n2b(b, dst[0]);
940 break;
941 case nir_op_ige:
942 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
943 dst[0]->cat2.condition = IR3_COND_GE;
944 dst[0] = ir3_n2b(b, dst[0]);
945 break;
946 case nir_op_ieq:
947 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
948 dst[0]->cat2.condition = IR3_COND_EQ;
949 dst[0] = ir3_n2b(b, dst[0]);
950 break;
951 case nir_op_ine:
952 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
953 dst[0]->cat2.condition = IR3_COND_NE;
954 dst[0] = ir3_n2b(b, dst[0]);
955 break;
956 case nir_op_ult:
957 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
958 dst[0]->cat2.condition = IR3_COND_LT;
959 dst[0] = ir3_n2b(b, dst[0]);
960 break;
961 case nir_op_uge:
962 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
963 dst[0]->cat2.condition = IR3_COND_GE;
964 dst[0] = ir3_n2b(b, dst[0]);
965 break;
966
967 case nir_op_bcsel:
968 dst[0] = ir3_SEL_B32(b, src[1], 0, ir3_b2n(b, src[0]), 0, src[2], 0);
969 break;
970
971 default:
972 compile_error(ctx, "Unhandled ALU op: %s\n",
973 nir_op_infos[alu->op].name);
974 break;
975 }
976 }
977
978 /* handles direct/indirect UBO reads: */
979 static void
980 emit_intrinsic_load_ubo(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
981 struct ir3_instruction **dst)
982 {
983 struct ir3_block *b = ctx->block;
984 struct ir3_instruction *addr, *src0, *src1;
985 /* UBO addresses are the first driver params: */
986 unsigned ubo = regid(ctx->so->first_driver_param, 0);
987 unsigned off = intr->const_index[0];
988
989 /* First src is ubo index, which could either be an immed or not: */
990 src0 = get_src(ctx, &intr->src[0])[0];
991 if (is_same_type_mov(src0) &&
992 (src0->regs[1]->flags & IR3_REG_IMMED)) {
993 addr = create_uniform(ctx, ubo + src0->regs[1]->iim_val);
994 } else {
995 addr = create_uniform_indirect(ctx, ubo, get_addr(ctx, src0));
996 }
997
998 if (intr->intrinsic == nir_intrinsic_load_ubo_indirect) {
999 /* For load_ubo_indirect, second src is indirect offset: */
1000 src1 = get_src(ctx, &intr->src[1])[0];
1001
1002 /* and add offset to addr: */
1003 addr = ir3_ADD_S(b, addr, 0, src1, 0);
1004 }
1005
1006 /* if offset is to large to encode in the ldg, split it out: */
1007 if ((off + (intr->num_components * 4)) > 1024) {
1008 /* split out the minimal amount to improve the odds that
1009 * cp can fit the immediate in the add.s instruction:
1010 */
1011 unsigned off2 = off + (intr->num_components * 4) - 1024;
1012 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
1013 off -= off2;
1014 }
1015
1016 for (int i = 0; i < intr->num_components; i++) {
1017 struct ir3_instruction *load =
1018 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
1019 load->cat6.type = TYPE_U32;
1020 load->cat6.offset = off + i * 4; /* byte offset */
1021 dst[i] = load;
1022 }
1023 }
1024
1025 /* handles array reads: */
1026 static void
1027 emit_intrinisic_load_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
1028 struct ir3_instruction **dst)
1029 {
1030 nir_deref_var *dvar = intr->variables[0];
1031 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
1032 struct ir3_array *arr = get_var(ctx, dvar->var);
1033
1034 compile_assert(ctx, dvar->deref.child &&
1035 (dvar->deref.child->deref_type == nir_deref_type_array));
1036
1037 switch (darr->deref_array_type) {
1038 case nir_deref_array_type_direct:
1039 /* direct access does not require anything special: */
1040 for (int i = 0; i < intr->num_components; i++) {
1041 unsigned n = darr->base_offset * 4 + i;
1042 compile_assert(ctx, n < arr->length);
1043 dst[i] = arr->arr[n];
1044 }
1045 break;
1046 case nir_deref_array_type_indirect: {
1047 /* for indirect, we need to collect all the array elements: */
1048 struct ir3_instruction *collect =
1049 create_collect(ctx->block, arr->arr, arr->length);
1050 struct ir3_instruction *addr =
1051 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1052 for (int i = 0; i < intr->num_components; i++) {
1053 unsigned n = darr->base_offset * 4 + i;
1054 compile_assert(ctx, n < arr->length);
1055 dst[i] = create_indirect_load(ctx, arr->length, n, addr, collect);
1056 }
1057 break;
1058 }
1059 default:
1060 compile_error(ctx, "Unhandled load deref type: %u\n",
1061 darr->deref_array_type);
1062 break;
1063 }
1064 }
1065
1066 /* handles array writes: */
1067 static void
1068 emit_intrinisic_store_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1069 {
1070 nir_deref_var *dvar = intr->variables[0];
1071 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
1072 struct ir3_array *arr = get_var(ctx, dvar->var);
1073 struct ir3_instruction **src;
1074
1075 compile_assert(ctx, dvar->deref.child &&
1076 (dvar->deref.child->deref_type == nir_deref_type_array));
1077
1078 src = get_src(ctx, &intr->src[0]);
1079
1080 switch (darr->deref_array_type) {
1081 case nir_deref_array_type_direct:
1082 /* direct access does not require anything special: */
1083 for (int i = 0; i < intr->num_components; i++) {
1084 unsigned n = darr->base_offset * 4 + i;
1085 compile_assert(ctx, n < arr->length);
1086 arr->arr[n] = src[i];
1087 }
1088 break;
1089 case nir_deref_array_type_indirect: {
1090 /* for indirect, create indirect-store and fan that out: */
1091 struct ir3_instruction *collect =
1092 create_collect(ctx->block, arr->arr, arr->length);
1093 struct ir3_instruction *addr =
1094 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1095 for (int i = 0; i < intr->num_components; i++) {
1096 struct ir3_instruction *store;
1097 unsigned n = darr->base_offset * 4 + i;
1098 compile_assert(ctx, n < arr->length);
1099
1100 store = create_indirect_store(ctx, arr->length,
1101 n, src[i], addr, collect);
1102
1103 store->fanin->fi.aid = arr->aid;
1104
1105 /* TODO: probably split this out to be used for
1106 * store_output_indirect? or move this into
1107 * create_indirect_store()?
1108 */
1109 for (int j = i; j < arr->length; j += 4) {
1110 struct ir3_instruction *split;
1111
1112 split = ir3_instr_create(ctx->block, -1, OPC_META_FO);
1113 split->fo.off = j;
1114 ir3_reg_create(split, 0, 0);
1115 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = store;
1116
1117 arr->arr[j] = split;
1118 }
1119 }
1120 break;
1121 }
1122 default:
1123 compile_error(ctx, "Unhandled store deref type: %u\n",
1124 darr->deref_array_type);
1125 break;
1126 }
1127 }
1128
1129 static void add_sysval_input(struct ir3_compile *ctx, unsigned name,
1130 struct ir3_instruction *instr)
1131 {
1132 struct ir3_shader_variant *so = ctx->so;
1133 unsigned r = regid(so->inputs_count, 0);
1134 unsigned n = so->inputs_count++;
1135
1136 so->inputs[n].semantic = ir3_semantic_name(name, 0);
1137 so->inputs[n].compmask = 1;
1138 so->inputs[n].regid = r;
1139 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1140 so->total_in++;
1141
1142 ctx->block->inputs[r] = instr;
1143 }
1144
1145 static void
1146 emit_intrinisic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1147 {
1148 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1149 struct ir3_instruction **dst, **src;
1150 struct ir3_block *b = ctx->block;
1151 unsigned idx = intr->const_index[0];
1152
1153 if (info->has_dest) {
1154 dst = get_dst(ctx, &intr->dest, intr->num_components);
1155 }
1156
1157 switch (intr->intrinsic) {
1158 case nir_intrinsic_load_uniform:
1159 compile_assert(ctx, intr->const_index[1] == 1);
1160 for (int i = 0; i < intr->num_components; i++) {
1161 unsigned n = idx * 4 + i;
1162 dst[i] = create_uniform(ctx, n);
1163 }
1164 break;
1165 case nir_intrinsic_load_uniform_indirect:
1166 compile_assert(ctx, intr->const_index[1] == 1);
1167 src = get_src(ctx, &intr->src[0]);
1168 for (int i = 0; i < intr->num_components; i++) {
1169 unsigned n = idx * 4 + i;
1170 dst[i] = create_uniform_indirect(ctx, n,
1171 get_addr(ctx, src[0]));
1172 }
1173 break;
1174 case nir_intrinsic_load_ubo:
1175 case nir_intrinsic_load_ubo_indirect:
1176 emit_intrinsic_load_ubo(ctx, intr, dst);
1177 break;
1178 case nir_intrinsic_load_input:
1179 compile_assert(ctx, intr->const_index[1] == 1);
1180 for (int i = 0; i < intr->num_components; i++) {
1181 unsigned n = idx * 4 + i;
1182 dst[i] = b->inputs[n];
1183 }
1184 break;
1185 case nir_intrinsic_load_input_indirect:
1186 compile_assert(ctx, intr->const_index[1] == 1);
1187 src = get_src(ctx, &intr->src[0]);
1188 struct ir3_instruction *collect =
1189 create_collect(b, b->inputs, b->ninputs);
1190 struct ir3_instruction *addr = get_addr(ctx, src[0]);
1191 for (int i = 0; i < intr->num_components; i++) {
1192 unsigned n = idx * 4 + i;
1193 dst[i] = create_indirect_load(ctx, b->ninputs, n, addr, collect);
1194 }
1195 break;
1196 case nir_intrinsic_load_var:
1197 emit_intrinisic_load_var(ctx, intr, dst);
1198 break;
1199 case nir_intrinsic_store_var:
1200 emit_intrinisic_store_var(ctx, intr);
1201 break;
1202 case nir_intrinsic_store_output:
1203 compile_assert(ctx, intr->const_index[1] == 1);
1204 src = get_src(ctx, &intr->src[0]);
1205 for (int i = 0; i < intr->num_components; i++) {
1206 unsigned n = idx * 4 + i;
1207 b->outputs[n] = src[i];
1208 }
1209 break;
1210 case nir_intrinsic_load_base_vertex:
1211 if (!ctx->basevertex) {
1212 /* first four vec4 sysval's reserved for UBOs: */
1213 unsigned r = regid(ctx->so->first_driver_param + 4, 0);
1214 ctx->basevertex = create_uniform(ctx, r);
1215 add_sysval_input(ctx, TGSI_SEMANTIC_BASEVERTEX,
1216 ctx->basevertex);
1217 }
1218 dst[0] = ctx->basevertex;
1219 break;
1220 case nir_intrinsic_load_vertex_id_zero_base:
1221 if (!ctx->vertex_id) {
1222 ctx->vertex_id = create_input(ctx->block, NULL, 0);
1223 add_sysval_input(ctx, TGSI_SEMANTIC_VERTEXID_NOBASE,
1224 ctx->vertex_id);
1225 }
1226 dst[0] = ctx->vertex_id;
1227 break;
1228 case nir_intrinsic_load_instance_id:
1229 if (!ctx->instance_id) {
1230 ctx->instance_id = create_input(ctx->block, NULL, 0);
1231 add_sysval_input(ctx, TGSI_SEMANTIC_INSTANCEID,
1232 ctx->instance_id);
1233 }
1234 dst[0] = ctx->instance_id;
1235 break;
1236 case nir_intrinsic_discard_if:
1237 case nir_intrinsic_discard: {
1238 struct ir3_instruction *cond, *kill;
1239
1240 if (intr->intrinsic == nir_intrinsic_discard_if) {
1241 /* conditional discard: */
1242 src = get_src(ctx, &intr->src[0]);
1243 cond = ir3_b2n(b, src[0]);
1244 } else {
1245 /* unconditional discard: */
1246 cond = create_immed(b, 1);
1247 }
1248
1249 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1250 cond->cat2.condition = IR3_COND_NE;
1251
1252 /* condition always goes in predicate register: */
1253 cond->regs[0]->num = regid(REG_P0, 0);
1254
1255 kill = ir3_KILL(b, cond, 0);
1256
1257 ctx->kill[ctx->kill_count++] = kill;
1258 ctx->so->has_kill = true;
1259
1260 break;
1261 }
1262 default:
1263 compile_error(ctx, "Unhandled intrinsic type: %s\n",
1264 nir_intrinsic_infos[intr->intrinsic].name);
1265 break;
1266 }
1267 }
1268
1269 static void
1270 emit_load_const(struct ir3_compile *ctx, nir_load_const_instr *instr)
1271 {
1272 struct ir3_instruction **dst = get_dst_ssa(ctx, &instr->def,
1273 instr->def.num_components);
1274 for (int i = 0; i < instr->def.num_components; i++)
1275 dst[i] = create_immed(ctx->block, instr->value.u[i]);
1276 }
1277
1278 static void
1279 emit_undef(struct ir3_compile *ctx, nir_ssa_undef_instr *undef)
1280 {
1281 struct ir3_instruction **dst = get_dst_ssa(ctx, &undef->def,
1282 undef->def.num_components);
1283 /* backend doesn't want undefined instructions, so just plug
1284 * in 0.0..
1285 */
1286 for (int i = 0; i < undef->def.num_components; i++)
1287 dst[i] = create_immed(ctx->block, fui(0.0));
1288 }
1289
1290 /*
1291 * texture fetch/sample instructions:
1292 */
1293
1294 static void
1295 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1296 {
1297 unsigned coords, flags = 0;
1298
1299 /* note: would use tex->coord_components.. except txs.. also,
1300 * since array index goes after shadow ref, we don't want to
1301 * count it:
1302 */
1303 switch (tex->sampler_dim) {
1304 case GLSL_SAMPLER_DIM_1D:
1305 case GLSL_SAMPLER_DIM_BUF:
1306 coords = 1;
1307 break;
1308 case GLSL_SAMPLER_DIM_2D:
1309 case GLSL_SAMPLER_DIM_RECT:
1310 case GLSL_SAMPLER_DIM_EXTERNAL:
1311 case GLSL_SAMPLER_DIM_MS:
1312 coords = 2;
1313 break;
1314 case GLSL_SAMPLER_DIM_3D:
1315 case GLSL_SAMPLER_DIM_CUBE:
1316 coords = 3;
1317 flags |= IR3_INSTR_3D;
1318 break;
1319 }
1320
1321 if (tex->is_shadow)
1322 flags |= IR3_INSTR_S;
1323
1324 if (tex->is_array)
1325 flags |= IR3_INSTR_A;
1326
1327 *flagsp = flags;
1328 *coordsp = coords;
1329 }
1330
1331 static void
1332 emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex)
1333 {
1334 struct ir3_block *b = ctx->block;
1335 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1336 struct ir3_instruction **coord, *lod, *compare, *proj, **off, **ddx, **ddy;
1337 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1338 unsigned i, coords, flags;
1339 unsigned nsrc0 = 0, nsrc1 = 0;
1340 type_t type;
1341 opc_t opc;
1342
1343 /* TODO: might just be one component for gathers? */
1344 dst = get_dst(ctx, &tex->dest, 4);
1345
1346 for (unsigned i = 0; i < tex->num_srcs; i++) {
1347 switch (tex->src[i].src_type) {
1348 case nir_tex_src_coord:
1349 coord = get_src(ctx, &tex->src[i].src);
1350 break;
1351 case nir_tex_src_bias:
1352 lod = get_src(ctx, &tex->src[i].src)[0];
1353 has_bias = true;
1354 break;
1355 case nir_tex_src_lod:
1356 lod = get_src(ctx, &tex->src[i].src)[0];
1357 has_lod = true;
1358 break;
1359 case nir_tex_src_comparitor: /* shadow comparator */
1360 compare = get_src(ctx, &tex->src[i].src)[0];
1361 break;
1362 case nir_tex_src_projector:
1363 proj = get_src(ctx, &tex->src[i].src)[0];
1364 has_proj = true;
1365 break;
1366 case nir_tex_src_offset:
1367 off = get_src(ctx, &tex->src[i].src);
1368 has_off = true;
1369 break;
1370 case nir_tex_src_ddx:
1371 ddx = get_src(ctx, &tex->src[i].src);
1372 break;
1373 case nir_tex_src_ddy:
1374 ddy = get_src(ctx, &tex->src[i].src);
1375 break;
1376 default:
1377 compile_error(ctx, "Unhandled NIR tex serc type: %d\n",
1378 tex->src[i].src_type);
1379 return;
1380 }
1381 }
1382
1383 /*
1384 * lay out the first argument in the proper order:
1385 * - actual coordinates first
1386 * - shadow reference
1387 * - array index
1388 * - projection w
1389 * - starting at offset 4, dpdx.xy, dpdy.xy
1390 *
1391 * bias/lod go into the second arg
1392 */
1393
1394 tex_info(tex, &flags, &coords);
1395
1396 /* insert tex coords: */
1397 for (i = 0; i < coords; i++)
1398 src0[nsrc0++] = coord[i];
1399
1400 if (coords == 1) {
1401 /* hw doesn't do 1d, so we treat it as 2d with
1402 * height of 1, and patch up the y coord.
1403 * TODO: y coord should be (int)0 in some cases..
1404 */
1405 src0[nsrc0++] = create_immed(b, fui(0.5));
1406 }
1407
1408 if (tex->is_shadow)
1409 src0[nsrc0++] = compare;
1410
1411 if (tex->is_array)
1412 src0[nsrc0++] = coord[coords];
1413
1414 if (has_proj) {
1415 src0[nsrc0++] = proj;
1416 flags |= IR3_INSTR_P;
1417 }
1418
1419 /* pad to 4, then ddx/ddy: */
1420 if (tex->op == nir_texop_txd) {
1421 while (nsrc0 < 4)
1422 src0[nsrc0++] = create_immed(b, fui(0.0));
1423 for (i = 0; i < coords; i++)
1424 src0[nsrc0++] = ddx[i];
1425 if (coords < 2)
1426 src0[nsrc0++] = create_immed(b, fui(0.0));
1427 for (i = 0; i < coords; i++)
1428 src0[nsrc0++] = ddy[i];
1429 if (coords < 2)
1430 src0[nsrc0++] = create_immed(b, fui(0.0));
1431 }
1432
1433 /*
1434 * second argument (if applicable):
1435 * - offsets
1436 * - lod
1437 * - bias
1438 */
1439 if (has_off | has_lod | has_bias) {
1440 if (has_off) {
1441 for (i = 0; i < coords; i++)
1442 src1[nsrc1++] = off[i];
1443 if (coords < 2)
1444 src1[nsrc1++] = create_immed(b, fui(0.0));
1445 flags |= IR3_INSTR_O;
1446 }
1447
1448 if (has_lod | has_bias)
1449 src1[nsrc1++] = lod;
1450 }
1451
1452 switch (tex->op) {
1453 case nir_texop_tex: opc = OPC_SAM; break;
1454 case nir_texop_txb: opc = OPC_SAMB; break;
1455 case nir_texop_txl: opc = OPC_SAML; break;
1456 case nir_texop_txd: opc = OPC_SAMGQ; break;
1457 case nir_texop_txf: opc = OPC_ISAML; break;
1458 case nir_texop_txf_ms:
1459 case nir_texop_txs:
1460 case nir_texop_lod:
1461 case nir_texop_tg4:
1462 case nir_texop_query_levels:
1463 compile_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1464 return;
1465 }
1466
1467 switch (tex->dest_type) {
1468 case nir_type_invalid:
1469 case nir_type_float:
1470 type = TYPE_F32;
1471 break;
1472 case nir_type_int:
1473 type = TYPE_S32;
1474 break;
1475 case nir_type_unsigned:
1476 case nir_type_bool:
1477 type = TYPE_U32;
1478 break;
1479 }
1480
1481 sam = ir3_SAM(b, opc, type, TGSI_WRITEMASK_XYZW,
1482 flags, tex->sampler_index, tex->sampler_index,
1483 create_collect(b, src0, nsrc0),
1484 create_collect(b, src1, nsrc1));
1485
1486 split_dest(b, dst, sam);
1487 }
1488
1489 static void
1490 emit_tex_query_levels(struct ir3_compile *ctx, nir_tex_instr *tex)
1491 {
1492 struct ir3_block *b = ctx->block;
1493 struct ir3_instruction **dst, *sam;
1494
1495 dst = get_dst(ctx, &tex->dest, 1);
1496
1497 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, TGSI_WRITEMASK_Z, 0,
1498 tex->sampler_index, tex->sampler_index, NULL, NULL);
1499
1500 /* even though there is only one component, since it ends
1501 * up in .z rather than .x, we need a split_dest()
1502 */
1503 split_dest(b, dst, sam);
1504
1505 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1506 * the value in TEX_CONST_0 is zero-based.
1507 */
1508 if (ctx->levels_add_one)
1509 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1510 }
1511
1512 static void
1513 emit_tex_txs(struct ir3_compile *ctx, nir_tex_instr *tex)
1514 {
1515 struct ir3_block *b = ctx->block;
1516 struct ir3_instruction **dst, *sam, *lod;
1517 unsigned flags, coords;
1518
1519 tex_info(tex, &flags, &coords);
1520
1521 dst = get_dst(ctx, &tex->dest, 4);
1522
1523 compile_assert(ctx, tex->num_srcs == 1);
1524 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
1525
1526 lod = get_src(ctx, &tex->src[0].src)[0];
1527
1528 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, TGSI_WRITEMASK_XYZW, flags,
1529 tex->sampler_index, tex->sampler_index, lod, NULL);
1530
1531 split_dest(b, dst, sam);
1532
1533 /* Array size actually ends up in .w rather than .z. This doesn't
1534 * matter for miplevel 0, but for higher mips the value in z is
1535 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1536 * returned, which means that we have to add 1 to it for arrays.
1537 */
1538 if (tex->is_array) {
1539 if (ctx->levels_add_one) {
1540 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
1541 } else {
1542 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
1543 }
1544 }
1545 }
1546
1547 static void
1548 emit_instr(struct ir3_compile *ctx, nir_instr *instr)
1549 {
1550 switch (instr->type) {
1551 case nir_instr_type_alu:
1552 emit_alu(ctx, nir_instr_as_alu(instr));
1553 break;
1554 case nir_instr_type_intrinsic:
1555 emit_intrinisic(ctx, nir_instr_as_intrinsic(instr));
1556 break;
1557 case nir_instr_type_load_const:
1558 emit_load_const(ctx, nir_instr_as_load_const(instr));
1559 break;
1560 case nir_instr_type_ssa_undef:
1561 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1562 break;
1563 case nir_instr_type_tex: {
1564 nir_tex_instr *tex = nir_instr_as_tex(instr);
1565 /* couple tex instructions get special-cased:
1566 */
1567 switch (tex->op) {
1568 case nir_texop_txs:
1569 emit_tex_txs(ctx, tex);
1570 break;
1571 case nir_texop_query_levels:
1572 emit_tex_query_levels(ctx, tex);
1573 break;
1574 default:
1575 emit_tex(ctx, tex);
1576 break;
1577 }
1578 break;
1579 }
1580 case nir_instr_type_call:
1581 case nir_instr_type_jump:
1582 case nir_instr_type_phi:
1583 case nir_instr_type_parallel_copy:
1584 compile_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1585 break;
1586 }
1587 }
1588
1589 static void
1590 emit_block(struct ir3_compile *ctx, nir_block *block)
1591 {
1592 nir_foreach_instr(block, instr) {
1593 emit_instr(ctx, instr);
1594 if (ctx->error)
1595 return;
1596 }
1597 }
1598
1599 static void
1600 emit_function(struct ir3_compile *ctx, nir_function_impl *impl)
1601 {
1602 foreach_list_typed(nir_cf_node, node, node, &impl->body) {
1603 switch (node->type) {
1604 case nir_cf_node_block:
1605 emit_block(ctx, nir_cf_node_as_block(node));
1606 break;
1607 case nir_cf_node_if:
1608 case nir_cf_node_loop:
1609 case nir_cf_node_function:
1610 compile_error(ctx, "TODO\n");
1611 break;
1612 }
1613 if (ctx->error)
1614 return;
1615 }
1616 }
1617
1618 static void
1619 setup_input(struct ir3_compile *ctx, nir_variable *in)
1620 {
1621 struct ir3_shader_variant *so = ctx->so;
1622 unsigned array_len = MAX2(glsl_get_length(in->type), 1);
1623 unsigned ncomp = glsl_get_components(in->type);
1624 /* XXX: map loc slots to semantics */
1625 unsigned semantic_name = in->data.location;
1626 unsigned semantic_index = in->data.index;
1627 unsigned n = in->data.driver_location;
1628
1629 DBG("; in: %u:%u, len=%ux%u, loc=%u\n",
1630 semantic_name, semantic_index, array_len,
1631 ncomp, n);
1632
1633 so->inputs[n].semantic =
1634 ir3_semantic_name(semantic_name, semantic_index);
1635 so->inputs[n].compmask = (1 << ncomp) - 1;
1636 so->inputs[n].inloc = ctx->next_inloc;
1637 so->inputs[n].interpolate = 0;
1638 so->inputs_count = MAX2(so->inputs_count, n + 1);
1639
1640 /* the fdN_program_emit() code expects tgsi consts here, so map
1641 * things back to tgsi for now:
1642 */
1643 switch (in->data.interpolation) {
1644 case INTERP_QUALIFIER_FLAT:
1645 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1646 break;
1647 case INTERP_QUALIFIER_NOPERSPECTIVE:
1648 so->inputs[n].interpolate = TGSI_INTERPOLATE_LINEAR;
1649 break;
1650 case INTERP_QUALIFIER_SMOOTH:
1651 so->inputs[n].interpolate = TGSI_INTERPOLATE_PERSPECTIVE;
1652 break;
1653 }
1654
1655 for (int i = 0; i < ncomp; i++) {
1656 struct ir3_instruction *instr = NULL;
1657 unsigned idx = (n * 4) + i;
1658
1659 if (ctx->so->type == SHADER_FRAGMENT) {
1660 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1661 so->inputs[n].bary = false;
1662 so->frag_coord = true;
1663 instr = create_frag_coord(ctx, i);
1664 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1665 so->inputs[n].bary = false;
1666 so->frag_face = true;
1667 instr = create_frag_face(ctx, i);
1668 } else {
1669 bool use_ldlv = false;
1670
1671 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1672 * from the semantic name:
1673 */
1674 if ((in->data.interpolation == INTERP_QUALIFIER_NONE) &&
1675 ((semantic_name == TGSI_SEMANTIC_COLOR) ||
1676 (semantic_name == TGSI_SEMANTIC_BCOLOR)))
1677 so->inputs[n].interpolate = TGSI_INTERPOLATE_COLOR;
1678
1679 if (ctx->flat_bypass) {
1680 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1681 * from the semantic name:
1682 */
1683 switch (so->inputs[n].interpolate) {
1684 case TGSI_INTERPOLATE_COLOR:
1685 if (!ctx->so->key.rasterflat)
1686 break;
1687 /* fallthrough */
1688 case TGSI_INTERPOLATE_CONSTANT:
1689 use_ldlv = true;
1690 break;
1691 }
1692 }
1693
1694 so->inputs[n].bary = true;
1695
1696 instr = create_frag_input(ctx, idx, use_ldlv);
1697 }
1698 } else {
1699 instr = create_input(ctx->block, NULL, idx);
1700 }
1701
1702 ctx->block->inputs[idx] = instr;
1703 }
1704
1705 if (so->inputs[n].bary || (ctx->so->type == SHADER_VERTEX)) {
1706 ctx->next_inloc += ncomp;
1707 so->total_in += ncomp;
1708 }
1709 }
1710
1711 static void
1712 setup_output(struct ir3_compile *ctx, nir_variable *out)
1713 {
1714 struct ir3_shader_variant *so = ctx->so;
1715 unsigned array_len = MAX2(glsl_get_length(out->type), 1);
1716 unsigned ncomp = glsl_get_components(out->type);
1717 /* XXX: map loc slots to semantics */
1718 unsigned semantic_name = out->data.location;
1719 unsigned semantic_index = out->data.index;
1720 unsigned n = out->data.driver_location;
1721 unsigned comp = 0;
1722
1723 DBG("; out: %u:%u, len=%ux%u, loc=%u\n",
1724 semantic_name, semantic_index, array_len,
1725 ncomp, n);
1726
1727 if (ctx->so->type == SHADER_VERTEX) {
1728 switch (semantic_name) {
1729 case TGSI_SEMANTIC_POSITION:
1730 so->writes_pos = true;
1731 break;
1732 case TGSI_SEMANTIC_PSIZE:
1733 so->writes_psize = true;
1734 break;
1735 case TGSI_SEMANTIC_COLOR:
1736 case TGSI_SEMANTIC_BCOLOR:
1737 case TGSI_SEMANTIC_GENERIC:
1738 case TGSI_SEMANTIC_FOG:
1739 case TGSI_SEMANTIC_TEXCOORD:
1740 break;
1741 default:
1742 compile_error(ctx, "unknown VS semantic name: %s\n",
1743 tgsi_semantic_names[semantic_name]);
1744 }
1745 } else {
1746 switch (semantic_name) {
1747 case TGSI_SEMANTIC_POSITION:
1748 comp = 2; /* tgsi will write to .z component */
1749 so->writes_pos = true;
1750 break;
1751 case TGSI_SEMANTIC_COLOR:
1752 break;
1753 default:
1754 compile_error(ctx, "unknown FS semantic name: %s\n",
1755 tgsi_semantic_names[semantic_name]);
1756 }
1757 }
1758
1759 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
1760
1761 so->outputs[n].semantic =
1762 ir3_semantic_name(semantic_name, semantic_index);
1763 so->outputs[n].regid = regid(n, comp);
1764 so->outputs_count = MAX2(so->outputs_count, n + 1);
1765
1766 for (int i = 0; i < ncomp; i++) {
1767 unsigned idx = (n * 4) + i;
1768
1769 ctx->block->outputs[idx] = create_immed(ctx->block, fui(0.0));
1770 }
1771 }
1772
1773 static void
1774 emit_instructions(struct ir3_compile *ctx)
1775 {
1776 unsigned ninputs = exec_list_length(&ctx->s->inputs) * 4;
1777 unsigned noutputs = exec_list_length(&ctx->s->outputs) * 4;
1778
1779 /* we need to allocate big enough outputs array so that
1780 * we can stuff the kill's at the end:
1781 */
1782 if (ctx->so->type == SHADER_FRAGMENT)
1783 noutputs += ARRAY_SIZE(ctx->kill);
1784
1785 ctx->block = ir3_block_create(ctx->ir, 0, ninputs, noutputs);
1786
1787 if (ctx->so->type == SHADER_FRAGMENT)
1788 ctx->block->noutputs -= ARRAY_SIZE(ctx->kill);
1789
1790
1791 /* for fragment shader, we have a single input register (usually
1792 * r0.xy) which is used as the base for bary.f varying fetch instrs:
1793 */
1794 if (ctx->so->type == SHADER_FRAGMENT) {
1795 // TODO maybe a helper for fi since we need it a few places..
1796 struct ir3_instruction *instr;
1797 instr = ir3_instr_create(ctx->block, -1, OPC_META_FI);
1798 ir3_reg_create(instr, 0, 0);
1799 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.x */
1800 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.y */
1801 ctx->frag_pos = instr;
1802 }
1803
1804 /* Setup inputs: */
1805 foreach_list_typed(nir_variable, var, node, &ctx->s->inputs) {
1806 setup_input(ctx, var);
1807 }
1808
1809 /* Setup outputs: */
1810 foreach_list_typed(nir_variable, var, node, &ctx->s->outputs) {
1811 setup_output(ctx, var);
1812 }
1813
1814 /* Setup variables (which should only be arrays): */
1815 foreach_list_typed(nir_variable, var, node, &ctx->s->globals) {
1816 declare_var(ctx, var);
1817 }
1818
1819 /* Find the main function and emit the body: */
1820 nir_foreach_overload(ctx->s, overload) {
1821 compile_assert(ctx, strcmp(overload->function->name, "main") == 0);
1822 compile_assert(ctx, overload->impl);
1823 emit_function(ctx, overload->impl);
1824 if (ctx->error)
1825 return;
1826 }
1827 }
1828
1829 /* from NIR perspective, we actually have inputs. But most of the "inputs"
1830 * for a fragment shader are just bary.f instructions. The *actual* inputs
1831 * from the hw perspective are the frag_pos and optionally frag_coord and
1832 * frag_face.
1833 */
1834 static void
1835 fixup_frag_inputs(struct ir3_compile *ctx)
1836 {
1837 struct ir3_shader_variant *so = ctx->so;
1838 struct ir3_block *block = ctx->block;
1839 struct ir3_instruction **inputs;
1840 struct ir3_instruction *instr;
1841 int n, regid = 0;
1842
1843 block->ninputs = 0;
1844
1845 n = 4; /* always have frag_pos */
1846 n += COND(so->frag_face, 4);
1847 n += COND(so->frag_coord, 4);
1848
1849 inputs = ir3_alloc(ctx->ir, n * (sizeof(struct ir3_instruction *)));
1850
1851 if (so->frag_face) {
1852 /* this ultimately gets assigned to hr0.x so doesn't conflict
1853 * with frag_coord/frag_pos..
1854 */
1855 inputs[block->ninputs++] = ctx->frag_face;
1856 ctx->frag_face->regs[0]->num = 0;
1857
1858 /* remaining channels not used, but let's avoid confusing
1859 * other parts that expect inputs to come in groups of vec4
1860 */
1861 inputs[block->ninputs++] = NULL;
1862 inputs[block->ninputs++] = NULL;
1863 inputs[block->ninputs++] = NULL;
1864 }
1865
1866 /* since we don't know where to set the regid for frag_coord,
1867 * we have to use r0.x for it. But we don't want to *always*
1868 * use r1.x for frag_pos as that could increase the register
1869 * footprint on simple shaders:
1870 */
1871 if (so->frag_coord) {
1872 ctx->frag_coord[0]->regs[0]->num = regid++;
1873 ctx->frag_coord[1]->regs[0]->num = regid++;
1874 ctx->frag_coord[2]->regs[0]->num = regid++;
1875 ctx->frag_coord[3]->regs[0]->num = regid++;
1876
1877 inputs[block->ninputs++] = ctx->frag_coord[0];
1878 inputs[block->ninputs++] = ctx->frag_coord[1];
1879 inputs[block->ninputs++] = ctx->frag_coord[2];
1880 inputs[block->ninputs++] = ctx->frag_coord[3];
1881 }
1882
1883 /* we always have frag_pos: */
1884 so->pos_regid = regid;
1885
1886 /* r0.x */
1887 instr = create_input(block, NULL, block->ninputs);
1888 instr->regs[0]->num = regid++;
1889 inputs[block->ninputs++] = instr;
1890 ctx->frag_pos->regs[1]->instr = instr;
1891
1892 /* r0.y */
1893 instr = create_input(block, NULL, block->ninputs);
1894 instr->regs[0]->num = regid++;
1895 inputs[block->ninputs++] = instr;
1896 ctx->frag_pos->regs[2]->instr = instr;
1897
1898 block->inputs = inputs;
1899 }
1900
1901 static void
1902 compile_dump(struct ir3_compile *ctx)
1903 {
1904 const char *name = (ctx->so->type == SHADER_VERTEX) ? "vert" : "frag";
1905 static unsigned n = 0;
1906 char fname[16];
1907 FILE *f;
1908 snprintf(fname, sizeof(fname), "%s-%04u.dot", name, n++);
1909 f = fopen(fname, "w");
1910 if (!f)
1911 return;
1912 ir3_block_depth(ctx->block);
1913 ir3_dump(ctx->ir, name, ctx->block, f);
1914 fclose(f);
1915 }
1916
1917 int
1918 ir3_compile_shader_nir(struct ir3_shader_variant *so,
1919 const struct tgsi_token *tokens, struct ir3_shader_key key)
1920 {
1921 struct ir3_compile *ctx;
1922 struct ir3_block *block;
1923 struct ir3_instruction **inputs;
1924 unsigned i, j, actual_in;
1925 int ret = 0, max_bary;
1926
1927 assert(!so->ir);
1928
1929 so->ir = ir3_create();
1930
1931 assert(so->ir);
1932
1933 ctx = compile_init(so, tokens);
1934 if (!ctx) {
1935 DBG("INIT failed!");
1936 ret = -1;
1937 goto out;
1938 }
1939
1940 emit_instructions(ctx);
1941
1942 if (ctx->error) {
1943 DBG("EMIT failed!");
1944 ret = -1;
1945 goto out;
1946 }
1947
1948 block = ctx->block;
1949 so->ir->block = block;
1950
1951 /* keep track of the inputs from TGSI perspective.. */
1952 inputs = block->inputs;
1953
1954 /* but fixup actual inputs for frag shader: */
1955 if (so->type == SHADER_FRAGMENT)
1956 fixup_frag_inputs(ctx);
1957
1958 /* at this point, for binning pass, throw away unneeded outputs: */
1959 if (key.binning_pass) {
1960 for (i = 0, j = 0; i < so->outputs_count; i++) {
1961 unsigned name = sem2name(so->outputs[i].semantic);
1962 unsigned idx = sem2idx(so->outputs[i].semantic);
1963
1964 /* throw away everything but first position/psize */
1965 if ((idx == 0) && ((name == TGSI_SEMANTIC_POSITION) ||
1966 (name == TGSI_SEMANTIC_PSIZE))) {
1967 if (i != j) {
1968 so->outputs[j] = so->outputs[i];
1969 block->outputs[(j*4)+0] = block->outputs[(i*4)+0];
1970 block->outputs[(j*4)+1] = block->outputs[(i*4)+1];
1971 block->outputs[(j*4)+2] = block->outputs[(i*4)+2];
1972 block->outputs[(j*4)+3] = block->outputs[(i*4)+3];
1973 }
1974 j++;
1975 }
1976 }
1977 so->outputs_count = j;
1978 block->noutputs = j * 4;
1979 }
1980
1981 /* if we want half-precision outputs, mark the output registers
1982 * as half:
1983 */
1984 if (key.half_precision) {
1985 for (i = 0; i < block->noutputs; i++) {
1986 if (!block->outputs[i])
1987 continue;
1988 block->outputs[i]->regs[0]->flags |= IR3_REG_HALF;
1989 }
1990 }
1991
1992 /* at this point, we want the kill's in the outputs array too,
1993 * so that they get scheduled (since they have no dst).. we've
1994 * already ensured that the array is big enough in push_block():
1995 */
1996 if (so->type == SHADER_FRAGMENT) {
1997 for (i = 0; i < ctx->kill_count; i++)
1998 block->outputs[block->noutputs++] = ctx->kill[i];
1999 }
2000
2001 if (fd_mesa_debug & FD_DBG_OPTDUMP)
2002 compile_dump(ctx);
2003
2004 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2005 printf("BEFORE CP:\n");
2006 ir3_dump_instr_list(block->head);
2007 }
2008
2009 ir3_block_depth(block);
2010
2011 ir3_block_cp(block);
2012
2013 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2014 printf("BEFORE GROUPING:\n");
2015 ir3_dump_instr_list(block->head);
2016 }
2017
2018 /* Group left/right neighbors, inserting mov's where needed to
2019 * solve conflicts:
2020 */
2021 ir3_block_group(block);
2022
2023 if (fd_mesa_debug & FD_DBG_OPTDUMP)
2024 compile_dump(ctx);
2025
2026 ir3_block_depth(block);
2027
2028 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2029 printf("AFTER DEPTH:\n");
2030 ir3_dump_instr_list(block->head);
2031 }
2032
2033 ret = ir3_block_sched(block);
2034 if (ret) {
2035 DBG("SCHED failed!");
2036 goto out;
2037 }
2038
2039 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2040 printf("AFTER SCHED:\n");
2041 ir3_dump_instr_list(block->head);
2042 }
2043
2044 ret = ir3_block_ra(block, so->type, so->frag_coord, so->frag_face);
2045 if (ret) {
2046 DBG("RA failed!");
2047 goto out;
2048 }
2049
2050 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2051 printf("AFTER RA:\n");
2052 ir3_dump_instr_list(block->head);
2053 }
2054
2055 ir3_block_legalize(block, &so->has_samp, &max_bary);
2056
2057 /* fixup input/outputs: */
2058 for (i = 0; i < so->outputs_count; i++) {
2059 so->outputs[i].regid = block->outputs[i*4]->regs[0]->num;
2060 /* preserve hack for depth output.. tgsi writes depth to .z,
2061 * but what we give the hw is the scalar register:
2062 */
2063 if ((so->type == SHADER_FRAGMENT) &&
2064 (sem2name(so->outputs[i].semantic) == TGSI_SEMANTIC_POSITION))
2065 so->outputs[i].regid += 2;
2066 }
2067
2068 /* Note that some or all channels of an input may be unused: */
2069 actual_in = 0;
2070 for (i = 0; i < so->inputs_count; i++) {
2071 unsigned j, regid = ~0, compmask = 0;
2072 so->inputs[i].ncomp = 0;
2073 for (j = 0; j < 4; j++) {
2074 struct ir3_instruction *in = inputs[(i*4) + j];
2075 if (in) {
2076 compmask |= (1 << j);
2077 regid = in->regs[0]->num - j;
2078 actual_in++;
2079 so->inputs[i].ncomp++;
2080 }
2081 }
2082 so->inputs[i].regid = regid;
2083 so->inputs[i].compmask = compmask;
2084 }
2085
2086 /* fragment shader always gets full vec4's even if it doesn't
2087 * fetch all components, but vertex shader we need to update
2088 * with the actual number of components fetch, otherwise thing
2089 * will hang due to mismaptch between VFD_DECODE's and
2090 * TOTALATTRTOVS
2091 */
2092 if (so->type == SHADER_VERTEX)
2093 so->total_in = actual_in;
2094 else
2095 so->total_in = align(max_bary + 1, 4);
2096
2097 out:
2098 if (ret) {
2099 ir3_destroy(so->ir);
2100 so->ir = NULL;
2101 }
2102 compile_free(ctx);
2103
2104 return ret;
2105 }