1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
40 #include "freedreno_util.h"
42 #include "ir3_compiler.h"
43 #include "ir3_shader.h"
46 #include "instr-a3xx.h"
51 struct ir3_compiler
*compiler
;
53 const struct tgsi_token
*tokens
;
57 struct ir3_shader_variant
*so
;
59 struct ir3_block
*block
; /* the current block */
60 struct ir3_block
*in_block
; /* block created for shader inputs */
62 nir_function_impl
*impl
;
64 /* For fragment shaders, from the hw perspective the only
65 * actual input is r0.xy position register passed to bary.f.
66 * But TGSI doesn't know that, it still declares things as
67 * IN[] registers. So we do all the input tracking normally
68 * and fix things up after compile_instructions()
70 * NOTE that frag_pos is the hardware position (possibly it
71 * is actually an index or tag or some such.. it is *not*
72 * values that can be directly used for gl_FragCoord..)
74 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
76 /* For vertex shaders, keep track of the system values sources */
77 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
79 /* mapping from nir_register to defining instruction: */
80 struct hash_table
*def_ht
;
82 /* mapping from nir_variable to ir3_array: */
83 struct hash_table
*var_ht
;
86 /* a common pattern for indirect addressing is to request the
87 * same address register multiple times. To avoid generating
88 * duplicate instruction sequences (which our backend does not
89 * try to clean up, since that should be done as the NIR stage)
90 * we cache the address value generated for a given src value:
92 struct hash_table
*addr_ht
;
94 /* maps nir_block to ir3_block, mostly for the purposes of
95 * figuring out the blocks successors
97 struct hash_table
*block_ht
;
99 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
100 * so we need to use ldlv.u32 to load the varying directly:
104 /* on a3xx, we need to add one to # of array levels:
108 /* on a3xx, we need to scale up integer coords for isaml based
111 bool unminify_coords
;
113 /* for looking up which system value is which */
114 unsigned sysval_semantics
[8];
116 /* set if we encounter something we can't handle yet, so we
117 * can bail cleanly and fallback to TGSI compiler f/e
123 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
124 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
126 static struct nir_shader
*to_nir(struct ir3_compile
*ctx
,
127 const struct tgsi_token
*tokens
, struct ir3_shader_variant
*so
)
129 static const nir_shader_compiler_options options
= {
134 .lower_ffract
= true,
135 .native_integers
= true,
137 struct nir_lower_tex_options tex_options
= {
143 case SHADER_FRAGMENT
:
145 tex_options
.saturate_s
= so
->key
.fsaturate_s
;
146 tex_options
.saturate_t
= so
->key
.fsaturate_t
;
147 tex_options
.saturate_r
= so
->key
.fsaturate_r
;
150 tex_options
.saturate_s
= so
->key
.vsaturate_s
;
151 tex_options
.saturate_t
= so
->key
.vsaturate_t
;
152 tex_options
.saturate_r
= so
->key
.vsaturate_r
;
156 if (ctx
->compiler
->gpu_id
>= 400) {
157 /* a4xx seems to have *no* sam.p */
158 tex_options
.lower_txp
= ~0; /* lower all txp */
160 /* a3xx just needs to avoid sam.p for 3d tex */
161 tex_options
.lower_txp
= (1 << GLSL_SAMPLER_DIM_3D
);
164 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
166 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
167 debug_printf("----------------------\n");
168 nir_print_shader(s
, stdout
);
169 debug_printf("----------------------\n");
172 nir_opt_global_to_local(s
);
173 nir_convert_to_ssa(s
);
174 if (s
->stage
== MESA_SHADER_VERTEX
) {
175 nir_lower_clip_vs(s
, so
->key
.ucp_enables
);
176 } else if (s
->stage
== MESA_SHADER_FRAGMENT
) {
177 nir_lower_clip_fs(s
, so
->key
.ucp_enables
);
179 nir_lower_tex(s
, &tex_options
);
180 if (so
->key
.color_two_side
)
181 nir_lower_two_sided_color(s
);
183 nir_lower_load_const_to_scalar(s
);
188 nir_lower_vars_to_ssa(s
);
189 nir_lower_alu_to_scalar(s
);
190 nir_lower_phis_to_scalar(s
);
192 progress
|= nir_copy_prop(s
);
193 progress
|= nir_opt_dce(s
);
194 progress
|= nir_opt_cse(s
);
195 progress
|= ir3_nir_lower_if_else(s
);
196 progress
|= nir_opt_algebraic(s
);
197 progress
|= nir_opt_constant_folding(s
);
201 nir_remove_dead_variables(s
);
202 nir_validate_shader(s
);
204 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
205 debug_printf("----------------------\n");
206 nir_print_shader(s
, stdout
);
207 debug_printf("----------------------\n");
213 static struct ir3_compile
*
214 compile_init(struct ir3_compiler
*compiler
,
215 struct ir3_shader_variant
*so
,
216 const struct tgsi_token
*tokens
)
218 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
220 if (compiler
->gpu_id
>= 400) {
221 /* need special handling for "flat" */
222 ctx
->flat_bypass
= true;
223 ctx
->levels_add_one
= false;
224 ctx
->unminify_coords
= false;
226 /* no special handling for "flat" */
227 ctx
->flat_bypass
= false;
228 ctx
->levels_add_one
= true;
229 ctx
->unminify_coords
= true;
232 ctx
->compiler
= compiler
;
235 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
236 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
237 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
238 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
239 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
240 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
241 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
242 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
244 ctx
->s
= to_nir(ctx
, tokens
, so
);
246 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
248 /* Layout of constant registers:
250 * num_uniform * vec4 - user consts
251 * 4 * vec4 - UBO addresses
252 * if (vertex shader) {
253 * N * vec4 - driver params (IR3_DP_*)
254 * 1 * vec4 - stream-out addresses
257 * TODO this could be made more dynamic, to at least skip sections
258 * that we don't need..
261 /* reserve 4 (vec4) slots for ubo base addresses: */
262 so
->first_immediate
+= 4;
264 if (so
->type
== SHADER_VERTEX
) {
265 /* driver params (see ir3_driver_param): */
266 so
->first_immediate
+= IR3_DP_COUNT
/4; /* convert to vec4 */
267 /* one (vec4) slot for stream-output base addresses: */
268 so
->first_immediate
++;
275 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
278 va_start(ap
, format
);
279 _debug_vprintf(format
, ap
);
281 nir_print_shader(ctx
->s
, stdout
);
286 #define compile_assert(ctx, cond) do { \
287 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
291 compile_free(struct ir3_compile
*ctx
)
296 /* global per-array information: */
298 unsigned length
, aid
;
301 /* per-block array state: */
302 struct ir3_array_value
{
303 /* TODO drop length/aid, and just have ptr back to ir3_array */
304 unsigned length
, aid
;
305 /* initial array element values are phi's, other than for the
306 * entry block. The phi src's get added later in a resolve step
307 * after we have visited all the blocks, to account for back
310 struct ir3_instruction
**phis
;
311 /* current array element values (as block is processed). When
312 * the array phi's are resolved, it will contain the array state
313 * at exit of block, so successor blocks can use it to add their
316 struct ir3_instruction
*arr
[];
319 /* track array assignments per basic block. When an array is read
320 * outside of the same basic block, we can use NIR's dominance-frontier
321 * information to figure out where phi nodes are needed.
323 struct ir3_nir_block_data
{
325 /* indexed by array-id (aid): */
326 struct ir3_array_value
*arrs
[];
329 static struct ir3_nir_block_data
*
330 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
333 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
334 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
341 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
343 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
344 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
345 arr
->length
= length
;
346 arr
->aid
= ++ctx
->num_arrays
;
347 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
351 nir_block_pred(nir_block
*block
)
353 assert(block
->predecessors
->entries
< 2);
354 if (block
->predecessors
->entries
== 0)
356 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
359 static struct ir3_array_value
*
360 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
362 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
363 struct ir3_block
*block
= ctx
->block
;
364 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
365 struct ir3_array
*arr
= entry
->data
;
367 if (!bd
->arrs
[arr
->aid
]) {
368 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
369 (arr
->length
* sizeof(av
->arr
[0])));
370 struct ir3_array_value
*defn
= NULL
;
371 nir_block
*pred_block
;
373 av
->length
= arr
->length
;
376 /* For loops, we have to consider that we have not visited some
377 * of the blocks who should feed into the phi (ie. back-edges in
378 * the cfg).. for example:
381 * block { load_var; ... }
382 * if then block {} else block {}
383 * block { store_var; ... }
384 * if then block {} else block {}
388 * We can skip the phi if we can chase the block predecessors
389 * until finding the block previously defining the array without
390 * crossing a block that has more than one predecessor.
392 * Otherwise create phi's and resolve them as a post-pass after
393 * all the blocks have been visited (to handle back-edges).
396 for (pred_block
= block
->nblock
;
397 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
398 pred_block
= nir_block_pred(pred_block
)) {
399 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
400 struct ir3_nir_block_data
*pbd
= pblock
->bd
;
403 defn
= pbd
->arrs
[arr
->aid
];
407 /* only one possible definer: */
408 for (unsigned i
= 0; i
< arr
->length
; i
++)
409 av
->arr
[i
] = defn
->arr
[i
];
410 } else if (pred_block
) {
411 /* not the first block, and multiple potential definers: */
412 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
414 for (unsigned i
= 0; i
< arr
->length
; i
++) {
415 struct ir3_instruction
*phi
;
417 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
418 1 + ctx
->impl
->num_blocks
);
419 ir3_reg_create(phi
, 0, 0); /* dst */
421 /* phi's should go at head of block: */
422 list_delinit(&phi
->node
);
423 list_add(&phi
->node
, &block
->instr_list
);
425 av
->phis
[i
] = av
->arr
[i
] = phi
;
428 /* Some shaders end up reading array elements without
429 * first writing.. so initialize things to prevent null
432 for (unsigned i
= 0; i
< arr
->length
; i
++)
433 av
->arr
[i
] = create_immed(block
, 0);
436 bd
->arrs
[arr
->aid
] = av
;
439 return bd
->arrs
[arr
->aid
];
443 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
444 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
446 struct ir3_block
*block
;
447 struct ir3_nir_block_data
*bd
;
449 if (BITSET_TEST(visited
, nblock
->index
))
452 BITSET_SET(visited
, nblock
->index
);
454 block
= get_block(ctx
, nblock
);
457 if (bd
&& bd
->arrs
[av
->aid
]) {
458 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
459 for (unsigned i
= 0; i
< av
->length
; i
++) {
460 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
464 /* didn't find defn, recurse predecessors: */
465 struct set_entry
*entry
;
466 set_foreach(nblock
->predecessors
, entry
) {
467 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
473 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
475 struct ir3_nir_block_data
*bd
= block
->bd
;
476 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
481 /* TODO use nir dom_frontier to help us with this? */
483 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
484 struct ir3_array_value
*av
= bd
->arrs
[i
];
485 BITSET_WORD visited
[bitset_words
];
486 struct set_entry
*entry
;
488 if (!(av
&& av
->phis
))
491 memset(visited
, 0, sizeof(visited
));
492 set_foreach(block
->nblock
->predecessors
, entry
) {
493 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
498 /* allocate a n element value array (to be populated by caller) and
501 static struct ir3_instruction
**
502 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
504 struct ir3_instruction
**value
=
505 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
506 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
510 static struct ir3_instruction
**
511 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
514 return __get_dst(ctx
, &dst
->ssa
, n
);
516 return __get_dst(ctx
, dst
->reg
.reg
, n
);
520 static struct ir3_instruction
**
521 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
523 return __get_dst(ctx
, dst
, n
);
526 static struct ir3_instruction
**
527 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
529 struct hash_entry
*entry
;
531 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
533 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
535 compile_assert(ctx
, entry
);
539 static struct ir3_instruction
*
540 create_immed(struct ir3_block
*block
, uint32_t val
)
542 struct ir3_instruction
*mov
;
544 mov
= ir3_instr_create(block
, 1, 0);
545 mov
->cat1
.src_type
= TYPE_U32
;
546 mov
->cat1
.dst_type
= TYPE_U32
;
547 ir3_reg_create(mov
, 0, 0);
548 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
553 static struct ir3_instruction
*
554 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
556 struct ir3_instruction
*instr
, *immed
;
558 /* TODO in at least some cases, the backend could probably be
559 * made clever enough to propagate IR3_REG_HALF..
561 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
562 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
564 immed
= create_immed(block
, 2);
565 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
567 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
568 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
569 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
571 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
572 instr
->regs
[0]->num
= regid(REG_A0
, 0);
573 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
574 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
579 /* caches addr values to avoid generating multiple cov/shl/mova
580 * sequences for each use of a given NIR level src as address
582 static struct ir3_instruction
*
583 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
585 struct ir3_instruction
*addr
;
586 struct hash_entry
*entry
;
587 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
591 /* TODO do we need to cache per block? */
592 addr
= create_addr(ctx
->block
, src
);
593 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
598 static struct ir3_instruction
*
599 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
601 struct ir3_block
*b
= ctx
->block
;
602 struct ir3_instruction
*cond
;
604 /* NOTE: only cmps.*.* can write p0.x: */
605 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
606 cond
->cat2
.condition
= IR3_COND_NE
;
608 /* condition always goes in predicate register: */
609 cond
->regs
[0]->num
= regid(REG_P0
, 0);
614 static struct ir3_instruction
*
615 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
617 struct ir3_instruction
*mov
;
619 mov
= ir3_instr_create(ctx
->block
, 1, 0);
620 /* TODO get types right? */
621 mov
->cat1
.src_type
= TYPE_F32
;
622 mov
->cat1
.dst_type
= TYPE_F32
;
623 ir3_reg_create(mov
, 0, 0);
624 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
629 static struct ir3_instruction
*
630 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
631 struct ir3_instruction
*address
)
633 struct ir3_instruction
*mov
;
635 mov
= ir3_instr_create(ctx
->block
, 1, 0);
636 mov
->cat1
.src_type
= TYPE_U32
;
637 mov
->cat1
.dst_type
= TYPE_U32
;
638 ir3_reg_create(mov
, 0, 0);
639 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
641 ir3_instr_set_address(mov
, address
);
646 static struct ir3_instruction
*
647 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
650 struct ir3_instruction
*collect
;
655 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
656 ir3_reg_create(collect
, 0, 0); /* dst */
657 for (unsigned i
= 0; i
< arrsz
; i
++)
658 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
663 static struct ir3_instruction
*
664 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
665 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
667 struct ir3_block
*block
= ctx
->block
;
668 struct ir3_instruction
*mov
;
669 struct ir3_register
*src
;
671 mov
= ir3_instr_create(block
, 1, 0);
672 mov
->cat1
.src_type
= TYPE_U32
;
673 mov
->cat1
.dst_type
= TYPE_U32
;
674 ir3_reg_create(mov
, 0, 0);
675 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
676 src
->instr
= collect
;
680 ir3_instr_set_address(mov
, address
);
685 static struct ir3_instruction
*
686 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
687 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
688 struct ir3_instruction
*collect
)
690 struct ir3_block
*block
= ctx
->block
;
691 struct ir3_instruction
*mov
;
692 struct ir3_register
*dst
;
694 mov
= ir3_instr_create(block
, 1, 0);
695 mov
->cat1
.src_type
= TYPE_U32
;
696 mov
->cat1
.dst_type
= TYPE_U32
;
697 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
700 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
701 mov
->fanin
= collect
;
703 ir3_instr_set_address(mov
, address
);
708 static struct ir3_instruction
*
709 create_input(struct ir3_block
*block
, unsigned n
)
711 struct ir3_instruction
*in
;
713 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
714 in
->inout
.block
= block
;
715 ir3_reg_create(in
, n
, 0);
720 static struct ir3_instruction
*
721 create_frag_input(struct ir3_compile
*ctx
, bool use_ldlv
)
723 struct ir3_block
*block
= ctx
->block
;
724 struct ir3_instruction
*instr
;
725 /* actual inloc is assigned and fixed up later: */
726 struct ir3_instruction
*inloc
= create_immed(block
, 0);
729 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
730 instr
->cat6
.type
= TYPE_U32
;
731 instr
->cat6
.iim_val
= 1;
733 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
734 instr
->regs
[2]->wrmask
= 0x3;
740 static struct ir3_instruction
*
741 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
743 struct ir3_block
*block
= ctx
->block
;
744 struct ir3_instruction
*instr
;
746 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
748 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
753 /* for frag_coord, we get unsigned values.. we need
754 * to subtract (integer) 8 and divide by 16 (right-
755 * shift by 4) then convert to float:
759 * mov.u32f32 dst, tmp
762 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
763 create_immed(block
, 8), 0);
764 instr
= ir3_SHR_B(block
, instr
, 0,
765 create_immed(block
, 4), 0);
766 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
772 /* seems that we can use these as-is: */
773 return ctx
->frag_coord
[comp
];
777 static struct ir3_instruction
*
778 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
780 struct ir3_block
*block
= ctx
->block
;
781 struct ir3_instruction
*instr
;
785 compile_assert(ctx
, !ctx
->frag_face
);
787 ctx
->frag_face
= create_input(block
, 0);
788 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
790 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
791 * positive vs negative float.. and piglit further seems to
792 * expect -1.0 or 1.0:
794 * mul.s tmp, hr0.x, 2
796 * mov.s32f32, dst, tmp
799 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
800 create_immed(block
, 2), 0);
801 instr
= ir3_ADD_S(block
, instr
, 0,
802 create_immed(block
, 1), 0);
803 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
808 return create_immed(block
, fui(0.0));
811 return create_immed(block
, fui(1.0));
815 static struct ir3_instruction
*
816 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
818 /* first four vec4 sysval's reserved for UBOs: */
819 /* NOTE: dp is in scalar, but there can be >4 dp components: */
820 unsigned n
= ctx
->so
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
821 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
822 return create_uniform(ctx
, r
);
825 /* helper for instructions that produce multiple consecutive scalar
826 * outputs which need to have a split/fanout meta instruction inserted
829 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
830 struct ir3_instruction
*src
, unsigned n
)
832 struct ir3_instruction
*prev
= NULL
;
833 for (int i
= 0, j
= 0; i
< n
; i
++) {
834 struct ir3_instruction
*split
=
835 ir3_instr_create(block
, -1, OPC_META_FO
);
836 ir3_reg_create(split
, 0, IR3_REG_SSA
);
837 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
841 split
->cp
.left
= prev
;
842 split
->cp
.left_cnt
++;
843 prev
->cp
.right
= split
;
844 prev
->cp
.right_cnt
++;
848 if (src
->regs
[0]->wrmask
& (1 << i
))
854 * Adreno uses uint rather than having dedicated bool type,
855 * which (potentially) requires some conversion, in particular
856 * when using output of an bool instr to int input, or visa
860 * -------+---------+-------+-
864 * To convert from an adreno bool (uint) to nir, use:
866 * absneg.s dst, (neg)src
868 * To convert back in the other direction:
870 * absneg.s dst, (abs)arc
872 * The CP step can clean up the absneg.s that cancel each other
873 * out, and with a slight bit of extra cleverness (to recognize
874 * the instructions which produce either a 0 or 1) can eliminate
875 * the absneg.s's completely when an instruction that wants
876 * 0/1 consumes the result. For example, when a nir 'bcsel'
877 * consumes the result of 'feq'. So we should be able to get by
878 * without a boolean resolve step, and without incuring any
879 * extra penalty in instruction count.
882 /* NIR bool -> native (adreno): */
883 static struct ir3_instruction
*
884 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
886 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
889 /* native (adreno) -> NIR bool: */
890 static struct ir3_instruction
*
891 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
893 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
897 * alu/sfu instructions:
901 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
903 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
904 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
905 struct ir3_block
*b
= ctx
->block
;
907 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
909 /* Vectors are special in that they have non-scalarized writemasks,
910 * and just take the first swizzle channel for each argument in
911 * order into each writemask channel.
913 if ((alu
->op
== nir_op_vec2
) ||
914 (alu
->op
== nir_op_vec3
) ||
915 (alu
->op
== nir_op_vec4
)) {
917 for (int i
= 0; i
< info
->num_inputs
; i
++) {
918 nir_alu_src
*asrc
= &alu
->src
[i
];
920 compile_assert(ctx
, !asrc
->abs
);
921 compile_assert(ctx
, !asrc
->negate
);
923 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
925 src
[i
] = create_immed(ctx
->block
, 0);
926 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
932 /* General case: We can just grab the one used channel per src. */
933 for (int i
= 0; i
< info
->num_inputs
; i
++) {
934 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
935 nir_alu_src
*asrc
= &alu
->src
[i
];
937 compile_assert(ctx
, !asrc
->abs
);
938 compile_assert(ctx
, !asrc
->negate
);
940 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
942 compile_assert(ctx
, src
[i
]);
947 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
950 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
953 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
956 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
959 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
962 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
965 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
966 dst
[0]->cat2
.condition
= IR3_COND_NE
;
967 dst
[0] = ir3_n2b(b
, dst
[0]);
970 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
973 dst
[0] = ir3_b2n(b
, src
[0]);
976 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
977 dst
[0]->cat2
.condition
= IR3_COND_NE
;
978 dst
[0] = ir3_n2b(b
, dst
[0]);
982 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
985 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
988 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
991 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
994 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
997 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1000 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1003 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1006 dst
[0] = ir3_DSX(b
, src
[0], 0);
1007 dst
[0]->cat5
.type
= TYPE_F32
;
1010 dst
[0] = ir3_DSY(b
, src
[0], 0);
1011 dst
[0]->cat5
.type
= TYPE_F32
;
1015 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1016 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1017 dst
[0] = ir3_n2b(b
, dst
[0]);
1020 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1021 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1022 dst
[0] = ir3_n2b(b
, dst
[0]);
1025 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1026 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1027 dst
[0] = ir3_n2b(b
, dst
[0]);
1030 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1031 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1032 dst
[0] = ir3_n2b(b
, dst
[0]);
1035 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1038 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1041 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1043 case nir_op_fround_even
:
1044 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1047 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1051 dst
[0] = ir3_SIN(b
, src
[0], 0);
1054 dst
[0] = ir3_COS(b
, src
[0], 0);
1057 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1060 dst
[0] = ir3_RCP(b
, src
[0], 0);
1063 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1066 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1069 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1073 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1076 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1079 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1082 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1085 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1088 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1095 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1096 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1097 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1098 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1100 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1101 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1102 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1105 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1108 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1111 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1114 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1117 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1119 case nir_op_isign
: {
1120 /* maybe this would be sane to lower in nir.. */
1121 struct ir3_instruction
*neg
, *pos
;
1123 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1124 neg
->cat2
.condition
= IR3_COND_LT
;
1126 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1127 pos
->cat2
.condition
= IR3_COND_GT
;
1129 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1134 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1137 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1140 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1143 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1144 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1145 dst
[0] = ir3_n2b(b
, dst
[0]);
1148 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1149 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1150 dst
[0] = ir3_n2b(b
, dst
[0]);
1153 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1154 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1155 dst
[0] = ir3_n2b(b
, dst
[0]);
1158 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1159 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1160 dst
[0] = ir3_n2b(b
, dst
[0]);
1163 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1164 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1165 dst
[0] = ir3_n2b(b
, dst
[0]);
1168 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1169 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1170 dst
[0] = ir3_n2b(b
, dst
[0]);
1174 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1177 case nir_op_bit_count
:
1178 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1180 case nir_op_ifind_msb
: {
1181 struct ir3_instruction
*cmp
;
1182 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1183 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1184 cmp
->cat2
.condition
= IR3_COND_GE
;
1185 dst
[0] = ir3_SEL_B32(b
,
1186 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1190 case nir_op_ufind_msb
:
1191 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1192 dst
[0] = ir3_SEL_B32(b
,
1193 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1194 src
[0], 0, dst
[0], 0);
1196 case nir_op_find_lsb
:
1197 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1198 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1200 case nir_op_bitfield_reverse
:
1201 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1205 compile_error(ctx
, "Unhandled ALU op: %s\n",
1206 nir_op_infos
[alu
->op
].name
);
1211 /* handles direct/indirect UBO reads: */
1213 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1214 struct ir3_instruction
**dst
)
1216 struct ir3_block
*b
= ctx
->block
;
1217 struct ir3_instruction
*addr
, *src0
, *src1
;
1218 /* UBO addresses are the first driver params: */
1219 unsigned ubo
= regid(ctx
->so
->first_driver_param
+ IR3_UBOS_OFF
, 0);
1220 unsigned off
= intr
->const_index
[0];
1222 /* First src is ubo index, which could either be an immed or not: */
1223 src0
= get_src(ctx
, &intr
->src
[0])[0];
1224 if (is_same_type_mov(src0
) &&
1225 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1226 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1228 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1231 if (intr
->intrinsic
== nir_intrinsic_load_ubo_indirect
) {
1232 /* For load_ubo_indirect, second src is indirect offset: */
1233 src1
= get_src(ctx
, &intr
->src
[1])[0];
1235 /* and add offset to addr: */
1236 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1239 /* if offset is to large to encode in the ldg, split it out: */
1240 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1241 /* split out the minimal amount to improve the odds that
1242 * cp can fit the immediate in the add.s instruction:
1244 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1245 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1249 for (int i
= 0; i
< intr
->num_components
; i
++) {
1250 struct ir3_instruction
*load
=
1251 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1252 load
->cat6
.type
= TYPE_U32
;
1253 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1258 /* handles array reads: */
1260 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1261 struct ir3_instruction
**dst
)
1263 nir_deref_var
*dvar
= intr
->variables
[0];
1264 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1265 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1267 compile_assert(ctx
, dvar
->deref
.child
&&
1268 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1270 switch (darr
->deref_array_type
) {
1271 case nir_deref_array_type_direct
:
1272 /* direct access does not require anything special: */
1273 for (int i
= 0; i
< intr
->num_components
; i
++) {
1274 unsigned n
= darr
->base_offset
* 4 + i
;
1275 compile_assert(ctx
, n
< arr
->length
);
1276 dst
[i
] = arr
->arr
[n
];
1279 case nir_deref_array_type_indirect
: {
1280 /* for indirect, we need to collect all the array elements: */
1281 struct ir3_instruction
*collect
=
1282 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1283 struct ir3_instruction
*addr
=
1284 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1285 for (int i
= 0; i
< intr
->num_components
; i
++) {
1286 unsigned n
= darr
->base_offset
* 4 + i
;
1287 compile_assert(ctx
, n
< arr
->length
);
1288 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1293 compile_error(ctx
, "Unhandled load deref type: %u\n",
1294 darr
->deref_array_type
);
1299 /* handles array writes: */
1301 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1303 nir_deref_var
*dvar
= intr
->variables
[0];
1304 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1305 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1306 struct ir3_instruction
**src
;
1308 compile_assert(ctx
, dvar
->deref
.child
&&
1309 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1311 src
= get_src(ctx
, &intr
->src
[0]);
1313 switch (darr
->deref_array_type
) {
1314 case nir_deref_array_type_direct
:
1315 /* direct access does not require anything special: */
1316 for (int i
= 0; i
< intr
->num_components
; i
++) {
1317 unsigned n
= darr
->base_offset
* 4 + i
;
1318 compile_assert(ctx
, n
< arr
->length
);
1319 arr
->arr
[n
] = src
[i
];
1322 case nir_deref_array_type_indirect
: {
1323 /* for indirect, create indirect-store and fan that out: */
1324 struct ir3_instruction
*collect
=
1325 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1326 struct ir3_instruction
*addr
=
1327 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1328 for (int i
= 0; i
< intr
->num_components
; i
++) {
1329 struct ir3_instruction
*store
;
1330 unsigned n
= darr
->base_offset
* 4 + i
;
1331 compile_assert(ctx
, n
< arr
->length
);
1333 store
= create_indirect_store(ctx
, arr
->length
,
1334 n
, src
[i
], addr
, collect
);
1336 store
->fanin
->fi
.aid
= arr
->aid
;
1338 /* TODO: probably split this out to be used for
1339 * store_output_indirect? or move this into
1340 * create_indirect_store()?
1342 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1343 struct ir3_instruction
*split
;
1345 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1347 ir3_reg_create(split
, 0, 0);
1348 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1350 arr
->arr
[j
] = split
;
1353 /* fixup fanout/split neighbors: */
1354 for (int i
= 0; i
< arr
->length
; i
++) {
1355 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1356 arr
->arr
[i
+1] : NULL
;
1357 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1358 arr
->arr
[i
-1] : NULL
;
1363 compile_error(ctx
, "Unhandled store deref type: %u\n",
1364 darr
->deref_array_type
);
1369 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1370 struct ir3_instruction
*instr
)
1372 struct ir3_shader_variant
*so
= ctx
->so
;
1373 unsigned r
= regid(so
->inputs_count
, 0);
1374 unsigned n
= so
->inputs_count
++;
1376 so
->inputs
[n
].sysval
= true;
1377 so
->inputs
[n
].slot
= slot
;
1378 so
->inputs
[n
].compmask
= 1;
1379 so
->inputs
[n
].regid
= r
;
1380 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_FLAT
;
1383 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1384 ctx
->ir
->inputs
[r
] = instr
;
1388 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1390 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1391 struct ir3_instruction
**dst
, **src
;
1392 struct ir3_block
*b
= ctx
->block
;
1393 unsigned idx
= intr
->const_index
[0];
1395 if (info
->has_dest
) {
1396 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1401 switch (intr
->intrinsic
) {
1402 case nir_intrinsic_load_uniform
:
1403 for (int i
= 0; i
< intr
->num_components
; i
++) {
1404 unsigned n
= idx
* 4 + i
;
1405 dst
[i
] = create_uniform(ctx
, n
);
1408 case nir_intrinsic_load_uniform_indirect
:
1409 src
= get_src(ctx
, &intr
->src
[0]);
1410 for (int i
= 0; i
< intr
->num_components
; i
++) {
1411 unsigned n
= idx
* 4 + i
;
1412 dst
[i
] = create_uniform_indirect(ctx
, n
,
1413 get_addr(ctx
, src
[0]));
1415 /* NOTE: if relative addressing is used, we set constlen in
1416 * the compiler (to worst-case value) since we don't know in
1417 * the assembler what the max addr reg value can be:
1419 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1421 case nir_intrinsic_load_ubo
:
1422 case nir_intrinsic_load_ubo_indirect
:
1423 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1425 case nir_intrinsic_load_input
:
1426 for (int i
= 0; i
< intr
->num_components
; i
++) {
1427 unsigned n
= idx
* 4 + i
;
1428 dst
[i
] = ctx
->ir
->inputs
[n
];
1431 case nir_intrinsic_load_input_indirect
:
1432 src
= get_src(ctx
, &intr
->src
[0]);
1433 struct ir3_instruction
*collect
=
1434 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1435 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1436 for (int i
= 0; i
< intr
->num_components
; i
++) {
1437 unsigned n
= idx
* 4 + i
;
1438 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1442 case nir_intrinsic_load_var
:
1443 emit_intrinisic_load_var(ctx
, intr
, dst
);
1445 case nir_intrinsic_store_var
:
1446 emit_intrinisic_store_var(ctx
, intr
);
1448 case nir_intrinsic_store_output
:
1449 src
= get_src(ctx
, &intr
->src
[0]);
1450 for (int i
= 0; i
< intr
->num_components
; i
++) {
1451 unsigned n
= idx
* 4 + i
;
1452 ctx
->ir
->outputs
[n
] = src
[i
];
1455 case nir_intrinsic_load_base_vertex
:
1456 if (!ctx
->basevertex
) {
1457 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1458 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1461 dst
[0] = ctx
->basevertex
;
1463 case nir_intrinsic_load_vertex_id_zero_base
:
1464 if (!ctx
->vertex_id
) {
1465 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1466 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
1469 dst
[0] = ctx
->vertex_id
;
1471 case nir_intrinsic_load_instance_id
:
1472 if (!ctx
->instance_id
) {
1473 ctx
->instance_id
= create_input(ctx
->block
, 0);
1474 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1477 dst
[0] = ctx
->instance_id
;
1479 case nir_intrinsic_load_user_clip_plane
:
1480 for (int i
= 0; i
< intr
->num_components
; i
++) {
1481 unsigned n
= idx
* 4 + i
;
1482 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1485 case nir_intrinsic_discard_if
:
1486 case nir_intrinsic_discard
: {
1487 struct ir3_instruction
*cond
, *kill
;
1489 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1490 /* conditional discard: */
1491 src
= get_src(ctx
, &intr
->src
[0]);
1492 cond
= ir3_b2n(b
, src
[0]);
1494 /* unconditional discard: */
1495 cond
= create_immed(b
, 1);
1498 /* NOTE: only cmps.*.* can write p0.x: */
1499 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1500 cond
->cat2
.condition
= IR3_COND_NE
;
1502 /* condition always goes in predicate register: */
1503 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1505 kill
= ir3_KILL(b
, cond
, 0);
1506 array_insert(ctx
->ir
->predicates
, kill
);
1508 array_insert(ctx
->ir
->keeps
, kill
);
1509 ctx
->so
->has_kill
= true;
1514 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1515 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1521 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1523 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1524 instr
->def
.num_components
);
1525 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1526 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1530 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1532 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1533 undef
->def
.num_components
);
1534 /* backend doesn't want undefined instructions, so just plug
1537 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1538 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1542 * texture fetch/sample instructions:
1546 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1548 unsigned coords
, flags
= 0;
1550 /* note: would use tex->coord_components.. except txs.. also,
1551 * since array index goes after shadow ref, we don't want to
1554 switch (tex
->sampler_dim
) {
1555 case GLSL_SAMPLER_DIM_1D
:
1556 case GLSL_SAMPLER_DIM_BUF
:
1559 case GLSL_SAMPLER_DIM_2D
:
1560 case GLSL_SAMPLER_DIM_RECT
:
1561 case GLSL_SAMPLER_DIM_EXTERNAL
:
1562 case GLSL_SAMPLER_DIM_MS
:
1565 case GLSL_SAMPLER_DIM_3D
:
1566 case GLSL_SAMPLER_DIM_CUBE
:
1568 flags
|= IR3_INSTR_3D
;
1571 unreachable("bad sampler_dim");
1574 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1575 flags
|= IR3_INSTR_S
;
1577 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1578 flags
|= IR3_INSTR_A
;
1585 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1587 struct ir3_block
*b
= ctx
->block
;
1588 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1589 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1590 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1591 unsigned i
, coords
, flags
;
1592 unsigned nsrc0
= 0, nsrc1
= 0;
1596 coord
= off
= ddx
= ddy
= NULL
;
1597 lod
= proj
= compare
= NULL
;
1599 /* TODO: might just be one component for gathers? */
1600 dst
= get_dst(ctx
, &tex
->dest
, 4);
1602 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1603 switch (tex
->src
[i
].src_type
) {
1604 case nir_tex_src_coord
:
1605 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1607 case nir_tex_src_bias
:
1608 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1611 case nir_tex_src_lod
:
1612 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1615 case nir_tex_src_comparitor
: /* shadow comparator */
1616 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1618 case nir_tex_src_projector
:
1619 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1622 case nir_tex_src_offset
:
1623 off
= get_src(ctx
, &tex
->src
[i
].src
);
1626 case nir_tex_src_ddx
:
1627 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1629 case nir_tex_src_ddy
:
1630 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1633 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1634 tex
->src
[i
].src_type
);
1640 case nir_texop_tex
: opc
= OPC_SAM
; break;
1641 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1642 case nir_texop_txl
: opc
= OPC_SAML
; break;
1643 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1644 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1645 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1646 case nir_texop_txf_ms
:
1649 case nir_texop_query_levels
:
1650 case nir_texop_texture_samples
:
1651 case nir_texop_samples_identical
:
1652 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1656 tex_info(tex
, &flags
, &coords
);
1658 /* scale up integer coords for TXF based on the LOD */
1659 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1661 for (i
= 0; i
< coords
; i
++)
1662 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1665 /* the array coord for cube arrays needs 0.5 added to it */
1666 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& tex
->is_array
&&
1668 coord
[3] = ir3_ADD_F(b
, coord
[3], 0, create_immed(b
, fui(0.5)), 0);
1671 * lay out the first argument in the proper order:
1672 * - actual coordinates first
1673 * - shadow reference
1676 * - starting at offset 4, dpdx.xy, dpdy.xy
1678 * bias/lod go into the second arg
1681 /* insert tex coords: */
1682 for (i
= 0; i
< coords
; i
++)
1683 src0
[nsrc0
++] = coord
[i
];
1686 /* hw doesn't do 1d, so we treat it as 2d with
1687 * height of 1, and patch up the y coord.
1688 * TODO: y coord should be (int)0 in some cases..
1690 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1693 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1694 src0
[nsrc0
++] = compare
;
1696 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1697 src0
[nsrc0
++] = coord
[coords
];
1700 src0
[nsrc0
++] = proj
;
1701 flags
|= IR3_INSTR_P
;
1704 /* pad to 4, then ddx/ddy: */
1705 if (tex
->op
== nir_texop_txd
) {
1707 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1708 for (i
= 0; i
< coords
; i
++)
1709 src0
[nsrc0
++] = ddx
[i
];
1711 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1712 for (i
= 0; i
< coords
; i
++)
1713 src0
[nsrc0
++] = ddy
[i
];
1715 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1719 * second argument (if applicable):
1724 if (has_off
| has_lod
| has_bias
) {
1726 for (i
= 0; i
< coords
; i
++)
1727 src1
[nsrc1
++] = off
[i
];
1729 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1730 flags
|= IR3_INSTR_O
;
1733 if (has_lod
| has_bias
)
1734 src1
[nsrc1
++] = lod
;
1737 switch (tex
->dest_type
) {
1738 case nir_type_invalid
:
1739 case nir_type_float
:
1750 unreachable("bad dest_type");
1753 if (opc
== OPC_GETLOD
)
1756 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1757 flags
, tex
->sampler_index
, tex
->sampler_index
,
1758 create_collect(b
, src0
, nsrc0
),
1759 create_collect(b
, src1
, nsrc1
));
1761 split_dest(b
, dst
, sam
, 4);
1763 /* GETLOD returns results in 4.8 fixed point */
1764 if (opc
== OPC_GETLOD
) {
1765 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1767 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1768 for (i
= 0; i
< 2; i
++) {
1769 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1776 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1778 struct ir3_block
*b
= ctx
->block
;
1779 struct ir3_instruction
**dst
, *sam
;
1781 dst
= get_dst(ctx
, &tex
->dest
, 1);
1783 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1784 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1786 /* even though there is only one component, since it ends
1787 * up in .z rather than .x, we need a split_dest()
1789 split_dest(b
, dst
, sam
, 3);
1791 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1792 * the value in TEX_CONST_0 is zero-based.
1794 if (ctx
->levels_add_one
)
1795 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1799 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1801 struct ir3_block
*b
= ctx
->block
;
1802 struct ir3_instruction
**dst
, *sam
, *lod
;
1803 unsigned flags
, coords
;
1805 tex_info(tex
, &flags
, &coords
);
1807 /* Actually we want the number of dimensions, not coordinates. This
1808 * distinction only matters for cubes.
1810 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1813 dst
= get_dst(ctx
, &tex
->dest
, 4);
1815 compile_assert(ctx
, tex
->num_srcs
== 1);
1816 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1818 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1820 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1821 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1823 split_dest(b
, dst
, sam
, 4);
1825 /* Array size actually ends up in .w rather than .z. This doesn't
1826 * matter for miplevel 0, but for higher mips the value in z is
1827 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1828 * returned, which means that we have to add 1 to it for arrays.
1830 if (tex
->is_array
) {
1831 if (ctx
->levels_add_one
) {
1832 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1834 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1840 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1842 struct ir3_instruction
*phi
, **dst
;
1844 /* NOTE: phi's should be lowered to scalar at this point */
1845 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1847 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1849 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1850 1 + exec_list_length(&nphi
->srcs
));
1851 ir3_reg_create(phi
, 0, 0); /* dst */
1852 phi
->phi
.nphi
= nphi
;
1857 /* phi instructions are left partially constructed. We don't resolve
1858 * their srcs until the end of the block, since (eg. loops) one of
1859 * the phi's srcs might be defined after the phi due to back edges in
1863 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1865 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1866 nir_phi_instr
*nphi
;
1868 /* phi's only come at start of block: */
1869 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1872 if (!instr
->phi
.nphi
)
1875 nphi
= instr
->phi
.nphi
;
1876 instr
->phi
.nphi
= NULL
;
1878 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1879 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1880 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1884 resolve_array_phis(ctx
, block
);
1888 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1890 switch (jump
->type
) {
1891 case nir_jump_break
:
1892 case nir_jump_continue
:
1893 /* I *think* we can simply just ignore this, and use the
1894 * successor block link to figure out where we need to
1895 * jump to for break/continue
1899 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1905 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1907 switch (instr
->type
) {
1908 case nir_instr_type_alu
:
1909 emit_alu(ctx
, nir_instr_as_alu(instr
));
1911 case nir_instr_type_intrinsic
:
1912 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1914 case nir_instr_type_load_const
:
1915 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1917 case nir_instr_type_ssa_undef
:
1918 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1920 case nir_instr_type_tex
: {
1921 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1922 /* couple tex instructions get special-cased:
1926 emit_tex_txs(ctx
, tex
);
1928 case nir_texop_query_levels
:
1929 emit_tex_query_levels(ctx
, tex
);
1931 case nir_texop_samples_identical
:
1932 unreachable("nir_texop_samples_identical");
1939 case nir_instr_type_phi
:
1940 emit_phi(ctx
, nir_instr_as_phi(instr
));
1942 case nir_instr_type_jump
:
1943 emit_jump(ctx
, nir_instr_as_jump(instr
));
1945 case nir_instr_type_call
:
1946 case nir_instr_type_parallel_copy
:
1947 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1952 static struct ir3_block
*
1953 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1955 struct ir3_block
*block
;
1956 struct hash_entry
*entry
;
1957 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1961 block
= ir3_block_create(ctx
->ir
);
1962 block
->nblock
= nblock
;
1963 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1969 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1971 struct ir3_block
*block
= get_block(ctx
, nblock
);
1973 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1974 if (nblock
->successors
[i
]) {
1975 block
->successors
[i
] =
1976 get_block(ctx
, nblock
->successors
[i
]);
1981 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1983 nir_foreach_instr(nblock
, instr
) {
1984 emit_instr(ctx
, instr
);
1990 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1993 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1995 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1997 ctx
->block
->condition
=
1998 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2000 emit_cf_list(ctx
, &nif
->then_list
);
2001 emit_cf_list(ctx
, &nif
->else_list
);
2005 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
2007 emit_cf_list(ctx
, &nloop
->body
);
2011 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
2013 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2014 switch (node
->type
) {
2015 case nir_cf_node_block
:
2016 emit_block(ctx
, nir_cf_node_as_block(node
));
2018 case nir_cf_node_if
:
2019 emit_if(ctx
, nir_cf_node_as_if(node
));
2021 case nir_cf_node_loop
:
2022 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2024 case nir_cf_node_function
:
2025 compile_error(ctx
, "TODO\n");
2031 /* emit stream-out code. At this point, the current block is the original
2032 * (nir) end block, and nir ensures that all flow control paths terminate
2033 * into the end block. We re-purpose the original end block to generate
2034 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2035 * block holding stream-out write instructions, followed by the new end
2039 * p0.x = (vtxcnt < maxvtxcnt)
2040 * // succs: blockStreamOut, blockNewEnd
2043 * ... stream-out instructions ...
2044 * // succs: blockNewEnd
2050 emit_stream_out(struct ir3_compile
*ctx
)
2052 struct ir3_shader_variant
*v
= ctx
->so
;
2053 struct ir3
*ir
= ctx
->ir
;
2054 struct pipe_stream_output_info
*strmout
=
2055 &ctx
->so
->shader
->stream_output
;
2056 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2057 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2058 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2060 /* create vtxcnt input in input block at top of shader,
2061 * so that it is seen as live over the entire duration
2064 vtxcnt
= create_input(ctx
->in_block
, 0);
2065 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2067 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2069 /* at this point, we are at the original 'end' block,
2070 * re-purpose this block to stream-out condition, then
2071 * append stream-out block and new-end block
2073 orig_end_block
= ctx
->block
;
2075 stream_out_block
= ir3_block_create(ir
);
2076 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2078 new_end_block
= ir3_block_create(ir
);
2079 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2081 orig_end_block
->successors
[0] = stream_out_block
;
2082 orig_end_block
->successors
[1] = new_end_block
;
2083 stream_out_block
->successors
[0] = new_end_block
;
2085 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2086 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2087 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2088 cond
->cat2
.condition
= IR3_COND_LT
;
2090 /* condition goes on previous block to the conditional,
2091 * since it is used to pick which of the two successor
2094 orig_end_block
->condition
= cond
;
2096 /* switch to stream_out_block to generate the stream-out
2099 ctx
->block
= stream_out_block
;
2101 /* Calculate base addresses based on vtxcnt. Instructions
2102 * generated for bases not used in following loop will be
2103 * stripped out in the backend.
2105 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2106 unsigned stride
= strmout
->stride
[i
];
2107 struct ir3_instruction
*base
, *off
;
2109 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ IR3_TFBOS_OFF
, i
));
2111 /* 24-bit should be enough: */
2112 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2113 create_immed(ctx
->block
, stride
* 4), 0);
2115 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2118 /* Generate the per-output store instructions: */
2119 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2120 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2121 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2122 struct ir3_instruction
*base
, *out
, *stg
;
2124 base
= bases
[strmout
->output
[i
].output_buffer
];
2125 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2127 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2128 create_immed(ctx
->block
, 1), 0);
2129 stg
->cat6
.type
= TYPE_U32
;
2130 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2132 array_insert(ctx
->ir
->keeps
, stg
);
2136 /* and finally switch to the new_end_block: */
2137 ctx
->block
= new_end_block
;
2141 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2143 emit_cf_list(ctx
, &impl
->body
);
2144 emit_block(ctx
, impl
->end_block
);
2146 /* at this point, we should have a single empty block,
2147 * into which we emit the 'end' instruction.
2149 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2151 /* If stream-out (aka transform-feedback) enabled, emit the
2152 * stream-out instructions, followed by a new empty block (into
2153 * which the 'end' instruction lands).
2155 * NOTE: it is done in this order, rather than inserting before
2156 * we emit end_block, because NIR guarantees that all blocks
2157 * flow into end_block, and that end_block has no successors.
2158 * So by re-purposing end_block as the first block of stream-
2159 * out, we guarantee that all exit paths flow into the stream-
2162 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2163 !ctx
->so
->key
.binning_pass
) {
2164 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2165 emit_stream_out(ctx
);
2168 ir3_END(ctx
->block
);
2172 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2174 struct ir3_shader_variant
*so
= ctx
->so
;
2175 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2176 unsigned ncomp
= glsl_get_components(in
->type
);
2177 unsigned n
= in
->data
.driver_location
;
2178 unsigned slot
= in
->data
.location
;
2180 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2181 slot
, array_len
, ncomp
, n
);
2183 so
->inputs
[n
].slot
= slot
;
2184 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2185 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2186 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2188 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2189 for (int i
= 0; i
< ncomp
; i
++) {
2190 struct ir3_instruction
*instr
= NULL
;
2191 unsigned idx
= (n
* 4) + i
;
2193 if (slot
== VARYING_SLOT_POS
) {
2194 so
->inputs
[n
].bary
= false;
2195 so
->frag_coord
= true;
2196 instr
= create_frag_coord(ctx
, i
);
2197 } else if (slot
== VARYING_SLOT_FACE
) {
2198 so
->inputs
[n
].bary
= false;
2199 so
->frag_face
= true;
2200 instr
= create_frag_face(ctx
, i
);
2202 bool use_ldlv
= false;
2204 /* detect the special case for front/back colors where
2205 * we need to do flat vs smooth shading depending on
2208 if (in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) {
2210 case VARYING_SLOT_COL0
:
2211 case VARYING_SLOT_COL1
:
2212 case VARYING_SLOT_BFC0
:
2213 case VARYING_SLOT_BFC1
:
2214 so
->inputs
[n
].rasterflat
= true;
2221 if (ctx
->flat_bypass
) {
2222 if ((so
->inputs
[n
].interpolate
== INTERP_QUALIFIER_FLAT
) ||
2223 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2227 so
->inputs
[n
].bary
= true;
2229 instr
= create_frag_input(ctx
, use_ldlv
);
2232 ctx
->ir
->inputs
[idx
] = instr
;
2234 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2235 for (int i
= 0; i
< ncomp
; i
++) {
2236 unsigned idx
= (n
* 4) + i
;
2237 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2240 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2243 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2244 so
->total_in
+= ncomp
;
2249 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2251 struct ir3_shader_variant
*so
= ctx
->so
;
2252 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2253 unsigned ncomp
= glsl_get_components(out
->type
);
2254 unsigned n
= out
->data
.driver_location
;
2255 unsigned slot
= out
->data
.location
;
2258 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2259 slot
, array_len
, ncomp
, n
);
2261 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2263 case FRAG_RESULT_DEPTH
:
2264 comp
= 2; /* tgsi will write to .z component */
2265 so
->writes_pos
= true;
2267 case FRAG_RESULT_COLOR
:
2271 if (slot
>= FRAG_RESULT_DATA0
)
2273 compile_error(ctx
, "unknown FS output name: %s\n",
2274 gl_frag_result_name(slot
));
2276 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2278 case VARYING_SLOT_POS
:
2279 so
->writes_pos
= true;
2281 case VARYING_SLOT_PSIZ
:
2282 so
->writes_psize
= true;
2284 case VARYING_SLOT_COL0
:
2285 case VARYING_SLOT_COL1
:
2286 case VARYING_SLOT_BFC0
:
2287 case VARYING_SLOT_BFC1
:
2288 case VARYING_SLOT_FOGC
:
2289 case VARYING_SLOT_CLIP_DIST0
:
2290 case VARYING_SLOT_CLIP_DIST1
:
2293 if (slot
>= VARYING_SLOT_VAR0
)
2295 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2297 compile_error(ctx
, "unknown VS output name: %s\n",
2298 gl_varying_slot_name(slot
));
2301 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2304 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2306 so
->outputs
[n
].slot
= slot
;
2307 so
->outputs
[n
].regid
= regid(n
, comp
);
2308 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2310 for (int i
= 0; i
< ncomp
; i
++) {
2311 unsigned idx
= (n
* 4) + i
;
2313 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2318 emit_instructions(struct ir3_compile
*ctx
)
2320 unsigned ninputs
, noutputs
;
2321 nir_function_impl
*fxn
= NULL
;
2323 /* Find the main function: */
2324 nir_foreach_overload(ctx
->s
, overload
) {
2325 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
2326 compile_assert(ctx
, overload
->impl
);
2327 fxn
= overload
->impl
;
2331 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2332 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2334 /* or vtx shaders, we need to leave room for sysvals:
2336 if (ctx
->so
->type
== SHADER_VERTEX
) {
2340 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2342 /* Create inputs in first block: */
2343 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2344 ctx
->in_block
= ctx
->block
;
2345 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2347 if (ctx
->so
->type
== SHADER_VERTEX
) {
2348 ctx
->ir
->ninputs
-= 8;
2351 /* for fragment shader, we have a single input register (usually
2352 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2354 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2355 // TODO maybe a helper for fi since we need it a few places..
2356 struct ir3_instruction
*instr
;
2357 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2358 ir3_reg_create(instr
, 0, 0);
2359 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2360 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2361 ctx
->frag_pos
= instr
;
2365 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2366 setup_input(ctx
, var
);
2369 /* Setup outputs: */
2370 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2371 setup_output(ctx
, var
);
2374 /* Setup variables (which should only be arrays): */
2375 nir_foreach_variable(var
, &ctx
->s
->globals
) {
2376 declare_var(ctx
, var
);
2379 /* And emit the body: */
2381 emit_function(ctx
, fxn
);
2383 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2384 resolve_phis(ctx
, block
);
2388 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2389 * for a fragment shader are just bary.f instructions. The *actual* inputs
2390 * from the hw perspective are the frag_pos and optionally frag_coord and
2394 fixup_frag_inputs(struct ir3_compile
*ctx
)
2396 struct ir3_shader_variant
*so
= ctx
->so
;
2397 struct ir3
*ir
= ctx
->ir
;
2398 struct ir3_instruction
**inputs
;
2399 struct ir3_instruction
*instr
;
2404 n
= 4; /* always have frag_pos */
2405 n
+= COND(so
->frag_face
, 4);
2406 n
+= COND(so
->frag_coord
, 4);
2408 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2410 if (so
->frag_face
) {
2411 /* this ultimately gets assigned to hr0.x so doesn't conflict
2412 * with frag_coord/frag_pos..
2414 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2415 ctx
->frag_face
->regs
[0]->num
= 0;
2417 /* remaining channels not used, but let's avoid confusing
2418 * other parts that expect inputs to come in groups of vec4
2420 inputs
[ir
->ninputs
++] = NULL
;
2421 inputs
[ir
->ninputs
++] = NULL
;
2422 inputs
[ir
->ninputs
++] = NULL
;
2425 /* since we don't know where to set the regid for frag_coord,
2426 * we have to use r0.x for it. But we don't want to *always*
2427 * use r1.x for frag_pos as that could increase the register
2428 * footprint on simple shaders:
2430 if (so
->frag_coord
) {
2431 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2432 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2433 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2434 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2436 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2437 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2438 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2439 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2442 /* we always have frag_pos: */
2443 so
->pos_regid
= regid
;
2446 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2447 instr
->regs
[0]->num
= regid
++;
2448 inputs
[ir
->ninputs
++] = instr
;
2449 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2452 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2453 instr
->regs
[0]->num
= regid
++;
2454 inputs
[ir
->ninputs
++] = instr
;
2455 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2457 ir
->inputs
= inputs
;
2461 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2462 struct ir3_shader_variant
*so
)
2464 struct ir3_compile
*ctx
;
2466 struct ir3_instruction
**inputs
;
2467 unsigned i
, j
, actual_in
, inloc
;
2468 int ret
= 0, max_bary
;
2472 ctx
= compile_init(compiler
, so
, so
->shader
->tokens
);
2474 DBG("INIT failed!");
2479 emit_instructions(ctx
);
2482 DBG("EMIT failed!");
2487 ir
= so
->ir
= ctx
->ir
;
2489 /* keep track of the inputs from TGSI perspective.. */
2490 inputs
= ir
->inputs
;
2492 /* but fixup actual inputs for frag shader: */
2493 if (so
->type
== SHADER_FRAGMENT
)
2494 fixup_frag_inputs(ctx
);
2496 /* at this point, for binning pass, throw away unneeded outputs: */
2497 if (so
->key
.binning_pass
) {
2498 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2499 unsigned slot
= so
->outputs
[i
].slot
;
2501 /* throw away everything but first position/psize */
2502 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2504 so
->outputs
[j
] = so
->outputs
[i
];
2505 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2506 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2507 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2508 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2513 so
->outputs_count
= j
;
2514 ir
->noutputs
= j
* 4;
2517 /* if we want half-precision outputs, mark the output registers
2520 if (so
->key
.half_precision
) {
2521 for (i
= 0; i
< ir
->noutputs
; i
++) {
2522 struct ir3_instruction
*out
= ir
->outputs
[i
];
2525 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2526 /* output could be a fanout (ie. texture fetch output)
2527 * in which case we need to propagate the half-reg flag
2528 * up to the definer so that RA sees it:
2530 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2531 out
= out
->regs
[1]->instr
;
2532 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2535 if (out
->category
== 1) {
2536 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2541 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2542 printf("BEFORE CP:\n");
2548 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2549 printf("BEFORE GROUPING:\n");
2553 /* Group left/right neighbors, inserting mov's where needed to
2560 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2561 printf("AFTER DEPTH:\n");
2565 ret
= ir3_sched(ir
);
2567 DBG("SCHED failed!");
2571 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2572 printf("AFTER SCHED:\n");
2576 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2582 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2583 printf("AFTER RA:\n");
2587 /* fixup input/outputs: */
2588 for (i
= 0; i
< so
->outputs_count
; i
++) {
2589 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2590 /* preserve hack for depth output.. tgsi writes depth to .z,
2591 * but what we give the hw is the scalar register:
2593 if ((so
->type
== SHADER_FRAGMENT
) &&
2594 (so
->outputs
[i
].slot
== FRAG_RESULT_DEPTH
))
2595 so
->outputs
[i
].regid
+= 2;
2598 /* Note that some or all channels of an input may be unused: */
2601 for (i
= 0; i
< so
->inputs_count
; i
++) {
2602 unsigned j
, regid
= ~0, compmask
= 0;
2603 so
->inputs
[i
].ncomp
= 0;
2604 so
->inputs
[i
].inloc
= inloc
+ 8;
2605 for (j
= 0; j
< 4; j
++) {
2606 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2607 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2608 compmask
|= (1 << j
);
2609 regid
= in
->regs
[0]->num
- j
;
2611 so
->inputs
[i
].ncomp
++;
2612 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2614 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2615 in
->regs
[1]->iim_val
= inloc
++;
2619 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
)
2621 so
->inputs
[i
].regid
= regid
;
2622 so
->inputs
[i
].compmask
= compmask
;
2625 /* We need to do legalize after (for frag shader's) the "bary.f"
2626 * offsets (inloc) have been assigned.
2628 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2630 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2631 printf("AFTER LEGALIZE:\n");
2635 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2636 if (so
->type
== SHADER_VERTEX
)
2637 so
->total_in
= actual_in
;
2639 so
->total_in
= max_bary
+ 1;
2644 ir3_destroy(so
->ir
);