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freedreno/ir3: silence warnings
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_compiler_nir.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include <stdarg.h>
30
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
37
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
40
41 #include "freedreno_util.h"
42
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
45 #include "ir3_nir.h"
46
47 #include "instr-a3xx.h"
48 #include "ir3.h"
49
50
51 static struct ir3_instruction * create_immed(struct ir3_block *block, uint32_t val);
52
53 struct ir3_compile {
54 const struct tgsi_token *tokens;
55 struct nir_shader *s;
56
57 struct ir3 *ir;
58 struct ir3_shader_variant *so;
59
60 /* bitmask of which samplers are integer: */
61 uint16_t integer_s;
62
63 struct ir3_block *block;
64
65 /* For fragment shaders, from the hw perspective the only
66 * actual input is r0.xy position register passed to bary.f.
67 * But TGSI doesn't know that, it still declares things as
68 * IN[] registers. So we do all the input tracking normally
69 * and fix things up after compile_instructions()
70 *
71 * NOTE that frag_pos is the hardware position (possibly it
72 * is actually an index or tag or some such.. it is *not*
73 * values that can be directly used for gl_FragCoord..)
74 */
75 struct ir3_instruction *frag_pos, *frag_face, *frag_coord[4];
76
77 /* For vertex shaders, keep track of the system values sources */
78 struct ir3_instruction *vertex_id, *basevertex, *instance_id;
79
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table *def_ht;
82
83 /* mapping from nir_variable to ir3_array: */
84 struct hash_table *var_ht;
85 unsigned num_arrays;
86
87 /* a common pattern for indirect addressing is to request the
88 * same address register multiple times. To avoid generating
89 * duplicate instruction sequences (which our backend does not
90 * try to clean up, since that should be done as the NIR stage)
91 * we cache the address value generated for a given src value:
92 */
93 struct hash_table *addr_ht;
94
95 /* for calculating input/output positions/linkages: */
96 unsigned next_inloc;
97
98 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
99 * so we need to use ldlv.u32 to load the varying directly:
100 */
101 bool flat_bypass;
102
103 /* on a3xx, we need to add one to # of array levels:
104 */
105 bool levels_add_one;
106
107 /* for looking up which system value is which */
108 unsigned sysval_semantics[8];
109
110 /* list of kill instructions: */
111 struct ir3_instruction *kill[16];
112 unsigned int kill_count;
113
114 /* set if we encounter something we can't handle yet, so we
115 * can bail cleanly and fallback to TGSI compiler f/e
116 */
117 bool error;
118 };
119
120
121 static struct nir_shader *to_nir(const struct tgsi_token *tokens)
122 {
123 struct nir_shader_compiler_options options = {
124 .lower_fpow = true,
125 .lower_fsat = true,
126 .lower_scmp = true,
127 .lower_flrp = true,
128 .native_integers = true,
129 };
130 bool progress;
131
132 struct nir_shader *s = tgsi_to_nir(tokens, &options);
133
134 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
135 debug_printf("----------------------\n");
136 nir_print_shader(s, stdout);
137 debug_printf("----------------------\n");
138 }
139
140 nir_opt_global_to_local(s);
141 nir_convert_to_ssa(s);
142 nir_lower_idiv(s);
143
144 do {
145 progress = false;
146
147 nir_lower_vars_to_ssa(s);
148 nir_lower_alu_to_scalar(s);
149
150 progress |= nir_copy_prop(s);
151 progress |= nir_opt_dce(s);
152 progress |= nir_opt_cse(s);
153 progress |= ir3_nir_lower_if_else(s);
154 progress |= nir_opt_algebraic(s);
155 progress |= nir_opt_constant_folding(s);
156
157 } while (progress);
158
159 nir_remove_dead_variables(s);
160 nir_validate_shader(s);
161
162 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
163 debug_printf("----------------------\n");
164 nir_print_shader(s, stdout);
165 debug_printf("----------------------\n");
166 }
167
168 return s;
169 }
170
171 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
172 static const struct tgsi_token *
173 lower_tgsi(const struct tgsi_token *tokens, struct ir3_shader_variant *so)
174 {
175 struct tgsi_shader_info info;
176 struct tgsi_lowering_config lconfig = {
177 .color_two_side = so->key.color_two_side,
178 .lower_FRC = true,
179 };
180
181 switch (so->type) {
182 case SHADER_FRAGMENT:
183 case SHADER_COMPUTE:
184 lconfig.saturate_s = so->key.fsaturate_s;
185 lconfig.saturate_t = so->key.fsaturate_t;
186 lconfig.saturate_r = so->key.fsaturate_r;
187 break;
188 case SHADER_VERTEX:
189 lconfig.saturate_s = so->key.vsaturate_s;
190 lconfig.saturate_t = so->key.vsaturate_t;
191 lconfig.saturate_r = so->key.vsaturate_r;
192 break;
193 }
194
195 if (!so->shader) {
196 /* hack for standalone compiler which does not have
197 * screen/context:
198 */
199 } else if (ir3_shader_gpuid(so->shader) >= 400) {
200 /* a4xx seems to have *no* sam.p */
201 lconfig.lower_TXP = ~0; /* lower all txp */
202 } else {
203 /* a3xx just needs to avoid sam.p for 3d tex */
204 lconfig.lower_TXP = (1 << TGSI_TEXTURE_3D);
205 }
206
207 return tgsi_transform_lowering(&lconfig, tokens, &info);
208 }
209
210 static struct ir3_compile *
211 compile_init(struct ir3_shader_variant *so,
212 const struct tgsi_token *tokens)
213 {
214 struct ir3_compile *ctx = rzalloc(NULL, struct ir3_compile);
215 const struct tgsi_token *lowered_tokens;
216
217 if (!so->shader) {
218 /* hack for standalone compiler which does not have
219 * screen/context:
220 */
221 } else if (ir3_shader_gpuid(so->shader) >= 400) {
222 /* need special handling for "flat" */
223 ctx->flat_bypass = true;
224 ctx->levels_add_one = false;
225 } else {
226 /* no special handling for "flat" */
227 ctx->flat_bypass = false;
228 ctx->levels_add_one = true;
229 }
230
231 switch (so->type) {
232 case SHADER_FRAGMENT:
233 case SHADER_COMPUTE:
234 ctx->integer_s = so->key.finteger_s;
235 break;
236 case SHADER_VERTEX:
237 ctx->integer_s = so->key.vinteger_s;
238 break;
239 }
240
241 ctx->ir = so->ir;
242 ctx->so = so;
243 ctx->next_inloc = 8;
244 ctx->def_ht = _mesa_hash_table_create(ctx,
245 _mesa_hash_pointer, _mesa_key_pointer_equal);
246 ctx->var_ht = _mesa_hash_table_create(ctx,
247 _mesa_hash_pointer, _mesa_key_pointer_equal);
248 ctx->addr_ht = _mesa_hash_table_create(ctx,
249 _mesa_hash_pointer, _mesa_key_pointer_equal);
250
251 lowered_tokens = lower_tgsi(tokens, so);
252 if (!lowered_tokens)
253 lowered_tokens = tokens;
254 ctx->s = to_nir(lowered_tokens);
255
256 if (lowered_tokens != tokens)
257 free((void *)lowered_tokens);
258
259 so->first_driver_param = so->first_immediate = ctx->s->num_uniforms;
260
261 /* one (vec4) slot for vertex id base: */
262 if (so->type == SHADER_VERTEX)
263 so->first_immediate++;
264
265 /* reserve 4 (vec4) slots for ubo base addresses: */
266 so->first_immediate += 4;
267
268 return ctx;
269 }
270
271 static void
272 compile_error(struct ir3_compile *ctx, const char *format, ...)
273 {
274 va_list ap;
275 va_start(ap, format);
276 _debug_vprintf(format, ap);
277 va_end(ap);
278 nir_print_shader(ctx->s, stdout);
279 ctx->error = true;
280 debug_assert(0);
281 }
282
283 #define compile_assert(ctx, cond) do { \
284 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
285 } while (0)
286
287 static void
288 compile_free(struct ir3_compile *ctx)
289 {
290 ralloc_free(ctx);
291 }
292
293
294 struct ir3_array {
295 unsigned length, aid;
296 struct ir3_instruction *arr[];
297 };
298
299 static void
300 declare_var(struct ir3_compile *ctx, nir_variable *var)
301 {
302 unsigned length = glsl_get_length(var->type) * 4; /* always vec4, at least with ttn */
303 struct ir3_array *arr = ralloc_size(ctx, sizeof(*arr) +
304 (length * sizeof(arr->arr[0])));
305 arr->length = length;
306 arr->aid = ++ctx->num_arrays;
307 /* Some shaders end up reading array elements without first writing..
308 * so initialize things to prevent null instr ptrs later:
309 */
310 for (unsigned i = 0; i < length; i++)
311 arr->arr[i] = create_immed(ctx->block, 0);
312 _mesa_hash_table_insert(ctx->var_ht, var, arr);
313 }
314
315 static struct ir3_array *
316 get_var(struct ir3_compile *ctx, nir_variable *var)
317 {
318 struct hash_entry *entry = _mesa_hash_table_search(ctx->var_ht, var);
319 return entry->data;
320 }
321
322 /* allocate a n element value array (to be populated by caller) and
323 * insert in def_ht
324 */
325 static struct ir3_instruction **
326 __get_dst(struct ir3_compile *ctx, void *key, unsigned n)
327 {
328 struct ir3_instruction **value =
329 ralloc_array(ctx->def_ht, struct ir3_instruction *, n);
330 _mesa_hash_table_insert(ctx->def_ht, key, value);
331 return value;
332 }
333
334 static struct ir3_instruction **
335 get_dst(struct ir3_compile *ctx, nir_dest *dst, unsigned n)
336 {
337 if (dst->is_ssa) {
338 return __get_dst(ctx, &dst->ssa, n);
339 } else {
340 return __get_dst(ctx, dst->reg.reg, n);
341 }
342 }
343
344 static struct ir3_instruction **
345 get_dst_ssa(struct ir3_compile *ctx, nir_ssa_def *dst, unsigned n)
346 {
347 return __get_dst(ctx, dst, n);
348 }
349
350 static struct ir3_instruction **
351 get_src(struct ir3_compile *ctx, nir_src *src)
352 {
353 struct hash_entry *entry;
354 if (src->is_ssa) {
355 entry = _mesa_hash_table_search(ctx->def_ht, src->ssa);
356 } else {
357 entry = _mesa_hash_table_search(ctx->def_ht, src->reg.reg);
358 }
359 compile_assert(ctx, entry);
360 return entry->data;
361 }
362
363 static struct ir3_instruction *
364 create_immed(struct ir3_block *block, uint32_t val)
365 {
366 struct ir3_instruction *mov;
367
368 mov = ir3_instr_create(block, 1, 0);
369 mov->cat1.src_type = TYPE_U32;
370 mov->cat1.dst_type = TYPE_U32;
371 ir3_reg_create(mov, 0, 0);
372 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
373
374 return mov;
375 }
376
377 static struct ir3_instruction *
378 create_addr(struct ir3_block *block, struct ir3_instruction *src)
379 {
380 struct ir3_instruction *instr, *immed;
381
382 /* TODO in at least some cases, the backend could probably be
383 * made clever enough to propagate IR3_REG_HALF..
384 */
385 instr = ir3_COV(block, src, TYPE_U32, TYPE_S16);
386 instr->regs[0]->flags |= IR3_REG_HALF;
387
388 immed = create_immed(block, 2);
389 immed->regs[0]->flags |= IR3_REG_HALF;
390
391 instr = ir3_SHL_B(block, instr, 0, immed, 0);
392 instr->regs[0]->flags |= IR3_REG_HALF;
393 instr->regs[1]->flags |= IR3_REG_HALF;
394
395 instr = ir3_MOV(block, instr, TYPE_S16);
396 instr->regs[0]->flags |= IR3_REG_ADDR | IR3_REG_HALF;
397 instr->regs[1]->flags |= IR3_REG_HALF;
398
399 return instr;
400 }
401
402 /* caches addr values to avoid generating multiple cov/shl/mova
403 * sequences for each use of a given NIR level src as address
404 */
405 static struct ir3_instruction *
406 get_addr(struct ir3_compile *ctx, struct ir3_instruction *src)
407 {
408 struct ir3_instruction *addr;
409 struct hash_entry *entry;
410 entry = _mesa_hash_table_search(ctx->addr_ht, src);
411 if (entry)
412 return entry->data;
413
414 /* TODO do we need to cache per block? */
415 addr = create_addr(ctx->block, src);
416 _mesa_hash_table_insert(ctx->addr_ht, src, addr);
417
418 return addr;
419 }
420
421 static struct ir3_instruction *
422 create_uniform(struct ir3_compile *ctx, unsigned n)
423 {
424 struct ir3_instruction *mov;
425
426 mov = ir3_instr_create(ctx->block, 1, 0);
427 /* TODO get types right? */
428 mov->cat1.src_type = TYPE_F32;
429 mov->cat1.dst_type = TYPE_F32;
430 ir3_reg_create(mov, 0, 0);
431 ir3_reg_create(mov, n, IR3_REG_CONST);
432
433 return mov;
434 }
435
436 static struct ir3_instruction *
437 create_uniform_indirect(struct ir3_compile *ctx, unsigned n,
438 struct ir3_instruction *address)
439 {
440 struct ir3_instruction *mov;
441
442 mov = ir3_instr_create(ctx->block, 1, 0);
443 mov->cat1.src_type = TYPE_U32;
444 mov->cat1.dst_type = TYPE_U32;
445 ir3_reg_create(mov, 0, 0);
446 ir3_reg_create(mov, n, IR3_REG_CONST | IR3_REG_RELATIV);
447 mov->address = address;
448
449 array_insert(ctx->ir->indirects, mov);
450
451 return mov;
452 }
453
454 static struct ir3_instruction *
455 create_collect(struct ir3_block *block, struct ir3_instruction **arr,
456 unsigned arrsz)
457 {
458 struct ir3_instruction *collect;
459
460 if (arrsz == 0)
461 return NULL;
462
463 collect = ir3_instr_create2(block, -1, OPC_META_FI, 1 + arrsz);
464 ir3_reg_create(collect, 0, 0);
465 for (unsigned i = 0; i < arrsz; i++)
466 ir3_reg_create(collect, 0, IR3_REG_SSA)->instr = arr[i];
467
468 return collect;
469 }
470
471 static struct ir3_instruction *
472 create_indirect_load(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
473 struct ir3_instruction *address, struct ir3_instruction *collect)
474 {
475 struct ir3_block *block = ctx->block;
476 struct ir3_instruction *mov;
477 struct ir3_register *src;
478
479 mov = ir3_instr_create(block, 1, 0);
480 mov->cat1.src_type = TYPE_U32;
481 mov->cat1.dst_type = TYPE_U32;
482 ir3_reg_create(mov, 0, 0);
483 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
484 src->instr = collect;
485 src->size = arrsz;
486 src->offset = n;
487 mov->address = address;
488
489 array_insert(ctx->ir->indirects, mov);
490
491 return mov;
492 }
493
494 static struct ir3_instruction *
495 create_indirect_store(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
496 struct ir3_instruction *src, struct ir3_instruction *address,
497 struct ir3_instruction *collect)
498 {
499 struct ir3_block *block = ctx->block;
500 struct ir3_instruction *mov;
501 struct ir3_register *dst;
502
503 mov = ir3_instr_create(block, 1, 0);
504 mov->cat1.src_type = TYPE_U32;
505 mov->cat1.dst_type = TYPE_U32;
506 dst = ir3_reg_create(mov, 0, IR3_REG_RELATIV);
507 dst->size = arrsz;
508 dst->offset = n;
509 ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src;
510 mov->address = address;
511 mov->fanin = collect;
512
513 array_insert(ctx->ir->indirects, mov);
514
515 return mov;
516 }
517
518 static struct ir3_instruction *
519 create_input(struct ir3_block *block, struct ir3_instruction *instr,
520 unsigned n)
521 {
522 struct ir3_instruction *in;
523
524 in = ir3_instr_create(block, -1, OPC_META_INPUT);
525 in->inout.block = block;
526 ir3_reg_create(in, n, 0);
527 if (instr)
528 ir3_reg_create(in, 0, IR3_REG_SSA)->instr = instr;
529
530 return in;
531 }
532
533 static struct ir3_instruction *
534 create_frag_input(struct ir3_compile *ctx, unsigned n, bool use_ldlv)
535 {
536 struct ir3_block *block = ctx->block;
537 struct ir3_instruction *instr;
538 struct ir3_instruction *inloc = create_immed(block, n);
539
540 if (use_ldlv) {
541 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
542 instr->cat6.type = TYPE_U32;
543 instr->cat6.iim_val = 1;
544 } else {
545 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_pos, 0);
546 instr->regs[2]->wrmask = 0x3;
547 }
548
549 return instr;
550 }
551
552 static struct ir3_instruction *
553 create_frag_coord(struct ir3_compile *ctx, unsigned comp)
554 {
555 struct ir3_block *block = ctx->block;
556 struct ir3_instruction *instr;
557
558 compile_assert(ctx, !ctx->frag_coord[comp]);
559
560 ctx->frag_coord[comp] = create_input(ctx->block, NULL, 0);
561
562 switch (comp) {
563 case 0: /* .x */
564 case 1: /* .y */
565 /* for frag_coord, we get unsigned values.. we need
566 * to subtract (integer) 8 and divide by 16 (right-
567 * shift by 4) then convert to float:
568 *
569 * sub.s tmp, src, 8
570 * shr.b tmp, tmp, 4
571 * mov.u32f32 dst, tmp
572 *
573 */
574 instr = ir3_SUB_S(block, ctx->frag_coord[comp], 0,
575 create_immed(block, 8), 0);
576 instr = ir3_SHR_B(block, instr, 0,
577 create_immed(block, 4), 0);
578 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
579
580 return instr;
581 case 2: /* .z */
582 case 3: /* .w */
583 default:
584 /* seems that we can use these as-is: */
585 return ctx->frag_coord[comp];
586 }
587 }
588
589 static struct ir3_instruction *
590 create_frag_face(struct ir3_compile *ctx, unsigned comp)
591 {
592 struct ir3_block *block = ctx->block;
593 struct ir3_instruction *instr;
594
595 switch (comp) {
596 case 0: /* .x */
597 compile_assert(ctx, !ctx->frag_face);
598
599 ctx->frag_face = create_input(block, NULL, 0);
600
601 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
602 * positive vs negative float.. and piglit further seems to
603 * expect -1.0 or 1.0:
604 *
605 * mul.s tmp, hr0.x, 2
606 * add.s tmp, tmp, 1
607 * mov.s32f32, dst, tmp
608 *
609 */
610 instr = ir3_MUL_S(block, ctx->frag_face, 0,
611 create_immed(block, 2), 0);
612 instr = ir3_ADD_S(block, instr, 0,
613 create_immed(block, 1), 0);
614 instr = ir3_COV(block, instr, TYPE_S32, TYPE_F32);
615
616 return instr;
617 case 1: /* .y */
618 case 2: /* .z */
619 return create_immed(block, fui(0.0));
620 default:
621 case 3: /* .w */
622 return create_immed(block, fui(1.0));
623 }
624 }
625
626 /* helper for instructions that produce multiple consecutive scalar
627 * outputs which need to have a split/fanout meta instruction inserted
628 */
629 static void
630 split_dest(struct ir3_block *block, struct ir3_instruction **dst,
631 struct ir3_instruction *src)
632 {
633 struct ir3_instruction *prev = NULL;
634 for (int i = 0, j = 0; i < 4; i++) {
635 struct ir3_instruction *split =
636 ir3_instr_create(block, -1, OPC_META_FO);
637 ir3_reg_create(split, 0, IR3_REG_SSA);
638 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = src;
639 split->fo.off = i;
640
641 if (prev) {
642 split->cp.left = prev;
643 split->cp.left_cnt++;
644 prev->cp.right = split;
645 prev->cp.right_cnt++;
646 }
647 prev = split;
648
649 if (src->regs[0]->wrmask & (1 << i))
650 dst[j++] = split;
651 }
652 }
653
654 /*
655 * Adreno uses uint rather than having dedicated bool type,
656 * which (potentially) requires some conversion, in particular
657 * when using output of an bool instr to int input, or visa
658 * versa.
659 *
660 * | Adreno | NIR |
661 * -------+---------+-------+-
662 * true | 1 | ~0 |
663 * false | 0 | 0 |
664 *
665 * To convert from an adreno bool (uint) to nir, use:
666 *
667 * absneg.s dst, (neg)src
668 *
669 * To convert back in the other direction:
670 *
671 * absneg.s dst, (abs)arc
672 *
673 * The CP step can clean up the absneg.s that cancel each other
674 * out, and with a slight bit of extra cleverness (to recognize
675 * the instructions which produce either a 0 or 1) can eliminate
676 * the absneg.s's completely when an instruction that wants
677 * 0/1 consumes the result. For example, when a nir 'bcsel'
678 * consumes the result of 'feq'. So we should be able to get by
679 * without a boolean resolve step, and without incuring any
680 * extra penalty in instruction count.
681 */
682
683 /* NIR bool -> native (adreno): */
684 static struct ir3_instruction *
685 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
686 {
687 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
688 }
689
690 /* native (adreno) -> NIR bool: */
691 static struct ir3_instruction *
692 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
693 {
694 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
695 }
696
697 /*
698 * alu/sfu instructions:
699 */
700
701 static void
702 emit_alu(struct ir3_compile *ctx, nir_alu_instr *alu)
703 {
704 const nir_op_info *info = &nir_op_infos[alu->op];
705 struct ir3_instruction **dst, *src[info->num_inputs];
706 struct ir3_block *b = ctx->block;
707
708 dst = get_dst(ctx, &alu->dest.dest, MAX2(info->output_size, 1));
709
710 /* Vectors are special in that they have non-scalarized writemasks,
711 * and just take the first swizzle channel for each argument in
712 * order into each writemask channel.
713 */
714 if ((alu->op == nir_op_vec2) ||
715 (alu->op == nir_op_vec3) ||
716 (alu->op == nir_op_vec4)) {
717
718 for (int i = 0; i < info->num_inputs; i++) {
719 nir_alu_src *asrc = &alu->src[i];
720
721 compile_assert(ctx, !asrc->abs);
722 compile_assert(ctx, !asrc->negate);
723
724 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[0]];
725 if (!src[i])
726 src[i] = create_immed(ctx->block, 0);
727 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
728 }
729
730 return;
731 }
732
733 /* General case: We can just grab the one used channel per src. */
734 for (int i = 0; i < info->num_inputs; i++) {
735 unsigned chan = ffs(alu->dest.write_mask) - 1;
736 nir_alu_src *asrc = &alu->src[i];
737
738 compile_assert(ctx, !asrc->abs);
739 compile_assert(ctx, !asrc->negate);
740
741 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
742
743 compile_assert(ctx, src[i]);
744 }
745
746 switch (alu->op) {
747 case nir_op_f2i:
748 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_S32);
749 break;
750 case nir_op_f2u:
751 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_U32);
752 break;
753 case nir_op_i2f:
754 dst[0] = ir3_COV(b, src[0], TYPE_S32, TYPE_F32);
755 break;
756 case nir_op_u2f:
757 dst[0] = ir3_COV(b, src[0], TYPE_U32, TYPE_F32);
758 break;
759 case nir_op_imov:
760 dst[0] = ir3_MOV(b, src[0], TYPE_S32);
761 break;
762 case nir_op_fmov:
763 dst[0] = ir3_MOV(b, src[0], TYPE_F32);
764 break;
765 case nir_op_f2b:
766 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
767 dst[0]->cat2.condition = IR3_COND_NE;
768 dst[0] = ir3_n2b(b, dst[0]);
769 break;
770 case nir_op_b2f:
771 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
772 break;
773 case nir_op_b2i:
774 dst[0] = ir3_b2n(b, src[0]);
775 break;
776 case nir_op_i2b:
777 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
778 dst[0]->cat2.condition = IR3_COND_NE;
779 dst[0] = ir3_n2b(b, dst[0]);
780 break;
781
782 case nir_op_fneg:
783 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
784 break;
785 case nir_op_fabs:
786 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
787 break;
788 case nir_op_fmax:
789 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
790 break;
791 case nir_op_fmin:
792 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
793 break;
794 case nir_op_fmul:
795 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
796 break;
797 case nir_op_fadd:
798 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
799 break;
800 case nir_op_fsub:
801 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
802 break;
803 case nir_op_ffma:
804 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
805 break;
806 case nir_op_fddx:
807 dst[0] = ir3_DSX(b, src[0], 0);
808 dst[0]->cat5.type = TYPE_F32;
809 break;
810 case nir_op_fddy:
811 dst[0] = ir3_DSY(b, src[0], 0);
812 dst[0]->cat5.type = TYPE_F32;
813 break;
814 break;
815 case nir_op_flt:
816 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
817 dst[0]->cat2.condition = IR3_COND_LT;
818 dst[0] = ir3_n2b(b, dst[0]);
819 break;
820 case nir_op_fge:
821 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
822 dst[0]->cat2.condition = IR3_COND_GE;
823 dst[0] = ir3_n2b(b, dst[0]);
824 break;
825 case nir_op_feq:
826 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
827 dst[0]->cat2.condition = IR3_COND_EQ;
828 dst[0] = ir3_n2b(b, dst[0]);
829 break;
830 case nir_op_fne:
831 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
832 dst[0]->cat2.condition = IR3_COND_NE;
833 dst[0] = ir3_n2b(b, dst[0]);
834 break;
835 case nir_op_fceil:
836 dst[0] = ir3_CEIL_F(b, src[0], 0);
837 break;
838 case nir_op_ffloor:
839 dst[0] = ir3_FLOOR_F(b, src[0], 0);
840 break;
841 case nir_op_ftrunc:
842 dst[0] = ir3_TRUNC_F(b, src[0], 0);
843 break;
844 case nir_op_fround_even:
845 dst[0] = ir3_RNDNE_F(b, src[0], 0);
846 break;
847 case nir_op_fsign:
848 dst[0] = ir3_SIGN_F(b, src[0], 0);
849 break;
850
851 case nir_op_fsin:
852 dst[0] = ir3_SIN(b, src[0], 0);
853 break;
854 case nir_op_fcos:
855 dst[0] = ir3_COS(b, src[0], 0);
856 break;
857 case nir_op_frsq:
858 dst[0] = ir3_RSQ(b, src[0], 0);
859 break;
860 case nir_op_frcp:
861 dst[0] = ir3_RCP(b, src[0], 0);
862 break;
863 case nir_op_flog2:
864 dst[0] = ir3_LOG2(b, src[0], 0);
865 break;
866 case nir_op_fexp2:
867 dst[0] = ir3_EXP2(b, src[0], 0);
868 break;
869 case nir_op_fsqrt:
870 dst[0] = ir3_SQRT(b, src[0], 0);
871 break;
872
873 case nir_op_iabs:
874 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
875 break;
876 case nir_op_iadd:
877 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
878 break;
879 case nir_op_iand:
880 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
881 break;
882 case nir_op_imax:
883 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
884 break;
885 case nir_op_imin:
886 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
887 break;
888 case nir_op_imul:
889 /*
890 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
891 * mull.u tmp0, a, b ; mul low, i.e. al * bl
892 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
893 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
894 */
895 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
896 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
897 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
898 break;
899 case nir_op_ineg:
900 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
901 break;
902 case nir_op_inot:
903 dst[0] = ir3_NOT_B(b, src[0], 0);
904 break;
905 case nir_op_ior:
906 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
907 break;
908 case nir_op_ishl:
909 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
910 break;
911 case nir_op_ishr:
912 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
913 break;
914 case nir_op_isign: {
915 /* maybe this would be sane to lower in nir.. */
916 struct ir3_instruction *neg, *pos;
917
918 neg = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
919 neg->cat2.condition = IR3_COND_LT;
920
921 pos = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
922 pos->cat2.condition = IR3_COND_GT;
923
924 dst[0] = ir3_SUB_U(b, pos, 0, neg, 0);
925
926 break;
927 }
928 case nir_op_isub:
929 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
930 break;
931 case nir_op_ixor:
932 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
933 break;
934 case nir_op_ushr:
935 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
936 break;
937 case nir_op_ilt:
938 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
939 dst[0]->cat2.condition = IR3_COND_LT;
940 dst[0] = ir3_n2b(b, dst[0]);
941 break;
942 case nir_op_ige:
943 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
944 dst[0]->cat2.condition = IR3_COND_GE;
945 dst[0] = ir3_n2b(b, dst[0]);
946 break;
947 case nir_op_ieq:
948 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
949 dst[0]->cat2.condition = IR3_COND_EQ;
950 dst[0] = ir3_n2b(b, dst[0]);
951 break;
952 case nir_op_ine:
953 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
954 dst[0]->cat2.condition = IR3_COND_NE;
955 dst[0] = ir3_n2b(b, dst[0]);
956 break;
957 case nir_op_ult:
958 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
959 dst[0]->cat2.condition = IR3_COND_LT;
960 dst[0] = ir3_n2b(b, dst[0]);
961 break;
962 case nir_op_uge:
963 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
964 dst[0]->cat2.condition = IR3_COND_GE;
965 dst[0] = ir3_n2b(b, dst[0]);
966 break;
967
968 case nir_op_bcsel:
969 dst[0] = ir3_SEL_B32(b, src[1], 0, ir3_b2n(b, src[0]), 0, src[2], 0);
970 break;
971
972 default:
973 compile_error(ctx, "Unhandled ALU op: %s\n",
974 nir_op_infos[alu->op].name);
975 break;
976 }
977 }
978
979 /* handles direct/indirect UBO reads: */
980 static void
981 emit_intrinsic_load_ubo(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
982 struct ir3_instruction **dst)
983 {
984 struct ir3_block *b = ctx->block;
985 struct ir3_instruction *addr, *src0, *src1;
986 /* UBO addresses are the first driver params: */
987 unsigned ubo = regid(ctx->so->first_driver_param, 0);
988 unsigned off = intr->const_index[0];
989
990 /* First src is ubo index, which could either be an immed or not: */
991 src0 = get_src(ctx, &intr->src[0])[0];
992 if (is_same_type_mov(src0) &&
993 (src0->regs[1]->flags & IR3_REG_IMMED)) {
994 addr = create_uniform(ctx, ubo + src0->regs[1]->iim_val);
995 } else {
996 addr = create_uniform_indirect(ctx, ubo, get_addr(ctx, src0));
997 }
998
999 if (intr->intrinsic == nir_intrinsic_load_ubo_indirect) {
1000 /* For load_ubo_indirect, second src is indirect offset: */
1001 src1 = get_src(ctx, &intr->src[1])[0];
1002
1003 /* and add offset to addr: */
1004 addr = ir3_ADD_S(b, addr, 0, src1, 0);
1005 }
1006
1007 /* if offset is to large to encode in the ldg, split it out: */
1008 if ((off + (intr->num_components * 4)) > 1024) {
1009 /* split out the minimal amount to improve the odds that
1010 * cp can fit the immediate in the add.s instruction:
1011 */
1012 unsigned off2 = off + (intr->num_components * 4) - 1024;
1013 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
1014 off -= off2;
1015 }
1016
1017 for (int i = 0; i < intr->num_components; i++) {
1018 struct ir3_instruction *load =
1019 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
1020 load->cat6.type = TYPE_U32;
1021 load->cat6.offset = off + i * 4; /* byte offset */
1022 dst[i] = load;
1023 }
1024 }
1025
1026 /* handles array reads: */
1027 static void
1028 emit_intrinisic_load_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
1029 struct ir3_instruction **dst)
1030 {
1031 nir_deref_var *dvar = intr->variables[0];
1032 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
1033 struct ir3_array *arr = get_var(ctx, dvar->var);
1034
1035 compile_assert(ctx, dvar->deref.child &&
1036 (dvar->deref.child->deref_type == nir_deref_type_array));
1037
1038 switch (darr->deref_array_type) {
1039 case nir_deref_array_type_direct:
1040 /* direct access does not require anything special: */
1041 for (int i = 0; i < intr->num_components; i++) {
1042 unsigned n = darr->base_offset * 4 + i;
1043 compile_assert(ctx, n < arr->length);
1044 dst[i] = arr->arr[n];
1045 }
1046 break;
1047 case nir_deref_array_type_indirect: {
1048 /* for indirect, we need to collect all the array elements: */
1049 struct ir3_instruction *collect =
1050 create_collect(ctx->block, arr->arr, arr->length);
1051 struct ir3_instruction *addr =
1052 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1053 for (int i = 0; i < intr->num_components; i++) {
1054 unsigned n = darr->base_offset * 4 + i;
1055 compile_assert(ctx, n < arr->length);
1056 dst[i] = create_indirect_load(ctx, arr->length, n, addr, collect);
1057 }
1058 break;
1059 }
1060 default:
1061 compile_error(ctx, "Unhandled load deref type: %u\n",
1062 darr->deref_array_type);
1063 break;
1064 }
1065 }
1066
1067 /* handles array writes: */
1068 static void
1069 emit_intrinisic_store_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1070 {
1071 nir_deref_var *dvar = intr->variables[0];
1072 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
1073 struct ir3_array *arr = get_var(ctx, dvar->var);
1074 struct ir3_instruction **src;
1075
1076 compile_assert(ctx, dvar->deref.child &&
1077 (dvar->deref.child->deref_type == nir_deref_type_array));
1078
1079 src = get_src(ctx, &intr->src[0]);
1080
1081 switch (darr->deref_array_type) {
1082 case nir_deref_array_type_direct:
1083 /* direct access does not require anything special: */
1084 for (int i = 0; i < intr->num_components; i++) {
1085 unsigned n = darr->base_offset * 4 + i;
1086 compile_assert(ctx, n < arr->length);
1087 arr->arr[n] = src[i];
1088 }
1089 break;
1090 case nir_deref_array_type_indirect: {
1091 /* for indirect, create indirect-store and fan that out: */
1092 struct ir3_instruction *collect =
1093 create_collect(ctx->block, arr->arr, arr->length);
1094 struct ir3_instruction *addr =
1095 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1096 for (int i = 0; i < intr->num_components; i++) {
1097 struct ir3_instruction *store;
1098 unsigned n = darr->base_offset * 4 + i;
1099 compile_assert(ctx, n < arr->length);
1100
1101 store = create_indirect_store(ctx, arr->length,
1102 n, src[i], addr, collect);
1103
1104 store->fanin->fi.aid = arr->aid;
1105
1106 /* TODO: probably split this out to be used for
1107 * store_output_indirect? or move this into
1108 * create_indirect_store()?
1109 */
1110 for (int j = i; j < arr->length; j += 4) {
1111 struct ir3_instruction *split;
1112
1113 split = ir3_instr_create(ctx->block, -1, OPC_META_FO);
1114 split->fo.off = j;
1115 ir3_reg_create(split, 0, 0);
1116 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = store;
1117
1118 arr->arr[j] = split;
1119 }
1120 }
1121 break;
1122 }
1123 default:
1124 compile_error(ctx, "Unhandled store deref type: %u\n",
1125 darr->deref_array_type);
1126 break;
1127 }
1128 }
1129
1130 static void add_sysval_input(struct ir3_compile *ctx, unsigned name,
1131 struct ir3_instruction *instr)
1132 {
1133 struct ir3_shader_variant *so = ctx->so;
1134 unsigned r = regid(so->inputs_count, 0);
1135 unsigned n = so->inputs_count++;
1136
1137 so->inputs[n].semantic = ir3_semantic_name(name, 0);
1138 so->inputs[n].compmask = 1;
1139 so->inputs[n].regid = r;
1140 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1141 so->total_in++;
1142
1143 ctx->block->ninputs = MAX2(ctx->block->ninputs, r + 1);
1144 ctx->block->inputs[r] = instr;
1145 }
1146
1147 static void
1148 emit_intrinisic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1149 {
1150 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1151 struct ir3_instruction **dst, **src;
1152 struct ir3_block *b = ctx->block;
1153 unsigned idx = intr->const_index[0];
1154
1155 if (info->has_dest) {
1156 dst = get_dst(ctx, &intr->dest, intr->num_components);
1157 } else {
1158 dst = NULL;
1159 }
1160
1161 switch (intr->intrinsic) {
1162 case nir_intrinsic_load_uniform:
1163 for (int i = 0; i < intr->num_components; i++) {
1164 unsigned n = idx * 4 + i;
1165 dst[i] = create_uniform(ctx, n);
1166 }
1167 break;
1168 case nir_intrinsic_load_uniform_indirect:
1169 src = get_src(ctx, &intr->src[0]);
1170 for (int i = 0; i < intr->num_components; i++) {
1171 unsigned n = idx * 4 + i;
1172 dst[i] = create_uniform_indirect(ctx, n,
1173 get_addr(ctx, src[0]));
1174 }
1175 break;
1176 case nir_intrinsic_load_ubo:
1177 case nir_intrinsic_load_ubo_indirect:
1178 emit_intrinsic_load_ubo(ctx, intr, dst);
1179 break;
1180 case nir_intrinsic_load_input:
1181 for (int i = 0; i < intr->num_components; i++) {
1182 unsigned n = idx * 4 + i;
1183 dst[i] = b->inputs[n];
1184 }
1185 break;
1186 case nir_intrinsic_load_input_indirect:
1187 src = get_src(ctx, &intr->src[0]);
1188 struct ir3_instruction *collect =
1189 create_collect(b, b->inputs, b->ninputs);
1190 struct ir3_instruction *addr = get_addr(ctx, src[0]);
1191 for (int i = 0; i < intr->num_components; i++) {
1192 unsigned n = idx * 4 + i;
1193 dst[i] = create_indirect_load(ctx, b->ninputs, n, addr, collect);
1194 }
1195 break;
1196 case nir_intrinsic_load_var:
1197 emit_intrinisic_load_var(ctx, intr, dst);
1198 break;
1199 case nir_intrinsic_store_var:
1200 emit_intrinisic_store_var(ctx, intr);
1201 break;
1202 case nir_intrinsic_store_output:
1203 src = get_src(ctx, &intr->src[0]);
1204 for (int i = 0; i < intr->num_components; i++) {
1205 unsigned n = idx * 4 + i;
1206 b->outputs[n] = src[i];
1207 }
1208 break;
1209 case nir_intrinsic_load_base_vertex:
1210 if (!ctx->basevertex) {
1211 /* first four vec4 sysval's reserved for UBOs: */
1212 unsigned r = regid(ctx->so->first_driver_param + 4, 0);
1213 ctx->basevertex = create_uniform(ctx, r);
1214 add_sysval_input(ctx, TGSI_SEMANTIC_BASEVERTEX,
1215 ctx->basevertex);
1216 }
1217 dst[0] = ctx->basevertex;
1218 break;
1219 case nir_intrinsic_load_vertex_id_zero_base:
1220 if (!ctx->vertex_id) {
1221 ctx->vertex_id = create_input(ctx->block, NULL, 0);
1222 add_sysval_input(ctx, TGSI_SEMANTIC_VERTEXID_NOBASE,
1223 ctx->vertex_id);
1224 }
1225 dst[0] = ctx->vertex_id;
1226 break;
1227 case nir_intrinsic_load_instance_id:
1228 if (!ctx->instance_id) {
1229 ctx->instance_id = create_input(ctx->block, NULL, 0);
1230 add_sysval_input(ctx, TGSI_SEMANTIC_INSTANCEID,
1231 ctx->instance_id);
1232 }
1233 dst[0] = ctx->instance_id;
1234 break;
1235 case nir_intrinsic_discard_if:
1236 case nir_intrinsic_discard: {
1237 struct ir3_instruction *cond, *kill;
1238
1239 if (intr->intrinsic == nir_intrinsic_discard_if) {
1240 /* conditional discard: */
1241 src = get_src(ctx, &intr->src[0]);
1242 cond = ir3_b2n(b, src[0]);
1243 } else {
1244 /* unconditional discard: */
1245 cond = create_immed(b, 1);
1246 }
1247
1248 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1249 cond->cat2.condition = IR3_COND_NE;
1250
1251 /* condition always goes in predicate register: */
1252 cond->regs[0]->num = regid(REG_P0, 0);
1253
1254 kill = ir3_KILL(b, cond, 0);
1255 array_insert(ctx->ir->predicates, kill);
1256
1257 ctx->kill[ctx->kill_count++] = kill;
1258 ctx->so->has_kill = true;
1259
1260 break;
1261 }
1262 default:
1263 compile_error(ctx, "Unhandled intrinsic type: %s\n",
1264 nir_intrinsic_infos[intr->intrinsic].name);
1265 break;
1266 }
1267 }
1268
1269 static void
1270 emit_load_const(struct ir3_compile *ctx, nir_load_const_instr *instr)
1271 {
1272 struct ir3_instruction **dst = get_dst_ssa(ctx, &instr->def,
1273 instr->def.num_components);
1274 for (int i = 0; i < instr->def.num_components; i++)
1275 dst[i] = create_immed(ctx->block, instr->value.u[i]);
1276 }
1277
1278 static void
1279 emit_undef(struct ir3_compile *ctx, nir_ssa_undef_instr *undef)
1280 {
1281 struct ir3_instruction **dst = get_dst_ssa(ctx, &undef->def,
1282 undef->def.num_components);
1283 /* backend doesn't want undefined instructions, so just plug
1284 * in 0.0..
1285 */
1286 for (int i = 0; i < undef->def.num_components; i++)
1287 dst[i] = create_immed(ctx->block, fui(0.0));
1288 }
1289
1290 /*
1291 * texture fetch/sample instructions:
1292 */
1293
1294 static void
1295 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1296 {
1297 unsigned coords, flags = 0;
1298
1299 /* note: would use tex->coord_components.. except txs.. also,
1300 * since array index goes after shadow ref, we don't want to
1301 * count it:
1302 */
1303 switch (tex->sampler_dim) {
1304 case GLSL_SAMPLER_DIM_1D:
1305 case GLSL_SAMPLER_DIM_BUF:
1306 coords = 1;
1307 break;
1308 case GLSL_SAMPLER_DIM_2D:
1309 case GLSL_SAMPLER_DIM_RECT:
1310 case GLSL_SAMPLER_DIM_EXTERNAL:
1311 case GLSL_SAMPLER_DIM_MS:
1312 coords = 2;
1313 break;
1314 case GLSL_SAMPLER_DIM_3D:
1315 case GLSL_SAMPLER_DIM_CUBE:
1316 coords = 3;
1317 flags |= IR3_INSTR_3D;
1318 break;
1319 default:
1320 unreachable("bad sampler_dim");
1321 }
1322
1323 if (tex->is_shadow)
1324 flags |= IR3_INSTR_S;
1325
1326 if (tex->is_array)
1327 flags |= IR3_INSTR_A;
1328
1329 *flagsp = flags;
1330 *coordsp = coords;
1331 }
1332
1333 static void
1334 emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex)
1335 {
1336 struct ir3_block *b = ctx->block;
1337 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1338 struct ir3_instruction **coord, *lod, *compare, *proj, **off, **ddx, **ddy;
1339 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1340 unsigned i, coords, flags;
1341 unsigned nsrc0 = 0, nsrc1 = 0;
1342 type_t type;
1343 opc_t opc = 0;
1344
1345 coord = off = ddx = ddy = NULL;
1346 lod = proj = compare = NULL;
1347
1348 /* TODO: might just be one component for gathers? */
1349 dst = get_dst(ctx, &tex->dest, 4);
1350
1351 for (unsigned i = 0; i < tex->num_srcs; i++) {
1352 switch (tex->src[i].src_type) {
1353 case nir_tex_src_coord:
1354 coord = get_src(ctx, &tex->src[i].src);
1355 break;
1356 case nir_tex_src_bias:
1357 lod = get_src(ctx, &tex->src[i].src)[0];
1358 has_bias = true;
1359 break;
1360 case nir_tex_src_lod:
1361 lod = get_src(ctx, &tex->src[i].src)[0];
1362 has_lod = true;
1363 break;
1364 case nir_tex_src_comparitor: /* shadow comparator */
1365 compare = get_src(ctx, &tex->src[i].src)[0];
1366 break;
1367 case nir_tex_src_projector:
1368 proj = get_src(ctx, &tex->src[i].src)[0];
1369 has_proj = true;
1370 break;
1371 case nir_tex_src_offset:
1372 off = get_src(ctx, &tex->src[i].src);
1373 has_off = true;
1374 break;
1375 case nir_tex_src_ddx:
1376 ddx = get_src(ctx, &tex->src[i].src);
1377 break;
1378 case nir_tex_src_ddy:
1379 ddy = get_src(ctx, &tex->src[i].src);
1380 break;
1381 default:
1382 compile_error(ctx, "Unhandled NIR tex serc type: %d\n",
1383 tex->src[i].src_type);
1384 return;
1385 }
1386 }
1387
1388 switch (tex->op) {
1389 case nir_texop_tex: opc = OPC_SAM; break;
1390 case nir_texop_txb: opc = OPC_SAMB; break;
1391 case nir_texop_txl: opc = OPC_SAML; break;
1392 case nir_texop_txd: opc = OPC_SAMGQ; break;
1393 case nir_texop_txf: opc = OPC_ISAML; break;
1394 case nir_texop_txf_ms:
1395 case nir_texop_txs:
1396 case nir_texop_lod:
1397 case nir_texop_tg4:
1398 case nir_texop_query_levels:
1399 compile_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1400 return;
1401 }
1402
1403 tex_info(tex, &flags, &coords);
1404
1405 /* scale up integer coords for TXF based on the LOD */
1406 if (opc == OPC_ISAML) {
1407 assert(has_lod);
1408 for (i = 0; i < coords; i++)
1409 coord[i] = ir3_SHL_B(b, coord[i], 0, lod, 0);
1410 }
1411 /*
1412 * lay out the first argument in the proper order:
1413 * - actual coordinates first
1414 * - shadow reference
1415 * - array index
1416 * - projection w
1417 * - starting at offset 4, dpdx.xy, dpdy.xy
1418 *
1419 * bias/lod go into the second arg
1420 */
1421
1422 /* insert tex coords: */
1423 for (i = 0; i < coords; i++)
1424 src0[nsrc0++] = coord[i];
1425
1426 if (coords == 1) {
1427 /* hw doesn't do 1d, so we treat it as 2d with
1428 * height of 1, and patch up the y coord.
1429 * TODO: y coord should be (int)0 in some cases..
1430 */
1431 src0[nsrc0++] = create_immed(b, fui(0.5));
1432 }
1433
1434 if (tex->is_shadow)
1435 src0[nsrc0++] = compare;
1436
1437 if (tex->is_array)
1438 src0[nsrc0++] = coord[coords];
1439
1440 if (has_proj) {
1441 src0[nsrc0++] = proj;
1442 flags |= IR3_INSTR_P;
1443 }
1444
1445 /* pad to 4, then ddx/ddy: */
1446 if (tex->op == nir_texop_txd) {
1447 while (nsrc0 < 4)
1448 src0[nsrc0++] = create_immed(b, fui(0.0));
1449 for (i = 0; i < coords; i++)
1450 src0[nsrc0++] = ddx[i];
1451 if (coords < 2)
1452 src0[nsrc0++] = create_immed(b, fui(0.0));
1453 for (i = 0; i < coords; i++)
1454 src0[nsrc0++] = ddy[i];
1455 if (coords < 2)
1456 src0[nsrc0++] = create_immed(b, fui(0.0));
1457 }
1458
1459 /*
1460 * second argument (if applicable):
1461 * - offsets
1462 * - lod
1463 * - bias
1464 */
1465 if (has_off | has_lod | has_bias) {
1466 if (has_off) {
1467 for (i = 0; i < coords; i++)
1468 src1[nsrc1++] = off[i];
1469 if (coords < 2)
1470 src1[nsrc1++] = create_immed(b, fui(0.0));
1471 flags |= IR3_INSTR_O;
1472 }
1473
1474 if (has_lod | has_bias)
1475 src1[nsrc1++] = lod;
1476 }
1477
1478 switch (tex->dest_type) {
1479 case nir_type_invalid:
1480 case nir_type_float:
1481 type = TYPE_F32;
1482 break;
1483 case nir_type_int:
1484 type = TYPE_S32;
1485 break;
1486 case nir_type_unsigned:
1487 case nir_type_bool:
1488 type = TYPE_U32;
1489 break;
1490 default:
1491 unreachable("bad dest_type");
1492 }
1493
1494 sam = ir3_SAM(b, opc, type, TGSI_WRITEMASK_XYZW,
1495 flags, tex->sampler_index, tex->sampler_index,
1496 create_collect(b, src0, nsrc0),
1497 create_collect(b, src1, nsrc1));
1498
1499 split_dest(b, dst, sam);
1500 }
1501
1502 static void
1503 emit_tex_query_levels(struct ir3_compile *ctx, nir_tex_instr *tex)
1504 {
1505 struct ir3_block *b = ctx->block;
1506 struct ir3_instruction **dst, *sam;
1507
1508 dst = get_dst(ctx, &tex->dest, 1);
1509
1510 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, TGSI_WRITEMASK_Z, 0,
1511 tex->sampler_index, tex->sampler_index, NULL, NULL);
1512
1513 /* even though there is only one component, since it ends
1514 * up in .z rather than .x, we need a split_dest()
1515 */
1516 split_dest(b, dst, sam);
1517
1518 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1519 * the value in TEX_CONST_0 is zero-based.
1520 */
1521 if (ctx->levels_add_one)
1522 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1523 }
1524
1525 static void
1526 emit_tex_txs(struct ir3_compile *ctx, nir_tex_instr *tex)
1527 {
1528 struct ir3_block *b = ctx->block;
1529 struct ir3_instruction **dst, *sam, *lod;
1530 unsigned flags, coords;
1531
1532 tex_info(tex, &flags, &coords);
1533
1534 dst = get_dst(ctx, &tex->dest, 4);
1535
1536 compile_assert(ctx, tex->num_srcs == 1);
1537 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
1538
1539 lod = get_src(ctx, &tex->src[0].src)[0];
1540
1541 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, TGSI_WRITEMASK_XYZW, flags,
1542 tex->sampler_index, tex->sampler_index, lod, NULL);
1543
1544 split_dest(b, dst, sam);
1545
1546 /* Array size actually ends up in .w rather than .z. This doesn't
1547 * matter for miplevel 0, but for higher mips the value in z is
1548 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1549 * returned, which means that we have to add 1 to it for arrays.
1550 */
1551 if (tex->is_array) {
1552 if (ctx->levels_add_one) {
1553 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
1554 } else {
1555 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
1556 }
1557 }
1558 }
1559
1560 static void
1561 emit_instr(struct ir3_compile *ctx, nir_instr *instr)
1562 {
1563 switch (instr->type) {
1564 case nir_instr_type_alu:
1565 emit_alu(ctx, nir_instr_as_alu(instr));
1566 break;
1567 case nir_instr_type_intrinsic:
1568 emit_intrinisic(ctx, nir_instr_as_intrinsic(instr));
1569 break;
1570 case nir_instr_type_load_const:
1571 emit_load_const(ctx, nir_instr_as_load_const(instr));
1572 break;
1573 case nir_instr_type_ssa_undef:
1574 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1575 break;
1576 case nir_instr_type_tex: {
1577 nir_tex_instr *tex = nir_instr_as_tex(instr);
1578 /* couple tex instructions get special-cased:
1579 */
1580 switch (tex->op) {
1581 case nir_texop_txs:
1582 emit_tex_txs(ctx, tex);
1583 break;
1584 case nir_texop_query_levels:
1585 emit_tex_query_levels(ctx, tex);
1586 break;
1587 default:
1588 emit_tex(ctx, tex);
1589 break;
1590 }
1591 break;
1592 }
1593 case nir_instr_type_call:
1594 case nir_instr_type_jump:
1595 case nir_instr_type_phi:
1596 case nir_instr_type_parallel_copy:
1597 compile_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1598 break;
1599 }
1600 }
1601
1602 static void
1603 emit_block(struct ir3_compile *ctx, nir_block *block)
1604 {
1605 nir_foreach_instr(block, instr) {
1606 emit_instr(ctx, instr);
1607 if (ctx->error)
1608 return;
1609 }
1610 }
1611
1612 static void
1613 emit_function(struct ir3_compile *ctx, nir_function_impl *impl)
1614 {
1615 foreach_list_typed(nir_cf_node, node, node, &impl->body) {
1616 switch (node->type) {
1617 case nir_cf_node_block:
1618 emit_block(ctx, nir_cf_node_as_block(node));
1619 break;
1620 case nir_cf_node_if:
1621 case nir_cf_node_loop:
1622 case nir_cf_node_function:
1623 compile_error(ctx, "TODO\n");
1624 break;
1625 }
1626 if (ctx->error)
1627 return;
1628 }
1629 }
1630
1631 static void
1632 setup_input(struct ir3_compile *ctx, nir_variable *in)
1633 {
1634 struct ir3_shader_variant *so = ctx->so;
1635 unsigned array_len = MAX2(glsl_get_length(in->type), 1);
1636 unsigned ncomp = glsl_get_components(in->type);
1637 /* XXX: map loc slots to semantics */
1638 unsigned semantic_name = in->data.location;
1639 unsigned semantic_index = in->data.index;
1640 unsigned n = in->data.driver_location;
1641
1642 DBG("; in: %u:%u, len=%ux%u, loc=%u\n",
1643 semantic_name, semantic_index, array_len,
1644 ncomp, n);
1645
1646 so->inputs[n].semantic =
1647 ir3_semantic_name(semantic_name, semantic_index);
1648 so->inputs[n].compmask = (1 << ncomp) - 1;
1649 so->inputs[n].inloc = ctx->next_inloc;
1650 so->inputs[n].interpolate = 0;
1651 so->inputs_count = MAX2(so->inputs_count, n + 1);
1652
1653 /* the fdN_program_emit() code expects tgsi consts here, so map
1654 * things back to tgsi for now:
1655 */
1656 switch (in->data.interpolation) {
1657 case INTERP_QUALIFIER_FLAT:
1658 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1659 break;
1660 case INTERP_QUALIFIER_NOPERSPECTIVE:
1661 so->inputs[n].interpolate = TGSI_INTERPOLATE_LINEAR;
1662 break;
1663 case INTERP_QUALIFIER_SMOOTH:
1664 so->inputs[n].interpolate = TGSI_INTERPOLATE_PERSPECTIVE;
1665 break;
1666 }
1667
1668 for (int i = 0; i < ncomp; i++) {
1669 struct ir3_instruction *instr = NULL;
1670 unsigned idx = (n * 4) + i;
1671
1672 if (ctx->so->type == SHADER_FRAGMENT) {
1673 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1674 so->inputs[n].bary = false;
1675 so->frag_coord = true;
1676 instr = create_frag_coord(ctx, i);
1677 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1678 so->inputs[n].bary = false;
1679 so->frag_face = true;
1680 instr = create_frag_face(ctx, i);
1681 } else {
1682 bool use_ldlv = false;
1683
1684 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1685 * from the semantic name:
1686 */
1687 if ((in->data.interpolation == INTERP_QUALIFIER_NONE) &&
1688 ((semantic_name == TGSI_SEMANTIC_COLOR) ||
1689 (semantic_name == TGSI_SEMANTIC_BCOLOR)))
1690 so->inputs[n].interpolate = TGSI_INTERPOLATE_COLOR;
1691
1692 if (ctx->flat_bypass) {
1693 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1694 * from the semantic name:
1695 */
1696 switch (so->inputs[n].interpolate) {
1697 case TGSI_INTERPOLATE_COLOR:
1698 if (!ctx->so->key.rasterflat)
1699 break;
1700 /* fallthrough */
1701 case TGSI_INTERPOLATE_CONSTANT:
1702 use_ldlv = true;
1703 break;
1704 }
1705 }
1706
1707 so->inputs[n].bary = true;
1708
1709 instr = create_frag_input(ctx,
1710 so->inputs[n].inloc + i - 8, use_ldlv);
1711 }
1712 } else {
1713 instr = create_input(ctx->block, NULL, idx);
1714 }
1715
1716 ctx->block->inputs[idx] = instr;
1717 }
1718
1719 if (so->inputs[n].bary || (ctx->so->type == SHADER_VERTEX)) {
1720 ctx->next_inloc += ncomp;
1721 so->total_in += ncomp;
1722 }
1723 }
1724
1725 static void
1726 setup_output(struct ir3_compile *ctx, nir_variable *out)
1727 {
1728 struct ir3_shader_variant *so = ctx->so;
1729 unsigned array_len = MAX2(glsl_get_length(out->type), 1);
1730 unsigned ncomp = glsl_get_components(out->type);
1731 /* XXX: map loc slots to semantics */
1732 unsigned semantic_name = out->data.location;
1733 unsigned semantic_index = out->data.index;
1734 unsigned n = out->data.driver_location;
1735 unsigned comp = 0;
1736
1737 DBG("; out: %u:%u, len=%ux%u, loc=%u\n",
1738 semantic_name, semantic_index, array_len,
1739 ncomp, n);
1740
1741 if (ctx->so->type == SHADER_VERTEX) {
1742 switch (semantic_name) {
1743 case TGSI_SEMANTIC_POSITION:
1744 so->writes_pos = true;
1745 break;
1746 case TGSI_SEMANTIC_PSIZE:
1747 so->writes_psize = true;
1748 break;
1749 case TGSI_SEMANTIC_COLOR:
1750 case TGSI_SEMANTIC_BCOLOR:
1751 case TGSI_SEMANTIC_GENERIC:
1752 case TGSI_SEMANTIC_FOG:
1753 case TGSI_SEMANTIC_TEXCOORD:
1754 break;
1755 default:
1756 compile_error(ctx, "unknown VS semantic name: %s\n",
1757 tgsi_semantic_names[semantic_name]);
1758 }
1759 } else {
1760 switch (semantic_name) {
1761 case TGSI_SEMANTIC_POSITION:
1762 comp = 2; /* tgsi will write to .z component */
1763 so->writes_pos = true;
1764 break;
1765 case TGSI_SEMANTIC_COLOR:
1766 break;
1767 default:
1768 compile_error(ctx, "unknown FS semantic name: %s\n",
1769 tgsi_semantic_names[semantic_name]);
1770 }
1771 }
1772
1773 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
1774
1775 so->outputs[n].semantic =
1776 ir3_semantic_name(semantic_name, semantic_index);
1777 so->outputs[n].regid = regid(n, comp);
1778 so->outputs_count = MAX2(so->outputs_count, n + 1);
1779
1780 for (int i = 0; i < ncomp; i++) {
1781 unsigned idx = (n * 4) + i;
1782
1783 ctx->block->outputs[idx] = create_immed(ctx->block, fui(0.0));
1784 }
1785 }
1786
1787 static void
1788 emit_instructions(struct ir3_compile *ctx)
1789 {
1790 unsigned ninputs = exec_list_length(&ctx->s->inputs) * 4;
1791 unsigned noutputs = exec_list_length(&ctx->s->outputs) * 4;
1792
1793 /* we need to allocate big enough outputs array so that
1794 * we can stuff the kill's at the end. Likewise for vtx
1795 * shaders, we need to leave room for sysvals:
1796 */
1797 if (ctx->so->type == SHADER_FRAGMENT) {
1798 noutputs += ARRAY_SIZE(ctx->kill);
1799 } else if (ctx->so->type == SHADER_VERTEX) {
1800 ninputs += 8;
1801 }
1802
1803 ctx->block = ir3_block_create(ctx->ir, 0, ninputs, noutputs);
1804
1805 if (ctx->so->type == SHADER_FRAGMENT) {
1806 ctx->block->noutputs -= ARRAY_SIZE(ctx->kill);
1807 } else if (ctx->so->type == SHADER_VERTEX) {
1808 ctx->block->ninputs -= 8;
1809 }
1810
1811 /* for fragment shader, we have a single input register (usually
1812 * r0.xy) which is used as the base for bary.f varying fetch instrs:
1813 */
1814 if (ctx->so->type == SHADER_FRAGMENT) {
1815 // TODO maybe a helper for fi since we need it a few places..
1816 struct ir3_instruction *instr;
1817 instr = ir3_instr_create(ctx->block, -1, OPC_META_FI);
1818 ir3_reg_create(instr, 0, 0);
1819 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.x */
1820 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.y */
1821 ctx->frag_pos = instr;
1822 }
1823
1824 /* Setup inputs: */
1825 foreach_list_typed(nir_variable, var, node, &ctx->s->inputs) {
1826 setup_input(ctx, var);
1827 }
1828
1829 /* Setup outputs: */
1830 foreach_list_typed(nir_variable, var, node, &ctx->s->outputs) {
1831 setup_output(ctx, var);
1832 }
1833
1834 /* Setup variables (which should only be arrays): */
1835 foreach_list_typed(nir_variable, var, node, &ctx->s->globals) {
1836 declare_var(ctx, var);
1837 }
1838
1839 /* Find the main function and emit the body: */
1840 nir_foreach_overload(ctx->s, overload) {
1841 compile_assert(ctx, strcmp(overload->function->name, "main") == 0);
1842 compile_assert(ctx, overload->impl);
1843 emit_function(ctx, overload->impl);
1844 if (ctx->error)
1845 return;
1846 }
1847 }
1848
1849 /* from NIR perspective, we actually have inputs. But most of the "inputs"
1850 * for a fragment shader are just bary.f instructions. The *actual* inputs
1851 * from the hw perspective are the frag_pos and optionally frag_coord and
1852 * frag_face.
1853 */
1854 static void
1855 fixup_frag_inputs(struct ir3_compile *ctx)
1856 {
1857 struct ir3_shader_variant *so = ctx->so;
1858 struct ir3_block *block = ctx->block;
1859 struct ir3_instruction **inputs;
1860 struct ir3_instruction *instr;
1861 int n, regid = 0;
1862
1863 block->ninputs = 0;
1864
1865 n = 4; /* always have frag_pos */
1866 n += COND(so->frag_face, 4);
1867 n += COND(so->frag_coord, 4);
1868
1869 inputs = ir3_alloc(ctx->ir, n * (sizeof(struct ir3_instruction *)));
1870
1871 if (so->frag_face) {
1872 /* this ultimately gets assigned to hr0.x so doesn't conflict
1873 * with frag_coord/frag_pos..
1874 */
1875 inputs[block->ninputs++] = ctx->frag_face;
1876 ctx->frag_face->regs[0]->num = 0;
1877
1878 /* remaining channels not used, but let's avoid confusing
1879 * other parts that expect inputs to come in groups of vec4
1880 */
1881 inputs[block->ninputs++] = NULL;
1882 inputs[block->ninputs++] = NULL;
1883 inputs[block->ninputs++] = NULL;
1884 }
1885
1886 /* since we don't know where to set the regid for frag_coord,
1887 * we have to use r0.x for it. But we don't want to *always*
1888 * use r1.x for frag_pos as that could increase the register
1889 * footprint on simple shaders:
1890 */
1891 if (so->frag_coord) {
1892 ctx->frag_coord[0]->regs[0]->num = regid++;
1893 ctx->frag_coord[1]->regs[0]->num = regid++;
1894 ctx->frag_coord[2]->regs[0]->num = regid++;
1895 ctx->frag_coord[3]->regs[0]->num = regid++;
1896
1897 inputs[block->ninputs++] = ctx->frag_coord[0];
1898 inputs[block->ninputs++] = ctx->frag_coord[1];
1899 inputs[block->ninputs++] = ctx->frag_coord[2];
1900 inputs[block->ninputs++] = ctx->frag_coord[3];
1901 }
1902
1903 /* we always have frag_pos: */
1904 so->pos_regid = regid;
1905
1906 /* r0.x */
1907 instr = create_input(block, NULL, block->ninputs);
1908 instr->regs[0]->num = regid++;
1909 inputs[block->ninputs++] = instr;
1910 ctx->frag_pos->regs[1]->instr = instr;
1911
1912 /* r0.y */
1913 instr = create_input(block, NULL, block->ninputs);
1914 instr->regs[0]->num = regid++;
1915 inputs[block->ninputs++] = instr;
1916 ctx->frag_pos->regs[2]->instr = instr;
1917
1918 block->inputs = inputs;
1919 }
1920
1921 int
1922 ir3_compile_shader_nir(struct ir3_shader_variant *so,
1923 const struct tgsi_token *tokens, struct ir3_shader_key key)
1924 {
1925 struct ir3_compile *ctx;
1926 struct ir3_block *block;
1927 struct ir3_instruction **inputs;
1928 unsigned i, j, actual_in;
1929 int ret = 0, max_bary;
1930
1931 assert(!so->ir);
1932
1933 so->ir = ir3_create();
1934
1935 assert(so->ir);
1936
1937 ctx = compile_init(so, tokens);
1938 if (!ctx) {
1939 DBG("INIT failed!");
1940 ret = -1;
1941 goto out;
1942 }
1943
1944 emit_instructions(ctx);
1945
1946 if (ctx->error) {
1947 DBG("EMIT failed!");
1948 ret = -1;
1949 goto out;
1950 }
1951
1952 block = ctx->block;
1953 so->ir->block = block;
1954
1955 /* keep track of the inputs from TGSI perspective.. */
1956 inputs = block->inputs;
1957
1958 /* but fixup actual inputs for frag shader: */
1959 if (so->type == SHADER_FRAGMENT)
1960 fixup_frag_inputs(ctx);
1961
1962 /* at this point, for binning pass, throw away unneeded outputs: */
1963 if (key.binning_pass) {
1964 for (i = 0, j = 0; i < so->outputs_count; i++) {
1965 unsigned name = sem2name(so->outputs[i].semantic);
1966 unsigned idx = sem2idx(so->outputs[i].semantic);
1967
1968 /* throw away everything but first position/psize */
1969 if ((idx == 0) && ((name == TGSI_SEMANTIC_POSITION) ||
1970 (name == TGSI_SEMANTIC_PSIZE))) {
1971 if (i != j) {
1972 so->outputs[j] = so->outputs[i];
1973 block->outputs[(j*4)+0] = block->outputs[(i*4)+0];
1974 block->outputs[(j*4)+1] = block->outputs[(i*4)+1];
1975 block->outputs[(j*4)+2] = block->outputs[(i*4)+2];
1976 block->outputs[(j*4)+3] = block->outputs[(i*4)+3];
1977 }
1978 j++;
1979 }
1980 }
1981 so->outputs_count = j;
1982 block->noutputs = j * 4;
1983 }
1984
1985 /* if we want half-precision outputs, mark the output registers
1986 * as half:
1987 */
1988 if (key.half_precision) {
1989 for (i = 0; i < block->noutputs; i++) {
1990 if (!block->outputs[i])
1991 continue;
1992 block->outputs[i]->regs[0]->flags |= IR3_REG_HALF;
1993 }
1994 }
1995
1996 /* at this point, we want the kill's in the outputs array too,
1997 * so that they get scheduled (since they have no dst).. we've
1998 * already ensured that the array is big enough in push_block():
1999 */
2000 if (so->type == SHADER_FRAGMENT) {
2001 for (i = 0; i < ctx->kill_count; i++)
2002 block->outputs[block->noutputs++] = ctx->kill[i];
2003 }
2004
2005 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2006 printf("BEFORE CP:\n");
2007 ir3_print(so->ir);
2008 }
2009
2010 ir3_block_depth(block);
2011
2012 ir3_block_cp(block);
2013
2014 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2015 printf("BEFORE GROUPING:\n");
2016 ir3_print(so->ir);
2017 }
2018
2019 /* Group left/right neighbors, inserting mov's where needed to
2020 * solve conflicts:
2021 */
2022 ir3_block_group(block);
2023
2024 ir3_block_depth(block);
2025
2026 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2027 printf("AFTER DEPTH:\n");
2028 ir3_print(so->ir);
2029 }
2030
2031 ret = ir3_block_sched(block);
2032 if (ret) {
2033 DBG("SCHED failed!");
2034 goto out;
2035 }
2036
2037 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2038 printf("AFTER SCHED:\n");
2039 ir3_print(so->ir);
2040 }
2041
2042 ret = ir3_block_ra(block, so->type, so->frag_coord, so->frag_face);
2043 if (ret) {
2044 DBG("RA failed!");
2045 goto out;
2046 }
2047
2048 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2049 printf("AFTER RA:\n");
2050 ir3_print(so->ir);
2051 }
2052
2053 ir3_block_legalize(block, &so->has_samp, &max_bary);
2054
2055 /* fixup input/outputs: */
2056 for (i = 0; i < so->outputs_count; i++) {
2057 so->outputs[i].regid = block->outputs[i*4]->regs[0]->num;
2058 /* preserve hack for depth output.. tgsi writes depth to .z,
2059 * but what we give the hw is the scalar register:
2060 */
2061 if ((so->type == SHADER_FRAGMENT) &&
2062 (sem2name(so->outputs[i].semantic) == TGSI_SEMANTIC_POSITION))
2063 so->outputs[i].regid += 2;
2064 }
2065
2066 /* Note that some or all channels of an input may be unused: */
2067 actual_in = 0;
2068 for (i = 0; i < so->inputs_count; i++) {
2069 unsigned j, regid = ~0, compmask = 0;
2070 so->inputs[i].ncomp = 0;
2071 for (j = 0; j < 4; j++) {
2072 struct ir3_instruction *in = inputs[(i*4) + j];
2073 if (in) {
2074 compmask |= (1 << j);
2075 regid = in->regs[0]->num - j;
2076 actual_in++;
2077 so->inputs[i].ncomp++;
2078 }
2079 }
2080 so->inputs[i].regid = regid;
2081 so->inputs[i].compmask = compmask;
2082 }
2083
2084 /* fragment shader always gets full vec4's even if it doesn't
2085 * fetch all components, but vertex shader we need to update
2086 * with the actual number of components fetch, otherwise thing
2087 * will hang due to mismaptch between VFD_DECODE's and
2088 * TOTALATTRTOVS
2089 */
2090 if (so->type == SHADER_VERTEX)
2091 so->total_in = actual_in;
2092 else
2093 so->total_in = align(max_bary + 1, 4);
2094
2095 out:
2096 if (ret) {
2097 ir3_destroy(so->ir);
2098 so->ir = NULL;
2099 }
2100 compile_free(ctx);
2101
2102 return ret;
2103 }