1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* mapping from nir_register to defining instruction: */
78 struct hash_table
*def_ht
;
82 /* a common pattern for indirect addressing is to request the
83 * same address register multiple times. To avoid generating
84 * duplicate instruction sequences (which our backend does not
85 * try to clean up, since that should be done as the NIR stage)
86 * we cache the address value generated for a given src value:
88 * Note that we have to cache these per alignment, since same
89 * src used for an array of vec1 cannot be also used for an
92 struct hash_table
*addr_ht
[4];
94 /* last dst array, for indirect we need to insert a var-store.
96 struct ir3_instruction
**last_dst
;
99 /* maps nir_block to ir3_block, mostly for the purposes of
100 * figuring out the blocks successors
102 struct hash_table
*block_ht
;
104 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
105 * so we need to use ldlv.u32 to load the varying directly:
109 /* on a3xx, we need to add one to # of array levels:
113 /* on a3xx, we need to scale up integer coords for isaml based
116 bool unminify_coords
;
118 /* on a4xx, for array textures we need to add 0.5 to the array
121 bool array_index_add_half
;
123 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
126 unsigned max_texture_index
;
128 /* set if we encounter something we can't handle yet, so we
129 * can bail cleanly and fallback to TGSI compiler f/e
134 /* gpu pointer size in units of 32bit registers/slots */
135 static unsigned pointer_size(struct ir3_context
*ctx
)
137 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
140 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
141 static struct ir3_block
* get_block(struct ir3_context
*ctx
, nir_block
*nblock
);
144 static struct ir3_context
*
145 compile_init(struct ir3_compiler
*compiler
,
146 struct ir3_shader_variant
*so
)
148 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
150 if (compiler
->gpu_id
>= 400) {
151 /* need special handling for "flat" */
152 ctx
->flat_bypass
= true;
153 ctx
->levels_add_one
= false;
154 ctx
->unminify_coords
= false;
155 ctx
->array_index_add_half
= true;
157 if (so
->type
== SHADER_VERTEX
)
158 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
159 else if (so
->type
== SHADER_FRAGMENT
)
160 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
163 /* no special handling for "flat" */
164 ctx
->flat_bypass
= false;
165 ctx
->levels_add_one
= true;
166 ctx
->unminify_coords
= true;
167 ctx
->array_index_add_half
= false;
170 ctx
->compiler
= compiler
;
173 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
174 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
175 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
176 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
178 /* TODO: maybe generate some sort of bitmask of what key
179 * lowers vs what shader has (ie. no need to lower
180 * texture clamp lowering if no texture sample instrs)..
181 * although should be done further up the stack to avoid
182 * creating duplicate variants..
185 if (ir3_key_lowers_nir(&so
->key
)) {
186 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
187 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
189 /* fast-path for shader key that lowers nothing in NIR: */
190 ctx
->s
= so
->shader
->nir
;
193 /* this needs to be the last pass run, so do this here instead of
194 * in ir3_optimize_nir():
196 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
198 if (fd_mesa_debug
& FD_DBG_DISASM
) {
199 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
200 so
->shader
->id
, so
->id
, so
->type
,
201 so
->key
.binning_pass
, so
->key
.color_two_side
,
202 so
->key
.half_precision
);
203 nir_print_shader(ctx
->s
, stdout
);
206 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
208 so
->num_uniforms
= ctx
->s
->num_uniforms
;
209 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
211 /* Layout of constant registers, each section aligned to vec4. Note
212 * that pointer size (ubo, etc) changes depending on generation.
217 * if (vertex shader) {
218 * driver params (IR3_DP_*)
219 * if (stream_output.num_outputs > 0)
220 * stream-out addresses
224 * Immediates go last mostly because they are inserted in the CP pass
225 * after the nir -> ir3 frontend.
227 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
228 unsigned ptrsz
= pointer_size(ctx
);
230 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
232 if (so
->num_ubos
> 0) {
233 so
->constbase
.ubo
= constoff
;
234 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
237 if (so
->const_layout
.ssbo_size
.count
> 0) {
238 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
239 so
->constbase
.ssbo_sizes
= constoff
;
240 constoff
+= align(cnt
, 4) / 4;
243 if (so
->const_layout
.image_dims
.count
> 0) {
244 unsigned cnt
= so
->const_layout
.image_dims
.count
;
245 so
->constbase
.image_dims
= constoff
;
246 constoff
+= align(cnt
, 4) / 4;
249 unsigned num_driver_params
= 0;
250 if (so
->type
== SHADER_VERTEX
) {
251 num_driver_params
= IR3_DP_VS_COUNT
;
252 } else if (so
->type
== SHADER_COMPUTE
) {
253 num_driver_params
= IR3_DP_CS_COUNT
;
256 so
->constbase
.driver_param
= constoff
;
257 constoff
+= align(num_driver_params
, 4) / 4;
259 if ((so
->type
== SHADER_VERTEX
) &&
260 (compiler
->gpu_id
< 500) &&
261 so
->shader
->stream_output
.num_outputs
> 0) {
262 so
->constbase
.tfbo
= constoff
;
263 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
266 so
->constbase
.immediate
= constoff
;
272 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
275 va_start(ap
, format
);
276 _debug_vprintf(format
, ap
);
278 nir_print_shader(ctx
->s
, stdout
);
283 #define compile_assert(ctx, cond) do { \
284 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
288 compile_free(struct ir3_context
*ctx
)
294 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
296 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
297 arr
->id
= ++ctx
->num_arrays
;
298 /* NOTE: sometimes we get non array regs, for example for arrays of
299 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
300 * treat a non-array as if it was an array of length 1.
302 * It would be nice if there was a nir pass to convert arrays of
305 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
306 compile_assert(ctx
, arr
->length
> 0);
308 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
311 static struct ir3_array
*
312 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
314 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
318 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
322 /* relative (indirect) if address!=NULL */
323 static struct ir3_instruction
*
324 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
325 struct ir3_instruction
*address
)
327 struct ir3_block
*block
= ctx
->block
;
328 struct ir3_instruction
*mov
;
329 struct ir3_register
*src
;
331 mov
= ir3_instr_create(block
, OPC_MOV
);
332 mov
->cat1
.src_type
= TYPE_U32
;
333 mov
->cat1
.dst_type
= TYPE_U32
;
334 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
335 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
336 ir3_reg_create(mov
, 0, 0);
337 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
338 COND(address
, IR3_REG_RELATIV
));
339 src
->instr
= arr
->last_write
;
340 src
->size
= arr
->length
;
341 src
->array
.id
= arr
->id
;
342 src
->array
.offset
= n
;
345 ir3_instr_set_address(mov
, address
);
350 /* relative (indirect) if address!=NULL */
351 static struct ir3_instruction
*
352 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
353 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
355 struct ir3_block
*block
= ctx
->block
;
356 struct ir3_instruction
*mov
;
357 struct ir3_register
*dst
;
359 mov
= ir3_instr_create(block
, OPC_MOV
);
360 mov
->cat1
.src_type
= TYPE_U32
;
361 mov
->cat1
.dst_type
= TYPE_U32
;
362 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
363 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
364 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
365 COND(address
, IR3_REG_RELATIV
));
366 dst
->instr
= arr
->last_write
;
367 dst
->size
= arr
->length
;
368 dst
->array
.id
= arr
->id
;
369 dst
->array
.offset
= n
;
370 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
373 ir3_instr_set_address(mov
, address
);
375 arr
->last_write
= mov
;
380 /* allocate a n element value array (to be populated by caller) and
383 static struct ir3_instruction
**
384 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
386 struct ir3_instruction
**value
=
387 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
388 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
392 static struct ir3_instruction
**
393 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
395 struct ir3_instruction
**value
;
398 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
400 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
403 /* NOTE: in non-ssa case, we don't really need to store last_dst
404 * but this helps us catch cases where put_dst() call is forgotten
406 compile_assert(ctx
, !ctx
->last_dst
);
407 ctx
->last_dst
= value
;
413 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
415 static struct ir3_instruction
* const *
416 get_src(struct ir3_context
*ctx
, nir_src
*src
)
419 struct hash_entry
*entry
;
420 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
421 compile_assert(ctx
, entry
);
424 nir_register
*reg
= src
->reg
.reg
;
425 struct ir3_array
*arr
= get_array(ctx
, reg
);
426 unsigned num_components
= arr
->r
->num_components
;
427 struct ir3_instruction
*addr
= NULL
;
428 struct ir3_instruction
**value
=
429 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
431 if (src
->reg
.indirect
)
432 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
433 reg
->num_components
);
435 for (unsigned i
= 0; i
< num_components
; i
++) {
436 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
437 compile_assert(ctx
, n
< arr
->length
);
438 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
446 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
449 nir_register
*reg
= dst
->reg
.reg
;
450 struct ir3_array
*arr
= get_array(ctx
, reg
);
451 unsigned num_components
= ctx
->last_dst_n
;
452 struct ir3_instruction
*addr
= NULL
;
454 if (dst
->reg
.indirect
)
455 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
456 reg
->num_components
);
458 for (unsigned i
= 0; i
< num_components
; i
++) {
459 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
460 compile_assert(ctx
, n
< arr
->length
);
461 if (!ctx
->last_dst
[i
])
463 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
466 ralloc_free(ctx
->last_dst
);
468 ctx
->last_dst
= NULL
;
472 static struct ir3_instruction
*
473 create_immed(struct ir3_block
*block
, uint32_t val
)
475 struct ir3_instruction
*mov
;
477 mov
= ir3_instr_create(block
, OPC_MOV
);
478 mov
->cat1
.src_type
= TYPE_U32
;
479 mov
->cat1
.dst_type
= TYPE_U32
;
480 ir3_reg_create(mov
, 0, 0);
481 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
486 static struct ir3_instruction
*
487 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
489 struct ir3_instruction
*instr
, *immed
;
491 /* TODO in at least some cases, the backend could probably be
492 * made clever enough to propagate IR3_REG_HALF..
494 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
495 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
502 /* src *= 2 => src <<= 1: */
503 immed
= create_immed(block
, 1);
504 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
506 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
507 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
508 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
512 immed
= create_immed(block
, 3);
513 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
515 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
516 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
517 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
520 /* src *= 4 => src <<= 2: */
521 immed
= create_immed(block
, 2);
522 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
524 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
525 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
526 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
529 unreachable("bad align");
533 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
534 instr
->regs
[0]->num
= regid(REG_A0
, 0);
535 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
536 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
541 /* caches addr values to avoid generating multiple cov/shl/mova
542 * sequences for each use of a given NIR level src as address
544 static struct ir3_instruction
*
545 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
547 struct ir3_instruction
*addr
;
548 unsigned idx
= align
- 1;
550 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
552 if (!ctx
->addr_ht
[idx
]) {
553 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
554 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
556 struct hash_entry
*entry
;
557 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
562 addr
= create_addr(ctx
->block
, src
, align
);
563 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
568 static struct ir3_instruction
*
569 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
571 struct ir3_block
*b
= ctx
->block
;
572 struct ir3_instruction
*cond
;
574 /* NOTE: only cmps.*.* can write p0.x: */
575 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
576 cond
->cat2
.condition
= IR3_COND_NE
;
578 /* condition always goes in predicate register: */
579 cond
->regs
[0]->num
= regid(REG_P0
, 0);
584 static struct ir3_instruction
*
585 create_uniform(struct ir3_context
*ctx
, unsigned n
)
587 struct ir3_instruction
*mov
;
589 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
590 /* TODO get types right? */
591 mov
->cat1
.src_type
= TYPE_F32
;
592 mov
->cat1
.dst_type
= TYPE_F32
;
593 ir3_reg_create(mov
, 0, 0);
594 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
599 static struct ir3_instruction
*
600 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
601 struct ir3_instruction
*address
)
603 struct ir3_instruction
*mov
;
605 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
606 mov
->cat1
.src_type
= TYPE_U32
;
607 mov
->cat1
.dst_type
= TYPE_U32
;
608 ir3_reg_create(mov
, 0, 0);
609 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
611 ir3_instr_set_address(mov
, address
);
616 static struct ir3_instruction
*
617 create_collect(struct ir3_block
*block
, struct ir3_instruction
*const *arr
,
620 struct ir3_instruction
*collect
;
625 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
626 ir3_reg_create(collect
, 0, 0); /* dst */
627 for (unsigned i
= 0; i
< arrsz
; i
++)
628 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
633 static struct ir3_instruction
*
634 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
635 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
637 struct ir3_block
*block
= ctx
->block
;
638 struct ir3_instruction
*mov
;
639 struct ir3_register
*src
;
641 mov
= ir3_instr_create(block
, OPC_MOV
);
642 mov
->cat1
.src_type
= TYPE_U32
;
643 mov
->cat1
.dst_type
= TYPE_U32
;
644 ir3_reg_create(mov
, 0, 0);
645 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
646 src
->instr
= collect
;
648 src
->array
.offset
= n
;
650 ir3_instr_set_address(mov
, address
);
655 static struct ir3_instruction
*
656 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
658 struct ir3_instruction
*in
;
660 in
= ir3_instr_create(block
, OPC_META_INPUT
);
661 in
->inout
.block
= block
;
662 ir3_reg_create(in
, n
, 0);
664 in
->regs
[0]->wrmask
= compmask
;
669 static struct ir3_instruction
*
670 create_input(struct ir3_block
*block
, unsigned n
)
672 return create_input_compmask(block
, n
, 0x1);
675 static struct ir3_instruction
*
676 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
678 struct ir3_block
*block
= ctx
->block
;
679 struct ir3_instruction
*instr
;
680 /* actual inloc is assigned and fixed up later: */
681 struct ir3_instruction
*inloc
= create_immed(block
, 0);
684 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
685 instr
->cat6
.type
= TYPE_U32
;
686 instr
->cat6
.iim_val
= 1;
688 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
689 instr
->regs
[2]->wrmask
= 0x3;
695 static struct ir3_instruction
*
696 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
698 struct ir3_block
*block
= ctx
->block
;
699 struct ir3_instruction
*instr
;
701 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
703 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
708 /* for frag_coord, we get unsigned values.. we need
709 * to subtract (integer) 8 and divide by 16 (right-
710 * shift by 4) then convert to float:
714 * mov.u32f32 dst, tmp
717 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
718 create_immed(block
, 8), 0);
719 instr
= ir3_SHR_B(block
, instr
, 0,
720 create_immed(block
, 4), 0);
721 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
727 /* seems that we can use these as-is: */
728 return ctx
->frag_coord
[comp
];
732 static struct ir3_instruction
*
733 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
735 /* first four vec4 sysval's reserved for UBOs: */
736 /* NOTE: dp is in scalar, but there can be >4 dp components: */
737 unsigned n
= ctx
->so
->constbase
.driver_param
;
738 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
739 return create_uniform(ctx
, r
);
742 /* helper for instructions that produce multiple consecutive scalar
743 * outputs which need to have a split/fanout meta instruction inserted
746 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
747 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
749 struct ir3_instruction
*prev
= NULL
;
751 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
756 for (int i
= 0, j
= 0; i
< n
; i
++) {
757 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
758 ir3_reg_create(split
, 0, IR3_REG_SSA
);
759 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
760 split
->fo
.off
= i
+ base
;
763 split
->cp
.left
= prev
;
764 split
->cp
.left_cnt
++;
765 prev
->cp
.right
= split
;
766 prev
->cp
.right_cnt
++;
770 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
776 * Adreno uses uint rather than having dedicated bool type,
777 * which (potentially) requires some conversion, in particular
778 * when using output of an bool instr to int input, or visa
782 * -------+---------+-------+-
786 * To convert from an adreno bool (uint) to nir, use:
788 * absneg.s dst, (neg)src
790 * To convert back in the other direction:
792 * absneg.s dst, (abs)arc
794 * The CP step can clean up the absneg.s that cancel each other
795 * out, and with a slight bit of extra cleverness (to recognize
796 * the instructions which produce either a 0 or 1) can eliminate
797 * the absneg.s's completely when an instruction that wants
798 * 0/1 consumes the result. For example, when a nir 'bcsel'
799 * consumes the result of 'feq'. So we should be able to get by
800 * without a boolean resolve step, and without incuring any
801 * extra penalty in instruction count.
804 /* NIR bool -> native (adreno): */
805 static struct ir3_instruction
*
806 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
808 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
811 /* native (adreno) -> NIR bool: */
812 static struct ir3_instruction
*
813 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
815 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
819 * alu/sfu instructions:
823 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
825 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
826 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
827 struct ir3_block
*b
= ctx
->block
;
828 unsigned dst_sz
, wrmask
;
830 if (alu
->dest
.dest
.is_ssa
) {
831 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
832 wrmask
= (1 << dst_sz
) - 1;
834 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
835 wrmask
= alu
->dest
.write_mask
;
838 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
840 /* Vectors are special in that they have non-scalarized writemasks,
841 * and just take the first swizzle channel for each argument in
842 * order into each writemask channel.
844 if ((alu
->op
== nir_op_vec2
) ||
845 (alu
->op
== nir_op_vec3
) ||
846 (alu
->op
== nir_op_vec4
)) {
848 for (int i
= 0; i
< info
->num_inputs
; i
++) {
849 nir_alu_src
*asrc
= &alu
->src
[i
];
851 compile_assert(ctx
, !asrc
->abs
);
852 compile_assert(ctx
, !asrc
->negate
);
854 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
856 src
[i
] = create_immed(ctx
->block
, 0);
857 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
860 put_dst(ctx
, &alu
->dest
.dest
);
864 /* We also get mov's with more than one component for mov's so
865 * handle those specially:
867 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
868 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
869 nir_alu_src
*asrc
= &alu
->src
[0];
870 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
872 for (unsigned i
= 0; i
< dst_sz
; i
++) {
873 if (wrmask
& (1 << i
)) {
874 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
880 put_dst(ctx
, &alu
->dest
.dest
);
884 compile_assert(ctx
, alu
->dest
.dest
.is_ssa
);
886 /* General case: We can just grab the one used channel per src. */
887 for (int i
= 0; i
< info
->num_inputs
; i
++) {
888 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
889 nir_alu_src
*asrc
= &alu
->src
[i
];
891 compile_assert(ctx
, !asrc
->abs
);
892 compile_assert(ctx
, !asrc
->negate
);
894 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
896 compile_assert(ctx
, src
[i
]);
901 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
904 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
907 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
910 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
913 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
914 dst
[0]->cat2
.condition
= IR3_COND_NE
;
915 dst
[0] = ir3_n2b(b
, dst
[0]);
918 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
921 dst
[0] = ir3_b2n(b
, src
[0]);
924 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
925 dst
[0]->cat2
.condition
= IR3_COND_NE
;
926 dst
[0] = ir3_n2b(b
, dst
[0]);
930 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
933 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
936 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
939 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
942 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
945 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
948 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
951 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
954 dst
[0] = ir3_DSX(b
, src
[0], 0);
955 dst
[0]->cat5
.type
= TYPE_F32
;
958 dst
[0] = ir3_DSY(b
, src
[0], 0);
959 dst
[0]->cat5
.type
= TYPE_F32
;
963 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
964 dst
[0]->cat2
.condition
= IR3_COND_LT
;
965 dst
[0] = ir3_n2b(b
, dst
[0]);
968 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
969 dst
[0]->cat2
.condition
= IR3_COND_GE
;
970 dst
[0] = ir3_n2b(b
, dst
[0]);
973 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
974 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
975 dst
[0] = ir3_n2b(b
, dst
[0]);
978 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
979 dst
[0]->cat2
.condition
= IR3_COND_NE
;
980 dst
[0] = ir3_n2b(b
, dst
[0]);
983 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
986 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
989 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
991 case nir_op_fround_even
:
992 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
995 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
999 dst
[0] = ir3_SIN(b
, src
[0], 0);
1002 dst
[0] = ir3_COS(b
, src
[0], 0);
1005 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1008 dst
[0] = ir3_RCP(b
, src
[0], 0);
1011 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1014 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1017 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1021 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1024 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1027 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1030 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1033 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1036 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1039 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1043 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1044 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1045 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1046 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1048 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1049 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1050 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1053 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1056 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1059 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1062 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1065 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1067 case nir_op_isign
: {
1068 /* maybe this would be sane to lower in nir.. */
1069 struct ir3_instruction
*neg
, *pos
;
1071 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1072 neg
->cat2
.condition
= IR3_COND_LT
;
1074 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1075 pos
->cat2
.condition
= IR3_COND_GT
;
1077 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1082 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1085 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1088 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1092 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1093 dst
[0] = ir3_n2b(b
, dst
[0]);
1096 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1097 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1098 dst
[0] = ir3_n2b(b
, dst
[0]);
1101 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1102 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1103 dst
[0] = ir3_n2b(b
, dst
[0]);
1106 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1107 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1108 dst
[0] = ir3_n2b(b
, dst
[0]);
1111 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1112 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1113 dst
[0] = ir3_n2b(b
, dst
[0]);
1116 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1117 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1118 dst
[0] = ir3_n2b(b
, dst
[0]);
1122 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1125 case nir_op_bit_count
:
1126 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1128 case nir_op_ifind_msb
: {
1129 struct ir3_instruction
*cmp
;
1130 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1131 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1132 cmp
->cat2
.condition
= IR3_COND_GE
;
1133 dst
[0] = ir3_SEL_B32(b
,
1134 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1138 case nir_op_ufind_msb
:
1139 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1140 dst
[0] = ir3_SEL_B32(b
,
1141 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1142 src
[0], 0, dst
[0], 0);
1144 case nir_op_find_lsb
:
1145 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1146 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1148 case nir_op_bitfield_reverse
:
1149 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1153 compile_error(ctx
, "Unhandled ALU op: %s\n",
1154 nir_op_infos
[alu
->op
].name
);
1158 put_dst(ctx
, &alu
->dest
.dest
);
1161 /* handles direct/indirect UBO reads: */
1163 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1164 struct ir3_instruction
**dst
)
1166 struct ir3_block
*b
= ctx
->block
;
1167 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1168 nir_const_value
*const_offset
;
1169 /* UBO addresses are the first driver params: */
1170 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1171 const unsigned ptrsz
= pointer_size(ctx
);
1175 /* First src is ubo index, which could either be an immed or not: */
1176 src0
= get_src(ctx
, &intr
->src
[0])[0];
1177 if (is_same_type_mov(src0
) &&
1178 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1179 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1180 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1182 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1183 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1186 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1189 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1191 off
+= const_offset
->u32
[0];
1193 /* For load_ubo_indirect, second src is indirect offset: */
1194 src1
= get_src(ctx
, &intr
->src
[1])[0];
1196 /* and add offset to addr: */
1197 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1200 /* if offset is to large to encode in the ldg, split it out: */
1201 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1202 /* split out the minimal amount to improve the odds that
1203 * cp can fit the immediate in the add.s instruction:
1205 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1206 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1211 struct ir3_instruction
*carry
;
1213 /* handle 32b rollover, ie:
1214 * if (addr < base_lo)
1217 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1218 carry
->cat2
.condition
= IR3_COND_LT
;
1219 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1221 addr
= create_collect(b
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1224 for (int i
= 0; i
< intr
->num_components
; i
++) {
1225 struct ir3_instruction
*load
=
1226 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1227 load
->cat6
.type
= TYPE_U32
;
1228 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1233 /* src[] = { buffer_index, offset }. No const_index */
1235 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1236 struct ir3_instruction
**dst
)
1238 struct ir3_block
*b
= ctx
->block
;
1239 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1240 nir_const_value
*const_offset
;
1242 /* can this be non-const buffer_index? how do we handle that? */
1243 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1244 compile_assert(ctx
, const_offset
);
1246 offset
= get_src(ctx
, &intr
->src
[1])[0];
1248 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1249 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1253 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1255 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1257 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1258 ldgb
->cat6
.iim_val
= intr
->num_components
;
1260 ldgb
->cat6
.type
= TYPE_U32
;
1261 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1262 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1264 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1267 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1269 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1271 struct ir3_block
*b
= ctx
->block
;
1272 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1273 nir_const_value
*const_offset
;
1274 /* TODO handle wrmask properly, see _store_shared().. but I think
1275 * it is more a PITA than that, since blob ends up loading the
1276 * masked components and writing them back out.
1278 unsigned wrmask
= intr
->const_index
[0];
1279 unsigned ncomp
= ffs(~wrmask
) - 1;
1281 /* can this be non-const buffer_index? how do we handle that? */
1282 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1283 compile_assert(ctx
, const_offset
);
1285 offset
= get_src(ctx
, &intr
->src
[2])[0];
1287 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1290 src0
= create_collect(b
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1291 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1292 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1297 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1298 src0
, 0, src1
, 0, src2
, 0);
1299 stgb
->cat6
.iim_val
= ncomp
;
1301 stgb
->cat6
.type
= TYPE_U32
;
1302 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1303 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1305 array_insert(b
, b
->keeps
, stgb
);
1308 /* src[] = { block_index } */
1310 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1311 struct ir3_instruction
**dst
)
1313 /* SSBO size stored as a const starting at ssbo_sizes: */
1314 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1315 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1316 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1318 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1320 dst
[0] = create_uniform(ctx
, idx
);
1324 * SSBO atomic intrinsics
1326 * All of the SSBO atomic memory operations read a value from memory,
1327 * compute a new value using one of the operations below, write the new
1328 * value to memory, and return the original value read.
1330 * All operations take 3 sources except CompSwap that takes 4. These
1331 * sources represent:
1333 * 0: The SSBO buffer index.
1334 * 1: The offset into the SSBO buffer of the variable that the atomic
1335 * operation will operate on.
1336 * 2: The data parameter to the atomic function (i.e. the value to add
1337 * in ssbo_atomic_add, etc).
1338 * 3: For CompSwap only: the second data parameter.
1340 static struct ir3_instruction
*
1341 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1343 struct ir3_block
*b
= ctx
->block
;
1344 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1345 nir_const_value
*const_offset
;
1346 type_t type
= TYPE_U32
;
1348 /* can this be non-const buffer_index? how do we handle that? */
1349 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1350 compile_assert(ctx
, const_offset
);
1351 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1353 offset
= get_src(ctx
, &intr
->src
[1])[0];
1355 /* src0 is data (or uvec2(data, compare))
1357 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1359 * Note that nir already multiplies the offset by four
1361 src0
= get_src(ctx
, &intr
->src
[2])[0];
1362 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1363 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1368 switch (intr
->intrinsic
) {
1369 case nir_intrinsic_ssbo_atomic_add
:
1370 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1372 case nir_intrinsic_ssbo_atomic_imin
:
1373 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1376 case nir_intrinsic_ssbo_atomic_umin
:
1377 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1379 case nir_intrinsic_ssbo_atomic_imax
:
1380 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1383 case nir_intrinsic_ssbo_atomic_umax
:
1384 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1386 case nir_intrinsic_ssbo_atomic_and
:
1387 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1389 case nir_intrinsic_ssbo_atomic_or
:
1390 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1392 case nir_intrinsic_ssbo_atomic_xor
:
1393 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1395 case nir_intrinsic_ssbo_atomic_exchange
:
1396 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1398 case nir_intrinsic_ssbo_atomic_comp_swap
:
1399 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1400 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1402 get_src(ctx
, &intr
->src
[3])[0],
1404 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1410 atomic
->cat6
.iim_val
= 1;
1412 atomic
->cat6
.type
= type
;
1413 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1414 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1416 /* even if nothing consume the result, we can't DCE the instruction: */
1417 array_insert(b
, b
->keeps
, atomic
);
1422 /* src[] = { offset }. const_index[] = { base } */
1424 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1425 struct ir3_instruction
**dst
)
1427 struct ir3_block
*b
= ctx
->block
;
1428 struct ir3_instruction
*ldl
, *offset
;
1431 offset
= get_src(ctx
, &intr
->src
[0])[0];
1432 base
= intr
->const_index
[0];
1434 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1435 ldl
->cat6
.src_offset
= base
;
1436 ldl
->cat6
.type
= TYPE_U32
;
1437 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1439 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1440 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1442 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1445 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1447 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1449 struct ir3_block
*b
= ctx
->block
;
1450 struct ir3_instruction
*stl
, *offset
;
1451 struct ir3_instruction
* const *value
;
1452 unsigned base
, wrmask
;
1454 value
= get_src(ctx
, &intr
->src
[0]);
1455 offset
= get_src(ctx
, &intr
->src
[1])[0];
1457 base
= intr
->const_index
[0];
1458 wrmask
= intr
->const_index
[1];
1460 /* Combine groups of consecutive enabled channels in one write
1461 * message. We use ffs to find the first enabled channel and then ffs on
1462 * the bit-inverse, down-shifted writemask to determine the length of
1463 * the block of enabled bits.
1465 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1468 unsigned first_component
= ffs(wrmask
) - 1;
1469 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1471 stl
= ir3_STL(b
, offset
, 0,
1472 create_collect(b
, &value
[first_component
], length
), 0,
1473 create_immed(b
, length
), 0);
1474 stl
->cat6
.dst_offset
= first_component
+ base
;
1475 stl
->cat6
.type
= TYPE_U32
;
1476 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1477 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1479 array_insert(b
, b
->keeps
, stl
);
1481 /* Clear the bits in the writemask that we just wrote, then try
1482 * again to see if more channels are left.
1484 wrmask
&= (15 << (first_component
+ length
));
1489 * CS shared variable atomic intrinsics
1491 * All of the shared variable atomic memory operations read a value from
1492 * memory, compute a new value using one of the operations below, write the
1493 * new value to memory, and return the original value read.
1495 * All operations take 2 sources except CompSwap that takes 3. These
1496 * sources represent:
1498 * 0: The offset into the shared variable storage region that the atomic
1499 * operation will operate on.
1500 * 1: The data parameter to the atomic function (i.e. the value to add
1501 * in shared_atomic_add, etc).
1502 * 2: For CompSwap only: the second data parameter.
1504 static struct ir3_instruction
*
1505 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1507 struct ir3_block
*b
= ctx
->block
;
1508 struct ir3_instruction
*atomic
, *src0
, *src1
;
1509 type_t type
= TYPE_U32
;
1511 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1512 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1514 switch (intr
->intrinsic
) {
1515 case nir_intrinsic_shared_atomic_add
:
1516 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1518 case nir_intrinsic_shared_atomic_imin
:
1519 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1522 case nir_intrinsic_shared_atomic_umin
:
1523 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1525 case nir_intrinsic_shared_atomic_imax
:
1526 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1529 case nir_intrinsic_shared_atomic_umax
:
1530 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1532 case nir_intrinsic_shared_atomic_and
:
1533 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1535 case nir_intrinsic_shared_atomic_or
:
1536 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1538 case nir_intrinsic_shared_atomic_xor
:
1539 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1541 case nir_intrinsic_shared_atomic_exchange
:
1542 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1544 case nir_intrinsic_shared_atomic_comp_swap
:
1545 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1546 src1
= create_collect(b
, (struct ir3_instruction
*[]){
1547 get_src(ctx
, &intr
->src
[2])[0],
1550 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1556 atomic
->cat6
.iim_val
= 1;
1558 atomic
->cat6
.type
= type
;
1559 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1560 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1562 /* even if nothing consume the result, we can't DCE the instruction: */
1563 array_insert(b
, b
->keeps
, atomic
);
1568 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1569 * state block (for load). To simplify things, invert the image id and
1570 * map it from end of state block, ie. image 0 becomes num-1, image 1
1571 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1572 * state when switching shaders.
1574 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1575 * coded. Also, since all the gl shader stages (ie. everything but CS)
1576 * share the same SSBO/image state block, this might require some more
1577 * logic if we supported images in anything other than FS..
1580 get_image_slot(struct ir3_context
*ctx
, const nir_variable
*var
)
1582 /* TODO figure out real limit per generation, and don't hardcode: */
1583 const unsigned max_samplers
= 16;
1584 return max_samplers
- var
->data
.driver_location
- 1;
1588 get_image_coords(const nir_variable
*var
)
1590 switch (glsl_get_sampler_dim(glsl_without_array(var
->type
))) {
1591 case GLSL_SAMPLER_DIM_1D
:
1592 case GLSL_SAMPLER_DIM_BUF
:
1595 case GLSL_SAMPLER_DIM_2D
:
1596 case GLSL_SAMPLER_DIM_RECT
:
1597 case GLSL_SAMPLER_DIM_EXTERNAL
:
1598 case GLSL_SAMPLER_DIM_MS
:
1600 case GLSL_SAMPLER_DIM_3D
:
1601 case GLSL_SAMPLER_DIM_CUBE
:
1604 unreachable("bad sampler dim");
1610 get_image_type(const nir_variable
*var
)
1612 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1613 case GLSL_TYPE_UINT
:
1617 case GLSL_TYPE_FLOAT
:
1620 unreachable("bad sampler type.");
1625 static struct ir3_instruction
*
1626 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1627 struct ir3_instruction
* const *coords
, bool byteoff
)
1629 struct ir3_block
*b
= ctx
->block
;
1630 struct ir3_instruction
*offset
;
1631 unsigned ncoords
= get_image_coords(var
);
1633 /* to calculate the byte offset (yes, uggg) we need (up to) three
1634 * const values to know the bytes per pixel, and y and z stride:
1636 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1637 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1639 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1640 (1 << var
->data
.driver_location
));
1642 /* offset = coords.x * bytes_per_pixel: */
1643 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1645 /* offset += coords.y * y_pitch: */
1646 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1647 coords
[1], 0, offset
, 0);
1650 /* offset += coords.z * z_pitch: */
1651 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1652 coords
[2], 0, offset
, 0);
1656 /* Some cases, like atomics, seem to use dword offset instead
1657 * of byte offsets.. blob just puts an extra shr.b in there
1660 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1663 return create_collect(b
, (struct ir3_instruction
*[]){
1669 /* src[] = { coord, sample_index }. const_index[] = {} */
1671 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1672 struct ir3_instruction
**dst
)
1674 struct ir3_block
*b
= ctx
->block
;
1675 const nir_variable
*var
= intr
->variables
[0]->var
;
1676 struct ir3_instruction
*sam
;
1677 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1678 unsigned ncoords
= get_image_coords(var
);
1679 unsigned tex_idx
= get_image_slot(ctx
, var
);
1680 type_t type
= get_image_type(var
);
1684 flags
|= IR3_INSTR_3D
;
1686 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1687 tex_idx
, tex_idx
, create_collect(b
, coords
, ncoords
), NULL
);
1689 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1690 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1692 split_dest(b
, dst
, sam
, 0, 4);
1695 /* src[] = { coord, sample_index, value }. const_index[] = {} */
1697 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1699 struct ir3_block
*b
= ctx
->block
;
1700 const nir_variable
*var
= intr
->variables
[0]->var
;
1701 struct ir3_instruction
*stib
, *offset
;
1702 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
1703 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1704 unsigned ncoords
= get_image_coords(var
);
1705 unsigned tex_idx
= get_image_slot(ctx
, var
);
1709 * src2 is 64b byte offset
1712 offset
= get_image_offset(ctx
, var
, coords
, true);
1714 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1715 * too and takes a dword offset.. not quite sure yet why blob uses
1716 * one over the other in various cases.
1719 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
1720 create_collect(b
, value
, 4), 0,
1721 create_collect(b
, coords
, ncoords
), 0,
1723 stib
->cat6
.iim_val
= 4;
1724 stib
->cat6
.d
= ncoords
;
1725 stib
->cat6
.type
= get_image_type(var
);
1726 stib
->cat6
.typed
= true;
1727 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1728 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1730 array_insert(b
, b
->keeps
, stib
);
1734 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1735 struct ir3_instruction
**dst
)
1737 struct ir3_block
*b
= ctx
->block
;
1738 const nir_variable
*var
= intr
->variables
[0]->var
;
1739 unsigned ncoords
= get_image_coords(var
);
1740 unsigned tex_idx
= get_image_slot(ctx
, var
);
1741 struct ir3_instruction
*sam
, *lod
;
1745 flags
= IR3_INSTR_3D
;
1747 lod
= create_immed(b
, 0);
1748 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1749 tex_idx
, tex_idx
, lod
, NULL
);
1751 split_dest(b
, dst
, sam
, 0, ncoords
);
1754 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
1755 static struct ir3_instruction
*
1756 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1758 struct ir3_block
*b
= ctx
->block
;
1759 const nir_variable
*var
= intr
->variables
[0]->var
;
1760 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
1761 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1762 unsigned ncoords
= get_image_coords(var
);
1764 image
= create_immed(b
, get_image_slot(ctx
, var
));
1766 /* src0 is value (or uvec2(value, compare))
1768 * src2 is 64b byte offset
1770 src0
= get_src(ctx
, &intr
->src
[2])[0];
1771 src1
= create_collect(b
, coords
, ncoords
);
1772 src2
= get_image_offset(ctx
, var
, coords
, false);
1774 switch (intr
->intrinsic
) {
1775 case nir_intrinsic_image_atomic_add
:
1776 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1778 case nir_intrinsic_image_atomic_min
:
1779 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1781 case nir_intrinsic_image_atomic_max
:
1782 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1784 case nir_intrinsic_image_atomic_and
:
1785 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1787 case nir_intrinsic_image_atomic_or
:
1788 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1790 case nir_intrinsic_image_atomic_xor
:
1791 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1793 case nir_intrinsic_image_atomic_exchange
:
1794 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1796 case nir_intrinsic_image_atomic_comp_swap
:
1797 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1798 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1800 get_src(ctx
, &intr
->src
[3])[0],
1802 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1808 atomic
->cat6
.iim_val
= 1;
1809 atomic
->cat6
.d
= ncoords
;
1810 atomic
->cat6
.type
= get_image_type(var
);
1811 atomic
->cat6
.typed
= true;
1812 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1813 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1815 /* even if nothing consume the result, we can't DCE the instruction: */
1816 array_insert(b
, b
->keeps
, atomic
);
1822 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1824 struct ir3_block
*b
= ctx
->block
;
1825 struct ir3_instruction
*barrier
;
1827 switch (intr
->intrinsic
) {
1828 case nir_intrinsic_barrier
:
1829 barrier
= ir3_BAR(b
);
1830 barrier
->cat7
.g
= true;
1831 barrier
->cat7
.l
= true;
1832 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1833 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1835 case nir_intrinsic_memory_barrier
:
1836 barrier
= ir3_FENCE(b
);
1837 barrier
->cat7
.g
= true;
1838 barrier
->cat7
.r
= true;
1839 barrier
->cat7
.w
= true;
1840 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1841 IR3_BARRIER_BUFFER_W
;
1842 barrier
->barrier_conflict
=
1843 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1844 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1846 case nir_intrinsic_memory_barrier_atomic_counter
:
1847 case nir_intrinsic_memory_barrier_buffer
:
1848 barrier
= ir3_FENCE(b
);
1849 barrier
->cat7
.g
= true;
1850 barrier
->cat7
.r
= true;
1851 barrier
->cat7
.w
= true;
1852 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1853 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1854 IR3_BARRIER_BUFFER_W
;
1856 case nir_intrinsic_memory_barrier_image
:
1857 // TODO double check if this should have .g set
1858 barrier
= ir3_FENCE(b
);
1859 barrier
->cat7
.g
= true;
1860 barrier
->cat7
.r
= true;
1861 barrier
->cat7
.w
= true;
1862 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1863 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1864 IR3_BARRIER_IMAGE_W
;
1866 case nir_intrinsic_memory_barrier_shared
:
1867 barrier
= ir3_FENCE(b
);
1868 barrier
->cat7
.g
= true;
1869 barrier
->cat7
.l
= true;
1870 barrier
->cat7
.r
= true;
1871 barrier
->cat7
.w
= true;
1872 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1873 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1874 IR3_BARRIER_SHARED_W
;
1876 case nir_intrinsic_group_memory_barrier
:
1877 barrier
= ir3_FENCE(b
);
1878 barrier
->cat7
.g
= true;
1879 barrier
->cat7
.l
= true;
1880 barrier
->cat7
.r
= true;
1881 barrier
->cat7
.w
= true;
1882 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1883 IR3_BARRIER_IMAGE_W
|
1884 IR3_BARRIER_BUFFER_W
;
1885 barrier
->barrier_conflict
=
1886 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1887 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1888 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1894 /* make sure barrier doesn't get DCE'd */
1895 array_insert(b
, b
->keeps
, barrier
);
1898 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1899 gl_system_value slot
, unsigned compmask
,
1900 struct ir3_instruction
*instr
)
1902 struct ir3_shader_variant
*so
= ctx
->so
;
1903 unsigned r
= regid(so
->inputs_count
, 0);
1904 unsigned n
= so
->inputs_count
++;
1906 so
->inputs
[n
].sysval
= true;
1907 so
->inputs
[n
].slot
= slot
;
1908 so
->inputs
[n
].compmask
= compmask
;
1909 so
->inputs
[n
].regid
= r
;
1910 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1913 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1914 ctx
->ir
->inputs
[r
] = instr
;
1917 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1918 struct ir3_instruction
*instr
)
1920 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1924 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1926 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1927 struct ir3_instruction
**dst
;
1928 struct ir3_instruction
* const *src
;
1929 struct ir3_block
*b
= ctx
->block
;
1930 nir_const_value
*const_offset
;
1933 if (info
->has_dest
) {
1935 if (info
->dest_components
)
1936 n
= info
->dest_components
;
1938 n
= intr
->num_components
;
1939 dst
= get_dst(ctx
, &intr
->dest
, n
);
1944 switch (intr
->intrinsic
) {
1945 case nir_intrinsic_load_uniform
:
1946 idx
= nir_intrinsic_base(intr
);
1947 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1949 idx
+= const_offset
->u32
[0];
1950 for (int i
= 0; i
< intr
->num_components
; i
++) {
1951 unsigned n
= idx
* 4 + i
;
1952 dst
[i
] = create_uniform(ctx
, n
);
1955 src
= get_src(ctx
, &intr
->src
[0]);
1956 for (int i
= 0; i
< intr
->num_components
; i
++) {
1957 int n
= idx
* 4 + i
;
1958 dst
[i
] = create_uniform_indirect(ctx
, n
,
1959 get_addr(ctx
, src
[0], 4));
1961 /* NOTE: if relative addressing is used, we set
1962 * constlen in the compiler (to worst-case value)
1963 * since we don't know in the assembler what the max
1964 * addr reg value can be:
1966 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1969 case nir_intrinsic_load_ubo
:
1970 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1972 case nir_intrinsic_load_input
:
1973 idx
= nir_intrinsic_base(intr
);
1974 comp
= nir_intrinsic_component(intr
);
1975 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1977 idx
+= const_offset
->u32
[0];
1978 for (int i
= 0; i
< intr
->num_components
; i
++) {
1979 unsigned n
= idx
* 4 + i
+ comp
;
1980 dst
[i
] = ctx
->ir
->inputs
[n
];
1983 src
= get_src(ctx
, &intr
->src
[0]);
1984 struct ir3_instruction
*collect
=
1985 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1986 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
1987 for (int i
= 0; i
< intr
->num_components
; i
++) {
1988 unsigned n
= idx
* 4 + i
+ comp
;
1989 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1994 case nir_intrinsic_load_ssbo
:
1995 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1997 case nir_intrinsic_store_ssbo
:
1998 emit_intrinsic_store_ssbo(ctx
, intr
);
2000 case nir_intrinsic_get_buffer_size
:
2001 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2003 case nir_intrinsic_ssbo_atomic_add
:
2004 case nir_intrinsic_ssbo_atomic_imin
:
2005 case nir_intrinsic_ssbo_atomic_umin
:
2006 case nir_intrinsic_ssbo_atomic_imax
:
2007 case nir_intrinsic_ssbo_atomic_umax
:
2008 case nir_intrinsic_ssbo_atomic_and
:
2009 case nir_intrinsic_ssbo_atomic_or
:
2010 case nir_intrinsic_ssbo_atomic_xor
:
2011 case nir_intrinsic_ssbo_atomic_exchange
:
2012 case nir_intrinsic_ssbo_atomic_comp_swap
:
2013 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2015 case nir_intrinsic_load_shared
:
2016 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2018 case nir_intrinsic_store_shared
:
2019 emit_intrinsic_store_shared(ctx
, intr
);
2021 case nir_intrinsic_shared_atomic_add
:
2022 case nir_intrinsic_shared_atomic_imin
:
2023 case nir_intrinsic_shared_atomic_umin
:
2024 case nir_intrinsic_shared_atomic_imax
:
2025 case nir_intrinsic_shared_atomic_umax
:
2026 case nir_intrinsic_shared_atomic_and
:
2027 case nir_intrinsic_shared_atomic_or
:
2028 case nir_intrinsic_shared_atomic_xor
:
2029 case nir_intrinsic_shared_atomic_exchange
:
2030 case nir_intrinsic_shared_atomic_comp_swap
:
2031 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2033 case nir_intrinsic_image_load
:
2034 emit_intrinsic_load_image(ctx
, intr
, dst
);
2036 case nir_intrinsic_image_store
:
2037 emit_intrinsic_store_image(ctx
, intr
);
2039 case nir_intrinsic_image_size
:
2040 emit_intrinsic_image_size(ctx
, intr
, dst
);
2042 case nir_intrinsic_image_atomic_add
:
2043 case nir_intrinsic_image_atomic_min
:
2044 case nir_intrinsic_image_atomic_max
:
2045 case nir_intrinsic_image_atomic_and
:
2046 case nir_intrinsic_image_atomic_or
:
2047 case nir_intrinsic_image_atomic_xor
:
2048 case nir_intrinsic_image_atomic_exchange
:
2049 case nir_intrinsic_image_atomic_comp_swap
:
2050 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2052 case nir_intrinsic_barrier
:
2053 case nir_intrinsic_memory_barrier
:
2054 case nir_intrinsic_group_memory_barrier
:
2055 case nir_intrinsic_memory_barrier_atomic_counter
:
2056 case nir_intrinsic_memory_barrier_buffer
:
2057 case nir_intrinsic_memory_barrier_image
:
2058 case nir_intrinsic_memory_barrier_shared
:
2059 emit_intrinsic_barrier(ctx
, intr
);
2060 /* note that blk ptr no longer valid, make that obvious: */
2063 case nir_intrinsic_store_output
:
2064 idx
= nir_intrinsic_base(intr
);
2065 comp
= nir_intrinsic_component(intr
);
2066 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2067 compile_assert(ctx
, const_offset
!= NULL
);
2068 idx
+= const_offset
->u32
[0];
2070 src
= get_src(ctx
, &intr
->src
[0]);
2071 for (int i
= 0; i
< intr
->num_components
; i
++) {
2072 unsigned n
= idx
* 4 + i
+ comp
;
2073 ctx
->ir
->outputs
[n
] = src
[i
];
2076 case nir_intrinsic_load_base_vertex
:
2077 if (!ctx
->basevertex
) {
2078 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2079 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
2082 dst
[0] = ctx
->basevertex
;
2084 case nir_intrinsic_load_vertex_id_zero_base
:
2085 case nir_intrinsic_load_vertex_id
:
2086 if (!ctx
->vertex_id
) {
2087 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2088 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2089 ctx
->vertex_id
= create_input(b
, 0);
2090 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2092 dst
[0] = ctx
->vertex_id
;
2094 case nir_intrinsic_load_instance_id
:
2095 if (!ctx
->instance_id
) {
2096 ctx
->instance_id
= create_input(b
, 0);
2097 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2100 dst
[0] = ctx
->instance_id
;
2102 case nir_intrinsic_load_user_clip_plane
:
2103 idx
= nir_intrinsic_ucp_id(intr
);
2104 for (int i
= 0; i
< intr
->num_components
; i
++) {
2105 unsigned n
= idx
* 4 + i
;
2106 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2109 case nir_intrinsic_load_front_face
:
2110 if (!ctx
->frag_face
) {
2111 ctx
->so
->frag_face
= true;
2112 ctx
->frag_face
= create_input(b
, 0);
2113 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2115 /* for fragface, we get -1 for back and 0 for front. However this is
2116 * the inverse of what nir expects (where ~0 is true).
2118 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2119 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2121 case nir_intrinsic_load_local_invocation_id
:
2122 if (!ctx
->local_invocation_id
) {
2123 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2124 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2125 0x7, ctx
->local_invocation_id
);
2127 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2129 case nir_intrinsic_load_work_group_id
:
2130 if (!ctx
->work_group_id
) {
2131 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2132 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2133 0x7, ctx
->work_group_id
);
2134 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2136 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2138 case nir_intrinsic_load_num_work_groups
:
2139 for (int i
= 0; i
< intr
->num_components
; i
++) {
2140 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2143 case nir_intrinsic_discard_if
:
2144 case nir_intrinsic_discard
: {
2145 struct ir3_instruction
*cond
, *kill
;
2147 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2148 /* conditional discard: */
2149 src
= get_src(ctx
, &intr
->src
[0]);
2150 cond
= ir3_b2n(b
, src
[0]);
2152 /* unconditional discard: */
2153 cond
= create_immed(b
, 1);
2156 /* NOTE: only cmps.*.* can write p0.x: */
2157 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2158 cond
->cat2
.condition
= IR3_COND_NE
;
2160 /* condition always goes in predicate register: */
2161 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2163 kill
= ir3_KILL(b
, cond
, 0);
2164 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2166 array_insert(b
, b
->keeps
, kill
);
2167 ctx
->so
->has_kill
= true;
2172 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2173 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2178 put_dst(ctx
, &intr
->dest
);
2182 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2184 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2185 instr
->def
.num_components
);
2186 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2187 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
2191 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2193 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2194 undef
->def
.num_components
);
2195 /* backend doesn't want undefined instructions, so just plug
2198 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2199 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
2203 * texture fetch/sample instructions:
2207 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2209 unsigned coords
, flags
= 0;
2211 /* note: would use tex->coord_components.. except txs.. also,
2212 * since array index goes after shadow ref, we don't want to
2215 switch (tex
->sampler_dim
) {
2216 case GLSL_SAMPLER_DIM_1D
:
2217 case GLSL_SAMPLER_DIM_BUF
:
2220 case GLSL_SAMPLER_DIM_2D
:
2221 case GLSL_SAMPLER_DIM_RECT
:
2222 case GLSL_SAMPLER_DIM_EXTERNAL
:
2223 case GLSL_SAMPLER_DIM_MS
:
2226 case GLSL_SAMPLER_DIM_3D
:
2227 case GLSL_SAMPLER_DIM_CUBE
:
2229 flags
|= IR3_INSTR_3D
;
2232 unreachable("bad sampler_dim");
2235 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2236 flags
|= IR3_INSTR_S
;
2238 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2239 flags
|= IR3_INSTR_A
;
2246 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2248 struct ir3_block
*b
= ctx
->block
;
2249 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2250 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2251 struct ir3_instruction
*lod
, *compare
, *proj
;
2252 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2253 unsigned i
, coords
, flags
;
2254 unsigned nsrc0
= 0, nsrc1
= 0;
2258 coord
= off
= ddx
= ddy
= NULL
;
2259 lod
= proj
= compare
= NULL
;
2261 /* TODO: might just be one component for gathers? */
2262 dst
= get_dst(ctx
, &tex
->dest
, 4);
2264 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2265 switch (tex
->src
[i
].src_type
) {
2266 case nir_tex_src_coord
:
2267 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2269 case nir_tex_src_bias
:
2270 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2273 case nir_tex_src_lod
:
2274 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2277 case nir_tex_src_comparator
: /* shadow comparator */
2278 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2280 case nir_tex_src_projector
:
2281 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2284 case nir_tex_src_offset
:
2285 off
= get_src(ctx
, &tex
->src
[i
].src
);
2288 case nir_tex_src_ddx
:
2289 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2291 case nir_tex_src_ddy
:
2292 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2295 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2296 tex
->src
[i
].src_type
);
2302 case nir_texop_tex
: opc
= OPC_SAM
; break;
2303 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2304 case nir_texop_txl
: opc
= OPC_SAML
; break;
2305 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2306 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2307 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2309 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2310 * what blob does, seems gather is broken?), and a3xx did
2311 * not support it (but probably could also emulate).
2313 switch (tex
->component
) {
2314 case 0: opc
= OPC_GATHER4R
; break;
2315 case 1: opc
= OPC_GATHER4G
; break;
2316 case 2: opc
= OPC_GATHER4B
; break;
2317 case 3: opc
= OPC_GATHER4A
; break;
2320 case nir_texop_txf_ms
:
2322 case nir_texop_query_levels
:
2323 case nir_texop_texture_samples
:
2324 case nir_texop_samples_identical
:
2325 case nir_texop_txf_ms_mcs
:
2326 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2330 tex_info(tex
, &flags
, &coords
);
2333 * lay out the first argument in the proper order:
2334 * - actual coordinates first
2335 * - shadow reference
2338 * - starting at offset 4, dpdx.xy, dpdy.xy
2340 * bias/lod go into the second arg
2343 /* insert tex coords: */
2344 for (i
= 0; i
< coords
; i
++)
2349 /* scale up integer coords for TXF based on the LOD */
2350 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2352 for (i
= 0; i
< coords
; i
++)
2353 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2357 /* hw doesn't do 1d, so we treat it as 2d with
2358 * height of 1, and patch up the y coord.
2359 * TODO: y coord should be (int)0 in some cases..
2361 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2364 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2365 src0
[nsrc0
++] = compare
;
2367 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2368 struct ir3_instruction
*idx
= coord
[coords
];
2370 /* the array coord for cube arrays needs 0.5 added to it */
2371 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2372 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2374 src0
[nsrc0
++] = idx
;
2378 src0
[nsrc0
++] = proj
;
2379 flags
|= IR3_INSTR_P
;
2382 /* pad to 4, then ddx/ddy: */
2383 if (tex
->op
== nir_texop_txd
) {
2385 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2386 for (i
= 0; i
< coords
; i
++)
2387 src0
[nsrc0
++] = ddx
[i
];
2389 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2390 for (i
= 0; i
< coords
; i
++)
2391 src0
[nsrc0
++] = ddy
[i
];
2393 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2397 * second argument (if applicable):
2402 if (has_off
| has_lod
| has_bias
) {
2404 unsigned off_coords
= coords
;
2405 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2407 for (i
= 0; i
< off_coords
; i
++)
2408 src1
[nsrc1
++] = off
[i
];
2410 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2411 flags
|= IR3_INSTR_O
;
2414 if (has_lod
| has_bias
)
2415 src1
[nsrc1
++] = lod
;
2418 switch (tex
->dest_type
) {
2419 case nir_type_invalid
:
2420 case nir_type_float
:
2431 unreachable("bad dest_type");
2434 if (opc
== OPC_GETLOD
)
2437 unsigned tex_idx
= tex
->texture_index
;
2439 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2441 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
2442 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
2444 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2445 tex_idx
, tex_idx
, col0
, col1
);
2447 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2448 /* only need first 3 components: */
2449 sam
->regs
[0]->wrmask
= 0x7;
2450 split_dest(b
, dst
, sam
, 0, 3);
2452 /* we need to sample the alpha separately with a non-ASTC
2455 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2456 tex_idx
, tex_idx
, col0
, col1
);
2458 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2460 /* fixup .w component: */
2461 split_dest(b
, &dst
[3], sam
, 3, 1);
2463 /* normal (non-workaround) case: */
2464 split_dest(b
, dst
, sam
, 0, 4);
2467 /* GETLOD returns results in 4.8 fixed point */
2468 if (opc
== OPC_GETLOD
) {
2469 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2471 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2472 for (i
= 0; i
< 2; i
++) {
2473 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2478 put_dst(ctx
, &tex
->dest
);
2482 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2484 struct ir3_block
*b
= ctx
->block
;
2485 struct ir3_instruction
**dst
, *sam
;
2487 dst
= get_dst(ctx
, &tex
->dest
, 1);
2489 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2490 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2492 /* even though there is only one component, since it ends
2493 * up in .z rather than .x, we need a split_dest()
2495 split_dest(b
, dst
, sam
, 0, 3);
2497 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2498 * the value in TEX_CONST_0 is zero-based.
2500 if (ctx
->levels_add_one
)
2501 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2503 put_dst(ctx
, &tex
->dest
);
2507 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2509 struct ir3_block
*b
= ctx
->block
;
2510 struct ir3_instruction
**dst
, *sam
;
2511 struct ir3_instruction
*lod
;
2512 unsigned flags
, coords
;
2514 tex_info(tex
, &flags
, &coords
);
2516 /* Actually we want the number of dimensions, not coordinates. This
2517 * distinction only matters for cubes.
2519 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2522 dst
= get_dst(ctx
, &tex
->dest
, 4);
2524 compile_assert(ctx
, tex
->num_srcs
== 1);
2525 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2527 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2529 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2530 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2532 split_dest(b
, dst
, sam
, 0, 4);
2534 /* Array size actually ends up in .w rather than .z. This doesn't
2535 * matter for miplevel 0, but for higher mips the value in z is
2536 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2537 * returned, which means that we have to add 1 to it for arrays.
2539 if (tex
->is_array
) {
2540 if (ctx
->levels_add_one
) {
2541 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2543 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2547 put_dst(ctx
, &tex
->dest
);
2551 emit_phi(struct ir3_context
*ctx
, nir_phi_instr
*nphi
)
2553 struct ir3_instruction
*phi
, **dst
;
2555 /* NOTE: phi's should be lowered to scalar at this point */
2556 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
2558 dst
= get_dst(ctx
, &nphi
->dest
, 1);
2560 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
2561 1 + exec_list_length(&nphi
->srcs
));
2562 ir3_reg_create(phi
, 0, 0); /* dst */
2563 phi
->phi
.nphi
= nphi
;
2567 put_dst(ctx
, &nphi
->dest
);
2570 /* phi instructions are left partially constructed. We don't resolve
2571 * their srcs until the end of the block, since (eg. loops) one of
2572 * the phi's srcs might be defined after the phi due to back edges in
2576 resolve_phis(struct ir3_context
*ctx
, struct ir3_block
*block
)
2578 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2579 nir_phi_instr
*nphi
;
2581 /* phi's only come at start of block: */
2582 if (instr
->opc
!= OPC_META_PHI
)
2585 if (!instr
->phi
.nphi
)
2588 nphi
= instr
->phi
.nphi
;
2589 instr
->phi
.nphi
= NULL
;
2591 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
2592 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
2594 /* NOTE: src might not be in the same block as it comes from
2595 * according to the phi.. but in the end the backend assumes
2596 * it will be able to assign the same register to each (which
2597 * only works if it is assigned in the src block), so insert
2598 * an extra mov to make sure the phi src is assigned in the
2599 * block it comes from:
2601 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
2603 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
2609 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2611 switch (jump
->type
) {
2612 case nir_jump_break
:
2613 case nir_jump_continue
:
2614 /* I *think* we can simply just ignore this, and use the
2615 * successor block link to figure out where we need to
2616 * jump to for break/continue
2620 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2626 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2628 switch (instr
->type
) {
2629 case nir_instr_type_alu
:
2630 emit_alu(ctx
, nir_instr_as_alu(instr
));
2632 case nir_instr_type_intrinsic
:
2633 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2635 case nir_instr_type_load_const
:
2636 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2638 case nir_instr_type_ssa_undef
:
2639 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2641 case nir_instr_type_tex
: {
2642 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2643 /* couple tex instructions get special-cased:
2647 emit_tex_txs(ctx
, tex
);
2649 case nir_texop_query_levels
:
2650 emit_tex_query_levels(ctx
, tex
);
2658 case nir_instr_type_phi
:
2659 emit_phi(ctx
, nir_instr_as_phi(instr
));
2661 case nir_instr_type_jump
:
2662 emit_jump(ctx
, nir_instr_as_jump(instr
));
2664 case nir_instr_type_call
:
2665 case nir_instr_type_parallel_copy
:
2666 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2671 static struct ir3_block
*
2672 get_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2674 struct ir3_block
*block
;
2675 struct hash_entry
*entry
;
2676 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2680 block
= ir3_block_create(ctx
->ir
);
2681 block
->nblock
= nblock
;
2682 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2688 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2690 struct ir3_block
*block
= get_block(ctx
, nblock
);
2692 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2693 if (nblock
->successors
[i
]) {
2694 block
->successors
[i
] =
2695 get_block(ctx
, nblock
->successors
[i
]);
2700 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2702 /* re-emit addr register in each block if needed: */
2703 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2704 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2705 ctx
->addr_ht
[i
] = NULL
;
2708 nir_foreach_instr(instr
, nblock
) {
2709 emit_instr(ctx
, instr
);
2715 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2718 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2720 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2722 ctx
->block
->condition
=
2723 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2725 emit_cf_list(ctx
, &nif
->then_list
);
2726 emit_cf_list(ctx
, &nif
->else_list
);
2730 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2732 emit_cf_list(ctx
, &nloop
->body
);
2736 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2738 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2739 switch (node
->type
) {
2740 case nir_cf_node_block
:
2741 emit_block(ctx
, nir_cf_node_as_block(node
));
2743 case nir_cf_node_if
:
2744 emit_if(ctx
, nir_cf_node_as_if(node
));
2746 case nir_cf_node_loop
:
2747 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2749 case nir_cf_node_function
:
2750 compile_error(ctx
, "TODO\n");
2756 /* emit stream-out code. At this point, the current block is the original
2757 * (nir) end block, and nir ensures that all flow control paths terminate
2758 * into the end block. We re-purpose the original end block to generate
2759 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2760 * block holding stream-out write instructions, followed by the new end
2764 * p0.x = (vtxcnt < maxvtxcnt)
2765 * // succs: blockStreamOut, blockNewEnd
2768 * ... stream-out instructions ...
2769 * // succs: blockNewEnd
2775 emit_stream_out(struct ir3_context
*ctx
)
2777 struct ir3_shader_variant
*v
= ctx
->so
;
2778 struct ir3
*ir
= ctx
->ir
;
2779 struct pipe_stream_output_info
*strmout
=
2780 &ctx
->so
->shader
->stream_output
;
2781 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2782 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2783 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2785 /* create vtxcnt input in input block at top of shader,
2786 * so that it is seen as live over the entire duration
2789 vtxcnt
= create_input(ctx
->in_block
, 0);
2790 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2792 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2794 /* at this point, we are at the original 'end' block,
2795 * re-purpose this block to stream-out condition, then
2796 * append stream-out block and new-end block
2798 orig_end_block
= ctx
->block
;
2800 stream_out_block
= ir3_block_create(ir
);
2801 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2803 new_end_block
= ir3_block_create(ir
);
2804 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2806 orig_end_block
->successors
[0] = stream_out_block
;
2807 orig_end_block
->successors
[1] = new_end_block
;
2808 stream_out_block
->successors
[0] = new_end_block
;
2810 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2811 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2812 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2813 cond
->cat2
.condition
= IR3_COND_LT
;
2815 /* condition goes on previous block to the conditional,
2816 * since it is used to pick which of the two successor
2819 orig_end_block
->condition
= cond
;
2821 /* switch to stream_out_block to generate the stream-out
2824 ctx
->block
= stream_out_block
;
2826 /* Calculate base addresses based on vtxcnt. Instructions
2827 * generated for bases not used in following loop will be
2828 * stripped out in the backend.
2830 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2831 unsigned stride
= strmout
->stride
[i
];
2832 struct ir3_instruction
*base
, *off
;
2834 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2836 /* 24-bit should be enough: */
2837 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2838 create_immed(ctx
->block
, stride
* 4), 0);
2840 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2843 /* Generate the per-output store instructions: */
2844 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2845 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2846 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2847 struct ir3_instruction
*base
, *out
, *stg
;
2849 base
= bases
[strmout
->output
[i
].output_buffer
];
2850 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2852 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2853 create_immed(ctx
->block
, 1), 0);
2854 stg
->cat6
.type
= TYPE_U32
;
2855 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2857 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2861 /* and finally switch to the new_end_block: */
2862 ctx
->block
= new_end_block
;
2866 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2868 nir_metadata_require(impl
, nir_metadata_block_index
);
2870 emit_cf_list(ctx
, &impl
->body
);
2871 emit_block(ctx
, impl
->end_block
);
2873 /* at this point, we should have a single empty block,
2874 * into which we emit the 'end' instruction.
2876 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2878 /* If stream-out (aka transform-feedback) enabled, emit the
2879 * stream-out instructions, followed by a new empty block (into
2880 * which the 'end' instruction lands).
2882 * NOTE: it is done in this order, rather than inserting before
2883 * we emit end_block, because NIR guarantees that all blocks
2884 * flow into end_block, and that end_block has no successors.
2885 * So by re-purposing end_block as the first block of stream-
2886 * out, we guarantee that all exit paths flow into the stream-
2889 if ((ctx
->compiler
->gpu_id
< 500) &&
2890 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2891 !ctx
->so
->key
.binning_pass
) {
2892 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2893 emit_stream_out(ctx
);
2896 ir3_END(ctx
->block
);
2900 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2902 struct ir3_shader_variant
*so
= ctx
->so
;
2903 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2904 unsigned ncomp
= glsl_get_components(in
->type
);
2905 unsigned n
= in
->data
.driver_location
;
2906 unsigned slot
= in
->data
.location
;
2908 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2909 slot
, array_len
, ncomp
, n
);
2911 /* let's pretend things other than vec4 don't exist: */
2912 ncomp
= MAX2(ncomp
, 4);
2913 compile_assert(ctx
, ncomp
== 4);
2915 so
->inputs
[n
].slot
= slot
;
2916 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2917 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2918 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2920 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2921 for (int i
= 0; i
< ncomp
; i
++) {
2922 struct ir3_instruction
*instr
= NULL
;
2923 unsigned idx
= (n
* 4) + i
;
2925 if (slot
== VARYING_SLOT_POS
) {
2926 so
->inputs
[n
].bary
= false;
2927 so
->frag_coord
= true;
2928 instr
= create_frag_coord(ctx
, i
);
2929 } else if (slot
== VARYING_SLOT_PNTC
) {
2930 /* see for example st_get_generic_varying_index().. this is
2931 * maybe a bit mesa/st specific. But we need things to line
2932 * up for this in fdN_program:
2933 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2934 * if (emit->sprite_coord_enable & texmask) {
2938 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2939 so
->inputs
[n
].bary
= true;
2940 instr
= create_frag_input(ctx
, false);
2942 bool use_ldlv
= false;
2944 /* detect the special case for front/back colors where
2945 * we need to do flat vs smooth shading depending on
2948 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2950 case VARYING_SLOT_COL0
:
2951 case VARYING_SLOT_COL1
:
2952 case VARYING_SLOT_BFC0
:
2953 case VARYING_SLOT_BFC1
:
2954 so
->inputs
[n
].rasterflat
= true;
2961 if (ctx
->flat_bypass
) {
2962 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2963 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2967 so
->inputs
[n
].bary
= true;
2969 instr
= create_frag_input(ctx
, use_ldlv
);
2972 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2974 ctx
->ir
->inputs
[idx
] = instr
;
2976 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2977 for (int i
= 0; i
< ncomp
; i
++) {
2978 unsigned idx
= (n
* 4) + i
;
2979 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2980 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2983 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2986 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2987 so
->total_in
+= ncomp
;
2992 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
2994 struct ir3_shader_variant
*so
= ctx
->so
;
2995 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2996 unsigned ncomp
= glsl_get_components(out
->type
);
2997 unsigned n
= out
->data
.driver_location
;
2998 unsigned slot
= out
->data
.location
;
3001 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3002 slot
, array_len
, ncomp
, n
);
3004 /* let's pretend things other than vec4 don't exist: */
3005 ncomp
= MAX2(ncomp
, 4);
3006 compile_assert(ctx
, ncomp
== 4);
3008 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3010 case FRAG_RESULT_DEPTH
:
3011 comp
= 2; /* tgsi will write to .z component */
3012 so
->writes_pos
= true;
3014 case FRAG_RESULT_COLOR
:
3018 if (slot
>= FRAG_RESULT_DATA0
)
3020 compile_error(ctx
, "unknown FS output name: %s\n",
3021 gl_frag_result_name(slot
));
3023 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3025 case VARYING_SLOT_POS
:
3026 so
->writes_pos
= true;
3028 case VARYING_SLOT_PSIZ
:
3029 so
->writes_psize
= true;
3031 case VARYING_SLOT_COL0
:
3032 case VARYING_SLOT_COL1
:
3033 case VARYING_SLOT_BFC0
:
3034 case VARYING_SLOT_BFC1
:
3035 case VARYING_SLOT_FOGC
:
3036 case VARYING_SLOT_CLIP_DIST0
:
3037 case VARYING_SLOT_CLIP_DIST1
:
3038 case VARYING_SLOT_CLIP_VERTEX
:
3041 if (slot
>= VARYING_SLOT_VAR0
)
3043 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3045 compile_error(ctx
, "unknown VS output name: %s\n",
3046 gl_varying_slot_name(slot
));
3049 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3052 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3054 so
->outputs
[n
].slot
= slot
;
3055 so
->outputs
[n
].regid
= regid(n
, comp
);
3056 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3058 for (int i
= 0; i
< ncomp
; i
++) {
3059 unsigned idx
= (n
* 4) + i
;
3060 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3061 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3066 max_drvloc(struct exec_list
*vars
)
3069 nir_foreach_variable(var
, vars
) {
3070 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3075 static const unsigned max_sysvals
[SHADER_MAX
] = {
3076 [SHADER_VERTEX
] = 16,
3077 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3081 emit_instructions(struct ir3_context
*ctx
)
3083 unsigned ninputs
, noutputs
;
3084 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3086 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3087 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3089 /* we need to leave room for sysvals:
3091 ninputs
+= max_sysvals
[ctx
->so
->type
];
3093 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3095 /* Create inputs in first block: */
3096 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3097 ctx
->in_block
= ctx
->block
;
3098 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3100 ninputs
-= max_sysvals
[ctx
->so
->type
];
3102 /* for fragment shader, we have a single input register (usually
3103 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3105 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3106 // TODO maybe a helper for fi since we need it a few places..
3107 struct ir3_instruction
*instr
;
3108 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3109 ir3_reg_create(instr
, 0, 0);
3110 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3111 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3112 ctx
->frag_pos
= instr
;
3116 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3117 setup_input(ctx
, var
);
3120 /* Setup outputs: */
3121 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3122 setup_output(ctx
, var
);
3125 /* Setup registers (which should only be arrays): */
3126 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3127 declare_array(ctx
, reg
);
3130 /* NOTE: need to do something more clever when we support >1 fxn */
3131 nir_foreach_register(reg
, &fxn
->registers
) {
3132 declare_array(ctx
, reg
);
3134 /* And emit the body: */
3136 emit_function(ctx
, fxn
);
3138 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
3139 resolve_phis(ctx
, block
);
3143 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3144 * for a fragment shader are just bary.f instructions. The *actual* inputs
3145 * from the hw perspective are the frag_pos and optionally frag_coord and
3149 fixup_frag_inputs(struct ir3_context
*ctx
)
3151 struct ir3_shader_variant
*so
= ctx
->so
;
3152 struct ir3
*ir
= ctx
->ir
;
3153 struct ir3_instruction
**inputs
;
3154 struct ir3_instruction
*instr
;
3159 n
= 4; /* always have frag_pos */
3160 n
+= COND(so
->frag_face
, 4);
3161 n
+= COND(so
->frag_coord
, 4);
3163 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3165 if (so
->frag_face
) {
3166 /* this ultimately gets assigned to hr0.x so doesn't conflict
3167 * with frag_coord/frag_pos..
3169 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3170 ctx
->frag_face
->regs
[0]->num
= 0;
3172 /* remaining channels not used, but let's avoid confusing
3173 * other parts that expect inputs to come in groups of vec4
3175 inputs
[ir
->ninputs
++] = NULL
;
3176 inputs
[ir
->ninputs
++] = NULL
;
3177 inputs
[ir
->ninputs
++] = NULL
;
3180 /* since we don't know where to set the regid for frag_coord,
3181 * we have to use r0.x for it. But we don't want to *always*
3182 * use r1.x for frag_pos as that could increase the register
3183 * footprint on simple shaders:
3185 if (so
->frag_coord
) {
3186 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3187 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3188 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3189 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3191 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3192 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3193 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3194 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3197 /* we always have frag_pos: */
3198 so
->pos_regid
= regid
;
3201 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3202 instr
->regs
[0]->num
= regid
++;
3203 inputs
[ir
->ninputs
++] = instr
;
3204 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3207 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3208 instr
->regs
[0]->num
= regid
++;
3209 inputs
[ir
->ninputs
++] = instr
;
3210 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3212 ir
->inputs
= inputs
;
3215 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3216 * need to assign the tex state indexes for these after we know the
3220 fixup_astc_srgb(struct ir3_context
*ctx
)
3222 struct ir3_shader_variant
*so
= ctx
->so
;
3223 /* indexed by original tex idx, value is newly assigned alpha sampler
3224 * state tex idx. Zero is invalid since there is at least one sampler
3227 unsigned alt_tex_state
[16] = {0};
3228 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3231 so
->astc_srgb
.base
= tex_idx
;
3233 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3234 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3236 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3238 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3239 /* assign new alternate/alpha tex state slot: */
3240 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3241 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3242 so
->astc_srgb
.count
++;
3245 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3250 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3251 struct ir3_shader_variant
*so
)
3253 struct ir3_context
*ctx
;
3255 struct ir3_instruction
**inputs
;
3256 unsigned i
, j
, actual_in
, inloc
;
3257 int ret
= 0, max_bary
;
3261 ctx
= compile_init(compiler
, so
);
3263 DBG("INIT failed!");
3268 emit_instructions(ctx
);
3271 DBG("EMIT failed!");
3276 ir
= so
->ir
= ctx
->ir
;
3278 /* keep track of the inputs from TGSI perspective.. */
3279 inputs
= ir
->inputs
;
3281 /* but fixup actual inputs for frag shader: */
3282 if (so
->type
== SHADER_FRAGMENT
)
3283 fixup_frag_inputs(ctx
);
3285 /* at this point, for binning pass, throw away unneeded outputs: */
3286 if (so
->key
.binning_pass
) {
3287 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3288 unsigned slot
= so
->outputs
[i
].slot
;
3290 /* throw away everything but first position/psize */
3291 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3293 so
->outputs
[j
] = so
->outputs
[i
];
3294 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3295 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3296 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3297 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3302 so
->outputs_count
= j
;
3303 ir
->noutputs
= j
* 4;
3306 /* if we want half-precision outputs, mark the output registers
3309 if (so
->key
.half_precision
) {
3310 for (i
= 0; i
< ir
->noutputs
; i
++) {
3311 struct ir3_instruction
*out
= ir
->outputs
[i
];
3316 /* if frag shader writes z, that needs to be full precision: */
3317 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3320 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3321 /* output could be a fanout (ie. texture fetch output)
3322 * in which case we need to propagate the half-reg flag
3323 * up to the definer so that RA sees it:
3325 if (out
->opc
== OPC_META_FO
) {
3326 out
= out
->regs
[1]->instr
;
3327 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3330 if (out
->opc
== OPC_MOV
) {
3331 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3336 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3337 printf("BEFORE CP:\n");
3343 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3344 printf("BEFORE GROUPING:\n");
3348 ir3_sched_add_deps(ir
);
3350 /* Group left/right neighbors, inserting mov's where needed to
3357 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3358 printf("AFTER DEPTH:\n");
3362 ret
= ir3_sched(ir
);
3364 DBG("SCHED failed!");
3368 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3369 printf("AFTER SCHED:\n");
3373 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3379 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3380 printf("AFTER RA:\n");
3384 /* fixup input/outputs: */
3385 for (i
= 0; i
< so
->outputs_count
; i
++) {
3386 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3389 /* Note that some or all channels of an input may be unused: */
3392 for (i
= 0; i
< so
->inputs_count
; i
++) {
3393 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3394 so
->inputs
[i
].ncomp
= 0;
3395 so
->inputs
[i
].inloc
= inloc
;
3396 for (j
= 0; j
< 4; j
++) {
3397 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3398 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3399 compmask
|= (1 << j
);
3400 regid
= in
->regs
[0]->num
- j
;
3402 so
->inputs
[i
].ncomp
++;
3403 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3405 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3406 in
->regs
[1]->iim_val
= inloc
+ j
;
3411 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3413 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3416 so
->inputs
[i
].compmask
= compmask
;
3418 so
->inputs
[i
].regid
= regid
;
3422 fixup_astc_srgb(ctx
);
3424 /* We need to do legalize after (for frag shader's) the "bary.f"
3425 * offsets (inloc) have been assigned.
3427 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3429 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3430 printf("AFTER LEGALIZE:\n");
3434 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3435 if (so
->type
== SHADER_VERTEX
)
3436 so
->total_in
= actual_in
;
3438 so
->total_in
= max_bary
+ 1;
3443 ir3_destroy(so
->ir
);