1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* For fragment shaders: */
75 struct ir3_instruction
*samp_id
, *samp_mask_in
;
77 /* Compute shader inputs: */
78 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
85 /* a common pattern for indirect addressing is to request the
86 * same address register multiple times. To avoid generating
87 * duplicate instruction sequences (which our backend does not
88 * try to clean up, since that should be done as the NIR stage)
89 * we cache the address value generated for a given src value:
91 * Note that we have to cache these per alignment, since same
92 * src used for an array of vec1 cannot be also used for an
95 struct hash_table
*addr_ht
[4];
97 /* last dst array, for indirect we need to insert a var-store.
99 struct ir3_instruction
**last_dst
;
102 /* maps nir_block to ir3_block, mostly for the purposes of
103 * figuring out the blocks successors
105 struct hash_table
*block_ht
;
107 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
108 * so we need to use ldlv.u32 to load the varying directly:
112 /* on a3xx, we need to add one to # of array levels:
116 /* on a3xx, we need to scale up integer coords for isaml based
119 bool unminify_coords
;
121 /* on a3xx do txf_ms w/ isaml and scaled coords: */
122 bool txf_ms_with_isaml
;
124 /* on a4xx, for array textures we need to add 0.5 to the array
127 bool array_index_add_half
;
129 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
132 unsigned samples
; /* bitmask of x,y sample shifts */
134 unsigned max_texture_index
;
136 /* set if we encounter something we can't handle yet, so we
137 * can bail cleanly and fallback to TGSI compiler f/e
142 /* gpu pointer size in units of 32bit registers/slots */
143 static unsigned pointer_size(struct ir3_context
*ctx
)
145 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
148 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
149 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
152 static struct ir3_context
*
153 compile_init(struct ir3_compiler
*compiler
,
154 struct ir3_shader_variant
*so
)
156 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
158 if (compiler
->gpu_id
>= 400) {
159 /* need special handling for "flat" */
160 ctx
->flat_bypass
= true;
161 ctx
->levels_add_one
= false;
162 ctx
->unminify_coords
= false;
163 ctx
->txf_ms_with_isaml
= false;
164 ctx
->array_index_add_half
= true;
166 if (so
->type
== SHADER_VERTEX
) {
167 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
168 } else if (so
->type
== SHADER_FRAGMENT
) {
169 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
173 /* no special handling for "flat" */
174 ctx
->flat_bypass
= false;
175 ctx
->levels_add_one
= true;
176 ctx
->unminify_coords
= true;
177 ctx
->txf_ms_with_isaml
= true;
178 ctx
->array_index_add_half
= false;
180 if (so
->type
== SHADER_VERTEX
) {
181 ctx
->samples
= so
->key
.vsamples
;
182 } else if (so
->type
== SHADER_FRAGMENT
) {
183 ctx
->samples
= so
->key
.fsamples
;
187 ctx
->compiler
= compiler
;
189 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
190 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
191 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
192 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
194 /* TODO: maybe generate some sort of bitmask of what key
195 * lowers vs what shader has (ie. no need to lower
196 * texture clamp lowering if no texture sample instrs)..
197 * although should be done further up the stack to avoid
198 * creating duplicate variants..
201 if (ir3_key_lowers_nir(&so
->key
)) {
202 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
203 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
205 /* fast-path for shader key that lowers nothing in NIR: */
206 ctx
->s
= so
->shader
->nir
;
209 /* this needs to be the last pass run, so do this here instead of
210 * in ir3_optimize_nir():
212 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
213 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
215 if (fd_mesa_debug
& FD_DBG_DISASM
) {
216 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
217 so
->shader
->id
, so
->id
, so
->type
,
218 so
->key
.binning_pass
, so
->key
.color_two_side
,
219 so
->key
.half_precision
);
220 nir_print_shader(ctx
->s
, stdout
);
223 if (shader_debug_enabled(so
->type
)) {
224 fprintf(stderr
, "NIR (final form) for %s shader:\n",
225 shader_stage_name(so
->type
));
226 nir_print_shader(ctx
->s
, stderr
);
229 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
231 so
->num_uniforms
= ctx
->s
->num_uniforms
;
232 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
234 /* Layout of constant registers, each section aligned to vec4. Note
235 * that pointer size (ubo, etc) changes depending on generation.
240 * if (vertex shader) {
241 * driver params (IR3_DP_*)
242 * if (stream_output.num_outputs > 0)
243 * stream-out addresses
247 * Immediates go last mostly because they are inserted in the CP pass
248 * after the nir -> ir3 frontend.
250 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
251 unsigned ptrsz
= pointer_size(ctx
);
253 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
255 if (so
->num_ubos
> 0) {
256 so
->constbase
.ubo
= constoff
;
257 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
260 if (so
->const_layout
.ssbo_size
.count
> 0) {
261 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
262 so
->constbase
.ssbo_sizes
= constoff
;
263 constoff
+= align(cnt
, 4) / 4;
266 if (so
->const_layout
.image_dims
.count
> 0) {
267 unsigned cnt
= so
->const_layout
.image_dims
.count
;
268 so
->constbase
.image_dims
= constoff
;
269 constoff
+= align(cnt
, 4) / 4;
272 unsigned num_driver_params
= 0;
273 if (so
->type
== SHADER_VERTEX
) {
274 num_driver_params
= IR3_DP_VS_COUNT
;
275 } else if (so
->type
== SHADER_COMPUTE
) {
276 num_driver_params
= IR3_DP_CS_COUNT
;
279 so
->constbase
.driver_param
= constoff
;
280 constoff
+= align(num_driver_params
, 4) / 4;
282 if ((so
->type
== SHADER_VERTEX
) &&
283 (compiler
->gpu_id
< 500) &&
284 so
->shader
->stream_output
.num_outputs
> 0) {
285 so
->constbase
.tfbo
= constoff
;
286 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
289 so
->constbase
.immediate
= constoff
;
295 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
298 va_start(ap
, format
);
299 _debug_vprintf(format
, ap
);
301 nir_print_shader(ctx
->s
, stdout
);
306 #define compile_assert(ctx, cond) do { \
307 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
311 compile_free(struct ir3_context
*ctx
)
317 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
319 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
320 arr
->id
= ++ctx
->num_arrays
;
321 /* NOTE: sometimes we get non array regs, for example for arrays of
322 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
323 * treat a non-array as if it was an array of length 1.
325 * It would be nice if there was a nir pass to convert arrays of
328 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
329 compile_assert(ctx
, arr
->length
> 0);
331 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
334 static struct ir3_array
*
335 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
337 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
341 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
345 /* relative (indirect) if address!=NULL */
346 static struct ir3_instruction
*
347 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
348 struct ir3_instruction
*address
)
350 struct ir3_block
*block
= ctx
->block
;
351 struct ir3_instruction
*mov
;
352 struct ir3_register
*src
;
354 mov
= ir3_instr_create(block
, OPC_MOV
);
355 mov
->cat1
.src_type
= TYPE_U32
;
356 mov
->cat1
.dst_type
= TYPE_U32
;
357 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
358 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
359 ir3_reg_create(mov
, 0, 0);
360 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
361 COND(address
, IR3_REG_RELATIV
));
362 src
->instr
= arr
->last_write
;
363 src
->size
= arr
->length
;
364 src
->array
.id
= arr
->id
;
365 src
->array
.offset
= n
;
368 ir3_instr_set_address(mov
, address
);
373 /* relative (indirect) if address!=NULL */
375 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
376 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
378 struct ir3_block
*block
= ctx
->block
;
379 struct ir3_instruction
*mov
;
380 struct ir3_register
*dst
;
382 /* if not relative store, don't create an extra mov, since that
383 * ends up being difficult for cp to remove.
388 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
389 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
391 dst
->flags
|= IR3_REG_ARRAY
;
392 dst
->instr
= arr
->last_write
;
393 dst
->size
= arr
->length
;
394 dst
->array
.id
= arr
->id
;
395 dst
->array
.offset
= n
;
397 arr
->last_write
= src
;
399 array_insert(block
, block
->keeps
, src
);
404 mov
= ir3_instr_create(block
, OPC_MOV
);
405 mov
->cat1
.src_type
= TYPE_U32
;
406 mov
->cat1
.dst_type
= TYPE_U32
;
407 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
408 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
409 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
410 COND(address
, IR3_REG_RELATIV
));
411 dst
->instr
= arr
->last_write
;
412 dst
->size
= arr
->length
;
413 dst
->array
.id
= arr
->id
;
414 dst
->array
.offset
= n
;
415 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
418 ir3_instr_set_address(mov
, address
);
420 arr
->last_write
= mov
;
422 /* the array store may only matter to something in an earlier
423 * block (ie. loops), but since arrays are not in SSA, depth
424 * pass won't know this.. so keep all array stores:
426 array_insert(block
, block
->keeps
, mov
);
429 static inline type_t
utype_for_size(unsigned bit_size
)
432 case 32: return TYPE_U32
;
433 case 16: return TYPE_U16
;
434 case 8: return TYPE_U8
;
435 default: unreachable("bad bitsize"); return ~0;
439 static inline type_t
utype_src(nir_src src
)
440 { return utype_for_size(nir_src_bit_size(src
)); }
442 static inline type_t
utype_dst(nir_dest dst
)
443 { return utype_for_size(nir_dest_bit_size(dst
)); }
445 /* allocate a n element value array (to be populated by caller) and
448 static struct ir3_instruction
**
449 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
451 struct ir3_instruction
**value
=
452 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
453 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
457 static struct ir3_instruction
**
458 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
460 struct ir3_instruction
**value
;
463 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
465 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
468 /* NOTE: in non-ssa case, we don't really need to store last_dst
469 * but this helps us catch cases where put_dst() call is forgotten
471 compile_assert(ctx
, !ctx
->last_dst
);
472 ctx
->last_dst
= value
;
478 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
480 static struct ir3_instruction
* const *
481 get_src(struct ir3_context
*ctx
, nir_src
*src
)
484 struct hash_entry
*entry
;
485 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
486 compile_assert(ctx
, entry
);
489 nir_register
*reg
= src
->reg
.reg
;
490 struct ir3_array
*arr
= get_array(ctx
, reg
);
491 unsigned num_components
= arr
->r
->num_components
;
492 struct ir3_instruction
*addr
= NULL
;
493 struct ir3_instruction
**value
=
494 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
496 if (src
->reg
.indirect
)
497 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
498 reg
->num_components
);
500 for (unsigned i
= 0; i
< num_components
; i
++) {
501 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
502 compile_assert(ctx
, n
< arr
->length
);
503 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
511 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
513 unsigned bit_size
= nir_dest_bit_size(*dst
);
516 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
517 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
518 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
519 if (ctx
->last_dst
[i
]->opc
== OPC_META_FO
)
520 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
525 nir_register
*reg
= dst
->reg
.reg
;
526 struct ir3_array
*arr
= get_array(ctx
, reg
);
527 unsigned num_components
= ctx
->last_dst_n
;
528 struct ir3_instruction
*addr
= NULL
;
530 if (dst
->reg
.indirect
)
531 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
532 reg
->num_components
);
534 for (unsigned i
= 0; i
< num_components
; i
++) {
535 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
536 compile_assert(ctx
, n
< arr
->length
);
537 if (!ctx
->last_dst
[i
])
539 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
542 ralloc_free(ctx
->last_dst
);
544 ctx
->last_dst
= NULL
;
548 static struct ir3_instruction
*
549 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
551 struct ir3_instruction
*mov
;
552 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
554 mov
= ir3_instr_create(block
, OPC_MOV
);
555 mov
->cat1
.src_type
= type
;
556 mov
->cat1
.dst_type
= type
;
557 ir3_reg_create(mov
, 0, flags
);
558 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
563 static struct ir3_instruction
*
564 create_immed(struct ir3_block
*block
, uint32_t val
)
566 return create_immed_typed(block
, val
, TYPE_U32
);
569 static struct ir3_instruction
*
570 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
572 struct ir3_instruction
*instr
, *immed
;
574 /* TODO in at least some cases, the backend could probably be
575 * made clever enough to propagate IR3_REG_HALF..
577 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
578 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
585 /* src *= 2 => src <<= 1: */
586 immed
= create_immed(block
, 1);
587 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
589 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
590 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
591 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
595 immed
= create_immed(block
, 3);
596 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
598 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
599 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
600 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
603 /* src *= 4 => src <<= 2: */
604 immed
= create_immed(block
, 2);
605 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
607 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
608 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
609 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
612 unreachable("bad align");
616 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
617 instr
->regs
[0]->num
= regid(REG_A0
, 0);
618 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
619 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
624 /* caches addr values to avoid generating multiple cov/shl/mova
625 * sequences for each use of a given NIR level src as address
627 static struct ir3_instruction
*
628 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
630 struct ir3_instruction
*addr
;
631 unsigned idx
= align
- 1;
633 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
635 if (!ctx
->addr_ht
[idx
]) {
636 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
637 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
639 struct hash_entry
*entry
;
640 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
645 addr
= create_addr(ctx
->block
, src
, align
);
646 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
651 static struct ir3_instruction
*
652 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
654 struct ir3_block
*b
= ctx
->block
;
655 struct ir3_instruction
*cond
;
657 /* NOTE: only cmps.*.* can write p0.x: */
658 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
659 cond
->cat2
.condition
= IR3_COND_NE
;
661 /* condition always goes in predicate register: */
662 cond
->regs
[0]->num
= regid(REG_P0
, 0);
667 static struct ir3_instruction
*
668 create_uniform(struct ir3_context
*ctx
, unsigned n
)
670 struct ir3_instruction
*mov
;
672 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
673 /* TODO get types right? */
674 mov
->cat1
.src_type
= TYPE_F32
;
675 mov
->cat1
.dst_type
= TYPE_F32
;
676 ir3_reg_create(mov
, 0, 0);
677 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
682 static struct ir3_instruction
*
683 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
684 struct ir3_instruction
*address
)
686 struct ir3_instruction
*mov
;
688 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
689 mov
->cat1
.src_type
= TYPE_U32
;
690 mov
->cat1
.dst_type
= TYPE_U32
;
691 ir3_reg_create(mov
, 0, 0);
692 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
694 ir3_instr_set_address(mov
, address
);
699 static struct ir3_instruction
*
700 create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
703 struct ir3_block
*block
= ctx
->block
;
704 struct ir3_instruction
*collect
;
709 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
711 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
712 ir3_reg_create(collect
, 0, flags
); /* dst */
713 for (unsigned i
= 0; i
< arrsz
; i
++) {
714 struct ir3_instruction
*elem
= arr
[i
];
716 /* Since arrays are pre-colored in RA, we can't assume that
717 * things will end up in the right place. (Ie. if a collect
718 * joins elements from two different arrays.) So insert an
721 * We could possibly skip this if all the collected elements
722 * are contiguous elements in a single array.. not sure how
723 * likely that is to happen.
725 * Fixes a problem with glamor shaders, that in effect do
732 * color = texture2D(tex, texcoord);
734 * In this case, texcoord will end up as nir registers (which
735 * translate to ir3 array's of length 1. And we can't assume
736 * the two (or more) arrays will get allocated in consecutive
740 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
741 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
742 elem
= ir3_MOV(block
, elem
, type
);
745 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
746 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
752 static struct ir3_instruction
*
753 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
754 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
756 struct ir3_block
*block
= ctx
->block
;
757 struct ir3_instruction
*mov
;
758 struct ir3_register
*src
;
760 mov
= ir3_instr_create(block
, OPC_MOV
);
761 mov
->cat1
.src_type
= TYPE_U32
;
762 mov
->cat1
.dst_type
= TYPE_U32
;
763 ir3_reg_create(mov
, 0, 0);
764 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
765 src
->instr
= collect
;
767 src
->array
.offset
= n
;
769 ir3_instr_set_address(mov
, address
);
774 static struct ir3_instruction
*
775 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
777 struct ir3_instruction
*in
;
779 in
= ir3_instr_create(block
, OPC_META_INPUT
);
780 in
->inout
.block
= block
;
781 ir3_reg_create(in
, n
, 0);
783 in
->regs
[0]->wrmask
= compmask
;
788 static struct ir3_instruction
*
789 create_input(struct ir3_block
*block
, unsigned n
)
791 return create_input_compmask(block
, n
, 0x1);
794 static struct ir3_instruction
*
795 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
797 struct ir3_block
*block
= ctx
->block
;
798 struct ir3_instruction
*instr
;
799 /* actual inloc is assigned and fixed up later: */
800 struct ir3_instruction
*inloc
= create_immed(block
, 0);
803 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
804 instr
->cat6
.type
= TYPE_U32
;
805 instr
->cat6
.iim_val
= 1;
807 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
808 instr
->regs
[2]->wrmask
= 0x3;
814 static struct ir3_instruction
*
815 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
817 struct ir3_block
*block
= ctx
->block
;
818 struct ir3_instruction
*instr
;
820 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
822 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
827 /* for frag_coord, we get unsigned values.. we need
828 * to subtract (integer) 8 and divide by 16 (right-
829 * shift by 4) then convert to float:
833 * mov.u32f32 dst, tmp
836 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
837 create_immed(block
, 8), 0);
838 instr
= ir3_SHR_B(block
, instr
, 0,
839 create_immed(block
, 4), 0);
840 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
846 /* seems that we can use these as-is: */
847 return ctx
->frag_coord
[comp
];
851 static struct ir3_instruction
*
852 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
854 /* first four vec4 sysval's reserved for UBOs: */
855 /* NOTE: dp is in scalar, but there can be >4 dp components: */
856 unsigned n
= ctx
->so
->constbase
.driver_param
;
857 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
858 return create_uniform(ctx
, r
);
861 /* helper for instructions that produce multiple consecutive scalar
862 * outputs which need to have a split/fanout meta instruction inserted
865 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
866 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
868 struct ir3_instruction
*prev
= NULL
;
870 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
875 for (int i
= 0, j
= 0; i
< n
; i
++) {
876 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
877 ir3_reg_create(split
, 0, IR3_REG_SSA
);
878 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
879 split
->fo
.off
= i
+ base
;
882 split
->cp
.left
= prev
;
883 split
->cp
.left_cnt
++;
884 prev
->cp
.right
= split
;
885 prev
->cp
.right_cnt
++;
889 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
895 * Adreno uses uint rather than having dedicated bool type,
896 * which (potentially) requires some conversion, in particular
897 * when using output of an bool instr to int input, or visa
901 * -------+---------+-------+-
905 * To convert from an adreno bool (uint) to nir, use:
907 * absneg.s dst, (neg)src
909 * To convert back in the other direction:
911 * absneg.s dst, (abs)arc
913 * The CP step can clean up the absneg.s that cancel each other
914 * out, and with a slight bit of extra cleverness (to recognize
915 * the instructions which produce either a 0 or 1) can eliminate
916 * the absneg.s's completely when an instruction that wants
917 * 0/1 consumes the result. For example, when a nir 'bcsel'
918 * consumes the result of 'feq'. So we should be able to get by
919 * without a boolean resolve step, and without incuring any
920 * extra penalty in instruction count.
923 /* NIR bool -> native (adreno): */
924 static struct ir3_instruction
*
925 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
927 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
930 /* native (adreno) -> NIR bool: */
931 static struct ir3_instruction
*
932 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
934 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
938 * alu/sfu instructions:
941 static struct ir3_instruction
*
942 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
943 unsigned src_bitsize
, nir_op op
)
945 type_t src_type
, dst_type
;
949 case nir_op_f2f16_rtne
:
950 case nir_op_f2f16_rtz
:
958 switch (src_bitsize
) {
966 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
975 switch (src_bitsize
) {
986 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
995 switch (src_bitsize
) {
1000 src_type
= TYPE_U16
;
1006 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
1011 compile_error(ctx
, "invalid conversion op: %u", op
);
1018 dst_type
= TYPE_F32
;
1021 case nir_op_f2f16_rtne
:
1022 case nir_op_f2f16_rtz
:
1024 /* TODO how to handle rounding mode? */
1027 dst_type
= TYPE_F16
;
1032 dst_type
= TYPE_S32
;
1037 dst_type
= TYPE_S16
;
1047 dst_type
= TYPE_U32
;
1052 dst_type
= TYPE_U16
;
1061 compile_error(ctx
, "invalid conversion op: %u", op
);
1064 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
1068 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
1070 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1071 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
1072 unsigned bs
[info
->num_inputs
]; /* bit size */
1073 struct ir3_block
*b
= ctx
->block
;
1074 unsigned dst_sz
, wrmask
;
1076 if (alu
->dest
.dest
.is_ssa
) {
1077 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
1078 wrmask
= (1 << dst_sz
) - 1;
1080 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
1081 wrmask
= alu
->dest
.write_mask
;
1084 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
1086 /* Vectors are special in that they have non-scalarized writemasks,
1087 * and just take the first swizzle channel for each argument in
1088 * order into each writemask channel.
1090 if ((alu
->op
== nir_op_vec2
) ||
1091 (alu
->op
== nir_op_vec3
) ||
1092 (alu
->op
== nir_op_vec4
)) {
1094 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1095 nir_alu_src
*asrc
= &alu
->src
[i
];
1097 compile_assert(ctx
, !asrc
->abs
);
1098 compile_assert(ctx
, !asrc
->negate
);
1100 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
1102 src
[i
] = create_immed(ctx
->block
, 0);
1103 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
1106 put_dst(ctx
, &alu
->dest
.dest
);
1110 /* We also get mov's with more than one component for mov's so
1111 * handle those specially:
1113 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
1114 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
1115 nir_alu_src
*asrc
= &alu
->src
[0];
1116 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
1118 for (unsigned i
= 0; i
< dst_sz
; i
++) {
1119 if (wrmask
& (1 << i
)) {
1120 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
1126 put_dst(ctx
, &alu
->dest
.dest
);
1130 /* General case: We can just grab the one used channel per src. */
1131 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1132 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
1133 nir_alu_src
*asrc
= &alu
->src
[i
];
1135 compile_assert(ctx
, !asrc
->abs
);
1136 compile_assert(ctx
, !asrc
->negate
);
1138 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
1139 bs
[i
] = nir_src_bit_size(asrc
->src
);
1141 compile_assert(ctx
, src
[i
]);
1146 case nir_op_f2f16_rtne
:
1147 case nir_op_f2f16_rtz
:
1165 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
1168 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
1169 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1170 dst
[0] = ir3_n2b(b
, dst
[0]);
1173 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
1176 dst
[0] = ir3_b2n(b
, src
[0]);
1179 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1180 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1181 dst
[0] = ir3_n2b(b
, dst
[0]);
1185 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1188 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1191 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1194 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1197 /* if there is just a single use of the src, and it supports
1198 * (sat) bit, we can just fold the (sat) flag back to the
1199 * src instruction and create a mov. This is easier for cp
1202 * TODO probably opc_cat==4 is ok too
1204 if (alu
->src
[0].src
.is_ssa
&&
1205 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
1206 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
1207 src
[0]->flags
|= IR3_INSTR_SAT
;
1208 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
1210 /* otherwise generate a max.f that saturates.. blob does
1211 * similar (generating a cat2 mov using max.f)
1213 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
1214 dst
[0]->flags
|= IR3_INSTR_SAT
;
1218 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1221 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1224 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1227 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1230 dst
[0] = ir3_DSX(b
, src
[0], 0);
1231 dst
[0]->cat5
.type
= TYPE_F32
;
1234 dst
[0] = ir3_DSY(b
, src
[0], 0);
1235 dst
[0]->cat5
.type
= TYPE_F32
;
1239 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1240 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1241 dst
[0] = ir3_n2b(b
, dst
[0]);
1244 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1245 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1246 dst
[0] = ir3_n2b(b
, dst
[0]);
1249 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1250 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1251 dst
[0] = ir3_n2b(b
, dst
[0]);
1254 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1255 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1256 dst
[0] = ir3_n2b(b
, dst
[0]);
1259 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1262 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1265 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1267 case nir_op_fround_even
:
1268 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1271 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1275 dst
[0] = ir3_SIN(b
, src
[0], 0);
1278 dst
[0] = ir3_COS(b
, src
[0], 0);
1281 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1284 dst
[0] = ir3_RCP(b
, src
[0], 0);
1287 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1290 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1293 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1297 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1300 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1303 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1306 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1309 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1312 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1315 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1319 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1320 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1321 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1322 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1324 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1325 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1326 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1329 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1332 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1335 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1338 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1341 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1343 case nir_op_isign
: {
1344 /* maybe this would be sane to lower in nir.. */
1345 struct ir3_instruction
*neg
, *pos
;
1347 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1348 neg
->cat2
.condition
= IR3_COND_LT
;
1350 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1351 pos
->cat2
.condition
= IR3_COND_GT
;
1353 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1358 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1361 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1364 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1367 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1368 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1369 dst
[0] = ir3_n2b(b
, dst
[0]);
1372 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1373 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1374 dst
[0] = ir3_n2b(b
, dst
[0]);
1377 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1378 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1379 dst
[0] = ir3_n2b(b
, dst
[0]);
1382 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1383 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1384 dst
[0] = ir3_n2b(b
, dst
[0]);
1387 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1388 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1389 dst
[0] = ir3_n2b(b
, dst
[0]);
1392 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1393 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1394 dst
[0] = ir3_n2b(b
, dst
[0]);
1397 case nir_op_bcsel
: {
1398 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
1399 compile_assert(ctx
, bs
[1] == bs
[2]);
1400 /* the boolean condition is 32b even if src[1] and src[2] are
1401 * half-precision, but sel.b16 wants all three src's to be the
1405 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
1406 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
1409 case nir_op_bit_count
:
1410 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1412 case nir_op_ifind_msb
: {
1413 struct ir3_instruction
*cmp
;
1414 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1415 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1416 cmp
->cat2
.condition
= IR3_COND_GE
;
1417 dst
[0] = ir3_SEL_B32(b
,
1418 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1422 case nir_op_ufind_msb
:
1423 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1424 dst
[0] = ir3_SEL_B32(b
,
1425 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1426 src
[0], 0, dst
[0], 0);
1428 case nir_op_find_lsb
:
1429 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1430 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1432 case nir_op_bitfield_reverse
:
1433 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1437 compile_error(ctx
, "Unhandled ALU op: %s\n",
1438 nir_op_infos
[alu
->op
].name
);
1442 put_dst(ctx
, &alu
->dest
.dest
);
1445 /* handles direct/indirect UBO reads: */
1447 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1448 struct ir3_instruction
**dst
)
1450 struct ir3_block
*b
= ctx
->block
;
1451 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1452 nir_const_value
*const_offset
;
1453 /* UBO addresses are the first driver params: */
1454 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1455 const unsigned ptrsz
= pointer_size(ctx
);
1459 /* First src is ubo index, which could either be an immed or not: */
1460 src0
= get_src(ctx
, &intr
->src
[0])[0];
1461 if (is_same_type_mov(src0
) &&
1462 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1463 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1464 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1466 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1467 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1470 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1473 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1475 off
+= const_offset
->u32
[0];
1477 /* For load_ubo_indirect, second src is indirect offset: */
1478 src1
= get_src(ctx
, &intr
->src
[1])[0];
1480 /* and add offset to addr: */
1481 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1484 /* if offset is to large to encode in the ldg, split it out: */
1485 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1486 /* split out the minimal amount to improve the odds that
1487 * cp can fit the immediate in the add.s instruction:
1489 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1490 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1495 struct ir3_instruction
*carry
;
1497 /* handle 32b rollover, ie:
1498 * if (addr < base_lo)
1501 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1502 carry
->cat2
.condition
= IR3_COND_LT
;
1503 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1505 addr
= create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1508 for (int i
= 0; i
< intr
->num_components
; i
++) {
1509 struct ir3_instruction
*load
=
1510 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1511 load
->cat6
.type
= TYPE_U32
;
1512 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1517 /* src[] = { buffer_index, offset }. No const_index */
1519 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1520 struct ir3_instruction
**dst
)
1522 struct ir3_block
*b
= ctx
->block
;
1523 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1524 nir_const_value
*const_offset
;
1526 /* can this be non-const buffer_index? how do we handle that? */
1527 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1528 compile_assert(ctx
, const_offset
);
1530 offset
= get_src(ctx
, &intr
->src
[1])[0];
1532 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1533 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1537 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1539 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1541 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1542 ldgb
->cat6
.iim_val
= intr
->num_components
;
1544 ldgb
->cat6
.type
= TYPE_U32
;
1545 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1546 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1548 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1551 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1553 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1555 struct ir3_block
*b
= ctx
->block
;
1556 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1557 nir_const_value
*const_offset
;
1558 /* TODO handle wrmask properly, see _store_shared().. but I think
1559 * it is more a PITA than that, since blob ends up loading the
1560 * masked components and writing them back out.
1562 unsigned wrmask
= intr
->const_index
[0];
1563 unsigned ncomp
= ffs(~wrmask
) - 1;
1565 /* can this be non-const buffer_index? how do we handle that? */
1566 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1567 compile_assert(ctx
, const_offset
);
1569 offset
= get_src(ctx
, &intr
->src
[2])[0];
1571 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1574 src0
= create_collect(ctx
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1575 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1576 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1581 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1582 src0
, 0, src1
, 0, src2
, 0);
1583 stgb
->cat6
.iim_val
= ncomp
;
1585 stgb
->cat6
.type
= TYPE_U32
;
1586 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1587 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1589 array_insert(b
, b
->keeps
, stgb
);
1592 /* src[] = { block_index } */
1594 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1595 struct ir3_instruction
**dst
)
1597 /* SSBO size stored as a const starting at ssbo_sizes: */
1598 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1599 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1600 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1602 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1604 dst
[0] = create_uniform(ctx
, idx
);
1608 * SSBO atomic intrinsics
1610 * All of the SSBO atomic memory operations read a value from memory,
1611 * compute a new value using one of the operations below, write the new
1612 * value to memory, and return the original value read.
1614 * All operations take 3 sources except CompSwap that takes 4. These
1615 * sources represent:
1617 * 0: The SSBO buffer index.
1618 * 1: The offset into the SSBO buffer of the variable that the atomic
1619 * operation will operate on.
1620 * 2: The data parameter to the atomic function (i.e. the value to add
1621 * in ssbo_atomic_add, etc).
1622 * 3: For CompSwap only: the second data parameter.
1624 static struct ir3_instruction
*
1625 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1627 struct ir3_block
*b
= ctx
->block
;
1628 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1629 nir_const_value
*const_offset
;
1630 type_t type
= TYPE_U32
;
1632 /* can this be non-const buffer_index? how do we handle that? */
1633 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1634 compile_assert(ctx
, const_offset
);
1635 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1637 offset
= get_src(ctx
, &intr
->src
[1])[0];
1639 /* src0 is data (or uvec2(data, compare))
1641 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1643 * Note that nir already multiplies the offset by four
1645 src0
= get_src(ctx
, &intr
->src
[2])[0];
1646 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1647 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1652 switch (intr
->intrinsic
) {
1653 case nir_intrinsic_ssbo_atomic_add
:
1654 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1656 case nir_intrinsic_ssbo_atomic_imin
:
1657 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1660 case nir_intrinsic_ssbo_atomic_umin
:
1661 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1663 case nir_intrinsic_ssbo_atomic_imax
:
1664 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1667 case nir_intrinsic_ssbo_atomic_umax
:
1668 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1670 case nir_intrinsic_ssbo_atomic_and
:
1671 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1673 case nir_intrinsic_ssbo_atomic_or
:
1674 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1676 case nir_intrinsic_ssbo_atomic_xor
:
1677 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1679 case nir_intrinsic_ssbo_atomic_exchange
:
1680 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1682 case nir_intrinsic_ssbo_atomic_comp_swap
:
1683 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1684 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1686 get_src(ctx
, &intr
->src
[3])[0],
1688 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1694 atomic
->cat6
.iim_val
= 1;
1696 atomic
->cat6
.type
= type
;
1697 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1698 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1700 /* even if nothing consume the result, we can't DCE the instruction: */
1701 array_insert(b
, b
->keeps
, atomic
);
1706 /* src[] = { offset }. const_index[] = { base } */
1708 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1709 struct ir3_instruction
**dst
)
1711 struct ir3_block
*b
= ctx
->block
;
1712 struct ir3_instruction
*ldl
, *offset
;
1715 offset
= get_src(ctx
, &intr
->src
[0])[0];
1716 base
= nir_intrinsic_base(intr
);
1718 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1719 ldl
->cat6
.src_offset
= base
;
1720 ldl
->cat6
.type
= utype_dst(intr
->dest
);
1721 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1723 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1724 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1726 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1729 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1731 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1733 struct ir3_block
*b
= ctx
->block
;
1734 struct ir3_instruction
*stl
, *offset
;
1735 struct ir3_instruction
* const *value
;
1736 unsigned base
, wrmask
;
1738 value
= get_src(ctx
, &intr
->src
[0]);
1739 offset
= get_src(ctx
, &intr
->src
[1])[0];
1741 base
= nir_intrinsic_base(intr
);
1742 wrmask
= nir_intrinsic_write_mask(intr
);
1744 /* Combine groups of consecutive enabled channels in one write
1745 * message. We use ffs to find the first enabled channel and then ffs on
1746 * the bit-inverse, down-shifted writemask to determine the length of
1747 * the block of enabled bits.
1749 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1752 unsigned first_component
= ffs(wrmask
) - 1;
1753 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1755 stl
= ir3_STL(b
, offset
, 0,
1756 create_collect(ctx
, &value
[first_component
], length
), 0,
1757 create_immed(b
, length
), 0);
1758 stl
->cat6
.dst_offset
= first_component
+ base
;
1759 stl
->cat6
.type
= utype_src(intr
->src
[0]);
1760 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1761 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1763 array_insert(b
, b
->keeps
, stl
);
1765 /* Clear the bits in the writemask that we just wrote, then try
1766 * again to see if more channels are left.
1768 wrmask
&= (15 << (first_component
+ length
));
1773 * CS shared variable atomic intrinsics
1775 * All of the shared variable atomic memory operations read a value from
1776 * memory, compute a new value using one of the operations below, write the
1777 * new value to memory, and return the original value read.
1779 * All operations take 2 sources except CompSwap that takes 3. These
1780 * sources represent:
1782 * 0: The offset into the shared variable storage region that the atomic
1783 * operation will operate on.
1784 * 1: The data parameter to the atomic function (i.e. the value to add
1785 * in shared_atomic_add, etc).
1786 * 2: For CompSwap only: the second data parameter.
1788 static struct ir3_instruction
*
1789 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1791 struct ir3_block
*b
= ctx
->block
;
1792 struct ir3_instruction
*atomic
, *src0
, *src1
;
1793 type_t type
= TYPE_U32
;
1795 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1796 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1798 switch (intr
->intrinsic
) {
1799 case nir_intrinsic_shared_atomic_add
:
1800 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1802 case nir_intrinsic_shared_atomic_imin
:
1803 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1806 case nir_intrinsic_shared_atomic_umin
:
1807 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1809 case nir_intrinsic_shared_atomic_imax
:
1810 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1813 case nir_intrinsic_shared_atomic_umax
:
1814 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1816 case nir_intrinsic_shared_atomic_and
:
1817 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1819 case nir_intrinsic_shared_atomic_or
:
1820 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1822 case nir_intrinsic_shared_atomic_xor
:
1823 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1825 case nir_intrinsic_shared_atomic_exchange
:
1826 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1828 case nir_intrinsic_shared_atomic_comp_swap
:
1829 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1830 src1
= create_collect(ctx
, (struct ir3_instruction
*[]){
1831 get_src(ctx
, &intr
->src
[2])[0],
1834 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1840 atomic
->cat6
.iim_val
= 1;
1842 atomic
->cat6
.type
= type
;
1843 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1844 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1846 /* even if nothing consume the result, we can't DCE the instruction: */
1847 array_insert(b
, b
->keeps
, atomic
);
1852 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1853 * state block (for load). To simplify things, invert the image id and
1854 * map it from end of state block, ie. image 0 becomes num-1, image 1
1855 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1856 * state when switching shaders.
1858 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1859 * coded. Also, since all the gl shader stages (ie. everything but CS)
1860 * share the same SSBO/image state block, this might require some more
1861 * logic if we supported images in anything other than FS..
1864 get_image_slot(struct ir3_context
*ctx
, nir_deref_instr
*deref
)
1866 unsigned int loc
= 0;
1867 unsigned inner_size
= 1;
1869 while (deref
->deref_type
!= nir_deref_type_var
) {
1870 assert(deref
->deref_type
== nir_deref_type_array
);
1871 nir_const_value
*const_index
= nir_src_as_const_value(deref
->arr
.index
);
1872 assert(const_index
);
1874 /* Go to the next instruction */
1875 deref
= nir_deref_instr_parent(deref
);
1877 assert(glsl_type_is_array(deref
->type
));
1878 const unsigned array_len
= glsl_get_length(deref
->type
);
1879 loc
+= MIN2(const_index
->u32
[0], array_len
- 1) * inner_size
;
1881 /* Update the inner size */
1882 inner_size
*= array_len
;
1885 loc
+= deref
->var
->data
.driver_location
;
1887 /* TODO figure out real limit per generation, and don't hardcode: */
1888 const unsigned max_samplers
= 16;
1889 return max_samplers
- loc
- 1;
1892 /* see tex_info() for equiv logic for texture instructions.. it would be
1893 * nice if this could be better unified..
1896 get_image_coords(const nir_variable
*var
, unsigned *flagsp
)
1898 const struct glsl_type
*type
= glsl_without_array(var
->type
);
1899 unsigned coords
, flags
= 0;
1901 switch (glsl_get_sampler_dim(type
)) {
1902 case GLSL_SAMPLER_DIM_1D
:
1903 case GLSL_SAMPLER_DIM_BUF
:
1906 case GLSL_SAMPLER_DIM_2D
:
1907 case GLSL_SAMPLER_DIM_RECT
:
1908 case GLSL_SAMPLER_DIM_EXTERNAL
:
1909 case GLSL_SAMPLER_DIM_MS
:
1912 case GLSL_SAMPLER_DIM_3D
:
1913 case GLSL_SAMPLER_DIM_CUBE
:
1914 flags
|= IR3_INSTR_3D
;
1918 unreachable("bad sampler dim");
1922 if (glsl_sampler_type_is_array(type
)) {
1923 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1925 flags
|= IR3_INSTR_A
;
1935 get_image_type(const nir_variable
*var
)
1937 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1938 case GLSL_TYPE_UINT
:
1942 case GLSL_TYPE_FLOAT
:
1945 unreachable("bad sampler type.");
1950 static struct ir3_instruction
*
1951 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1952 struct ir3_instruction
* const *coords
, bool byteoff
)
1954 struct ir3_block
*b
= ctx
->block
;
1955 struct ir3_instruction
*offset
;
1956 unsigned ncoords
= get_image_coords(var
, NULL
);
1958 /* to calculate the byte offset (yes, uggg) we need (up to) three
1959 * const values to know the bytes per pixel, and y and z stride:
1961 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1962 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1964 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1965 (1 << var
->data
.driver_location
));
1967 /* offset = coords.x * bytes_per_pixel: */
1968 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1970 /* offset += coords.y * y_pitch: */
1971 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1972 coords
[1], 0, offset
, 0);
1975 /* offset += coords.z * z_pitch: */
1976 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1977 coords
[2], 0, offset
, 0);
1981 /* Some cases, like atomics, seem to use dword offset instead
1982 * of byte offsets.. blob just puts an extra shr.b in there
1985 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1988 return create_collect(ctx
, (struct ir3_instruction
*[]){
1994 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1996 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1997 struct ir3_instruction
**dst
)
1999 struct ir3_block
*b
= ctx
->block
;
2000 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2001 struct ir3_instruction
*sam
;
2002 struct ir3_instruction
* const *src0
= get_src(ctx
, &intr
->src
[1]);
2003 struct ir3_instruction
*coords
[4];
2004 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
2005 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
2006 type_t type
= get_image_type(var
);
2008 /* hmm, this seems a bit odd, but it is what blob does and (at least
2009 * a5xx) just faults on bogus addresses otherwise:
2011 if (flags
& IR3_INSTR_3D
) {
2012 flags
&= ~IR3_INSTR_3D
;
2013 flags
|= IR3_INSTR_A
;
2016 for (unsigned i
= 0; i
< ncoords
; i
++)
2017 coords
[i
] = src0
[i
];
2020 coords
[ncoords
++] = create_immed(b
, 0);
2022 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2023 tex_idx
, tex_idx
, create_collect(ctx
, coords
, ncoords
), NULL
);
2025 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
2026 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
2028 split_dest(b
, dst
, sam
, 0, 4);
2031 /* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
2033 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2035 struct ir3_block
*b
= ctx
->block
;
2036 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2037 struct ir3_instruction
*stib
, *offset
;
2038 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[3]);
2039 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[1]);
2040 unsigned ncoords
= get_image_coords(var
, NULL
);
2041 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
2045 * src2 is 64b byte offset
2048 offset
= get_image_offset(ctx
, var
, coords
, true);
2050 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
2051 * too and takes a dword offset.. not quite sure yet why blob uses
2052 * one over the other in various cases.
2055 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
2056 create_collect(ctx
, value
, 4), 0,
2057 create_collect(ctx
, coords
, ncoords
), 0,
2059 stib
->cat6
.iim_val
= 4;
2060 stib
->cat6
.d
= ncoords
;
2061 stib
->cat6
.type
= get_image_type(var
);
2062 stib
->cat6
.typed
= true;
2063 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2064 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2066 array_insert(b
, b
->keeps
, stib
);
2070 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
2071 struct ir3_instruction
**dst
)
2073 struct ir3_block
*b
= ctx
->block
;
2074 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2075 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
2076 struct ir3_instruction
*sam
, *lod
;
2077 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
2079 lod
= create_immed(b
, 0);
2080 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2081 tex_idx
, tex_idx
, lod
, NULL
);
2083 /* Array size actually ends up in .w rather than .z. This doesn't
2084 * matter for miplevel 0, but for higher mips the value in z is
2085 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2086 * returned, which means that we have to add 1 to it for arrays for
2089 * Note use a temporary dst and then copy, since the size of the dst
2090 * array that is passed in is based on nir's understanding of the
2091 * result size, not the hardware's
2093 struct ir3_instruction
*tmp
[4];
2095 split_dest(b
, tmp
, sam
, 0, 4);
2097 for (unsigned i
= 0; i
< ncoords
; i
++)
2100 if (flags
& IR3_INSTR_A
) {
2101 if (ctx
->levels_add_one
) {
2102 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
2104 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
2109 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
2110 static struct ir3_instruction
*
2111 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2113 struct ir3_block
*b
= ctx
->block
;
2114 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2115 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
2116 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[1]);
2117 unsigned ncoords
= get_image_coords(var
, NULL
);
2119 image
= create_immed(b
, get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0])));
2121 /* src0 is value (or uvec2(value, compare))
2123 * src2 is 64b byte offset
2125 src0
= get_src(ctx
, &intr
->src
[3])[0];
2126 src1
= create_collect(ctx
, coords
, ncoords
);
2127 src2
= get_image_offset(ctx
, var
, coords
, false);
2129 switch (intr
->intrinsic
) {
2130 case nir_intrinsic_image_deref_atomic_add
:
2131 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2133 case nir_intrinsic_image_deref_atomic_min
:
2134 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2136 case nir_intrinsic_image_deref_atomic_max
:
2137 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2139 case nir_intrinsic_image_deref_atomic_and
:
2140 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2142 case nir_intrinsic_image_deref_atomic_or
:
2143 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2145 case nir_intrinsic_image_deref_atomic_xor
:
2146 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2148 case nir_intrinsic_image_deref_atomic_exchange
:
2149 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2151 case nir_intrinsic_image_deref_atomic_comp_swap
:
2152 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
2153 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
2155 get_src(ctx
, &intr
->src
[4])[0],
2157 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2163 atomic
->cat6
.iim_val
= 1;
2164 atomic
->cat6
.d
= ncoords
;
2165 atomic
->cat6
.type
= get_image_type(var
);
2166 atomic
->cat6
.typed
= true;
2167 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2168 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2170 /* even if nothing consume the result, we can't DCE the instruction: */
2171 array_insert(b
, b
->keeps
, atomic
);
2177 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2179 struct ir3_block
*b
= ctx
->block
;
2180 struct ir3_instruction
*barrier
;
2182 switch (intr
->intrinsic
) {
2183 case nir_intrinsic_barrier
:
2184 barrier
= ir3_BAR(b
);
2185 barrier
->cat7
.g
= true;
2186 barrier
->cat7
.l
= true;
2187 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
2188 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2190 case nir_intrinsic_memory_barrier
:
2191 barrier
= ir3_FENCE(b
);
2192 barrier
->cat7
.g
= true;
2193 barrier
->cat7
.r
= true;
2194 barrier
->cat7
.w
= true;
2195 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
2196 IR3_BARRIER_BUFFER_W
;
2197 barrier
->barrier_conflict
=
2198 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2199 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2201 case nir_intrinsic_memory_barrier_atomic_counter
:
2202 case nir_intrinsic_memory_barrier_buffer
:
2203 barrier
= ir3_FENCE(b
);
2204 barrier
->cat7
.g
= true;
2205 barrier
->cat7
.r
= true;
2206 barrier
->cat7
.w
= true;
2207 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
2208 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
2209 IR3_BARRIER_BUFFER_W
;
2211 case nir_intrinsic_memory_barrier_image
:
2212 // TODO double check if this should have .g set
2213 barrier
= ir3_FENCE(b
);
2214 barrier
->cat7
.g
= true;
2215 barrier
->cat7
.r
= true;
2216 barrier
->cat7
.w
= true;
2217 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2218 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
2219 IR3_BARRIER_IMAGE_W
;
2221 case nir_intrinsic_memory_barrier_shared
:
2222 barrier
= ir3_FENCE(b
);
2223 barrier
->cat7
.g
= true;
2224 barrier
->cat7
.l
= true;
2225 barrier
->cat7
.r
= true;
2226 barrier
->cat7
.w
= true;
2227 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
2228 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
2229 IR3_BARRIER_SHARED_W
;
2231 case nir_intrinsic_group_memory_barrier
:
2232 barrier
= ir3_FENCE(b
);
2233 barrier
->cat7
.g
= true;
2234 barrier
->cat7
.l
= true;
2235 barrier
->cat7
.r
= true;
2236 barrier
->cat7
.w
= true;
2237 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
2238 IR3_BARRIER_IMAGE_W
|
2239 IR3_BARRIER_BUFFER_W
;
2240 barrier
->barrier_conflict
=
2241 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
2242 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2243 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2249 /* make sure barrier doesn't get DCE'd */
2250 array_insert(b
, b
->keeps
, barrier
);
2253 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
2254 gl_system_value slot
, unsigned compmask
,
2255 struct ir3_instruction
*instr
)
2257 struct ir3_shader_variant
*so
= ctx
->so
;
2258 unsigned r
= regid(so
->inputs_count
, 0);
2259 unsigned n
= so
->inputs_count
++;
2261 so
->inputs
[n
].sysval
= true;
2262 so
->inputs
[n
].slot
= slot
;
2263 so
->inputs
[n
].compmask
= compmask
;
2264 so
->inputs
[n
].regid
= r
;
2265 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
2268 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
2269 ctx
->ir
->inputs
[r
] = instr
;
2272 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
2273 struct ir3_instruction
*instr
)
2275 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
2279 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2281 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
2282 struct ir3_instruction
**dst
;
2283 struct ir3_instruction
* const *src
;
2284 struct ir3_block
*b
= ctx
->block
;
2285 nir_const_value
*const_offset
;
2288 if (info
->has_dest
) {
2289 unsigned n
= nir_intrinsic_dest_components(intr
);
2290 dst
= get_dst(ctx
, &intr
->dest
, n
);
2295 switch (intr
->intrinsic
) {
2296 case nir_intrinsic_load_uniform
:
2297 idx
= nir_intrinsic_base(intr
);
2298 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2300 idx
+= const_offset
->u32
[0];
2301 for (int i
= 0; i
< intr
->num_components
; i
++) {
2302 unsigned n
= idx
* 4 + i
;
2303 dst
[i
] = create_uniform(ctx
, n
);
2306 src
= get_src(ctx
, &intr
->src
[0]);
2307 for (int i
= 0; i
< intr
->num_components
; i
++) {
2308 int n
= idx
* 4 + i
;
2309 dst
[i
] = create_uniform_indirect(ctx
, n
,
2310 get_addr(ctx
, src
[0], 4));
2312 /* NOTE: if relative addressing is used, we set
2313 * constlen in the compiler (to worst-case value)
2314 * since we don't know in the assembler what the max
2315 * addr reg value can be:
2317 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2320 case nir_intrinsic_load_ubo
:
2321 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2323 case nir_intrinsic_load_input
:
2324 idx
= nir_intrinsic_base(intr
);
2325 comp
= nir_intrinsic_component(intr
);
2326 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2328 idx
+= const_offset
->u32
[0];
2329 for (int i
= 0; i
< intr
->num_components
; i
++) {
2330 unsigned n
= idx
* 4 + i
+ comp
;
2331 dst
[i
] = ctx
->ir
->inputs
[n
];
2334 src
= get_src(ctx
, &intr
->src
[0]);
2335 struct ir3_instruction
*collect
=
2336 create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2337 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2338 for (int i
= 0; i
< intr
->num_components
; i
++) {
2339 unsigned n
= idx
* 4 + i
+ comp
;
2340 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2345 case nir_intrinsic_load_ssbo
:
2346 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2348 case nir_intrinsic_store_ssbo
:
2349 emit_intrinsic_store_ssbo(ctx
, intr
);
2351 case nir_intrinsic_get_buffer_size
:
2352 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2354 case nir_intrinsic_ssbo_atomic_add
:
2355 case nir_intrinsic_ssbo_atomic_imin
:
2356 case nir_intrinsic_ssbo_atomic_umin
:
2357 case nir_intrinsic_ssbo_atomic_imax
:
2358 case nir_intrinsic_ssbo_atomic_umax
:
2359 case nir_intrinsic_ssbo_atomic_and
:
2360 case nir_intrinsic_ssbo_atomic_or
:
2361 case nir_intrinsic_ssbo_atomic_xor
:
2362 case nir_intrinsic_ssbo_atomic_exchange
:
2363 case nir_intrinsic_ssbo_atomic_comp_swap
:
2364 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2366 case nir_intrinsic_load_shared
:
2367 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2369 case nir_intrinsic_store_shared
:
2370 emit_intrinsic_store_shared(ctx
, intr
);
2372 case nir_intrinsic_shared_atomic_add
:
2373 case nir_intrinsic_shared_atomic_imin
:
2374 case nir_intrinsic_shared_atomic_umin
:
2375 case nir_intrinsic_shared_atomic_imax
:
2376 case nir_intrinsic_shared_atomic_umax
:
2377 case nir_intrinsic_shared_atomic_and
:
2378 case nir_intrinsic_shared_atomic_or
:
2379 case nir_intrinsic_shared_atomic_xor
:
2380 case nir_intrinsic_shared_atomic_exchange
:
2381 case nir_intrinsic_shared_atomic_comp_swap
:
2382 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2384 case nir_intrinsic_image_deref_load
:
2385 emit_intrinsic_load_image(ctx
, intr
, dst
);
2387 case nir_intrinsic_image_deref_store
:
2388 emit_intrinsic_store_image(ctx
, intr
);
2390 case nir_intrinsic_image_deref_size
:
2391 emit_intrinsic_image_size(ctx
, intr
, dst
);
2393 case nir_intrinsic_image_deref_atomic_add
:
2394 case nir_intrinsic_image_deref_atomic_min
:
2395 case nir_intrinsic_image_deref_atomic_max
:
2396 case nir_intrinsic_image_deref_atomic_and
:
2397 case nir_intrinsic_image_deref_atomic_or
:
2398 case nir_intrinsic_image_deref_atomic_xor
:
2399 case nir_intrinsic_image_deref_atomic_exchange
:
2400 case nir_intrinsic_image_deref_atomic_comp_swap
:
2401 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2403 case nir_intrinsic_barrier
:
2404 case nir_intrinsic_memory_barrier
:
2405 case nir_intrinsic_group_memory_barrier
:
2406 case nir_intrinsic_memory_barrier_atomic_counter
:
2407 case nir_intrinsic_memory_barrier_buffer
:
2408 case nir_intrinsic_memory_barrier_image
:
2409 case nir_intrinsic_memory_barrier_shared
:
2410 emit_intrinsic_barrier(ctx
, intr
);
2411 /* note that blk ptr no longer valid, make that obvious: */
2414 case nir_intrinsic_store_output
:
2415 idx
= nir_intrinsic_base(intr
);
2416 comp
= nir_intrinsic_component(intr
);
2417 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2418 compile_assert(ctx
, const_offset
!= NULL
);
2419 idx
+= const_offset
->u32
[0];
2421 src
= get_src(ctx
, &intr
->src
[0]);
2422 for (int i
= 0; i
< intr
->num_components
; i
++) {
2423 unsigned n
= idx
* 4 + i
+ comp
;
2424 ctx
->ir
->outputs
[n
] = src
[i
];
2427 case nir_intrinsic_load_base_vertex
:
2428 case nir_intrinsic_load_first_vertex
:
2429 if (!ctx
->basevertex
) {
2430 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2431 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
2433 dst
[0] = ctx
->basevertex
;
2435 case nir_intrinsic_load_vertex_id_zero_base
:
2436 case nir_intrinsic_load_vertex_id
:
2437 if (!ctx
->vertex_id
) {
2438 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2439 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2440 ctx
->vertex_id
= create_input(b
, 0);
2441 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2443 dst
[0] = ctx
->vertex_id
;
2445 case nir_intrinsic_load_instance_id
:
2446 if (!ctx
->instance_id
) {
2447 ctx
->instance_id
= create_input(b
, 0);
2448 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2451 dst
[0] = ctx
->instance_id
;
2453 case nir_intrinsic_load_sample_id
:
2454 case nir_intrinsic_load_sample_id_no_per_sample
:
2455 if (!ctx
->samp_id
) {
2456 ctx
->samp_id
= create_input(b
, 0);
2457 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
2458 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
2461 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
2463 case nir_intrinsic_load_sample_mask_in
:
2464 if (!ctx
->samp_mask_in
) {
2465 ctx
->samp_mask_in
= create_input(b
, 0);
2466 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
2469 dst
[0] = ctx
->samp_mask_in
;
2471 case nir_intrinsic_load_user_clip_plane
:
2472 idx
= nir_intrinsic_ucp_id(intr
);
2473 for (int i
= 0; i
< intr
->num_components
; i
++) {
2474 unsigned n
= idx
* 4 + i
;
2475 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2478 case nir_intrinsic_load_front_face
:
2479 if (!ctx
->frag_face
) {
2480 ctx
->so
->frag_face
= true;
2481 ctx
->frag_face
= create_input(b
, 0);
2482 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2484 /* for fragface, we get -1 for back and 0 for front. However this is
2485 * the inverse of what nir expects (where ~0 is true).
2487 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2488 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2490 case nir_intrinsic_load_local_invocation_id
:
2491 if (!ctx
->local_invocation_id
) {
2492 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2493 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2494 0x7, ctx
->local_invocation_id
);
2496 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2498 case nir_intrinsic_load_work_group_id
:
2499 if (!ctx
->work_group_id
) {
2500 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2501 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2502 0x7, ctx
->work_group_id
);
2503 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2505 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2507 case nir_intrinsic_load_num_work_groups
:
2508 for (int i
= 0; i
< intr
->num_components
; i
++) {
2509 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2512 case nir_intrinsic_load_local_group_size
:
2513 for (int i
= 0; i
< intr
->num_components
; i
++) {
2514 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2517 case nir_intrinsic_discard_if
:
2518 case nir_intrinsic_discard
: {
2519 struct ir3_instruction
*cond
, *kill
;
2521 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2522 /* conditional discard: */
2523 src
= get_src(ctx
, &intr
->src
[0]);
2524 cond
= ir3_b2n(b
, src
[0]);
2526 /* unconditional discard: */
2527 cond
= create_immed(b
, 1);
2530 /* NOTE: only cmps.*.* can write p0.x: */
2531 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2532 cond
->cat2
.condition
= IR3_COND_NE
;
2534 /* condition always goes in predicate register: */
2535 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2537 kill
= ir3_KILL(b
, cond
, 0);
2538 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2540 array_insert(b
, b
->keeps
, kill
);
2541 ctx
->so
->has_kill
= true;
2546 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2547 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2552 put_dst(ctx
, &intr
->dest
);
2556 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2558 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2559 instr
->def
.num_components
);
2560 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2562 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2563 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
.u32
[i
], type
);
2567 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2569 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2570 undef
->def
.num_components
);
2571 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2573 /* backend doesn't want undefined instructions, so just plug
2576 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2577 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2581 * texture fetch/sample instructions:
2585 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2587 unsigned coords
, flags
= 0;
2589 /* note: would use tex->coord_components.. except txs.. also,
2590 * since array index goes after shadow ref, we don't want to
2593 switch (tex
->sampler_dim
) {
2594 case GLSL_SAMPLER_DIM_1D
:
2595 case GLSL_SAMPLER_DIM_BUF
:
2598 case GLSL_SAMPLER_DIM_2D
:
2599 case GLSL_SAMPLER_DIM_RECT
:
2600 case GLSL_SAMPLER_DIM_EXTERNAL
:
2601 case GLSL_SAMPLER_DIM_MS
:
2604 case GLSL_SAMPLER_DIM_3D
:
2605 case GLSL_SAMPLER_DIM_CUBE
:
2607 flags
|= IR3_INSTR_3D
;
2610 unreachable("bad sampler_dim");
2613 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2614 flags
|= IR3_INSTR_S
;
2616 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2617 flags
|= IR3_INSTR_A
;
2624 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2626 struct ir3_block
*b
= ctx
->block
;
2627 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2628 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2629 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2630 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2631 unsigned i
, coords
, flags
;
2632 unsigned nsrc0
= 0, nsrc1
= 0;
2636 coord
= off
= ddx
= ddy
= NULL
;
2637 lod
= proj
= compare
= sample_index
= NULL
;
2639 /* TODO: might just be one component for gathers? */
2640 dst
= get_dst(ctx
, &tex
->dest
, 4);
2642 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2643 switch (tex
->src
[i
].src_type
) {
2644 case nir_tex_src_coord
:
2645 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2647 case nir_tex_src_bias
:
2648 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2651 case nir_tex_src_lod
:
2652 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2655 case nir_tex_src_comparator
: /* shadow comparator */
2656 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2658 case nir_tex_src_projector
:
2659 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2662 case nir_tex_src_offset
:
2663 off
= get_src(ctx
, &tex
->src
[i
].src
);
2666 case nir_tex_src_ddx
:
2667 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2669 case nir_tex_src_ddy
:
2670 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2672 case nir_tex_src_ms_index
:
2673 sample_index
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2676 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2677 tex
->src
[i
].src_type
);
2683 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2684 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2685 case nir_texop_txl
: opc
= OPC_SAML
; break;
2686 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2687 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2688 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2690 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2691 * what blob does, seems gather is broken?), and a3xx did
2692 * not support it (but probably could also emulate).
2694 switch (tex
->component
) {
2695 case 0: opc
= OPC_GATHER4R
; break;
2696 case 1: opc
= OPC_GATHER4G
; break;
2697 case 2: opc
= OPC_GATHER4B
; break;
2698 case 3: opc
= OPC_GATHER4A
; break;
2701 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2703 case nir_texop_query_levels
:
2704 case nir_texop_texture_samples
:
2705 case nir_texop_samples_identical
:
2706 case nir_texop_txf_ms_mcs
:
2707 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2711 tex_info(tex
, &flags
, &coords
);
2714 * lay out the first argument in the proper order:
2715 * - actual coordinates first
2716 * - shadow reference
2719 * - starting at offset 4, dpdx.xy, dpdy.xy
2721 * bias/lod go into the second arg
2724 /* insert tex coords: */
2725 for (i
= 0; i
< coords
; i
++)
2730 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2731 * with scaled x coord according to requested sample:
2733 if (tex
->op
== nir_texop_txf_ms
) {
2734 if (ctx
->txf_ms_with_isaml
) {
2735 /* the samples are laid out in x dimension as
2737 * x_ms = (x << ms) + sample_index;
2739 struct ir3_instruction
*ms
;
2740 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2742 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2743 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2747 src0
[nsrc0
++] = sample_index
;
2751 /* scale up integer coords for TXF based on the LOD */
2752 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2754 for (i
= 0; i
< coords
; i
++)
2755 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2759 /* hw doesn't do 1d, so we treat it as 2d with
2760 * height of 1, and patch up the y coord.
2761 * TODO: y coord should be (int)0 in some cases..
2763 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2766 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2767 src0
[nsrc0
++] = compare
;
2769 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2770 struct ir3_instruction
*idx
= coord
[coords
];
2772 /* the array coord for cube arrays needs 0.5 added to it */
2773 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2774 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2776 src0
[nsrc0
++] = idx
;
2780 src0
[nsrc0
++] = proj
;
2781 flags
|= IR3_INSTR_P
;
2784 /* pad to 4, then ddx/ddy: */
2785 if (tex
->op
== nir_texop_txd
) {
2787 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2788 for (i
= 0; i
< coords
; i
++)
2789 src0
[nsrc0
++] = ddx
[i
];
2791 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2792 for (i
= 0; i
< coords
; i
++)
2793 src0
[nsrc0
++] = ddy
[i
];
2795 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2799 * second argument (if applicable):
2804 if (has_off
| has_lod
| has_bias
) {
2806 unsigned off_coords
= coords
;
2807 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2809 for (i
= 0; i
< off_coords
; i
++)
2810 src1
[nsrc1
++] = off
[i
];
2812 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2813 flags
|= IR3_INSTR_O
;
2816 if (has_lod
| has_bias
)
2817 src1
[nsrc1
++] = lod
;
2820 switch (tex
->dest_type
) {
2821 case nir_type_invalid
:
2822 case nir_type_float
:
2833 unreachable("bad dest_type");
2836 if (opc
== OPC_GETLOD
)
2839 unsigned tex_idx
= tex
->texture_index
;
2841 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2843 struct ir3_instruction
*col0
= create_collect(ctx
, src0
, nsrc0
);
2844 struct ir3_instruction
*col1
= create_collect(ctx
, src1
, nsrc1
);
2846 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2847 tex_idx
, tex_idx
, col0
, col1
);
2849 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2850 /* only need first 3 components: */
2851 sam
->regs
[0]->wrmask
= 0x7;
2852 split_dest(b
, dst
, sam
, 0, 3);
2854 /* we need to sample the alpha separately with a non-ASTC
2857 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2858 tex_idx
, tex_idx
, col0
, col1
);
2860 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2862 /* fixup .w component: */
2863 split_dest(b
, &dst
[3], sam
, 3, 1);
2865 /* normal (non-workaround) case: */
2866 split_dest(b
, dst
, sam
, 0, 4);
2869 /* GETLOD returns results in 4.8 fixed point */
2870 if (opc
== OPC_GETLOD
) {
2871 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2873 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2874 for (i
= 0; i
< 2; i
++) {
2875 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2880 put_dst(ctx
, &tex
->dest
);
2884 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2886 struct ir3_block
*b
= ctx
->block
;
2887 struct ir3_instruction
**dst
, *sam
;
2889 dst
= get_dst(ctx
, &tex
->dest
, 1);
2891 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2892 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2894 /* even though there is only one component, since it ends
2895 * up in .z rather than .x, we need a split_dest()
2897 split_dest(b
, dst
, sam
, 0, 3);
2899 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2900 * the value in TEX_CONST_0 is zero-based.
2902 if (ctx
->levels_add_one
)
2903 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2905 put_dst(ctx
, &tex
->dest
);
2909 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2911 struct ir3_block
*b
= ctx
->block
;
2912 struct ir3_instruction
**dst
, *sam
;
2913 struct ir3_instruction
*lod
;
2914 unsigned flags
, coords
;
2916 tex_info(tex
, &flags
, &coords
);
2918 /* Actually we want the number of dimensions, not coordinates. This
2919 * distinction only matters for cubes.
2921 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2924 dst
= get_dst(ctx
, &tex
->dest
, 4);
2926 compile_assert(ctx
, tex
->num_srcs
== 1);
2927 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2929 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2931 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2932 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2934 split_dest(b
, dst
, sam
, 0, 4);
2936 /* Array size actually ends up in .w rather than .z. This doesn't
2937 * matter for miplevel 0, but for higher mips the value in z is
2938 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2939 * returned, which means that we have to add 1 to it for arrays.
2941 if (tex
->is_array
) {
2942 if (ctx
->levels_add_one
) {
2943 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2945 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2949 put_dst(ctx
, &tex
->dest
);
2953 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2955 switch (jump
->type
) {
2956 case nir_jump_break
:
2957 case nir_jump_continue
:
2958 case nir_jump_return
:
2959 /* I *think* we can simply just ignore this, and use the
2960 * successor block link to figure out where we need to
2961 * jump to for break/continue
2965 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2971 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2973 switch (instr
->type
) {
2974 case nir_instr_type_alu
:
2975 emit_alu(ctx
, nir_instr_as_alu(instr
));
2977 case nir_instr_type_deref
:
2978 /* ignored, handled as part of the intrinsic they are src to */
2980 case nir_instr_type_intrinsic
:
2981 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2983 case nir_instr_type_load_const
:
2984 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2986 case nir_instr_type_ssa_undef
:
2987 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2989 case nir_instr_type_tex
: {
2990 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2991 /* couple tex instructions get special-cased:
2995 emit_tex_txs(ctx
, tex
);
2997 case nir_texop_query_levels
:
2998 emit_tex_query_levels(ctx
, tex
);
3006 case nir_instr_type_jump
:
3007 emit_jump(ctx
, nir_instr_as_jump(instr
));
3009 case nir_instr_type_phi
:
3010 /* we have converted phi webs to regs in NIR by now */
3011 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
3013 case nir_instr_type_call
:
3014 case nir_instr_type_parallel_copy
:
3015 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
3020 static struct ir3_block
*
3021 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
3023 struct ir3_block
*block
;
3024 struct hash_entry
*hentry
;
3025 struct set_entry
*sentry
;
3028 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
3030 return hentry
->data
;
3032 block
= ir3_block_create(ctx
->ir
);
3033 block
->nblock
= nblock
;
3034 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
3036 block
->predecessors_count
= nblock
->predecessors
->entries
;
3037 block
->predecessors
= ralloc_array_size(block
,
3038 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
3040 set_foreach(nblock
->predecessors
, sentry
) {
3041 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
3048 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
3050 struct ir3_block
*block
= get_block(ctx
, nblock
);
3052 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
3053 if (nblock
->successors
[i
]) {
3054 block
->successors
[i
] =
3055 get_block(ctx
, nblock
->successors
[i
]);
3060 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
3062 /* re-emit addr register in each block if needed: */
3063 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
3064 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
3065 ctx
->addr_ht
[i
] = NULL
;
3068 nir_foreach_instr(instr
, nblock
) {
3069 emit_instr(ctx
, instr
);
3075 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
3078 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
3080 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
3082 ctx
->block
->condition
=
3083 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
3085 emit_cf_list(ctx
, &nif
->then_list
);
3086 emit_cf_list(ctx
, &nif
->else_list
);
3090 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
3092 emit_cf_list(ctx
, &nloop
->body
);
3096 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
3098 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3099 switch (node
->type
) {
3100 case nir_cf_node_block
:
3101 emit_block(ctx
, nir_cf_node_as_block(node
));
3103 case nir_cf_node_if
:
3104 emit_if(ctx
, nir_cf_node_as_if(node
));
3106 case nir_cf_node_loop
:
3107 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3109 case nir_cf_node_function
:
3110 compile_error(ctx
, "TODO\n");
3116 /* emit stream-out code. At this point, the current block is the original
3117 * (nir) end block, and nir ensures that all flow control paths terminate
3118 * into the end block. We re-purpose the original end block to generate
3119 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
3120 * block holding stream-out write instructions, followed by the new end
3124 * p0.x = (vtxcnt < maxvtxcnt)
3125 * // succs: blockStreamOut, blockNewEnd
3128 * ... stream-out instructions ...
3129 * // succs: blockNewEnd
3135 emit_stream_out(struct ir3_context
*ctx
)
3137 struct ir3_shader_variant
*v
= ctx
->so
;
3138 struct ir3
*ir
= ctx
->ir
;
3139 struct pipe_stream_output_info
*strmout
=
3140 &ctx
->so
->shader
->stream_output
;
3141 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
3142 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
3143 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
3145 /* create vtxcnt input in input block at top of shader,
3146 * so that it is seen as live over the entire duration
3149 vtxcnt
= create_input(ctx
->in_block
, 0);
3150 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
3152 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
3154 /* at this point, we are at the original 'end' block,
3155 * re-purpose this block to stream-out condition, then
3156 * append stream-out block and new-end block
3158 orig_end_block
= ctx
->block
;
3160 // TODO these blocks need to update predecessors..
3161 // maybe w/ store_global intrinsic, we could do this
3162 // stuff in nir->nir pass
3164 stream_out_block
= ir3_block_create(ir
);
3165 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
3167 new_end_block
= ir3_block_create(ir
);
3168 list_addtail(&new_end_block
->node
, &ir
->block_list
);
3170 orig_end_block
->successors
[0] = stream_out_block
;
3171 orig_end_block
->successors
[1] = new_end_block
;
3172 stream_out_block
->successors
[0] = new_end_block
;
3174 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
3175 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
3176 cond
->regs
[0]->num
= regid(REG_P0
, 0);
3177 cond
->cat2
.condition
= IR3_COND_LT
;
3179 /* condition goes on previous block to the conditional,
3180 * since it is used to pick which of the two successor
3183 orig_end_block
->condition
= cond
;
3185 /* switch to stream_out_block to generate the stream-out
3188 ctx
->block
= stream_out_block
;
3190 /* Calculate base addresses based on vtxcnt. Instructions
3191 * generated for bases not used in following loop will be
3192 * stripped out in the backend.
3194 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3195 unsigned stride
= strmout
->stride
[i
];
3196 struct ir3_instruction
*base
, *off
;
3198 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
3200 /* 24-bit should be enough: */
3201 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
3202 create_immed(ctx
->block
, stride
* 4), 0);
3204 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
3207 /* Generate the per-output store instructions: */
3208 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
3209 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
3210 unsigned c
= j
+ strmout
->output
[i
].start_component
;
3211 struct ir3_instruction
*base
, *out
, *stg
;
3213 base
= bases
[strmout
->output
[i
].output_buffer
];
3214 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
3216 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
3217 create_immed(ctx
->block
, 1), 0);
3218 stg
->cat6
.type
= TYPE_U32
;
3219 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
3221 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
3225 /* and finally switch to the new_end_block: */
3226 ctx
->block
= new_end_block
;
3230 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
3232 nir_metadata_require(impl
, nir_metadata_block_index
);
3234 emit_cf_list(ctx
, &impl
->body
);
3235 emit_block(ctx
, impl
->end_block
);
3237 /* at this point, we should have a single empty block,
3238 * into which we emit the 'end' instruction.
3240 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
3242 /* If stream-out (aka transform-feedback) enabled, emit the
3243 * stream-out instructions, followed by a new empty block (into
3244 * which the 'end' instruction lands).
3246 * NOTE: it is done in this order, rather than inserting before
3247 * we emit end_block, because NIR guarantees that all blocks
3248 * flow into end_block, and that end_block has no successors.
3249 * So by re-purposing end_block as the first block of stream-
3250 * out, we guarantee that all exit paths flow into the stream-
3253 if ((ctx
->compiler
->gpu_id
< 500) &&
3254 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
3255 !ctx
->so
->key
.binning_pass
) {
3256 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
3257 emit_stream_out(ctx
);
3260 ir3_END(ctx
->block
);
3264 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
3266 struct ir3_shader_variant
*so
= ctx
->so
;
3267 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
3268 unsigned ncomp
= glsl_get_components(in
->type
);
3269 unsigned n
= in
->data
.driver_location
;
3270 unsigned slot
= in
->data
.location
;
3272 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
3273 slot
, array_len
, ncomp
, n
);
3275 /* let's pretend things other than vec4 don't exist: */
3276 ncomp
= MAX2(ncomp
, 4);
3277 compile_assert(ctx
, ncomp
== 4);
3279 so
->inputs
[n
].slot
= slot
;
3280 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
3281 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
3282 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
3284 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3285 for (int i
= 0; i
< ncomp
; i
++) {
3286 struct ir3_instruction
*instr
= NULL
;
3287 unsigned idx
= (n
* 4) + i
;
3289 if (slot
== VARYING_SLOT_POS
) {
3290 so
->inputs
[n
].bary
= false;
3291 so
->frag_coord
= true;
3292 instr
= create_frag_coord(ctx
, i
);
3293 } else if (slot
== VARYING_SLOT_PNTC
) {
3294 /* see for example st_get_generic_varying_index().. this is
3295 * maybe a bit mesa/st specific. But we need things to line
3296 * up for this in fdN_program:
3297 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
3298 * if (emit->sprite_coord_enable & texmask) {
3302 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
3303 so
->inputs
[n
].bary
= true;
3304 instr
= create_frag_input(ctx
, false);
3306 bool use_ldlv
= false;
3308 /* detect the special case for front/back colors where
3309 * we need to do flat vs smooth shading depending on
3312 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3314 case VARYING_SLOT_COL0
:
3315 case VARYING_SLOT_COL1
:
3316 case VARYING_SLOT_BFC0
:
3317 case VARYING_SLOT_BFC1
:
3318 so
->inputs
[n
].rasterflat
= true;
3325 if (ctx
->flat_bypass
) {
3326 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3327 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3331 so
->inputs
[n
].bary
= true;
3333 instr
= create_frag_input(ctx
, use_ldlv
);
3336 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3338 ctx
->ir
->inputs
[idx
] = instr
;
3340 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3341 for (int i
= 0; i
< ncomp
; i
++) {
3342 unsigned idx
= (n
* 4) + i
;
3343 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3344 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
3347 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3350 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3351 so
->total_in
+= ncomp
;
3356 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3358 struct ir3_shader_variant
*so
= ctx
->so
;
3359 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3360 unsigned ncomp
= glsl_get_components(out
->type
);
3361 unsigned n
= out
->data
.driver_location
;
3362 unsigned slot
= out
->data
.location
;
3365 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3366 slot
, array_len
, ncomp
, n
);
3368 /* let's pretend things other than vec4 don't exist: */
3369 ncomp
= MAX2(ncomp
, 4);
3370 compile_assert(ctx
, ncomp
== 4);
3372 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3374 case FRAG_RESULT_DEPTH
:
3375 comp
= 2; /* tgsi will write to .z component */
3376 so
->writes_pos
= true;
3378 case FRAG_RESULT_COLOR
:
3382 if (slot
>= FRAG_RESULT_DATA0
)
3384 compile_error(ctx
, "unknown FS output name: %s\n",
3385 gl_frag_result_name(slot
));
3387 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3389 case VARYING_SLOT_POS
:
3390 so
->writes_pos
= true;
3392 case VARYING_SLOT_PSIZ
:
3393 so
->writes_psize
= true;
3395 case VARYING_SLOT_COL0
:
3396 case VARYING_SLOT_COL1
:
3397 case VARYING_SLOT_BFC0
:
3398 case VARYING_SLOT_BFC1
:
3399 case VARYING_SLOT_FOGC
:
3400 case VARYING_SLOT_CLIP_DIST0
:
3401 case VARYING_SLOT_CLIP_DIST1
:
3402 case VARYING_SLOT_CLIP_VERTEX
:
3405 if (slot
>= VARYING_SLOT_VAR0
)
3407 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3409 compile_error(ctx
, "unknown VS output name: %s\n",
3410 gl_varying_slot_name(slot
));
3413 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3416 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3418 so
->outputs
[n
].slot
= slot
;
3419 so
->outputs
[n
].regid
= regid(n
, comp
);
3420 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3422 for (int i
= 0; i
< ncomp
; i
++) {
3423 unsigned idx
= (n
* 4) + i
;
3424 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3425 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3430 max_drvloc(struct exec_list
*vars
)
3433 nir_foreach_variable(var
, vars
) {
3434 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3439 static const unsigned max_sysvals
[SHADER_MAX
] = {
3440 [SHADER_FRAGMENT
] = 8,
3441 [SHADER_VERTEX
] = 16,
3442 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3446 emit_instructions(struct ir3_context
*ctx
)
3448 unsigned ninputs
, noutputs
;
3449 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3451 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3452 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3454 /* we need to leave room for sysvals:
3456 ninputs
+= max_sysvals
[ctx
->so
->type
];
3458 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3460 /* Create inputs in first block: */
3461 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3462 ctx
->in_block
= ctx
->block
;
3463 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3465 ninputs
-= max_sysvals
[ctx
->so
->type
];
3467 /* for fragment shader, we have a single input register (usually
3468 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3470 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3471 // TODO maybe a helper for fi since we need it a few places..
3472 struct ir3_instruction
*instr
;
3473 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3474 ir3_reg_create(instr
, 0, 0);
3475 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3476 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3477 ctx
->frag_pos
= instr
;
3481 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3482 setup_input(ctx
, var
);
3485 /* Setup outputs: */
3486 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3487 setup_output(ctx
, var
);
3490 /* Setup registers (which should only be arrays): */
3491 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3492 declare_array(ctx
, reg
);
3495 /* NOTE: need to do something more clever when we support >1 fxn */
3496 nir_foreach_register(reg
, &fxn
->registers
) {
3497 declare_array(ctx
, reg
);
3499 /* And emit the body: */
3501 emit_function(ctx
, fxn
);
3504 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3505 * for a fragment shader are just bary.f instructions. The *actual* inputs
3506 * from the hw perspective are the frag_pos and optionally frag_coord and
3510 fixup_frag_inputs(struct ir3_context
*ctx
)
3512 struct ir3_shader_variant
*so
= ctx
->so
;
3513 struct ir3
*ir
= ctx
->ir
;
3514 struct ir3_instruction
**inputs
;
3515 struct ir3_instruction
*instr
;
3520 n
= 4; /* always have frag_pos */
3521 n
+= COND(so
->frag_face
, 4);
3522 n
+= COND(so
->frag_coord
, 4);
3524 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3526 if (so
->frag_face
) {
3527 /* this ultimately gets assigned to hr0.x so doesn't conflict
3528 * with frag_coord/frag_pos..
3530 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3531 ctx
->frag_face
->regs
[0]->num
= 0;
3533 /* remaining channels not used, but let's avoid confusing
3534 * other parts that expect inputs to come in groups of vec4
3536 inputs
[ir
->ninputs
++] = NULL
;
3537 inputs
[ir
->ninputs
++] = NULL
;
3538 inputs
[ir
->ninputs
++] = NULL
;
3541 /* since we don't know where to set the regid for frag_coord,
3542 * we have to use r0.x for it. But we don't want to *always*
3543 * use r1.x for frag_pos as that could increase the register
3544 * footprint on simple shaders:
3546 if (so
->frag_coord
) {
3547 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3548 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3549 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3550 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3552 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3553 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3554 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3555 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3558 /* we always have frag_pos: */
3559 so
->pos_regid
= regid
;
3562 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3563 instr
->regs
[0]->num
= regid
++;
3564 inputs
[ir
->ninputs
++] = instr
;
3565 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3568 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3569 instr
->regs
[0]->num
= regid
++;
3570 inputs
[ir
->ninputs
++] = instr
;
3571 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3573 ir
->inputs
= inputs
;
3576 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3577 * need to assign the tex state indexes for these after we know the
3581 fixup_astc_srgb(struct ir3_context
*ctx
)
3583 struct ir3_shader_variant
*so
= ctx
->so
;
3584 /* indexed by original tex idx, value is newly assigned alpha sampler
3585 * state tex idx. Zero is invalid since there is at least one sampler
3588 unsigned alt_tex_state
[16] = {0};
3589 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3592 so
->astc_srgb
.base
= tex_idx
;
3594 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3595 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3597 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3599 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3600 /* assign new alternate/alpha tex state slot: */
3601 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3602 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3603 so
->astc_srgb
.count
++;
3606 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3611 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3612 struct ir3_shader_variant
*so
)
3614 struct ir3_context
*ctx
;
3616 struct ir3_instruction
**inputs
;
3617 unsigned i
, j
, actual_in
, inloc
;
3618 int ret
= 0, max_bary
;
3622 ctx
= compile_init(compiler
, so
);
3624 DBG("INIT failed!");
3629 emit_instructions(ctx
);
3632 DBG("EMIT failed!");
3637 ir
= so
->ir
= ctx
->ir
;
3639 /* keep track of the inputs from TGSI perspective.. */
3640 inputs
= ir
->inputs
;
3642 /* but fixup actual inputs for frag shader: */
3643 if (so
->type
== SHADER_FRAGMENT
)
3644 fixup_frag_inputs(ctx
);
3646 /* at this point, for binning pass, throw away unneeded outputs: */
3647 if (so
->key
.binning_pass
) {
3648 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3649 unsigned slot
= so
->outputs
[i
].slot
;
3651 /* throw away everything but first position/psize */
3652 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3654 so
->outputs
[j
] = so
->outputs
[i
];
3655 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3656 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3657 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3658 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3663 so
->outputs_count
= j
;
3664 ir
->noutputs
= j
* 4;
3667 /* if we want half-precision outputs, mark the output registers
3670 if (so
->key
.half_precision
) {
3671 for (i
= 0; i
< ir
->noutputs
; i
++) {
3672 struct ir3_instruction
*out
= ir
->outputs
[i
];
3677 /* if frag shader writes z, that needs to be full precision: */
3678 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3681 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3682 /* output could be a fanout (ie. texture fetch output)
3683 * in which case we need to propagate the half-reg flag
3684 * up to the definer so that RA sees it:
3686 if (out
->opc
== OPC_META_FO
) {
3687 out
= out
->regs
[1]->instr
;
3688 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3691 if (out
->opc
== OPC_MOV
) {
3692 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3697 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3698 printf("BEFORE CP:\n");
3704 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3705 printf("BEFORE GROUPING:\n");
3709 ir3_sched_add_deps(ir
);
3711 /* Group left/right neighbors, inserting mov's where needed to
3716 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3717 printf("AFTER GROUPING:\n");
3723 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3724 printf("AFTER DEPTH:\n");
3728 ret
= ir3_sched(ir
);
3730 DBG("SCHED failed!");
3734 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3735 printf("AFTER SCHED:\n");
3739 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3745 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3746 printf("AFTER RA:\n");
3750 /* fixup input/outputs: */
3751 for (i
= 0; i
< so
->outputs_count
; i
++) {
3752 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3755 /* Note that some or all channels of an input may be unused: */
3758 for (i
= 0; i
< so
->inputs_count
; i
++) {
3759 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3760 so
->inputs
[i
].ncomp
= 0;
3761 so
->inputs
[i
].inloc
= inloc
;
3762 for (j
= 0; j
< 4; j
++) {
3763 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3764 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3765 compmask
|= (1 << j
);
3766 regid
= in
->regs
[0]->num
- j
;
3768 so
->inputs
[i
].ncomp
++;
3769 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3771 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3772 in
->regs
[1]->iim_val
= inloc
+ j
;
3777 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3779 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3781 } else if (!so
->inputs
[i
].sysval
) {
3782 so
->inputs
[i
].compmask
= compmask
;
3784 so
->inputs
[i
].regid
= regid
;
3788 fixup_astc_srgb(ctx
);
3790 /* We need to do legalize after (for frag shader's) the "bary.f"
3791 * offsets (inloc) have been assigned.
3793 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3795 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3796 printf("AFTER LEGALIZE:\n");
3800 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3801 if (so
->type
== SHADER_VERTEX
)
3802 so
->total_in
= actual_in
;
3804 so
->total_in
= max_bary
+ 1;
3809 ir3_destroy(so
->ir
);