1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* mapping from nir_register to defining instruction: */
78 struct hash_table
*def_ht
;
82 /* a common pattern for indirect addressing is to request the
83 * same address register multiple times. To avoid generating
84 * duplicate instruction sequences (which our backend does not
85 * try to clean up, since that should be done as the NIR stage)
86 * we cache the address value generated for a given src value:
88 * Note that we have to cache these per alignment, since same
89 * src used for an array of vec1 cannot be also used for an
92 struct hash_table
*addr_ht
[4];
94 /* last dst array, for indirect we need to insert a var-store.
96 struct ir3_instruction
**last_dst
;
99 /* maps nir_block to ir3_block, mostly for the purposes of
100 * figuring out the blocks successors
102 struct hash_table
*block_ht
;
104 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
105 * so we need to use ldlv.u32 to load the varying directly:
109 /* on a3xx, we need to add one to # of array levels:
113 /* on a3xx, we need to scale up integer coords for isaml based
116 bool unminify_coords
;
118 /* on a4xx, for array textures we need to add 0.5 to the array
121 bool array_index_add_half
;
123 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
126 unsigned max_texture_index
;
128 /* set if we encounter something we can't handle yet, so we
129 * can bail cleanly and fallback to TGSI compiler f/e
134 /* gpu pointer size in units of 32bit registers/slots */
135 static unsigned pointer_size(struct ir3_context
*ctx
)
137 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
140 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
141 static struct ir3_block
* get_block(struct ir3_context
*ctx
, nir_block
*nblock
);
144 static struct ir3_context
*
145 compile_init(struct ir3_compiler
*compiler
,
146 struct ir3_shader_variant
*so
)
148 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
150 if (compiler
->gpu_id
>= 400) {
151 /* need special handling for "flat" */
152 ctx
->flat_bypass
= true;
153 ctx
->levels_add_one
= false;
154 ctx
->unminify_coords
= false;
155 ctx
->array_index_add_half
= true;
157 if (so
->type
== SHADER_VERTEX
)
158 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
159 else if (so
->type
== SHADER_FRAGMENT
)
160 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
163 /* no special handling for "flat" */
164 ctx
->flat_bypass
= false;
165 ctx
->levels_add_one
= true;
166 ctx
->unminify_coords
= true;
167 ctx
->array_index_add_half
= false;
170 ctx
->compiler
= compiler
;
173 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
174 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
175 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
176 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
178 /* TODO: maybe generate some sort of bitmask of what key
179 * lowers vs what shader has (ie. no need to lower
180 * texture clamp lowering if no texture sample instrs)..
181 * although should be done further up the stack to avoid
182 * creating duplicate variants..
185 if (ir3_key_lowers_nir(&so
->key
)) {
186 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
187 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
189 /* fast-path for shader key that lowers nothing in NIR: */
190 ctx
->s
= so
->shader
->nir
;
193 /* this needs to be the last pass run, so do this here instead of
194 * in ir3_optimize_nir():
196 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
198 if (fd_mesa_debug
& FD_DBG_DISASM
) {
199 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
200 so
->shader
->id
, so
->id
, so
->type
,
201 so
->key
.binning_pass
, so
->key
.color_two_side
,
202 so
->key
.half_precision
);
203 nir_print_shader(ctx
->s
, stdout
);
206 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
208 so
->num_uniforms
= ctx
->s
->num_uniforms
;
209 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
211 /* Layout of constant registers, each section aligned to vec4. Note
212 * that pointer size (ubo, etc) changes depending on generation.
217 * if (vertex shader) {
218 * driver params (IR3_DP_*)
219 * if (stream_output.num_outputs > 0)
220 * stream-out addresses
224 * Immediates go last mostly because they are inserted in the CP pass
225 * after the nir -> ir3 frontend.
227 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
228 unsigned ptrsz
= pointer_size(ctx
);
230 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
232 if (so
->num_ubos
> 0) {
233 so
->constbase
.ubo
= constoff
;
234 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
237 if (so
->const_layout
.ssbo_size
.count
> 0) {
238 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
239 so
->constbase
.ssbo_sizes
= constoff
;
240 constoff
+= align(cnt
, 4) / 4;
243 if (so
->const_layout
.image_dims
.count
> 0) {
244 unsigned cnt
= so
->const_layout
.image_dims
.count
;
245 so
->constbase
.image_dims
= constoff
;
246 constoff
+= align(cnt
, 4) / 4;
249 unsigned num_driver_params
= 0;
250 if (so
->type
== SHADER_VERTEX
) {
251 num_driver_params
= IR3_DP_VS_COUNT
;
252 } else if (so
->type
== SHADER_COMPUTE
) {
253 num_driver_params
= IR3_DP_CS_COUNT
;
256 so
->constbase
.driver_param
= constoff
;
257 constoff
+= align(num_driver_params
, 4) / 4;
259 if ((so
->type
== SHADER_VERTEX
) &&
260 (compiler
->gpu_id
< 500) &&
261 so
->shader
->stream_output
.num_outputs
> 0) {
262 so
->constbase
.tfbo
= constoff
;
263 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
266 so
->constbase
.immediate
= constoff
;
272 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
275 va_start(ap
, format
);
276 _debug_vprintf(format
, ap
);
278 nir_print_shader(ctx
->s
, stdout
);
283 #define compile_assert(ctx, cond) do { \
284 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
288 compile_free(struct ir3_context
*ctx
)
294 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
296 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
297 arr
->id
= ++ctx
->num_arrays
;
298 /* NOTE: sometimes we get non array regs, for example for arrays of
299 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
300 * treat a non-array as if it was an array of length 1.
302 * It would be nice if there was a nir pass to convert arrays of
305 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
306 compile_assert(ctx
, arr
->length
> 0);
308 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
311 static struct ir3_array
*
312 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
314 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
318 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
322 /* relative (indirect) if address!=NULL */
323 static struct ir3_instruction
*
324 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
325 struct ir3_instruction
*address
)
327 struct ir3_block
*block
= ctx
->block
;
328 struct ir3_instruction
*mov
;
329 struct ir3_register
*src
;
331 mov
= ir3_instr_create(block
, OPC_MOV
);
332 mov
->cat1
.src_type
= TYPE_U32
;
333 mov
->cat1
.dst_type
= TYPE_U32
;
334 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
335 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
336 ir3_reg_create(mov
, 0, 0);
337 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
338 COND(address
, IR3_REG_RELATIV
));
339 src
->instr
= arr
->last_write
;
340 src
->size
= arr
->length
;
341 src
->array
.id
= arr
->id
;
342 src
->array
.offset
= n
;
345 ir3_instr_set_address(mov
, address
);
350 /* relative (indirect) if address!=NULL */
351 static struct ir3_instruction
*
352 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
353 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
355 struct ir3_block
*block
= ctx
->block
;
356 struct ir3_instruction
*mov
;
357 struct ir3_register
*dst
;
359 mov
= ir3_instr_create(block
, OPC_MOV
);
360 mov
->cat1
.src_type
= TYPE_U32
;
361 mov
->cat1
.dst_type
= TYPE_U32
;
362 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
363 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
364 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
365 COND(address
, IR3_REG_RELATIV
));
366 dst
->instr
= arr
->last_write
;
367 dst
->size
= arr
->length
;
368 dst
->array
.id
= arr
->id
;
369 dst
->array
.offset
= n
;
370 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
373 ir3_instr_set_address(mov
, address
);
375 arr
->last_write
= mov
;
380 /* allocate a n element value array (to be populated by caller) and
383 static struct ir3_instruction
**
384 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
386 struct ir3_instruction
**value
=
387 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
388 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
392 static struct ir3_instruction
**
393 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
395 struct ir3_instruction
**value
;
398 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
400 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
403 /* NOTE: in non-ssa case, we don't really need to store last_dst
404 * but this helps us catch cases where put_dst() call is forgotten
406 compile_assert(ctx
, !ctx
->last_dst
);
407 ctx
->last_dst
= value
;
413 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
415 static struct ir3_instruction
* const *
416 get_src(struct ir3_context
*ctx
, nir_src
*src
)
419 struct hash_entry
*entry
;
420 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
421 compile_assert(ctx
, entry
);
424 nir_register
*reg
= src
->reg
.reg
;
425 struct ir3_array
*arr
= get_array(ctx
, reg
);
426 unsigned num_components
= arr
->r
->num_components
;
427 struct ir3_instruction
*addr
= NULL
;
428 struct ir3_instruction
**value
=
429 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
431 if (src
->reg
.indirect
)
432 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
433 reg
->num_components
);
435 for (unsigned i
= 0; i
< num_components
; i
++) {
436 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
437 compile_assert(ctx
, n
< arr
->length
);
438 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
446 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
449 nir_register
*reg
= dst
->reg
.reg
;
450 struct ir3_array
*arr
= get_array(ctx
, reg
);
451 unsigned num_components
= ctx
->last_dst_n
;
452 struct ir3_instruction
*addr
= NULL
;
454 if (dst
->reg
.indirect
)
455 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
456 reg
->num_components
);
458 for (unsigned i
= 0; i
< num_components
; i
++) {
459 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
460 compile_assert(ctx
, n
< arr
->length
);
461 if (!ctx
->last_dst
[i
])
463 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
466 ralloc_free(ctx
->last_dst
);
468 ctx
->last_dst
= NULL
;
472 static struct ir3_instruction
*
473 create_immed(struct ir3_block
*block
, uint32_t val
)
475 struct ir3_instruction
*mov
;
477 mov
= ir3_instr_create(block
, OPC_MOV
);
478 mov
->cat1
.src_type
= TYPE_U32
;
479 mov
->cat1
.dst_type
= TYPE_U32
;
480 ir3_reg_create(mov
, 0, 0);
481 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
486 static struct ir3_instruction
*
487 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
489 struct ir3_instruction
*instr
, *immed
;
491 /* TODO in at least some cases, the backend could probably be
492 * made clever enough to propagate IR3_REG_HALF..
494 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
495 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
502 /* src *= 2 => src <<= 1: */
503 immed
= create_immed(block
, 1);
504 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
506 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
507 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
508 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
512 immed
= create_immed(block
, 3);
513 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
515 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
516 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
517 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
520 /* src *= 4 => src <<= 2: */
521 immed
= create_immed(block
, 2);
522 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
524 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
525 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
526 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
529 unreachable("bad align");
533 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
534 instr
->regs
[0]->num
= regid(REG_A0
, 0);
535 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
536 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
541 /* caches addr values to avoid generating multiple cov/shl/mova
542 * sequences for each use of a given NIR level src as address
544 static struct ir3_instruction
*
545 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
547 struct ir3_instruction
*addr
;
548 unsigned idx
= align
- 1;
550 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
552 if (!ctx
->addr_ht
[idx
]) {
553 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
554 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
556 struct hash_entry
*entry
;
557 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
562 addr
= create_addr(ctx
->block
, src
, align
);
563 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
568 static struct ir3_instruction
*
569 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
571 struct ir3_block
*b
= ctx
->block
;
572 struct ir3_instruction
*cond
;
574 /* NOTE: only cmps.*.* can write p0.x: */
575 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
576 cond
->cat2
.condition
= IR3_COND_NE
;
578 /* condition always goes in predicate register: */
579 cond
->regs
[0]->num
= regid(REG_P0
, 0);
584 static struct ir3_instruction
*
585 create_uniform(struct ir3_context
*ctx
, unsigned n
)
587 struct ir3_instruction
*mov
;
589 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
590 /* TODO get types right? */
591 mov
->cat1
.src_type
= TYPE_F32
;
592 mov
->cat1
.dst_type
= TYPE_F32
;
593 ir3_reg_create(mov
, 0, 0);
594 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
599 static struct ir3_instruction
*
600 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
601 struct ir3_instruction
*address
)
603 struct ir3_instruction
*mov
;
605 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
606 mov
->cat1
.src_type
= TYPE_U32
;
607 mov
->cat1
.dst_type
= TYPE_U32
;
608 ir3_reg_create(mov
, 0, 0);
609 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
611 ir3_instr_set_address(mov
, address
);
616 static struct ir3_instruction
*
617 create_collect(struct ir3_block
*block
, struct ir3_instruction
*const *arr
,
620 struct ir3_instruction
*collect
;
625 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
626 ir3_reg_create(collect
, 0, 0); /* dst */
627 for (unsigned i
= 0; i
< arrsz
; i
++)
628 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
633 static struct ir3_instruction
*
634 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
635 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
637 struct ir3_block
*block
= ctx
->block
;
638 struct ir3_instruction
*mov
;
639 struct ir3_register
*src
;
641 mov
= ir3_instr_create(block
, OPC_MOV
);
642 mov
->cat1
.src_type
= TYPE_U32
;
643 mov
->cat1
.dst_type
= TYPE_U32
;
644 ir3_reg_create(mov
, 0, 0);
645 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
646 src
->instr
= collect
;
648 src
->array
.offset
= n
;
650 ir3_instr_set_address(mov
, address
);
655 static struct ir3_instruction
*
656 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
658 struct ir3_instruction
*in
;
660 in
= ir3_instr_create(block
, OPC_META_INPUT
);
661 in
->inout
.block
= block
;
662 ir3_reg_create(in
, n
, 0);
664 in
->regs
[0]->wrmask
= compmask
;
669 static struct ir3_instruction
*
670 create_input(struct ir3_block
*block
, unsigned n
)
672 return create_input_compmask(block
, n
, 0x1);
675 static struct ir3_instruction
*
676 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
678 struct ir3_block
*block
= ctx
->block
;
679 struct ir3_instruction
*instr
;
680 /* actual inloc is assigned and fixed up later: */
681 struct ir3_instruction
*inloc
= create_immed(block
, 0);
684 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
685 instr
->cat6
.type
= TYPE_U32
;
686 instr
->cat6
.iim_val
= 1;
688 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
689 instr
->regs
[2]->wrmask
= 0x3;
695 static struct ir3_instruction
*
696 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
698 struct ir3_block
*block
= ctx
->block
;
699 struct ir3_instruction
*instr
;
701 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
703 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
708 /* for frag_coord, we get unsigned values.. we need
709 * to subtract (integer) 8 and divide by 16 (right-
710 * shift by 4) then convert to float:
714 * mov.u32f32 dst, tmp
717 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
718 create_immed(block
, 8), 0);
719 instr
= ir3_SHR_B(block
, instr
, 0,
720 create_immed(block
, 4), 0);
721 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
727 /* seems that we can use these as-is: */
728 return ctx
->frag_coord
[comp
];
732 static struct ir3_instruction
*
733 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
735 /* first four vec4 sysval's reserved for UBOs: */
736 /* NOTE: dp is in scalar, but there can be >4 dp components: */
737 unsigned n
= ctx
->so
->constbase
.driver_param
;
738 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
739 return create_uniform(ctx
, r
);
742 /* helper for instructions that produce multiple consecutive scalar
743 * outputs which need to have a split/fanout meta instruction inserted
746 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
747 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
749 struct ir3_instruction
*prev
= NULL
;
750 for (int i
= 0, j
= 0; i
< n
; i
++) {
751 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
752 ir3_reg_create(split
, 0, IR3_REG_SSA
);
753 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
754 split
->fo
.off
= i
+ base
;
757 split
->cp
.left
= prev
;
758 split
->cp
.left_cnt
++;
759 prev
->cp
.right
= split
;
760 prev
->cp
.right_cnt
++;
764 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
770 * Adreno uses uint rather than having dedicated bool type,
771 * which (potentially) requires some conversion, in particular
772 * when using output of an bool instr to int input, or visa
776 * -------+---------+-------+-
780 * To convert from an adreno bool (uint) to nir, use:
782 * absneg.s dst, (neg)src
784 * To convert back in the other direction:
786 * absneg.s dst, (abs)arc
788 * The CP step can clean up the absneg.s that cancel each other
789 * out, and with a slight bit of extra cleverness (to recognize
790 * the instructions which produce either a 0 or 1) can eliminate
791 * the absneg.s's completely when an instruction that wants
792 * 0/1 consumes the result. For example, when a nir 'bcsel'
793 * consumes the result of 'feq'. So we should be able to get by
794 * without a boolean resolve step, and without incuring any
795 * extra penalty in instruction count.
798 /* NIR bool -> native (adreno): */
799 static struct ir3_instruction
*
800 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
802 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
805 /* native (adreno) -> NIR bool: */
806 static struct ir3_instruction
*
807 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
809 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
813 * alu/sfu instructions:
817 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
819 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
820 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
821 struct ir3_block
*b
= ctx
->block
;
822 unsigned dst_sz
, wrmask
;
824 if (alu
->dest
.dest
.is_ssa
) {
825 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
826 wrmask
= (1 << dst_sz
) - 1;
828 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
829 wrmask
= alu
->dest
.write_mask
;
832 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
834 /* Vectors are special in that they have non-scalarized writemasks,
835 * and just take the first swizzle channel for each argument in
836 * order into each writemask channel.
838 if ((alu
->op
== nir_op_vec2
) ||
839 (alu
->op
== nir_op_vec3
) ||
840 (alu
->op
== nir_op_vec4
)) {
842 for (int i
= 0; i
< info
->num_inputs
; i
++) {
843 nir_alu_src
*asrc
= &alu
->src
[i
];
845 compile_assert(ctx
, !asrc
->abs
);
846 compile_assert(ctx
, !asrc
->negate
);
848 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
850 src
[i
] = create_immed(ctx
->block
, 0);
851 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
854 put_dst(ctx
, &alu
->dest
.dest
);
858 /* We also get mov's with more than one component for mov's so
859 * handle those specially:
861 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
862 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
863 nir_alu_src
*asrc
= &alu
->src
[0];
864 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
866 for (unsigned i
= 0; i
< dst_sz
; i
++) {
867 if (wrmask
& (1 << i
)) {
868 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
874 put_dst(ctx
, &alu
->dest
.dest
);
878 compile_assert(ctx
, alu
->dest
.dest
.is_ssa
);
880 /* General case: We can just grab the one used channel per src. */
881 for (int i
= 0; i
< info
->num_inputs
; i
++) {
882 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
883 nir_alu_src
*asrc
= &alu
->src
[i
];
885 compile_assert(ctx
, !asrc
->abs
);
886 compile_assert(ctx
, !asrc
->negate
);
888 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
890 compile_assert(ctx
, src
[i
]);
895 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
898 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
901 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
904 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
907 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
908 dst
[0]->cat2
.condition
= IR3_COND_NE
;
909 dst
[0] = ir3_n2b(b
, dst
[0]);
912 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
915 dst
[0] = ir3_b2n(b
, src
[0]);
918 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
919 dst
[0]->cat2
.condition
= IR3_COND_NE
;
920 dst
[0] = ir3_n2b(b
, dst
[0]);
924 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
927 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
930 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
933 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
936 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
939 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
942 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
945 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
948 dst
[0] = ir3_DSX(b
, src
[0], 0);
949 dst
[0]->cat5
.type
= TYPE_F32
;
952 dst
[0] = ir3_DSY(b
, src
[0], 0);
953 dst
[0]->cat5
.type
= TYPE_F32
;
957 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
958 dst
[0]->cat2
.condition
= IR3_COND_LT
;
959 dst
[0] = ir3_n2b(b
, dst
[0]);
962 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
963 dst
[0]->cat2
.condition
= IR3_COND_GE
;
964 dst
[0] = ir3_n2b(b
, dst
[0]);
967 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
968 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
969 dst
[0] = ir3_n2b(b
, dst
[0]);
972 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
973 dst
[0]->cat2
.condition
= IR3_COND_NE
;
974 dst
[0] = ir3_n2b(b
, dst
[0]);
977 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
980 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
983 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
985 case nir_op_fround_even
:
986 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
989 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
993 dst
[0] = ir3_SIN(b
, src
[0], 0);
996 dst
[0] = ir3_COS(b
, src
[0], 0);
999 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1002 dst
[0] = ir3_RCP(b
, src
[0], 0);
1005 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1008 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1011 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1015 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1018 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1021 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1024 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1027 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1030 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1033 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1037 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1038 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1039 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1040 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1042 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1043 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1044 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1047 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1050 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1053 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1056 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1059 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1061 case nir_op_isign
: {
1062 /* maybe this would be sane to lower in nir.. */
1063 struct ir3_instruction
*neg
, *pos
;
1065 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1066 neg
->cat2
.condition
= IR3_COND_LT
;
1068 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1069 pos
->cat2
.condition
= IR3_COND_GT
;
1071 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1076 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1079 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1082 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1085 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1086 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1087 dst
[0] = ir3_n2b(b
, dst
[0]);
1090 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1091 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1092 dst
[0] = ir3_n2b(b
, dst
[0]);
1095 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1096 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1097 dst
[0] = ir3_n2b(b
, dst
[0]);
1100 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1101 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1102 dst
[0] = ir3_n2b(b
, dst
[0]);
1105 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1106 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1107 dst
[0] = ir3_n2b(b
, dst
[0]);
1110 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1111 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1112 dst
[0] = ir3_n2b(b
, dst
[0]);
1116 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1119 case nir_op_bit_count
:
1120 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1122 case nir_op_ifind_msb
: {
1123 struct ir3_instruction
*cmp
;
1124 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1125 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1126 cmp
->cat2
.condition
= IR3_COND_GE
;
1127 dst
[0] = ir3_SEL_B32(b
,
1128 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1132 case nir_op_ufind_msb
:
1133 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1134 dst
[0] = ir3_SEL_B32(b
,
1135 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1136 src
[0], 0, dst
[0], 0);
1138 case nir_op_find_lsb
:
1139 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1140 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1142 case nir_op_bitfield_reverse
:
1143 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1147 compile_error(ctx
, "Unhandled ALU op: %s\n",
1148 nir_op_infos
[alu
->op
].name
);
1152 put_dst(ctx
, &alu
->dest
.dest
);
1155 /* handles direct/indirect UBO reads: */
1157 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1158 struct ir3_instruction
**dst
)
1160 struct ir3_block
*b
= ctx
->block
;
1161 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1162 nir_const_value
*const_offset
;
1163 /* UBO addresses are the first driver params: */
1164 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1165 const unsigned ptrsz
= pointer_size(ctx
);
1169 /* First src is ubo index, which could either be an immed or not: */
1170 src0
= get_src(ctx
, &intr
->src
[0])[0];
1171 if (is_same_type_mov(src0
) &&
1172 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1173 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1174 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1176 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1177 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1180 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1183 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1185 off
+= const_offset
->u32
[0];
1187 /* For load_ubo_indirect, second src is indirect offset: */
1188 src1
= get_src(ctx
, &intr
->src
[1])[0];
1190 /* and add offset to addr: */
1191 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1194 /* if offset is to large to encode in the ldg, split it out: */
1195 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1196 /* split out the minimal amount to improve the odds that
1197 * cp can fit the immediate in the add.s instruction:
1199 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1200 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1205 struct ir3_instruction
*carry
;
1207 /* handle 32b rollover, ie:
1208 * if (addr < base_lo)
1211 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1212 carry
->cat2
.condition
= IR3_COND_LT
;
1213 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1215 addr
= create_collect(b
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1218 for (int i
= 0; i
< intr
->num_components
; i
++) {
1219 struct ir3_instruction
*load
=
1220 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1221 load
->cat6
.type
= TYPE_U32
;
1222 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1227 /* src[] = { buffer_index, offset }. No const_index */
1229 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1230 struct ir3_instruction
**dst
)
1232 struct ir3_block
*b
= ctx
->block
;
1233 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1234 nir_const_value
*const_offset
;
1236 /* can this be non-const buffer_index? how do we handle that? */
1237 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1238 compile_assert(ctx
, const_offset
);
1240 offset
= get_src(ctx
, &intr
->src
[1])[0];
1242 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1243 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1247 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1249 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1251 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1252 ldgb
->cat6
.iim_val
= intr
->num_components
;
1254 ldgb
->cat6
.type
= TYPE_U32
;
1255 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1256 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1258 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1261 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1263 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1265 struct ir3_block
*b
= ctx
->block
;
1266 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1267 nir_const_value
*const_offset
;
1268 /* TODO handle wrmask properly, see _store_shared().. but I think
1269 * it is more a PITA than that, since blob ends up loading the
1270 * masked components and writing them back out.
1272 unsigned wrmask
= intr
->const_index
[0];
1273 unsigned ncomp
= ffs(~wrmask
) - 1;
1275 /* can this be non-const buffer_index? how do we handle that? */
1276 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1277 compile_assert(ctx
, const_offset
);
1279 offset
= get_src(ctx
, &intr
->src
[2])[0];
1281 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1284 src0
= create_collect(b
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1285 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1286 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1291 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1292 src0
, 0, src1
, 0, src2
, 0);
1293 stgb
->cat6
.iim_val
= ncomp
;
1295 stgb
->cat6
.type
= TYPE_U32
;
1296 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1297 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1299 array_insert(b
, b
->keeps
, stgb
);
1302 /* src[] = { block_index } */
1304 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1305 struct ir3_instruction
**dst
)
1307 /* SSBO size stored as a const starting at ssbo_sizes: */
1308 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1309 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1310 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1312 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1314 dst
[0] = create_uniform(ctx
, idx
);
1318 * SSBO atomic intrinsics
1320 * All of the SSBO atomic memory operations read a value from memory,
1321 * compute a new value using one of the operations below, write the new
1322 * value to memory, and return the original value read.
1324 * All operations take 3 sources except CompSwap that takes 4. These
1325 * sources represent:
1327 * 0: The SSBO buffer index.
1328 * 1: The offset into the SSBO buffer of the variable that the atomic
1329 * operation will operate on.
1330 * 2: The data parameter to the atomic function (i.e. the value to add
1331 * in ssbo_atomic_add, etc).
1332 * 3: For CompSwap only: the second data parameter.
1334 static struct ir3_instruction
*
1335 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1337 struct ir3_block
*b
= ctx
->block
;
1338 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1339 nir_const_value
*const_offset
;
1340 type_t type
= TYPE_U32
;
1342 /* can this be non-const buffer_index? how do we handle that? */
1343 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1344 compile_assert(ctx
, const_offset
);
1345 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1347 offset
= get_src(ctx
, &intr
->src
[1])[0];
1349 /* src0 is data (or uvec2(data, compare))
1351 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1353 * Note that nir already multiplies the offset by four
1355 src0
= get_src(ctx
, &intr
->src
[2])[0];
1356 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1357 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1362 switch (intr
->intrinsic
) {
1363 case nir_intrinsic_ssbo_atomic_add
:
1364 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1366 case nir_intrinsic_ssbo_atomic_imin
:
1367 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1370 case nir_intrinsic_ssbo_atomic_umin
:
1371 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1373 case nir_intrinsic_ssbo_atomic_imax
:
1374 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1377 case nir_intrinsic_ssbo_atomic_umax
:
1378 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1380 case nir_intrinsic_ssbo_atomic_and
:
1381 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1383 case nir_intrinsic_ssbo_atomic_or
:
1384 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1386 case nir_intrinsic_ssbo_atomic_xor
:
1387 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1389 case nir_intrinsic_ssbo_atomic_exchange
:
1390 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1392 case nir_intrinsic_ssbo_atomic_comp_swap
:
1393 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1394 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1396 get_src(ctx
, &intr
->src
[3])[0],
1398 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1404 atomic
->cat6
.iim_val
= 1;
1406 atomic
->cat6
.type
= type
;
1407 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1408 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1410 /* even if nothing consume the result, we can't DCE the instruction: */
1411 array_insert(b
, b
->keeps
, atomic
);
1416 /* src[] = { offset }. const_index[] = { base } */
1418 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1419 struct ir3_instruction
**dst
)
1421 struct ir3_block
*b
= ctx
->block
;
1422 struct ir3_instruction
*ldl
, *offset
;
1425 offset
= get_src(ctx
, &intr
->src
[0])[0];
1426 base
= intr
->const_index
[0];
1428 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1429 ldl
->cat6
.src_offset
= base
;
1430 ldl
->cat6
.type
= TYPE_U32
;
1431 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1433 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1434 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1436 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1439 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1441 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1443 struct ir3_block
*b
= ctx
->block
;
1444 struct ir3_instruction
*stl
, *offset
;
1445 struct ir3_instruction
* const *value
;
1446 unsigned base
, wrmask
;
1448 value
= get_src(ctx
, &intr
->src
[0]);
1449 offset
= get_src(ctx
, &intr
->src
[1])[0];
1451 base
= intr
->const_index
[0];
1452 wrmask
= intr
->const_index
[1];
1454 /* Combine groups of consecutive enabled channels in one write
1455 * message. We use ffs to find the first enabled channel and then ffs on
1456 * the bit-inverse, down-shifted writemask to determine the length of
1457 * the block of enabled bits.
1459 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1462 unsigned first_component
= ffs(wrmask
) - 1;
1463 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1465 stl
= ir3_STL(b
, offset
, 0,
1466 create_collect(b
, &value
[first_component
], length
), 0,
1467 create_immed(b
, length
), 0);
1468 stl
->cat6
.dst_offset
= first_component
+ base
;
1469 stl
->cat6
.type
= TYPE_U32
;
1470 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1471 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1473 array_insert(b
, b
->keeps
, stl
);
1475 /* Clear the bits in the writemask that we just wrote, then try
1476 * again to see if more channels are left.
1478 wrmask
&= (15 << (first_component
+ length
));
1483 * CS shared variable atomic intrinsics
1485 * All of the shared variable atomic memory operations read a value from
1486 * memory, compute a new value using one of the operations below, write the
1487 * new value to memory, and return the original value read.
1489 * All operations take 2 sources except CompSwap that takes 3. These
1490 * sources represent:
1492 * 0: The offset into the shared variable storage region that the atomic
1493 * operation will operate on.
1494 * 1: The data parameter to the atomic function (i.e. the value to add
1495 * in shared_atomic_add, etc).
1496 * 2: For CompSwap only: the second data parameter.
1498 static struct ir3_instruction
*
1499 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1501 struct ir3_block
*b
= ctx
->block
;
1502 struct ir3_instruction
*atomic
, *src0
, *src1
;
1503 type_t type
= TYPE_U32
;
1505 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1506 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1508 switch (intr
->intrinsic
) {
1509 case nir_intrinsic_shared_atomic_add
:
1510 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1512 case nir_intrinsic_shared_atomic_imin
:
1513 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1516 case nir_intrinsic_shared_atomic_umin
:
1517 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1519 case nir_intrinsic_shared_atomic_imax
:
1520 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1523 case nir_intrinsic_shared_atomic_umax
:
1524 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1526 case nir_intrinsic_shared_atomic_and
:
1527 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1529 case nir_intrinsic_shared_atomic_or
:
1530 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1532 case nir_intrinsic_shared_atomic_xor
:
1533 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1535 case nir_intrinsic_shared_atomic_exchange
:
1536 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1538 case nir_intrinsic_shared_atomic_comp_swap
:
1539 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1540 src1
= create_collect(b
, (struct ir3_instruction
*[]){
1541 get_src(ctx
, &intr
->src
[2])[0],
1544 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1550 atomic
->cat6
.iim_val
= 1;
1552 atomic
->cat6
.type
= type
;
1553 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1554 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1556 /* even if nothing consume the result, we can't DCE the instruction: */
1557 array_insert(b
, b
->keeps
, atomic
);
1562 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1563 * state block (for load). To simplify things, invert the image id and
1564 * map it from end of state block, ie. image 0 becomes num-1, image 1
1565 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1566 * state when switching shaders.
1568 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1569 * coded. Also, since all the gl shader stages (ie. everything but CS)
1570 * share the same SSBO/image state block, this might require some more
1571 * logic if we supported images in anything other than FS..
1574 get_image_slot(struct ir3_context
*ctx
, const nir_variable
*var
)
1576 /* TODO figure out real limit per generation, and don't hardcode: */
1577 const unsigned max_samplers
= 16;
1578 return max_samplers
- var
->data
.driver_location
- 1;
1582 get_image_coords(const nir_variable
*var
)
1584 switch (glsl_get_sampler_dim(glsl_without_array(var
->type
))) {
1585 case GLSL_SAMPLER_DIM_1D
:
1586 case GLSL_SAMPLER_DIM_BUF
:
1589 case GLSL_SAMPLER_DIM_2D
:
1590 case GLSL_SAMPLER_DIM_RECT
:
1591 case GLSL_SAMPLER_DIM_EXTERNAL
:
1592 case GLSL_SAMPLER_DIM_MS
:
1594 case GLSL_SAMPLER_DIM_3D
:
1595 case GLSL_SAMPLER_DIM_CUBE
:
1598 unreachable("bad sampler dim");
1604 get_image_type(const nir_variable
*var
)
1606 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1607 case GLSL_TYPE_UINT
:
1611 case GLSL_TYPE_FLOAT
:
1614 unreachable("bad sampler type.");
1619 static struct ir3_instruction
*
1620 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1621 struct ir3_instruction
* const *coords
, bool byteoff
)
1623 struct ir3_block
*b
= ctx
->block
;
1624 struct ir3_instruction
*offset
;
1625 unsigned ncoords
= get_image_coords(var
);
1627 /* to calculate the byte offset (yes, uggg) we need (up to) three
1628 * const values to know the bytes per pixel, and y and z stride:
1630 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1631 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1633 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1634 (1 << var
->data
.driver_location
));
1636 /* offset = coords.x * bytes_per_pixel: */
1637 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1639 /* offset += coords.y * y_pitch: */
1640 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1641 coords
[1], 0, offset
, 0);
1644 /* offset += coords.z * z_pitch: */
1645 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1646 coords
[2], 0, offset
, 0);
1650 /* Some cases, like atomics, seem to use dword offset instead
1651 * of byte offsets.. blob just puts an extra shr.b in there
1654 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1657 return create_collect(b
, (struct ir3_instruction
*[]){
1663 /* src[] = { coord, sample_index }. const_index[] = {} */
1665 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1666 struct ir3_instruction
**dst
)
1668 struct ir3_block
*b
= ctx
->block
;
1669 const nir_variable
*var
= intr
->variables
[0]->var
;
1670 struct ir3_instruction
*sam
;
1671 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1672 unsigned ncoords
= get_image_coords(var
);
1673 unsigned tex_idx
= get_image_slot(ctx
, var
);
1674 type_t type
= get_image_type(var
);
1678 flags
|= IR3_INSTR_3D
;
1680 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1681 tex_idx
, tex_idx
, create_collect(b
, coords
, ncoords
), NULL
);
1683 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1684 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1686 split_dest(b
, dst
, sam
, 0, 4);
1689 /* src[] = { coord, sample_index, value }. const_index[] = {} */
1691 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1693 struct ir3_block
*b
= ctx
->block
;
1694 const nir_variable
*var
= intr
->variables
[0]->var
;
1695 struct ir3_instruction
*stib
, *offset
;
1696 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
1697 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1698 unsigned ncoords
= get_image_coords(var
);
1699 unsigned tex_idx
= get_image_slot(ctx
, var
);
1703 * src2 is 64b byte offset
1706 offset
= get_image_offset(ctx
, var
, coords
, true);
1708 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1709 * too and takes a dword offset.. not quite sure yet why blob uses
1710 * one over the other in various cases.
1713 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
1714 create_collect(b
, value
, 4), 0,
1715 create_collect(b
, coords
, ncoords
), 0,
1717 stib
->cat6
.iim_val
= 4;
1718 stib
->cat6
.d
= ncoords
;
1719 stib
->cat6
.type
= get_image_type(var
);
1720 stib
->cat6
.typed
= true;
1721 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1722 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1724 array_insert(b
, b
->keeps
, stib
);
1728 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1729 struct ir3_instruction
**dst
)
1731 struct ir3_block
*b
= ctx
->block
;
1732 const nir_variable
*var
= intr
->variables
[0]->var
;
1733 unsigned ncoords
= get_image_coords(var
);
1734 unsigned tex_idx
= get_image_slot(ctx
, var
);
1735 struct ir3_instruction
*sam
, *lod
;
1739 flags
= IR3_INSTR_3D
;
1741 lod
= create_immed(b
, 0);
1742 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1743 tex_idx
, tex_idx
, lod
, NULL
);
1745 split_dest(b
, dst
, sam
, 0, ncoords
);
1748 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
1749 static struct ir3_instruction
*
1750 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1752 struct ir3_block
*b
= ctx
->block
;
1753 const nir_variable
*var
= intr
->variables
[0]->var
;
1754 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
1755 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1756 unsigned ncoords
= get_image_coords(var
);
1758 image
= create_immed(b
, get_image_slot(ctx
, var
));
1760 /* src0 is value (or uvec2(value, compare))
1762 * src2 is 64b byte offset
1764 src0
= get_src(ctx
, &intr
->src
[2])[0];
1765 src1
= create_collect(b
, coords
, ncoords
);
1766 src2
= get_image_offset(ctx
, var
, coords
, false);
1768 switch (intr
->intrinsic
) {
1769 case nir_intrinsic_image_atomic_add
:
1770 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1772 case nir_intrinsic_image_atomic_min
:
1773 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1775 case nir_intrinsic_image_atomic_max
:
1776 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1778 case nir_intrinsic_image_atomic_and
:
1779 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1781 case nir_intrinsic_image_atomic_or
:
1782 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1784 case nir_intrinsic_image_atomic_xor
:
1785 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1787 case nir_intrinsic_image_atomic_exchange
:
1788 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1790 case nir_intrinsic_image_atomic_comp_swap
:
1791 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1792 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1794 get_src(ctx
, &intr
->src
[3])[0],
1796 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1802 atomic
->cat6
.iim_val
= 1;
1803 atomic
->cat6
.d
= ncoords
;
1804 atomic
->cat6
.type
= get_image_type(var
);
1805 atomic
->cat6
.typed
= true;
1806 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1807 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1809 /* even if nothing consume the result, we can't DCE the instruction: */
1810 array_insert(b
, b
->keeps
, atomic
);
1816 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1818 struct ir3_block
*b
= ctx
->block
;
1819 struct ir3_instruction
*barrier
;
1821 switch (intr
->intrinsic
) {
1822 case nir_intrinsic_barrier
:
1823 barrier
= ir3_BAR(b
);
1824 barrier
->cat7
.g
= true;
1825 barrier
->cat7
.l
= true;
1826 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1827 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1829 case nir_intrinsic_memory_barrier
:
1830 barrier
= ir3_FENCE(b
);
1831 barrier
->cat7
.g
= true;
1832 barrier
->cat7
.r
= true;
1833 barrier
->cat7
.w
= true;
1834 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1835 IR3_BARRIER_BUFFER_W
;
1836 barrier
->barrier_conflict
=
1837 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1838 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1840 case nir_intrinsic_memory_barrier_atomic_counter
:
1841 case nir_intrinsic_memory_barrier_buffer
:
1842 barrier
= ir3_FENCE(b
);
1843 barrier
->cat7
.g
= true;
1844 barrier
->cat7
.r
= true;
1845 barrier
->cat7
.w
= true;
1846 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1847 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1848 IR3_BARRIER_BUFFER_W
;
1850 case nir_intrinsic_memory_barrier_image
:
1851 // TODO double check if this should have .g set
1852 barrier
= ir3_FENCE(b
);
1853 barrier
->cat7
.g
= true;
1854 barrier
->cat7
.r
= true;
1855 barrier
->cat7
.w
= true;
1856 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1857 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1858 IR3_BARRIER_IMAGE_W
;
1860 case nir_intrinsic_memory_barrier_shared
:
1861 barrier
= ir3_FENCE(b
);
1862 barrier
->cat7
.g
= true;
1863 barrier
->cat7
.l
= true;
1864 barrier
->cat7
.r
= true;
1865 barrier
->cat7
.w
= true;
1866 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1867 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1868 IR3_BARRIER_SHARED_W
;
1870 case nir_intrinsic_group_memory_barrier
:
1871 barrier
= ir3_FENCE(b
);
1872 barrier
->cat7
.g
= true;
1873 barrier
->cat7
.l
= true;
1874 barrier
->cat7
.r
= true;
1875 barrier
->cat7
.w
= true;
1876 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1877 IR3_BARRIER_IMAGE_W
|
1878 IR3_BARRIER_BUFFER_W
;
1879 barrier
->barrier_conflict
=
1880 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1881 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1882 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1888 /* make sure barrier doesn't get DCE'd */
1889 array_insert(b
, b
->keeps
, barrier
);
1892 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1893 gl_system_value slot
, unsigned compmask
,
1894 struct ir3_instruction
*instr
)
1896 struct ir3_shader_variant
*so
= ctx
->so
;
1897 unsigned r
= regid(so
->inputs_count
, 0);
1898 unsigned n
= so
->inputs_count
++;
1900 so
->inputs
[n
].sysval
= true;
1901 so
->inputs
[n
].slot
= slot
;
1902 so
->inputs
[n
].compmask
= compmask
;
1903 so
->inputs
[n
].regid
= r
;
1904 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1907 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1908 ctx
->ir
->inputs
[r
] = instr
;
1911 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1912 struct ir3_instruction
*instr
)
1914 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1918 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1920 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1921 struct ir3_instruction
**dst
;
1922 struct ir3_instruction
* const *src
;
1923 struct ir3_block
*b
= ctx
->block
;
1924 nir_const_value
*const_offset
;
1927 if (info
->has_dest
) {
1929 if (info
->dest_components
)
1930 n
= info
->dest_components
;
1932 n
= intr
->num_components
;
1933 dst
= get_dst(ctx
, &intr
->dest
, n
);
1938 switch (intr
->intrinsic
) {
1939 case nir_intrinsic_load_uniform
:
1940 idx
= nir_intrinsic_base(intr
);
1941 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1943 idx
+= const_offset
->u32
[0];
1944 for (int i
= 0; i
< intr
->num_components
; i
++) {
1945 unsigned n
= idx
* 4 + i
;
1946 dst
[i
] = create_uniform(ctx
, n
);
1949 src
= get_src(ctx
, &intr
->src
[0]);
1950 for (int i
= 0; i
< intr
->num_components
; i
++) {
1951 int n
= idx
* 4 + i
;
1952 dst
[i
] = create_uniform_indirect(ctx
, n
,
1953 get_addr(ctx
, src
[0], 4));
1955 /* NOTE: if relative addressing is used, we set
1956 * constlen in the compiler (to worst-case value)
1957 * since we don't know in the assembler what the max
1958 * addr reg value can be:
1960 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1963 case nir_intrinsic_load_ubo
:
1964 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1966 case nir_intrinsic_load_input
:
1967 idx
= nir_intrinsic_base(intr
);
1968 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1970 idx
+= const_offset
->u32
[0];
1971 for (int i
= 0; i
< intr
->num_components
; i
++) {
1972 unsigned n
= idx
* 4 + i
;
1973 dst
[i
] = ctx
->ir
->inputs
[n
];
1976 src
= get_src(ctx
, &intr
->src
[0]);
1977 struct ir3_instruction
*collect
=
1978 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1979 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
1980 for (int i
= 0; i
< intr
->num_components
; i
++) {
1981 unsigned n
= idx
* 4 + i
;
1982 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1987 case nir_intrinsic_load_ssbo
:
1988 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1990 case nir_intrinsic_store_ssbo
:
1991 emit_intrinsic_store_ssbo(ctx
, intr
);
1993 case nir_intrinsic_get_buffer_size
:
1994 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1996 case nir_intrinsic_ssbo_atomic_add
:
1997 case nir_intrinsic_ssbo_atomic_imin
:
1998 case nir_intrinsic_ssbo_atomic_umin
:
1999 case nir_intrinsic_ssbo_atomic_imax
:
2000 case nir_intrinsic_ssbo_atomic_umax
:
2001 case nir_intrinsic_ssbo_atomic_and
:
2002 case nir_intrinsic_ssbo_atomic_or
:
2003 case nir_intrinsic_ssbo_atomic_xor
:
2004 case nir_intrinsic_ssbo_atomic_exchange
:
2005 case nir_intrinsic_ssbo_atomic_comp_swap
:
2006 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2008 case nir_intrinsic_load_shared
:
2009 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2011 case nir_intrinsic_store_shared
:
2012 emit_intrinsic_store_shared(ctx
, intr
);
2014 case nir_intrinsic_shared_atomic_add
:
2015 case nir_intrinsic_shared_atomic_imin
:
2016 case nir_intrinsic_shared_atomic_umin
:
2017 case nir_intrinsic_shared_atomic_imax
:
2018 case nir_intrinsic_shared_atomic_umax
:
2019 case nir_intrinsic_shared_atomic_and
:
2020 case nir_intrinsic_shared_atomic_or
:
2021 case nir_intrinsic_shared_atomic_xor
:
2022 case nir_intrinsic_shared_atomic_exchange
:
2023 case nir_intrinsic_shared_atomic_comp_swap
:
2024 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2026 case nir_intrinsic_image_load
:
2027 emit_intrinsic_load_image(ctx
, intr
, dst
);
2029 case nir_intrinsic_image_store
:
2030 emit_intrinsic_store_image(ctx
, intr
);
2032 case nir_intrinsic_image_size
:
2033 emit_intrinsic_image_size(ctx
, intr
, dst
);
2035 case nir_intrinsic_image_atomic_add
:
2036 case nir_intrinsic_image_atomic_min
:
2037 case nir_intrinsic_image_atomic_max
:
2038 case nir_intrinsic_image_atomic_and
:
2039 case nir_intrinsic_image_atomic_or
:
2040 case nir_intrinsic_image_atomic_xor
:
2041 case nir_intrinsic_image_atomic_exchange
:
2042 case nir_intrinsic_image_atomic_comp_swap
:
2043 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2045 case nir_intrinsic_barrier
:
2046 case nir_intrinsic_memory_barrier
:
2047 case nir_intrinsic_group_memory_barrier
:
2048 case nir_intrinsic_memory_barrier_atomic_counter
:
2049 case nir_intrinsic_memory_barrier_buffer
:
2050 case nir_intrinsic_memory_barrier_image
:
2051 case nir_intrinsic_memory_barrier_shared
:
2052 emit_intrinsic_barrier(ctx
, intr
);
2053 /* note that blk ptr no longer valid, make that obvious: */
2056 case nir_intrinsic_store_output
:
2057 idx
= nir_intrinsic_base(intr
);
2058 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2059 compile_assert(ctx
, const_offset
!= NULL
);
2060 idx
+= const_offset
->u32
[0];
2062 src
= get_src(ctx
, &intr
->src
[0]);
2063 for (int i
= 0; i
< intr
->num_components
; i
++) {
2064 unsigned n
= idx
* 4 + i
;
2065 ctx
->ir
->outputs
[n
] = src
[i
];
2068 case nir_intrinsic_load_base_vertex
:
2069 if (!ctx
->basevertex
) {
2070 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2071 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
2074 dst
[0] = ctx
->basevertex
;
2076 case nir_intrinsic_load_vertex_id_zero_base
:
2077 case nir_intrinsic_load_vertex_id
:
2078 if (!ctx
->vertex_id
) {
2079 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2080 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2081 ctx
->vertex_id
= create_input(b
, 0);
2082 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2084 dst
[0] = ctx
->vertex_id
;
2086 case nir_intrinsic_load_instance_id
:
2087 if (!ctx
->instance_id
) {
2088 ctx
->instance_id
= create_input(b
, 0);
2089 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2092 dst
[0] = ctx
->instance_id
;
2094 case nir_intrinsic_load_user_clip_plane
:
2095 idx
= nir_intrinsic_ucp_id(intr
);
2096 for (int i
= 0; i
< intr
->num_components
; i
++) {
2097 unsigned n
= idx
* 4 + i
;
2098 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2101 case nir_intrinsic_load_front_face
:
2102 if (!ctx
->frag_face
) {
2103 ctx
->so
->frag_face
= true;
2104 ctx
->frag_face
= create_input(b
, 0);
2105 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2107 /* for fragface, we get -1 for back and 0 for front. However this is
2108 * the inverse of what nir expects (where ~0 is true).
2110 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2111 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2113 case nir_intrinsic_load_local_invocation_id
:
2114 if (!ctx
->local_invocation_id
) {
2115 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2116 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2117 0x7, ctx
->local_invocation_id
);
2119 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2121 case nir_intrinsic_load_work_group_id
:
2122 if (!ctx
->work_group_id
) {
2123 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2124 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2125 0x7, ctx
->work_group_id
);
2126 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2128 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2130 case nir_intrinsic_load_num_work_groups
:
2131 for (int i
= 0; i
< intr
->num_components
; i
++) {
2132 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2135 case nir_intrinsic_discard_if
:
2136 case nir_intrinsic_discard
: {
2137 struct ir3_instruction
*cond
, *kill
;
2139 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2140 /* conditional discard: */
2141 src
= get_src(ctx
, &intr
->src
[0]);
2142 cond
= ir3_b2n(b
, src
[0]);
2144 /* unconditional discard: */
2145 cond
= create_immed(b
, 1);
2148 /* NOTE: only cmps.*.* can write p0.x: */
2149 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2150 cond
->cat2
.condition
= IR3_COND_NE
;
2152 /* condition always goes in predicate register: */
2153 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2155 kill
= ir3_KILL(b
, cond
, 0);
2156 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2158 array_insert(b
, b
->keeps
, kill
);
2159 ctx
->so
->has_kill
= true;
2164 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2165 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2170 put_dst(ctx
, &intr
->dest
);
2174 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2176 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2177 instr
->def
.num_components
);
2178 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2179 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
2183 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2185 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2186 undef
->def
.num_components
);
2187 /* backend doesn't want undefined instructions, so just plug
2190 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2191 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
2195 * texture fetch/sample instructions:
2199 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2201 unsigned coords
, flags
= 0;
2203 /* note: would use tex->coord_components.. except txs.. also,
2204 * since array index goes after shadow ref, we don't want to
2207 switch (tex
->sampler_dim
) {
2208 case GLSL_SAMPLER_DIM_1D
:
2209 case GLSL_SAMPLER_DIM_BUF
:
2212 case GLSL_SAMPLER_DIM_2D
:
2213 case GLSL_SAMPLER_DIM_RECT
:
2214 case GLSL_SAMPLER_DIM_EXTERNAL
:
2215 case GLSL_SAMPLER_DIM_MS
:
2218 case GLSL_SAMPLER_DIM_3D
:
2219 case GLSL_SAMPLER_DIM_CUBE
:
2221 flags
|= IR3_INSTR_3D
;
2224 unreachable("bad sampler_dim");
2227 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2228 flags
|= IR3_INSTR_S
;
2230 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2231 flags
|= IR3_INSTR_A
;
2238 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2240 struct ir3_block
*b
= ctx
->block
;
2241 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2242 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2243 struct ir3_instruction
*lod
, *compare
, *proj
;
2244 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2245 unsigned i
, coords
, flags
;
2246 unsigned nsrc0
= 0, nsrc1
= 0;
2250 coord
= off
= ddx
= ddy
= NULL
;
2251 lod
= proj
= compare
= NULL
;
2253 /* TODO: might just be one component for gathers? */
2254 dst
= get_dst(ctx
, &tex
->dest
, 4);
2256 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2257 switch (tex
->src
[i
].src_type
) {
2258 case nir_tex_src_coord
:
2259 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2261 case nir_tex_src_bias
:
2262 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2265 case nir_tex_src_lod
:
2266 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2269 case nir_tex_src_comparator
: /* shadow comparator */
2270 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2272 case nir_tex_src_projector
:
2273 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2276 case nir_tex_src_offset
:
2277 off
= get_src(ctx
, &tex
->src
[i
].src
);
2280 case nir_tex_src_ddx
:
2281 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2283 case nir_tex_src_ddy
:
2284 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2287 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2288 tex
->src
[i
].src_type
);
2294 case nir_texop_tex
: opc
= OPC_SAM
; break;
2295 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2296 case nir_texop_txl
: opc
= OPC_SAML
; break;
2297 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2298 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2299 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2300 case nir_texop_txf_ms
:
2303 case nir_texop_query_levels
:
2304 case nir_texop_texture_samples
:
2305 case nir_texop_samples_identical
:
2306 case nir_texop_txf_ms_mcs
:
2307 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2311 tex_info(tex
, &flags
, &coords
);
2314 * lay out the first argument in the proper order:
2315 * - actual coordinates first
2316 * - shadow reference
2319 * - starting at offset 4, dpdx.xy, dpdy.xy
2321 * bias/lod go into the second arg
2324 /* insert tex coords: */
2325 for (i
= 0; i
< coords
; i
++)
2330 /* scale up integer coords for TXF based on the LOD */
2331 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2333 for (i
= 0; i
< coords
; i
++)
2334 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2338 /* hw doesn't do 1d, so we treat it as 2d with
2339 * height of 1, and patch up the y coord.
2340 * TODO: y coord should be (int)0 in some cases..
2342 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2345 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2346 src0
[nsrc0
++] = compare
;
2348 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2349 struct ir3_instruction
*idx
= coord
[coords
];
2351 /* the array coord for cube arrays needs 0.5 added to it */
2352 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2353 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2355 src0
[nsrc0
++] = idx
;
2359 src0
[nsrc0
++] = proj
;
2360 flags
|= IR3_INSTR_P
;
2363 /* pad to 4, then ddx/ddy: */
2364 if (tex
->op
== nir_texop_txd
) {
2366 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2367 for (i
= 0; i
< coords
; i
++)
2368 src0
[nsrc0
++] = ddx
[i
];
2370 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2371 for (i
= 0; i
< coords
; i
++)
2372 src0
[nsrc0
++] = ddy
[i
];
2374 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2378 * second argument (if applicable):
2383 if (has_off
| has_lod
| has_bias
) {
2385 for (i
= 0; i
< coords
; i
++)
2386 src1
[nsrc1
++] = off
[i
];
2388 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2389 flags
|= IR3_INSTR_O
;
2392 if (has_lod
| has_bias
)
2393 src1
[nsrc1
++] = lod
;
2396 switch (tex
->dest_type
) {
2397 case nir_type_invalid
:
2398 case nir_type_float
:
2409 unreachable("bad dest_type");
2412 if (opc
== OPC_GETLOD
)
2415 unsigned tex_idx
= tex
->texture_index
;
2417 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2419 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
2420 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
2422 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2423 tex_idx
, tex_idx
, col0
, col1
);
2425 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2426 /* only need first 3 components: */
2427 sam
->regs
[0]->wrmask
= 0x7;
2428 split_dest(b
, dst
, sam
, 0, 3);
2430 /* we need to sample the alpha separately with a non-ASTC
2433 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2434 tex_idx
, tex_idx
, col0
, col1
);
2436 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2438 /* fixup .w component: */
2439 split_dest(b
, &dst
[3], sam
, 3, 1);
2441 /* normal (non-workaround) case: */
2442 split_dest(b
, dst
, sam
, 0, 4);
2445 /* GETLOD returns results in 4.8 fixed point */
2446 if (opc
== OPC_GETLOD
) {
2447 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2449 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2450 for (i
= 0; i
< 2; i
++) {
2451 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2456 put_dst(ctx
, &tex
->dest
);
2460 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2462 struct ir3_block
*b
= ctx
->block
;
2463 struct ir3_instruction
**dst
, *sam
;
2465 dst
= get_dst(ctx
, &tex
->dest
, 1);
2467 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2468 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2470 /* even though there is only one component, since it ends
2471 * up in .z rather than .x, we need a split_dest()
2473 split_dest(b
, dst
, sam
, 0, 3);
2475 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2476 * the value in TEX_CONST_0 is zero-based.
2478 if (ctx
->levels_add_one
)
2479 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2481 put_dst(ctx
, &tex
->dest
);
2485 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2487 struct ir3_block
*b
= ctx
->block
;
2488 struct ir3_instruction
**dst
, *sam
;
2489 struct ir3_instruction
*lod
;
2490 unsigned flags
, coords
;
2492 tex_info(tex
, &flags
, &coords
);
2494 /* Actually we want the number of dimensions, not coordinates. This
2495 * distinction only matters for cubes.
2497 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2500 dst
= get_dst(ctx
, &tex
->dest
, 4);
2502 compile_assert(ctx
, tex
->num_srcs
== 1);
2503 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2505 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2507 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2508 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2510 split_dest(b
, dst
, sam
, 0, 4);
2512 /* Array size actually ends up in .w rather than .z. This doesn't
2513 * matter for miplevel 0, but for higher mips the value in z is
2514 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2515 * returned, which means that we have to add 1 to it for arrays.
2517 if (tex
->is_array
) {
2518 if (ctx
->levels_add_one
) {
2519 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2521 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2525 put_dst(ctx
, &tex
->dest
);
2529 emit_phi(struct ir3_context
*ctx
, nir_phi_instr
*nphi
)
2531 struct ir3_instruction
*phi
, **dst
;
2533 /* NOTE: phi's should be lowered to scalar at this point */
2534 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
2536 dst
= get_dst(ctx
, &nphi
->dest
, 1);
2538 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
2539 1 + exec_list_length(&nphi
->srcs
));
2540 ir3_reg_create(phi
, 0, 0); /* dst */
2541 phi
->phi
.nphi
= nphi
;
2545 put_dst(ctx
, &nphi
->dest
);
2548 /* phi instructions are left partially constructed. We don't resolve
2549 * their srcs until the end of the block, since (eg. loops) one of
2550 * the phi's srcs might be defined after the phi due to back edges in
2554 resolve_phis(struct ir3_context
*ctx
, struct ir3_block
*block
)
2556 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2557 nir_phi_instr
*nphi
;
2559 /* phi's only come at start of block: */
2560 if (instr
->opc
!= OPC_META_PHI
)
2563 if (!instr
->phi
.nphi
)
2566 nphi
= instr
->phi
.nphi
;
2567 instr
->phi
.nphi
= NULL
;
2569 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
2570 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
2572 /* NOTE: src might not be in the same block as it comes from
2573 * according to the phi.. but in the end the backend assumes
2574 * it will be able to assign the same register to each (which
2575 * only works if it is assigned in the src block), so insert
2576 * an extra mov to make sure the phi src is assigned in the
2577 * block it comes from:
2579 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
2581 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
2587 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2589 switch (jump
->type
) {
2590 case nir_jump_break
:
2591 case nir_jump_continue
:
2592 /* I *think* we can simply just ignore this, and use the
2593 * successor block link to figure out where we need to
2594 * jump to for break/continue
2598 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2604 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2606 switch (instr
->type
) {
2607 case nir_instr_type_alu
:
2608 emit_alu(ctx
, nir_instr_as_alu(instr
));
2610 case nir_instr_type_intrinsic
:
2611 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2613 case nir_instr_type_load_const
:
2614 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2616 case nir_instr_type_ssa_undef
:
2617 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2619 case nir_instr_type_tex
: {
2620 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2621 /* couple tex instructions get special-cased:
2625 emit_tex_txs(ctx
, tex
);
2627 case nir_texop_query_levels
:
2628 emit_tex_query_levels(ctx
, tex
);
2636 case nir_instr_type_phi
:
2637 emit_phi(ctx
, nir_instr_as_phi(instr
));
2639 case nir_instr_type_jump
:
2640 emit_jump(ctx
, nir_instr_as_jump(instr
));
2642 case nir_instr_type_call
:
2643 case nir_instr_type_parallel_copy
:
2644 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2649 static struct ir3_block
*
2650 get_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2652 struct ir3_block
*block
;
2653 struct hash_entry
*entry
;
2654 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2658 block
= ir3_block_create(ctx
->ir
);
2659 block
->nblock
= nblock
;
2660 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2666 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2668 struct ir3_block
*block
= get_block(ctx
, nblock
);
2670 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2671 if (nblock
->successors
[i
]) {
2672 block
->successors
[i
] =
2673 get_block(ctx
, nblock
->successors
[i
]);
2678 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2680 /* re-emit addr register in each block if needed: */
2681 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2682 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2683 ctx
->addr_ht
[i
] = NULL
;
2686 nir_foreach_instr(instr
, nblock
) {
2687 emit_instr(ctx
, instr
);
2693 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2696 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2698 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2700 ctx
->block
->condition
=
2701 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2703 emit_cf_list(ctx
, &nif
->then_list
);
2704 emit_cf_list(ctx
, &nif
->else_list
);
2708 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2710 emit_cf_list(ctx
, &nloop
->body
);
2714 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2716 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2717 switch (node
->type
) {
2718 case nir_cf_node_block
:
2719 emit_block(ctx
, nir_cf_node_as_block(node
));
2721 case nir_cf_node_if
:
2722 emit_if(ctx
, nir_cf_node_as_if(node
));
2724 case nir_cf_node_loop
:
2725 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2727 case nir_cf_node_function
:
2728 compile_error(ctx
, "TODO\n");
2734 /* emit stream-out code. At this point, the current block is the original
2735 * (nir) end block, and nir ensures that all flow control paths terminate
2736 * into the end block. We re-purpose the original end block to generate
2737 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2738 * block holding stream-out write instructions, followed by the new end
2742 * p0.x = (vtxcnt < maxvtxcnt)
2743 * // succs: blockStreamOut, blockNewEnd
2746 * ... stream-out instructions ...
2747 * // succs: blockNewEnd
2753 emit_stream_out(struct ir3_context
*ctx
)
2755 struct ir3_shader_variant
*v
= ctx
->so
;
2756 struct ir3
*ir
= ctx
->ir
;
2757 struct pipe_stream_output_info
*strmout
=
2758 &ctx
->so
->shader
->stream_output
;
2759 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2760 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2761 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2763 /* create vtxcnt input in input block at top of shader,
2764 * so that it is seen as live over the entire duration
2767 vtxcnt
= create_input(ctx
->in_block
, 0);
2768 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2770 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2772 /* at this point, we are at the original 'end' block,
2773 * re-purpose this block to stream-out condition, then
2774 * append stream-out block and new-end block
2776 orig_end_block
= ctx
->block
;
2778 stream_out_block
= ir3_block_create(ir
);
2779 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2781 new_end_block
= ir3_block_create(ir
);
2782 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2784 orig_end_block
->successors
[0] = stream_out_block
;
2785 orig_end_block
->successors
[1] = new_end_block
;
2786 stream_out_block
->successors
[0] = new_end_block
;
2788 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2789 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2790 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2791 cond
->cat2
.condition
= IR3_COND_LT
;
2793 /* condition goes on previous block to the conditional,
2794 * since it is used to pick which of the two successor
2797 orig_end_block
->condition
= cond
;
2799 /* switch to stream_out_block to generate the stream-out
2802 ctx
->block
= stream_out_block
;
2804 /* Calculate base addresses based on vtxcnt. Instructions
2805 * generated for bases not used in following loop will be
2806 * stripped out in the backend.
2808 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2809 unsigned stride
= strmout
->stride
[i
];
2810 struct ir3_instruction
*base
, *off
;
2812 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2814 /* 24-bit should be enough: */
2815 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2816 create_immed(ctx
->block
, stride
* 4), 0);
2818 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2821 /* Generate the per-output store instructions: */
2822 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2823 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2824 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2825 struct ir3_instruction
*base
, *out
, *stg
;
2827 base
= bases
[strmout
->output
[i
].output_buffer
];
2828 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2830 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2831 create_immed(ctx
->block
, 1), 0);
2832 stg
->cat6
.type
= TYPE_U32
;
2833 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2835 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2839 /* and finally switch to the new_end_block: */
2840 ctx
->block
= new_end_block
;
2844 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2846 nir_metadata_require(impl
, nir_metadata_block_index
);
2848 emit_cf_list(ctx
, &impl
->body
);
2849 emit_block(ctx
, impl
->end_block
);
2851 /* at this point, we should have a single empty block,
2852 * into which we emit the 'end' instruction.
2854 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2856 /* If stream-out (aka transform-feedback) enabled, emit the
2857 * stream-out instructions, followed by a new empty block (into
2858 * which the 'end' instruction lands).
2860 * NOTE: it is done in this order, rather than inserting before
2861 * we emit end_block, because NIR guarantees that all blocks
2862 * flow into end_block, and that end_block has no successors.
2863 * So by re-purposing end_block as the first block of stream-
2864 * out, we guarantee that all exit paths flow into the stream-
2867 if ((ctx
->compiler
->gpu_id
< 500) &&
2868 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2869 !ctx
->so
->key
.binning_pass
) {
2870 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2871 emit_stream_out(ctx
);
2874 ir3_END(ctx
->block
);
2878 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2880 struct ir3_shader_variant
*so
= ctx
->so
;
2881 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2882 unsigned ncomp
= glsl_get_components(in
->type
);
2883 unsigned n
= in
->data
.driver_location
;
2884 unsigned slot
= in
->data
.location
;
2886 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2887 slot
, array_len
, ncomp
, n
);
2889 /* let's pretend things other than vec4 don't exist: */
2890 ncomp
= MAX2(ncomp
, 4);
2891 compile_assert(ctx
, ncomp
== 4);
2893 so
->inputs
[n
].slot
= slot
;
2894 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2895 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2896 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2898 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2899 for (int i
= 0; i
< ncomp
; i
++) {
2900 struct ir3_instruction
*instr
= NULL
;
2901 unsigned idx
= (n
* 4) + i
;
2903 if (slot
== VARYING_SLOT_POS
) {
2904 so
->inputs
[n
].bary
= false;
2905 so
->frag_coord
= true;
2906 instr
= create_frag_coord(ctx
, i
);
2907 } else if (slot
== VARYING_SLOT_PNTC
) {
2908 /* see for example st_get_generic_varying_index().. this is
2909 * maybe a bit mesa/st specific. But we need things to line
2910 * up for this in fdN_program:
2911 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2912 * if (emit->sprite_coord_enable & texmask) {
2916 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2917 so
->inputs
[n
].bary
= true;
2918 instr
= create_frag_input(ctx
, false);
2920 bool use_ldlv
= false;
2922 /* detect the special case for front/back colors where
2923 * we need to do flat vs smooth shading depending on
2926 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2928 case VARYING_SLOT_COL0
:
2929 case VARYING_SLOT_COL1
:
2930 case VARYING_SLOT_BFC0
:
2931 case VARYING_SLOT_BFC1
:
2932 so
->inputs
[n
].rasterflat
= true;
2939 if (ctx
->flat_bypass
) {
2940 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2941 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2945 so
->inputs
[n
].bary
= true;
2947 instr
= create_frag_input(ctx
, use_ldlv
);
2950 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2952 ctx
->ir
->inputs
[idx
] = instr
;
2954 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2955 for (int i
= 0; i
< ncomp
; i
++) {
2956 unsigned idx
= (n
* 4) + i
;
2957 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2958 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2961 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2964 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2965 so
->total_in
+= ncomp
;
2970 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
2972 struct ir3_shader_variant
*so
= ctx
->so
;
2973 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2974 unsigned ncomp
= glsl_get_components(out
->type
);
2975 unsigned n
= out
->data
.driver_location
;
2976 unsigned slot
= out
->data
.location
;
2979 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2980 slot
, array_len
, ncomp
, n
);
2982 /* let's pretend things other than vec4 don't exist: */
2983 ncomp
= MAX2(ncomp
, 4);
2984 compile_assert(ctx
, ncomp
== 4);
2986 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2988 case FRAG_RESULT_DEPTH
:
2989 comp
= 2; /* tgsi will write to .z component */
2990 so
->writes_pos
= true;
2992 case FRAG_RESULT_COLOR
:
2996 if (slot
>= FRAG_RESULT_DATA0
)
2998 compile_error(ctx
, "unknown FS output name: %s\n",
2999 gl_frag_result_name(slot
));
3001 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3003 case VARYING_SLOT_POS
:
3004 so
->writes_pos
= true;
3006 case VARYING_SLOT_PSIZ
:
3007 so
->writes_psize
= true;
3009 case VARYING_SLOT_COL0
:
3010 case VARYING_SLOT_COL1
:
3011 case VARYING_SLOT_BFC0
:
3012 case VARYING_SLOT_BFC1
:
3013 case VARYING_SLOT_FOGC
:
3014 case VARYING_SLOT_CLIP_DIST0
:
3015 case VARYING_SLOT_CLIP_DIST1
:
3016 case VARYING_SLOT_CLIP_VERTEX
:
3019 if (slot
>= VARYING_SLOT_VAR0
)
3021 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3023 compile_error(ctx
, "unknown VS output name: %s\n",
3024 gl_varying_slot_name(slot
));
3027 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3030 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3032 so
->outputs
[n
].slot
= slot
;
3033 so
->outputs
[n
].regid
= regid(n
, comp
);
3034 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3036 for (int i
= 0; i
< ncomp
; i
++) {
3037 unsigned idx
= (n
* 4) + i
;
3038 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3039 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3044 max_drvloc(struct exec_list
*vars
)
3047 nir_foreach_variable(var
, vars
) {
3048 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3053 static const unsigned max_sysvals
[SHADER_MAX
] = {
3054 [SHADER_VERTEX
] = 16,
3055 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3059 emit_instructions(struct ir3_context
*ctx
)
3061 unsigned ninputs
, noutputs
;
3062 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3064 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3065 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3067 /* we need to leave room for sysvals:
3069 ninputs
+= max_sysvals
[ctx
->so
->type
];
3071 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3073 /* Create inputs in first block: */
3074 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3075 ctx
->in_block
= ctx
->block
;
3076 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3078 ninputs
-= max_sysvals
[ctx
->so
->type
];
3080 /* for fragment shader, we have a single input register (usually
3081 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3083 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3084 // TODO maybe a helper for fi since we need it a few places..
3085 struct ir3_instruction
*instr
;
3086 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3087 ir3_reg_create(instr
, 0, 0);
3088 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3089 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3090 ctx
->frag_pos
= instr
;
3094 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3095 setup_input(ctx
, var
);
3098 /* Setup outputs: */
3099 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3100 setup_output(ctx
, var
);
3103 /* Setup registers (which should only be arrays): */
3104 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3105 declare_array(ctx
, reg
);
3108 /* NOTE: need to do something more clever when we support >1 fxn */
3109 nir_foreach_register(reg
, &fxn
->registers
) {
3110 declare_array(ctx
, reg
);
3112 /* And emit the body: */
3114 emit_function(ctx
, fxn
);
3116 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
3117 resolve_phis(ctx
, block
);
3121 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3122 * for a fragment shader are just bary.f instructions. The *actual* inputs
3123 * from the hw perspective are the frag_pos and optionally frag_coord and
3127 fixup_frag_inputs(struct ir3_context
*ctx
)
3129 struct ir3_shader_variant
*so
= ctx
->so
;
3130 struct ir3
*ir
= ctx
->ir
;
3131 struct ir3_instruction
**inputs
;
3132 struct ir3_instruction
*instr
;
3137 n
= 4; /* always have frag_pos */
3138 n
+= COND(so
->frag_face
, 4);
3139 n
+= COND(so
->frag_coord
, 4);
3141 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3143 if (so
->frag_face
) {
3144 /* this ultimately gets assigned to hr0.x so doesn't conflict
3145 * with frag_coord/frag_pos..
3147 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3148 ctx
->frag_face
->regs
[0]->num
= 0;
3150 /* remaining channels not used, but let's avoid confusing
3151 * other parts that expect inputs to come in groups of vec4
3153 inputs
[ir
->ninputs
++] = NULL
;
3154 inputs
[ir
->ninputs
++] = NULL
;
3155 inputs
[ir
->ninputs
++] = NULL
;
3158 /* since we don't know where to set the regid for frag_coord,
3159 * we have to use r0.x for it. But we don't want to *always*
3160 * use r1.x for frag_pos as that could increase the register
3161 * footprint on simple shaders:
3163 if (so
->frag_coord
) {
3164 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3165 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3166 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3167 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3169 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3170 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3171 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3172 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3175 /* we always have frag_pos: */
3176 so
->pos_regid
= regid
;
3179 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3180 instr
->regs
[0]->num
= regid
++;
3181 inputs
[ir
->ninputs
++] = instr
;
3182 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3185 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3186 instr
->regs
[0]->num
= regid
++;
3187 inputs
[ir
->ninputs
++] = instr
;
3188 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3190 ir
->inputs
= inputs
;
3193 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3194 * need to assign the tex state indexes for these after we know the
3198 fixup_astc_srgb(struct ir3_context
*ctx
)
3200 struct ir3_shader_variant
*so
= ctx
->so
;
3201 /* indexed by original tex idx, value is newly assigned alpha sampler
3202 * state tex idx. Zero is invalid since there is at least one sampler
3205 unsigned alt_tex_state
[16] = {0};
3206 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3209 so
->astc_srgb
.base
= tex_idx
;
3211 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3212 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3214 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3216 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3217 /* assign new alternate/alpha tex state slot: */
3218 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3219 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3220 so
->astc_srgb
.count
++;
3223 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3228 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3229 struct ir3_shader_variant
*so
)
3231 struct ir3_context
*ctx
;
3233 struct ir3_instruction
**inputs
;
3234 unsigned i
, j
, actual_in
, inloc
;
3235 int ret
= 0, max_bary
;
3239 ctx
= compile_init(compiler
, so
);
3241 DBG("INIT failed!");
3246 emit_instructions(ctx
);
3249 DBG("EMIT failed!");
3254 ir
= so
->ir
= ctx
->ir
;
3256 /* keep track of the inputs from TGSI perspective.. */
3257 inputs
= ir
->inputs
;
3259 /* but fixup actual inputs for frag shader: */
3260 if (so
->type
== SHADER_FRAGMENT
)
3261 fixup_frag_inputs(ctx
);
3263 /* at this point, for binning pass, throw away unneeded outputs: */
3264 if (so
->key
.binning_pass
) {
3265 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3266 unsigned slot
= so
->outputs
[i
].slot
;
3268 /* throw away everything but first position/psize */
3269 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3271 so
->outputs
[j
] = so
->outputs
[i
];
3272 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3273 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3274 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3275 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3280 so
->outputs_count
= j
;
3281 ir
->noutputs
= j
* 4;
3284 /* if we want half-precision outputs, mark the output registers
3287 if (so
->key
.half_precision
) {
3288 for (i
= 0; i
< ir
->noutputs
; i
++) {
3289 struct ir3_instruction
*out
= ir
->outputs
[i
];
3294 /* if frag shader writes z, that needs to be full precision: */
3295 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3298 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3299 /* output could be a fanout (ie. texture fetch output)
3300 * in which case we need to propagate the half-reg flag
3301 * up to the definer so that RA sees it:
3303 if (out
->opc
== OPC_META_FO
) {
3304 out
= out
->regs
[1]->instr
;
3305 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3308 if (out
->opc
== OPC_MOV
) {
3309 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3314 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3315 printf("BEFORE CP:\n");
3321 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3322 printf("BEFORE GROUPING:\n");
3326 ir3_sched_add_deps(ir
);
3328 /* Group left/right neighbors, inserting mov's where needed to
3335 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3336 printf("AFTER DEPTH:\n");
3340 ret
= ir3_sched(ir
);
3342 DBG("SCHED failed!");
3346 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3347 printf("AFTER SCHED:\n");
3351 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3357 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3358 printf("AFTER RA:\n");
3362 /* fixup input/outputs: */
3363 for (i
= 0; i
< so
->outputs_count
; i
++) {
3364 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3367 /* Note that some or all channels of an input may be unused: */
3370 for (i
= 0; i
< so
->inputs_count
; i
++) {
3371 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3372 so
->inputs
[i
].ncomp
= 0;
3373 so
->inputs
[i
].inloc
= inloc
;
3374 for (j
= 0; j
< 4; j
++) {
3375 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3376 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3377 compmask
|= (1 << j
);
3378 regid
= in
->regs
[0]->num
- j
;
3380 so
->inputs
[i
].ncomp
++;
3381 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3383 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3384 in
->regs
[1]->iim_val
= inloc
+ j
;
3389 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3391 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3394 so
->inputs
[i
].compmask
= compmask
;
3396 so
->inputs
[i
].regid
= regid
;
3400 fixup_astc_srgb(ctx
);
3402 /* We need to do legalize after (for frag shader's) the "bary.f"
3403 * offsets (inloc) have been assigned.
3405 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3407 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3408 printf("AFTER LEGALIZE:\n");
3412 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3413 if (so
->type
== SHADER_VERTEX
)
3414 so
->total_in
= actual_in
;
3416 so
->total_in
= max_bary
+ 1;
3421 ir3_destroy(so
->ir
);