1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* For SSBO's and atomics, we need to preserve order, such
78 * that reads don't overtake writes, and the order of writes
79 * is preserved. Atomics are considered as a write.
81 * To do this, we track last write and last access, in a
82 * similar way to ir3_array. But since we don't know whether
83 * the same SSBO is bound to multiple slots, so we simply
84 * track this globally rather than per-SSBO.
86 * TODO should we track this per block instead? I guess it
87 * shouldn't matter much?
89 struct ir3_instruction
*last_write
, *last_access
;
91 /* mapping from nir_register to defining instruction: */
92 struct hash_table
*def_ht
;
96 /* a common pattern for indirect addressing is to request the
97 * same address register multiple times. To avoid generating
98 * duplicate instruction sequences (which our backend does not
99 * try to clean up, since that should be done as the NIR stage)
100 * we cache the address value generated for a given src value:
102 * Note that we have to cache these per alignment, since same
103 * src used for an array of vec1 cannot be also used for an
106 struct hash_table
*addr_ht
[4];
108 /* last dst array, for indirect we need to insert a var-store.
110 struct ir3_instruction
**last_dst
;
113 /* maps nir_block to ir3_block, mostly for the purposes of
114 * figuring out the blocks successors
116 struct hash_table
*block_ht
;
118 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
119 * so we need to use ldlv.u32 to load the varying directly:
123 /* on a3xx, we need to add one to # of array levels:
127 /* on a3xx, we need to scale up integer coords for isaml based
130 bool unminify_coords
;
132 /* on a4xx, for array textures we need to add 0.5 to the array
135 bool array_index_add_half
;
137 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
140 unsigned max_texture_index
;
142 /* set if we encounter something we can't handle yet, so we
143 * can bail cleanly and fallback to TGSI compiler f/e
148 /* gpu pointer size in units of 32bit registers/slots */
149 static unsigned pointer_size(struct ir3_compile
*ctx
)
151 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
154 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
155 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
158 static struct ir3_compile
*
159 compile_init(struct ir3_compiler
*compiler
,
160 struct ir3_shader_variant
*so
)
162 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
164 if (compiler
->gpu_id
>= 400) {
165 /* need special handling for "flat" */
166 ctx
->flat_bypass
= true;
167 ctx
->levels_add_one
= false;
168 ctx
->unminify_coords
= false;
169 ctx
->array_index_add_half
= true;
171 if (so
->type
== SHADER_VERTEX
)
172 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
173 else if (so
->type
== SHADER_FRAGMENT
)
174 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
177 /* no special handling for "flat" */
178 ctx
->flat_bypass
= false;
179 ctx
->levels_add_one
= true;
180 ctx
->unminify_coords
= true;
181 ctx
->array_index_add_half
= false;
184 ctx
->compiler
= compiler
;
187 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
188 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
189 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
190 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
192 /* TODO: maybe generate some sort of bitmask of what key
193 * lowers vs what shader has (ie. no need to lower
194 * texture clamp lowering if no texture sample instrs)..
195 * although should be done further up the stack to avoid
196 * creating duplicate variants..
199 if (ir3_key_lowers_nir(&so
->key
)) {
200 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
201 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
203 /* fast-path for shader key that lowers nothing in NIR: */
204 ctx
->s
= so
->shader
->nir
;
207 /* this needs to be the last pass run, so do this here instead of
208 * in ir3_optimize_nir():
210 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
212 if (fd_mesa_debug
& FD_DBG_DISASM
) {
213 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
214 so
->shader
->id
, so
->id
, so
->type
,
215 so
->key
.binning_pass
, so
->key
.color_two_side
,
216 so
->key
.half_precision
);
217 nir_print_shader(ctx
->s
, stdout
);
220 so
->num_uniforms
= ctx
->s
->num_uniforms
;
221 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
223 /* Layout of constant registers, each section aligned to vec4. Note
224 * that pointer size (ubo, etc) changes depending on generation.
228 * if (vertex shader) {
229 * driver params (IR3_DP_*)
230 * if (stream_output.num_outputs > 0)
231 * stream-out addresses
235 * Immediates go last mostly because they are inserted in the CP pass
236 * after the nir -> ir3 frontend.
238 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
239 unsigned ptrsz
= pointer_size(ctx
);
241 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
243 if (so
->num_ubos
> 0) {
244 so
->constbase
.ubo
= constoff
;
245 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
248 unsigned num_driver_params
= 0;
249 if (so
->type
== SHADER_VERTEX
) {
250 num_driver_params
= IR3_DP_VS_COUNT
;
251 } else if (so
->type
== SHADER_COMPUTE
) {
252 num_driver_params
= IR3_DP_CS_COUNT
;
255 so
->constbase
.driver_param
= constoff
;
256 constoff
+= align(num_driver_params
, 4) / 4;
258 if ((so
->type
== SHADER_VERTEX
) &&
259 (compiler
->gpu_id
< 500) &&
260 so
->shader
->stream_output
.num_outputs
> 0) {
261 so
->constbase
.tfbo
= constoff
;
262 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
265 so
->constbase
.immediate
= constoff
;
271 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
274 va_start(ap
, format
);
275 _debug_vprintf(format
, ap
);
277 nir_print_shader(ctx
->s
, stdout
);
282 #define compile_assert(ctx, cond) do { \
283 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
287 compile_free(struct ir3_compile
*ctx
)
293 declare_array(struct ir3_compile
*ctx
, nir_register
*reg
)
295 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
296 arr
->id
= ++ctx
->num_arrays
;
297 /* NOTE: sometimes we get non array regs, for example for arrays of
298 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
299 * treat a non-array as if it was an array of length 1.
301 * It would be nice if there was a nir pass to convert arrays of
304 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
305 compile_assert(ctx
, arr
->length
> 0);
307 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
310 static struct ir3_array
*
311 get_array(struct ir3_compile
*ctx
, nir_register
*reg
)
313 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
317 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
321 /* relative (indirect) if address!=NULL */
322 static struct ir3_instruction
*
323 create_array_load(struct ir3_compile
*ctx
, struct ir3_array
*arr
, int n
,
324 struct ir3_instruction
*address
)
326 struct ir3_block
*block
= ctx
->block
;
327 struct ir3_instruction
*mov
;
328 struct ir3_register
*src
;
330 mov
= ir3_instr_create(block
, OPC_MOV
);
331 mov
->cat1
.src_type
= TYPE_U32
;
332 mov
->cat1
.dst_type
= TYPE_U32
;
333 ir3_reg_create(mov
, 0, 0);
334 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
335 COND(address
, IR3_REG_RELATIV
));
336 src
->instr
= arr
->last_write
;
337 src
->size
= arr
->length
;
338 src
->array
.id
= arr
->id
;
339 src
->array
.offset
= n
;
342 ir3_instr_set_address(mov
, address
);
344 arr
->last_access
= mov
;
349 /* relative (indirect) if address!=NULL */
350 static struct ir3_instruction
*
351 create_array_store(struct ir3_compile
*ctx
, struct ir3_array
*arr
, int n
,
352 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
354 struct ir3_block
*block
= ctx
->block
;
355 struct ir3_instruction
*mov
;
356 struct ir3_register
*dst
;
358 mov
= ir3_instr_create(block
, OPC_MOV
);
359 mov
->cat1
.src_type
= TYPE_U32
;
360 mov
->cat1
.dst_type
= TYPE_U32
;
361 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
362 COND(address
, IR3_REG_RELATIV
));
363 dst
->instr
= arr
->last_access
;
364 dst
->size
= arr
->length
;
365 dst
->array
.id
= arr
->id
;
366 dst
->array
.offset
= n
;
367 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
370 ir3_instr_set_address(mov
, address
);
372 arr
->last_write
= arr
->last_access
= mov
;
377 /* allocate a n element value array (to be populated by caller) and
380 static struct ir3_instruction
**
381 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
383 struct ir3_instruction
**value
=
384 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
385 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
389 static struct ir3_instruction
**
390 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
392 struct ir3_instruction
**value
;
395 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
397 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
400 /* NOTE: in non-ssa case, we don't really need to store last_dst
401 * but this helps us catch cases where put_dst() call is forgotten
403 compile_assert(ctx
, !ctx
->last_dst
);
404 ctx
->last_dst
= value
;
410 static struct ir3_instruction
* get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
, int align
);
412 static struct ir3_instruction
* const *
413 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
416 struct hash_entry
*entry
;
417 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
418 compile_assert(ctx
, entry
);
421 nir_register
*reg
= src
->reg
.reg
;
422 struct ir3_array
*arr
= get_array(ctx
, reg
);
423 unsigned num_components
= arr
->r
->num_components
;
424 struct ir3_instruction
*addr
= NULL
;
425 struct ir3_instruction
**value
=
426 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
428 if (src
->reg
.indirect
)
429 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
430 reg
->num_components
);
432 for (unsigned i
= 0; i
< num_components
; i
++) {
433 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
434 compile_assert(ctx
, n
< arr
->length
);
435 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
443 put_dst(struct ir3_compile
*ctx
, nir_dest
*dst
)
446 nir_register
*reg
= dst
->reg
.reg
;
447 struct ir3_array
*arr
= get_array(ctx
, reg
);
448 unsigned num_components
= ctx
->last_dst_n
;
449 struct ir3_instruction
*addr
= NULL
;
451 if (dst
->reg
.indirect
)
452 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
453 reg
->num_components
);
455 for (unsigned i
= 0; i
< num_components
; i
++) {
456 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
457 compile_assert(ctx
, n
< arr
->length
);
458 if (!ctx
->last_dst
[i
])
460 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
463 ralloc_free(ctx
->last_dst
);
465 ctx
->last_dst
= NULL
;
469 static struct ir3_instruction
*
470 create_immed(struct ir3_block
*block
, uint32_t val
)
472 struct ir3_instruction
*mov
;
474 mov
= ir3_instr_create(block
, OPC_MOV
);
475 mov
->cat1
.src_type
= TYPE_U32
;
476 mov
->cat1
.dst_type
= TYPE_U32
;
477 ir3_reg_create(mov
, 0, 0);
478 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
483 static struct ir3_instruction
*
484 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
486 struct ir3_instruction
*instr
, *immed
;
488 /* TODO in at least some cases, the backend could probably be
489 * made clever enough to propagate IR3_REG_HALF..
491 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
492 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
499 /* src *= 2 => src <<= 1: */
500 immed
= create_immed(block
, 1);
501 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
503 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
504 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
505 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
509 immed
= create_immed(block
, 3);
510 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
512 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
513 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
514 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
517 /* src *= 4 => src <<= 2: */
518 immed
= create_immed(block
, 2);
519 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
521 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
522 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
523 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
526 unreachable("bad align");
530 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
531 instr
->regs
[0]->num
= regid(REG_A0
, 0);
532 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
533 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
538 /* caches addr values to avoid generating multiple cov/shl/mova
539 * sequences for each use of a given NIR level src as address
541 static struct ir3_instruction
*
542 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
, int align
)
544 struct ir3_instruction
*addr
;
545 unsigned idx
= align
- 1;
547 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
549 if (!ctx
->addr_ht
[idx
]) {
550 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
551 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
553 struct hash_entry
*entry
;
554 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
559 addr
= create_addr(ctx
->block
, src
, align
);
560 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
565 static struct ir3_instruction
*
566 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
568 struct ir3_block
*b
= ctx
->block
;
569 struct ir3_instruction
*cond
;
571 /* NOTE: only cmps.*.* can write p0.x: */
572 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
573 cond
->cat2
.condition
= IR3_COND_NE
;
575 /* condition always goes in predicate register: */
576 cond
->regs
[0]->num
= regid(REG_P0
, 0);
581 static struct ir3_instruction
*
582 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
584 struct ir3_instruction
*mov
;
586 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
587 /* TODO get types right? */
588 mov
->cat1
.src_type
= TYPE_F32
;
589 mov
->cat1
.dst_type
= TYPE_F32
;
590 ir3_reg_create(mov
, 0, 0);
591 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
596 static struct ir3_instruction
*
597 create_uniform_indirect(struct ir3_compile
*ctx
, int n
,
598 struct ir3_instruction
*address
)
600 struct ir3_instruction
*mov
;
602 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
603 mov
->cat1
.src_type
= TYPE_U32
;
604 mov
->cat1
.dst_type
= TYPE_U32
;
605 ir3_reg_create(mov
, 0, 0);
606 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
608 ir3_instr_set_address(mov
, address
);
613 static struct ir3_instruction
*
614 create_collect(struct ir3_block
*block
, struct ir3_instruction
*const *arr
,
617 struct ir3_instruction
*collect
;
622 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
623 ir3_reg_create(collect
, 0, 0); /* dst */
624 for (unsigned i
= 0; i
< arrsz
; i
++)
625 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
630 static struct ir3_instruction
*
631 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, int n
,
632 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
634 struct ir3_block
*block
= ctx
->block
;
635 struct ir3_instruction
*mov
;
636 struct ir3_register
*src
;
638 mov
= ir3_instr_create(block
, OPC_MOV
);
639 mov
->cat1
.src_type
= TYPE_U32
;
640 mov
->cat1
.dst_type
= TYPE_U32
;
641 ir3_reg_create(mov
, 0, 0);
642 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
643 src
->instr
= collect
;
645 src
->array
.offset
= n
;
647 ir3_instr_set_address(mov
, address
);
652 static struct ir3_instruction
*
653 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
655 struct ir3_instruction
*in
;
657 in
= ir3_instr_create(block
, OPC_META_INPUT
);
658 in
->inout
.block
= block
;
659 ir3_reg_create(in
, n
, 0);
661 in
->regs
[0]->wrmask
= compmask
;
666 static struct ir3_instruction
*
667 create_input(struct ir3_block
*block
, unsigned n
)
669 return create_input_compmask(block
, n
, 0x1);
672 static struct ir3_instruction
*
673 create_frag_input(struct ir3_compile
*ctx
, bool use_ldlv
)
675 struct ir3_block
*block
= ctx
->block
;
676 struct ir3_instruction
*instr
;
677 /* actual inloc is assigned and fixed up later: */
678 struct ir3_instruction
*inloc
= create_immed(block
, 0);
681 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
682 instr
->cat6
.type
= TYPE_U32
;
683 instr
->cat6
.iim_val
= 1;
685 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
686 instr
->regs
[2]->wrmask
= 0x3;
692 static struct ir3_instruction
*
693 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
695 struct ir3_block
*block
= ctx
->block
;
696 struct ir3_instruction
*instr
;
698 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
700 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
705 /* for frag_coord, we get unsigned values.. we need
706 * to subtract (integer) 8 and divide by 16 (right-
707 * shift by 4) then convert to float:
711 * mov.u32f32 dst, tmp
714 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
715 create_immed(block
, 8), 0);
716 instr
= ir3_SHR_B(block
, instr
, 0,
717 create_immed(block
, 4), 0);
718 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
724 /* seems that we can use these as-is: */
725 return ctx
->frag_coord
[comp
];
729 static struct ir3_instruction
*
730 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
732 /* first four vec4 sysval's reserved for UBOs: */
733 /* NOTE: dp is in scalar, but there can be >4 dp components: */
734 unsigned n
= ctx
->so
->constbase
.driver_param
;
735 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
736 return create_uniform(ctx
, r
);
739 /* helper for instructions that produce multiple consecutive scalar
740 * outputs which need to have a split/fanout meta instruction inserted
743 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
744 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
746 struct ir3_instruction
*prev
= NULL
;
747 for (int i
= 0, j
= 0; i
< n
; i
++) {
748 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
749 ir3_reg_create(split
, 0, IR3_REG_SSA
);
750 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
751 split
->fo
.off
= i
+ base
;
754 split
->cp
.left
= prev
;
755 split
->cp
.left_cnt
++;
756 prev
->cp
.right
= split
;
757 prev
->cp
.right_cnt
++;
761 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
767 * Adreno uses uint rather than having dedicated bool type,
768 * which (potentially) requires some conversion, in particular
769 * when using output of an bool instr to int input, or visa
773 * -------+---------+-------+-
777 * To convert from an adreno bool (uint) to nir, use:
779 * absneg.s dst, (neg)src
781 * To convert back in the other direction:
783 * absneg.s dst, (abs)arc
785 * The CP step can clean up the absneg.s that cancel each other
786 * out, and with a slight bit of extra cleverness (to recognize
787 * the instructions which produce either a 0 or 1) can eliminate
788 * the absneg.s's completely when an instruction that wants
789 * 0/1 consumes the result. For example, when a nir 'bcsel'
790 * consumes the result of 'feq'. So we should be able to get by
791 * without a boolean resolve step, and without incuring any
792 * extra penalty in instruction count.
795 /* NIR bool -> native (adreno): */
796 static struct ir3_instruction
*
797 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
799 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
802 /* native (adreno) -> NIR bool: */
803 static struct ir3_instruction
*
804 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
806 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
810 * alu/sfu instructions:
814 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
816 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
817 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
818 struct ir3_block
*b
= ctx
->block
;
819 unsigned dst_sz
, wrmask
;
821 if (alu
->dest
.dest
.is_ssa
) {
822 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
823 wrmask
= (1 << dst_sz
) - 1;
825 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
826 wrmask
= alu
->dest
.write_mask
;
829 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
831 /* Vectors are special in that they have non-scalarized writemasks,
832 * and just take the first swizzle channel for each argument in
833 * order into each writemask channel.
835 if ((alu
->op
== nir_op_vec2
) ||
836 (alu
->op
== nir_op_vec3
) ||
837 (alu
->op
== nir_op_vec4
)) {
839 for (int i
= 0; i
< info
->num_inputs
; i
++) {
840 nir_alu_src
*asrc
= &alu
->src
[i
];
842 compile_assert(ctx
, !asrc
->abs
);
843 compile_assert(ctx
, !asrc
->negate
);
845 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
847 src
[i
] = create_immed(ctx
->block
, 0);
848 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
851 put_dst(ctx
, &alu
->dest
.dest
);
855 /* We also get mov's with more than one component for mov's so
856 * handle those specially:
858 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
859 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
860 nir_alu_src
*asrc
= &alu
->src
[0];
861 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
863 for (unsigned i
= 0; i
< dst_sz
; i
++) {
864 if (wrmask
& (1 << i
)) {
865 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
871 put_dst(ctx
, &alu
->dest
.dest
);
875 compile_assert(ctx
, alu
->dest
.dest
.is_ssa
);
877 /* General case: We can just grab the one used channel per src. */
878 for (int i
= 0; i
< info
->num_inputs
; i
++) {
879 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
880 nir_alu_src
*asrc
= &alu
->src
[i
];
882 compile_assert(ctx
, !asrc
->abs
);
883 compile_assert(ctx
, !asrc
->negate
);
885 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
887 compile_assert(ctx
, src
[i
]);
892 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
895 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
898 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
901 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
904 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
905 dst
[0]->cat2
.condition
= IR3_COND_NE
;
906 dst
[0] = ir3_n2b(b
, dst
[0]);
909 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
912 dst
[0] = ir3_b2n(b
, src
[0]);
915 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
916 dst
[0]->cat2
.condition
= IR3_COND_NE
;
917 dst
[0] = ir3_n2b(b
, dst
[0]);
921 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
924 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
927 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
930 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
933 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
936 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
939 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
942 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
945 dst
[0] = ir3_DSX(b
, src
[0], 0);
946 dst
[0]->cat5
.type
= TYPE_F32
;
949 dst
[0] = ir3_DSY(b
, src
[0], 0);
950 dst
[0]->cat5
.type
= TYPE_F32
;
954 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
955 dst
[0]->cat2
.condition
= IR3_COND_LT
;
956 dst
[0] = ir3_n2b(b
, dst
[0]);
959 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
960 dst
[0]->cat2
.condition
= IR3_COND_GE
;
961 dst
[0] = ir3_n2b(b
, dst
[0]);
964 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
965 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
966 dst
[0] = ir3_n2b(b
, dst
[0]);
969 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
970 dst
[0]->cat2
.condition
= IR3_COND_NE
;
971 dst
[0] = ir3_n2b(b
, dst
[0]);
974 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
977 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
980 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
982 case nir_op_fround_even
:
983 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
986 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
990 dst
[0] = ir3_SIN(b
, src
[0], 0);
993 dst
[0] = ir3_COS(b
, src
[0], 0);
996 dst
[0] = ir3_RSQ(b
, src
[0], 0);
999 dst
[0] = ir3_RCP(b
, src
[0], 0);
1002 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1005 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1008 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1012 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1015 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1018 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1021 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1024 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1027 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1030 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1034 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1035 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1036 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1037 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1039 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1040 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1041 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1044 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1047 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1050 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1053 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1056 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1058 case nir_op_isign
: {
1059 /* maybe this would be sane to lower in nir.. */
1060 struct ir3_instruction
*neg
, *pos
;
1062 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1063 neg
->cat2
.condition
= IR3_COND_LT
;
1065 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1066 pos
->cat2
.condition
= IR3_COND_GT
;
1068 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1073 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1076 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1079 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1082 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1083 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1084 dst
[0] = ir3_n2b(b
, dst
[0]);
1087 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1088 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1089 dst
[0] = ir3_n2b(b
, dst
[0]);
1092 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1093 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1094 dst
[0] = ir3_n2b(b
, dst
[0]);
1097 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1098 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1099 dst
[0] = ir3_n2b(b
, dst
[0]);
1102 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1103 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1104 dst
[0] = ir3_n2b(b
, dst
[0]);
1107 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1108 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1109 dst
[0] = ir3_n2b(b
, dst
[0]);
1113 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1116 case nir_op_bit_count
:
1117 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1119 case nir_op_ifind_msb
: {
1120 struct ir3_instruction
*cmp
;
1121 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1122 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1123 cmp
->cat2
.condition
= IR3_COND_GE
;
1124 dst
[0] = ir3_SEL_B32(b
,
1125 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1129 case nir_op_ufind_msb
:
1130 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1131 dst
[0] = ir3_SEL_B32(b
,
1132 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1133 src
[0], 0, dst
[0], 0);
1135 case nir_op_find_lsb
:
1136 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1137 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1139 case nir_op_bitfield_reverse
:
1140 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1144 compile_error(ctx
, "Unhandled ALU op: %s\n",
1145 nir_op_infos
[alu
->op
].name
);
1149 put_dst(ctx
, &alu
->dest
.dest
);
1152 /* handles direct/indirect UBO reads: */
1154 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1155 struct ir3_instruction
**dst
)
1157 struct ir3_block
*b
= ctx
->block
;
1158 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1159 nir_const_value
*const_offset
;
1160 /* UBO addresses are the first driver params: */
1161 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1162 const unsigned ptrsz
= pointer_size(ctx
);
1166 /* First src is ubo index, which could either be an immed or not: */
1167 src0
= get_src(ctx
, &intr
->src
[0])[0];
1168 if (is_same_type_mov(src0
) &&
1169 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1170 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1171 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1173 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1174 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1177 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1180 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1182 off
+= const_offset
->u32
[0];
1184 /* For load_ubo_indirect, second src is indirect offset: */
1185 src1
= get_src(ctx
, &intr
->src
[1])[0];
1187 /* and add offset to addr: */
1188 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1191 /* if offset is to large to encode in the ldg, split it out: */
1192 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1193 /* split out the minimal amount to improve the odds that
1194 * cp can fit the immediate in the add.s instruction:
1196 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1197 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1202 struct ir3_instruction
*carry
;
1204 /* handle 32b rollover, ie:
1205 * if (addr < base_lo)
1208 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1209 carry
->cat2
.condition
= IR3_COND_LT
;
1210 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1212 addr
= create_collect(b
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1215 for (int i
= 0; i
< intr
->num_components
; i
++) {
1216 struct ir3_instruction
*load
=
1217 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1218 load
->cat6
.type
= TYPE_U32
;
1219 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1225 mark_ssbo_read(struct ir3_compile
*ctx
, struct ir3_instruction
*instr
)
1227 instr
->regs
[0]->instr
= ctx
->last_write
;
1228 instr
->regs
[0]->flags
|= IR3_REG_SSA
;
1229 ctx
->last_access
= instr
;
1233 mark_ssbo_write(struct ir3_compile
*ctx
, struct ir3_instruction
*instr
)
1235 instr
->regs
[0]->instr
= ctx
->last_access
;
1236 instr
->regs
[0]->flags
|= IR3_REG_SSA
;
1237 ctx
->last_write
= ctx
->last_access
= instr
;
1241 emit_intrinsic_load_ssbo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1242 struct ir3_instruction
**dst
)
1244 struct ir3_block
*b
= ctx
->block
;
1245 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1246 nir_const_value
*const_offset
;
1248 /* can this be non-const buffer_index? how do we handle that? */
1249 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1250 compile_assert(ctx
, const_offset
);
1252 offset
= get_src(ctx
, &intr
->src
[1])[0];
1254 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1255 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1259 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1261 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1263 ldgb
->regs
[0]->wrmask
= (1 << intr
->num_components
) - 1;
1264 ldgb
->cat6
.iim_val
= intr
->num_components
;
1265 ldgb
->cat6
.type
= TYPE_U32
;
1266 mark_ssbo_read(ctx
, ldgb
);
1268 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1271 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1273 emit_intrinsic_store_ssbo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1275 struct ir3_block
*b
= ctx
->block
;
1276 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1277 nir_const_value
*const_offset
;
1278 unsigned ncomp
= ffs(~intr
->const_index
[0]) - 1;
1280 /* can this be non-const buffer_index? how do we handle that? */
1281 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1282 compile_assert(ctx
, const_offset
);
1284 offset
= get_src(ctx
, &intr
->src
[2])[0];
1286 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1289 src0
= create_collect(b
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1290 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1291 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1296 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1297 src0
, 0, src1
, 0, src2
, 0);
1298 stgb
->cat6
.iim_val
= ncomp
;
1299 stgb
->cat6
.type
= TYPE_U32
;
1300 mark_ssbo_write(ctx
, stgb
);
1302 array_insert(b
, b
->keeps
, stgb
);
1305 static struct ir3_instruction
*
1306 emit_intrinsic_atomic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1308 struct ir3_block
*b
= ctx
->block
;
1309 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1310 nir_const_value
*const_offset
;
1311 type_t type
= TYPE_U32
;
1313 /* can this be non-const buffer_index? how do we handle that? */
1314 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1315 compile_assert(ctx
, const_offset
);
1316 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1318 offset
= get_src(ctx
, &intr
->src
[1])[0];
1320 /* src0 is data (or uvec2(data, compare)
1322 * src2 is uvec2(offset*4, 0)
1324 * Note that nir already multiplies the offset by four
1326 src0
= get_src(ctx
, &intr
->src
[2])[0];
1327 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1328 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1333 switch (intr
->intrinsic
) {
1334 case nir_intrinsic_ssbo_atomic_add
:
1335 atomic
= ir3_ATOMIC_ADD(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1337 case nir_intrinsic_ssbo_atomic_imin
:
1338 atomic
= ir3_ATOMIC_MIN(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1341 case nir_intrinsic_ssbo_atomic_umin
:
1342 atomic
= ir3_ATOMIC_MIN(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1344 case nir_intrinsic_ssbo_atomic_imax
:
1345 atomic
= ir3_ATOMIC_MAX(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1348 case nir_intrinsic_ssbo_atomic_umax
:
1349 atomic
= ir3_ATOMIC_MAX(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1351 case nir_intrinsic_ssbo_atomic_and
:
1352 atomic
= ir3_ATOMIC_AND(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1354 case nir_intrinsic_ssbo_atomic_or
:
1355 atomic
= ir3_ATOMIC_OR(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1357 case nir_intrinsic_ssbo_atomic_xor
:
1358 atomic
= ir3_ATOMIC_XOR(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1360 case nir_intrinsic_ssbo_atomic_exchange
:
1361 atomic
= ir3_ATOMIC_XCHG(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1363 case nir_intrinsic_ssbo_atomic_comp_swap
:
1364 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1365 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1367 get_src(ctx
, &intr
->src
[3])[0],
1369 atomic
= ir3_ATOMIC_CMPXCHG(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1375 atomic
->cat6
.iim_val
= 1;
1376 atomic
->cat6
.type
= type
;
1377 mark_ssbo_write(ctx
, atomic
);
1379 /* even if nothing consume the result, we can't DCE the instruction: */
1380 array_insert(b
, b
->keeps
, atomic
);
1385 static void add_sysval_input_compmask(struct ir3_compile
*ctx
,
1386 gl_system_value slot
, unsigned compmask
,
1387 struct ir3_instruction
*instr
)
1389 struct ir3_shader_variant
*so
= ctx
->so
;
1390 unsigned r
= regid(so
->inputs_count
, 0);
1391 unsigned n
= so
->inputs_count
++;
1393 so
->inputs
[n
].sysval
= true;
1394 so
->inputs
[n
].slot
= slot
;
1395 so
->inputs
[n
].compmask
= compmask
;
1396 so
->inputs
[n
].regid
= r
;
1397 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1400 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1401 ctx
->ir
->inputs
[r
] = instr
;
1404 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1405 struct ir3_instruction
*instr
)
1407 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1411 emit_intrinsic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1413 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1414 struct ir3_instruction
**dst
;
1415 struct ir3_instruction
* const *src
;
1416 struct ir3_block
*b
= ctx
->block
;
1417 nir_const_value
*const_offset
;
1420 if (info
->has_dest
) {
1421 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1426 switch (intr
->intrinsic
) {
1427 case nir_intrinsic_load_uniform
:
1428 idx
= nir_intrinsic_base(intr
);
1429 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1431 idx
+= const_offset
->u32
[0];
1432 for (int i
= 0; i
< intr
->num_components
; i
++) {
1433 unsigned n
= idx
* 4 + i
;
1434 dst
[i
] = create_uniform(ctx
, n
);
1437 src
= get_src(ctx
, &intr
->src
[0]);
1438 for (int i
= 0; i
< intr
->num_components
; i
++) {
1439 int n
= idx
* 4 + i
;
1440 dst
[i
] = create_uniform_indirect(ctx
, n
,
1441 get_addr(ctx
, src
[0], 4));
1443 /* NOTE: if relative addressing is used, we set
1444 * constlen in the compiler (to worst-case value)
1445 * since we don't know in the assembler what the max
1446 * addr reg value can be:
1448 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1451 case nir_intrinsic_load_ubo
:
1452 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1454 case nir_intrinsic_load_input
:
1455 idx
= nir_intrinsic_base(intr
);
1456 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1458 idx
+= const_offset
->u32
[0];
1459 for (int i
= 0; i
< intr
->num_components
; i
++) {
1460 unsigned n
= idx
* 4 + i
;
1461 dst
[i
] = ctx
->ir
->inputs
[n
];
1464 src
= get_src(ctx
, &intr
->src
[0]);
1465 struct ir3_instruction
*collect
=
1466 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1467 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
1468 for (int i
= 0; i
< intr
->num_components
; i
++) {
1469 unsigned n
= idx
* 4 + i
;
1470 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1475 case nir_intrinsic_load_ssbo
:
1476 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1478 case nir_intrinsic_store_ssbo
:
1479 emit_intrinsic_store_ssbo(ctx
, intr
);
1481 case nir_intrinsic_ssbo_atomic_add
:
1482 case nir_intrinsic_ssbo_atomic_imin
:
1483 case nir_intrinsic_ssbo_atomic_umin
:
1484 case nir_intrinsic_ssbo_atomic_imax
:
1485 case nir_intrinsic_ssbo_atomic_umax
:
1486 case nir_intrinsic_ssbo_atomic_and
:
1487 case nir_intrinsic_ssbo_atomic_or
:
1488 case nir_intrinsic_ssbo_atomic_xor
:
1489 case nir_intrinsic_ssbo_atomic_exchange
:
1490 case nir_intrinsic_ssbo_atomic_comp_swap
:
1491 if (info
->has_dest
) {
1492 compile_assert(ctx
, intr
->num_components
== 1);
1493 dst
[0] = emit_intrinsic_atomic(ctx
, intr
);
1495 emit_intrinsic_atomic(ctx
, intr
);
1498 case nir_intrinsic_store_output
:
1499 idx
= nir_intrinsic_base(intr
);
1500 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1501 compile_assert(ctx
, const_offset
!= NULL
);
1502 idx
+= const_offset
->u32
[0];
1504 src
= get_src(ctx
, &intr
->src
[0]);
1505 for (int i
= 0; i
< intr
->num_components
; i
++) {
1506 unsigned n
= idx
* 4 + i
;
1507 ctx
->ir
->outputs
[n
] = src
[i
];
1510 case nir_intrinsic_load_base_vertex
:
1511 if (!ctx
->basevertex
) {
1512 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1513 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1516 dst
[0] = ctx
->basevertex
;
1518 case nir_intrinsic_load_vertex_id_zero_base
:
1519 case nir_intrinsic_load_vertex_id
:
1520 if (!ctx
->vertex_id
) {
1521 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1522 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1523 ctx
->vertex_id
= create_input(b
, 0);
1524 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
1526 dst
[0] = ctx
->vertex_id
;
1528 case nir_intrinsic_load_instance_id
:
1529 if (!ctx
->instance_id
) {
1530 ctx
->instance_id
= create_input(b
, 0);
1531 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1534 dst
[0] = ctx
->instance_id
;
1536 case nir_intrinsic_load_user_clip_plane
:
1537 idx
= nir_intrinsic_ucp_id(intr
);
1538 for (int i
= 0; i
< intr
->num_components
; i
++) {
1539 unsigned n
= idx
* 4 + i
;
1540 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1543 case nir_intrinsic_load_front_face
:
1544 if (!ctx
->frag_face
) {
1545 ctx
->so
->frag_face
= true;
1546 ctx
->frag_face
= create_input(b
, 0);
1547 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1549 /* for fragface, we get -1 for back and 0 for front. However this is
1550 * the inverse of what nir expects (where ~0 is true).
1552 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1553 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1555 case nir_intrinsic_load_local_invocation_id
:
1556 if (!ctx
->local_invocation_id
) {
1557 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
1558 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
1559 0x7, ctx
->local_invocation_id
);
1561 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1563 case nir_intrinsic_load_work_group_id
:
1564 if (!ctx
->work_group_id
) {
1565 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
1566 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
1567 0x7, ctx
->work_group_id
);
1568 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1570 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1572 case nir_intrinsic_load_num_work_groups
:
1573 for (int i
= 0; i
< intr
->num_components
; i
++) {
1574 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1577 case nir_intrinsic_discard_if
:
1578 case nir_intrinsic_discard
: {
1579 struct ir3_instruction
*cond
, *kill
;
1581 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1582 /* conditional discard: */
1583 src
= get_src(ctx
, &intr
->src
[0]);
1584 cond
= ir3_b2n(b
, src
[0]);
1586 /* unconditional discard: */
1587 cond
= create_immed(b
, 1);
1590 /* NOTE: only cmps.*.* can write p0.x: */
1591 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1592 cond
->cat2
.condition
= IR3_COND_NE
;
1594 /* condition always goes in predicate register: */
1595 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1597 kill
= ir3_KILL(b
, cond
, 0);
1598 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1600 array_insert(b
, b
->keeps
, kill
);
1601 ctx
->so
->has_kill
= true;
1606 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1607 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1612 put_dst(ctx
, &intr
->dest
);
1616 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1618 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1619 instr
->def
.num_components
);
1620 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1621 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
1625 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1627 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1628 undef
->def
.num_components
);
1629 /* backend doesn't want undefined instructions, so just plug
1632 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1633 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1637 * texture fetch/sample instructions:
1641 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1643 unsigned coords
, flags
= 0;
1645 /* note: would use tex->coord_components.. except txs.. also,
1646 * since array index goes after shadow ref, we don't want to
1649 switch (tex
->sampler_dim
) {
1650 case GLSL_SAMPLER_DIM_1D
:
1651 case GLSL_SAMPLER_DIM_BUF
:
1654 case GLSL_SAMPLER_DIM_2D
:
1655 case GLSL_SAMPLER_DIM_RECT
:
1656 case GLSL_SAMPLER_DIM_EXTERNAL
:
1657 case GLSL_SAMPLER_DIM_MS
:
1660 case GLSL_SAMPLER_DIM_3D
:
1661 case GLSL_SAMPLER_DIM_CUBE
:
1663 flags
|= IR3_INSTR_3D
;
1666 unreachable("bad sampler_dim");
1669 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1670 flags
|= IR3_INSTR_S
;
1672 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1673 flags
|= IR3_INSTR_A
;
1680 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1682 struct ir3_block
*b
= ctx
->block
;
1683 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1684 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1685 struct ir3_instruction
*lod
, *compare
, *proj
;
1686 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1687 unsigned i
, coords
, flags
;
1688 unsigned nsrc0
= 0, nsrc1
= 0;
1692 coord
= off
= ddx
= ddy
= NULL
;
1693 lod
= proj
= compare
= NULL
;
1695 /* TODO: might just be one component for gathers? */
1696 dst
= get_dst(ctx
, &tex
->dest
, 4);
1698 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1699 switch (tex
->src
[i
].src_type
) {
1700 case nir_tex_src_coord
:
1701 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1703 case nir_tex_src_bias
:
1704 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1707 case nir_tex_src_lod
:
1708 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1711 case nir_tex_src_comparator
: /* shadow comparator */
1712 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1714 case nir_tex_src_projector
:
1715 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1718 case nir_tex_src_offset
:
1719 off
= get_src(ctx
, &tex
->src
[i
].src
);
1722 case nir_tex_src_ddx
:
1723 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1725 case nir_tex_src_ddy
:
1726 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1729 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
1730 tex
->src
[i
].src_type
);
1736 case nir_texop_tex
: opc
= OPC_SAM
; break;
1737 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1738 case nir_texop_txl
: opc
= OPC_SAML
; break;
1739 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1740 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1741 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1742 case nir_texop_txf_ms
:
1745 case nir_texop_query_levels
:
1746 case nir_texop_texture_samples
:
1747 case nir_texop_samples_identical
:
1748 case nir_texop_txf_ms_mcs
:
1749 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1753 tex_info(tex
, &flags
, &coords
);
1756 * lay out the first argument in the proper order:
1757 * - actual coordinates first
1758 * - shadow reference
1761 * - starting at offset 4, dpdx.xy, dpdy.xy
1763 * bias/lod go into the second arg
1766 /* insert tex coords: */
1767 for (i
= 0; i
< coords
; i
++)
1772 /* scale up integer coords for TXF based on the LOD */
1773 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1775 for (i
= 0; i
< coords
; i
++)
1776 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
1780 /* hw doesn't do 1d, so we treat it as 2d with
1781 * height of 1, and patch up the y coord.
1782 * TODO: y coord should be (int)0 in some cases..
1784 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1787 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1788 src0
[nsrc0
++] = compare
;
1790 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
1791 struct ir3_instruction
*idx
= coord
[coords
];
1793 /* the array coord for cube arrays needs 0.5 added to it */
1794 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
1795 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
1797 src0
[nsrc0
++] = idx
;
1801 src0
[nsrc0
++] = proj
;
1802 flags
|= IR3_INSTR_P
;
1805 /* pad to 4, then ddx/ddy: */
1806 if (tex
->op
== nir_texop_txd
) {
1808 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1809 for (i
= 0; i
< coords
; i
++)
1810 src0
[nsrc0
++] = ddx
[i
];
1812 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1813 for (i
= 0; i
< coords
; i
++)
1814 src0
[nsrc0
++] = ddy
[i
];
1816 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1820 * second argument (if applicable):
1825 if (has_off
| has_lod
| has_bias
) {
1827 for (i
= 0; i
< coords
; i
++)
1828 src1
[nsrc1
++] = off
[i
];
1830 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1831 flags
|= IR3_INSTR_O
;
1834 if (has_lod
| has_bias
)
1835 src1
[nsrc1
++] = lod
;
1838 switch (tex
->dest_type
) {
1839 case nir_type_invalid
:
1840 case nir_type_float
:
1851 unreachable("bad dest_type");
1854 if (opc
== OPC_GETLOD
)
1857 unsigned tex_idx
= tex
->texture_index
;
1859 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
1861 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
1862 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
1864 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1865 tex_idx
, tex_idx
, col0
, col1
);
1867 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
1868 /* only need first 3 components: */
1869 sam
->regs
[0]->wrmask
= 0x7;
1870 split_dest(b
, dst
, sam
, 0, 3);
1872 /* we need to sample the alpha separately with a non-ASTC
1875 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
1876 tex_idx
, tex_idx
, col0
, col1
);
1878 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
1880 /* fixup .w component: */
1881 split_dest(b
, &dst
[3], sam
, 3, 1);
1883 /* normal (non-workaround) case: */
1884 split_dest(b
, dst
, sam
, 0, 4);
1887 /* GETLOD returns results in 4.8 fixed point */
1888 if (opc
== OPC_GETLOD
) {
1889 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1891 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1892 for (i
= 0; i
< 2; i
++) {
1893 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1898 put_dst(ctx
, &tex
->dest
);
1902 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1904 struct ir3_block
*b
= ctx
->block
;
1905 struct ir3_instruction
**dst
, *sam
;
1907 dst
= get_dst(ctx
, &tex
->dest
, 1);
1909 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1910 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
1912 /* even though there is only one component, since it ends
1913 * up in .z rather than .x, we need a split_dest()
1915 split_dest(b
, dst
, sam
, 0, 3);
1917 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1918 * the value in TEX_CONST_0 is zero-based.
1920 if (ctx
->levels_add_one
)
1921 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1923 put_dst(ctx
, &tex
->dest
);
1927 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1929 struct ir3_block
*b
= ctx
->block
;
1930 struct ir3_instruction
**dst
, *sam
;
1931 struct ir3_instruction
*lod
;
1932 unsigned flags
, coords
;
1934 tex_info(tex
, &flags
, &coords
);
1936 /* Actually we want the number of dimensions, not coordinates. This
1937 * distinction only matters for cubes.
1939 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1942 dst
= get_dst(ctx
, &tex
->dest
, 4);
1944 compile_assert(ctx
, tex
->num_srcs
== 1);
1945 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1947 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1949 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1950 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
1952 split_dest(b
, dst
, sam
, 0, 4);
1954 /* Array size actually ends up in .w rather than .z. This doesn't
1955 * matter for miplevel 0, but for higher mips the value in z is
1956 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1957 * returned, which means that we have to add 1 to it for arrays.
1959 if (tex
->is_array
) {
1960 if (ctx
->levels_add_one
) {
1961 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1963 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1967 put_dst(ctx
, &tex
->dest
);
1971 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1973 struct ir3_instruction
*phi
, **dst
;
1975 /* NOTE: phi's should be lowered to scalar at this point */
1976 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1978 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1980 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
1981 1 + exec_list_length(&nphi
->srcs
));
1982 ir3_reg_create(phi
, 0, 0); /* dst */
1983 phi
->phi
.nphi
= nphi
;
1987 put_dst(ctx
, &nphi
->dest
);
1990 /* phi instructions are left partially constructed. We don't resolve
1991 * their srcs until the end of the block, since (eg. loops) one of
1992 * the phi's srcs might be defined after the phi due to back edges in
1996 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1998 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1999 nir_phi_instr
*nphi
;
2001 /* phi's only come at start of block: */
2002 if (instr
->opc
!= OPC_META_PHI
)
2005 if (!instr
->phi
.nphi
)
2008 nphi
= instr
->phi
.nphi
;
2009 instr
->phi
.nphi
= NULL
;
2011 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
2012 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
2014 /* NOTE: src might not be in the same block as it comes from
2015 * according to the phi.. but in the end the backend assumes
2016 * it will be able to assign the same register to each (which
2017 * only works if it is assigned in the src block), so insert
2018 * an extra mov to make sure the phi src is assigned in the
2019 * block it comes from:
2021 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
2023 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
2029 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
2031 switch (jump
->type
) {
2032 case nir_jump_break
:
2033 case nir_jump_continue
:
2034 /* I *think* we can simply just ignore this, and use the
2035 * successor block link to figure out where we need to
2036 * jump to for break/continue
2040 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2046 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
2048 switch (instr
->type
) {
2049 case nir_instr_type_alu
:
2050 emit_alu(ctx
, nir_instr_as_alu(instr
));
2052 case nir_instr_type_intrinsic
:
2053 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2055 case nir_instr_type_load_const
:
2056 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2058 case nir_instr_type_ssa_undef
:
2059 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2061 case nir_instr_type_tex
: {
2062 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2063 /* couple tex instructions get special-cased:
2067 emit_tex_txs(ctx
, tex
);
2069 case nir_texop_query_levels
:
2070 emit_tex_query_levels(ctx
, tex
);
2078 case nir_instr_type_phi
:
2079 emit_phi(ctx
, nir_instr_as_phi(instr
));
2081 case nir_instr_type_jump
:
2082 emit_jump(ctx
, nir_instr_as_jump(instr
));
2084 case nir_instr_type_call
:
2085 case nir_instr_type_parallel_copy
:
2086 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2091 static struct ir3_block
*
2092 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
2094 struct ir3_block
*block
;
2095 struct hash_entry
*entry
;
2096 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2100 block
= ir3_block_create(ctx
->ir
);
2101 block
->nblock
= nblock
;
2102 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2108 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
2110 struct ir3_block
*block
= get_block(ctx
, nblock
);
2112 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2113 if (nblock
->successors
[i
]) {
2114 block
->successors
[i
] =
2115 get_block(ctx
, nblock
->successors
[i
]);
2120 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2122 /* re-emit addr register in each block if needed: */
2123 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2124 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2125 ctx
->addr_ht
[i
] = NULL
;
2128 nir_foreach_instr(instr
, nblock
) {
2129 emit_instr(ctx
, instr
);
2135 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
2138 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
2140 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2142 ctx
->block
->condition
=
2143 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2145 emit_cf_list(ctx
, &nif
->then_list
);
2146 emit_cf_list(ctx
, &nif
->else_list
);
2150 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
2152 emit_cf_list(ctx
, &nloop
->body
);
2156 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
2158 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2159 switch (node
->type
) {
2160 case nir_cf_node_block
:
2161 emit_block(ctx
, nir_cf_node_as_block(node
));
2163 case nir_cf_node_if
:
2164 emit_if(ctx
, nir_cf_node_as_if(node
));
2166 case nir_cf_node_loop
:
2167 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2169 case nir_cf_node_function
:
2170 compile_error(ctx
, "TODO\n");
2176 /* emit stream-out code. At this point, the current block is the original
2177 * (nir) end block, and nir ensures that all flow control paths terminate
2178 * into the end block. We re-purpose the original end block to generate
2179 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2180 * block holding stream-out write instructions, followed by the new end
2184 * p0.x = (vtxcnt < maxvtxcnt)
2185 * // succs: blockStreamOut, blockNewEnd
2188 * ... stream-out instructions ...
2189 * // succs: blockNewEnd
2195 emit_stream_out(struct ir3_compile
*ctx
)
2197 struct ir3_shader_variant
*v
= ctx
->so
;
2198 struct ir3
*ir
= ctx
->ir
;
2199 struct pipe_stream_output_info
*strmout
=
2200 &ctx
->so
->shader
->stream_output
;
2201 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2202 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2203 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2205 /* create vtxcnt input in input block at top of shader,
2206 * so that it is seen as live over the entire duration
2209 vtxcnt
= create_input(ctx
->in_block
, 0);
2210 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2212 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2214 /* at this point, we are at the original 'end' block,
2215 * re-purpose this block to stream-out condition, then
2216 * append stream-out block and new-end block
2218 orig_end_block
= ctx
->block
;
2220 stream_out_block
= ir3_block_create(ir
);
2221 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2223 new_end_block
= ir3_block_create(ir
);
2224 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2226 orig_end_block
->successors
[0] = stream_out_block
;
2227 orig_end_block
->successors
[1] = new_end_block
;
2228 stream_out_block
->successors
[0] = new_end_block
;
2230 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2231 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2232 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2233 cond
->cat2
.condition
= IR3_COND_LT
;
2235 /* condition goes on previous block to the conditional,
2236 * since it is used to pick which of the two successor
2239 orig_end_block
->condition
= cond
;
2241 /* switch to stream_out_block to generate the stream-out
2244 ctx
->block
= stream_out_block
;
2246 /* Calculate base addresses based on vtxcnt. Instructions
2247 * generated for bases not used in following loop will be
2248 * stripped out in the backend.
2250 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2251 unsigned stride
= strmout
->stride
[i
];
2252 struct ir3_instruction
*base
, *off
;
2254 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2256 /* 24-bit should be enough: */
2257 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2258 create_immed(ctx
->block
, stride
* 4), 0);
2260 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2263 /* Generate the per-output store instructions: */
2264 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2265 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2266 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2267 struct ir3_instruction
*base
, *out
, *stg
;
2269 base
= bases
[strmout
->output
[i
].output_buffer
];
2270 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2272 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2273 create_immed(ctx
->block
, 1), 0);
2274 stg
->cat6
.type
= TYPE_U32
;
2275 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2277 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2281 /* and finally switch to the new_end_block: */
2282 ctx
->block
= new_end_block
;
2286 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2288 nir_metadata_require(impl
, nir_metadata_block_index
);
2290 emit_cf_list(ctx
, &impl
->body
);
2291 emit_block(ctx
, impl
->end_block
);
2293 /* at this point, we should have a single empty block,
2294 * into which we emit the 'end' instruction.
2296 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2298 /* If stream-out (aka transform-feedback) enabled, emit the
2299 * stream-out instructions, followed by a new empty block (into
2300 * which the 'end' instruction lands).
2302 * NOTE: it is done in this order, rather than inserting before
2303 * we emit end_block, because NIR guarantees that all blocks
2304 * flow into end_block, and that end_block has no successors.
2305 * So by re-purposing end_block as the first block of stream-
2306 * out, we guarantee that all exit paths flow into the stream-
2309 if ((ctx
->compiler
->gpu_id
< 500) &&
2310 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2311 !ctx
->so
->key
.binning_pass
) {
2312 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2313 emit_stream_out(ctx
);
2316 ir3_END(ctx
->block
);
2320 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2322 struct ir3_shader_variant
*so
= ctx
->so
;
2323 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2324 unsigned ncomp
= glsl_get_components(in
->type
);
2325 unsigned n
= in
->data
.driver_location
;
2326 unsigned slot
= in
->data
.location
;
2328 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2329 slot
, array_len
, ncomp
, n
);
2331 /* let's pretend things other than vec4 don't exist: */
2332 ncomp
= MAX2(ncomp
, 4);
2333 compile_assert(ctx
, ncomp
== 4);
2335 so
->inputs
[n
].slot
= slot
;
2336 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2337 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2338 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2340 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2341 for (int i
= 0; i
< ncomp
; i
++) {
2342 struct ir3_instruction
*instr
= NULL
;
2343 unsigned idx
= (n
* 4) + i
;
2345 if (slot
== VARYING_SLOT_POS
) {
2346 so
->inputs
[n
].bary
= false;
2347 so
->frag_coord
= true;
2348 instr
= create_frag_coord(ctx
, i
);
2349 } else if (slot
== VARYING_SLOT_PNTC
) {
2350 /* see for example st_get_generic_varying_index().. this is
2351 * maybe a bit mesa/st specific. But we need things to line
2352 * up for this in fdN_program:
2353 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2354 * if (emit->sprite_coord_enable & texmask) {
2358 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2359 so
->inputs
[n
].bary
= true;
2360 instr
= create_frag_input(ctx
, false);
2362 bool use_ldlv
= false;
2364 /* detect the special case for front/back colors where
2365 * we need to do flat vs smooth shading depending on
2368 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2370 case VARYING_SLOT_COL0
:
2371 case VARYING_SLOT_COL1
:
2372 case VARYING_SLOT_BFC0
:
2373 case VARYING_SLOT_BFC1
:
2374 so
->inputs
[n
].rasterflat
= true;
2381 if (ctx
->flat_bypass
) {
2382 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2383 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2387 so
->inputs
[n
].bary
= true;
2389 instr
= create_frag_input(ctx
, use_ldlv
);
2392 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2394 ctx
->ir
->inputs
[idx
] = instr
;
2396 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2397 for (int i
= 0; i
< ncomp
; i
++) {
2398 unsigned idx
= (n
* 4) + i
;
2399 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2400 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2403 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2406 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2407 so
->total_in
+= ncomp
;
2412 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2414 struct ir3_shader_variant
*so
= ctx
->so
;
2415 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2416 unsigned ncomp
= glsl_get_components(out
->type
);
2417 unsigned n
= out
->data
.driver_location
;
2418 unsigned slot
= out
->data
.location
;
2421 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2422 slot
, array_len
, ncomp
, n
);
2424 /* let's pretend things other than vec4 don't exist: */
2425 ncomp
= MAX2(ncomp
, 4);
2426 compile_assert(ctx
, ncomp
== 4);
2428 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2430 case FRAG_RESULT_DEPTH
:
2431 comp
= 2; /* tgsi will write to .z component */
2432 so
->writes_pos
= true;
2434 case FRAG_RESULT_COLOR
:
2438 if (slot
>= FRAG_RESULT_DATA0
)
2440 compile_error(ctx
, "unknown FS output name: %s\n",
2441 gl_frag_result_name(slot
));
2443 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2445 case VARYING_SLOT_POS
:
2446 so
->writes_pos
= true;
2448 case VARYING_SLOT_PSIZ
:
2449 so
->writes_psize
= true;
2451 case VARYING_SLOT_COL0
:
2452 case VARYING_SLOT_COL1
:
2453 case VARYING_SLOT_BFC0
:
2454 case VARYING_SLOT_BFC1
:
2455 case VARYING_SLOT_FOGC
:
2456 case VARYING_SLOT_CLIP_DIST0
:
2457 case VARYING_SLOT_CLIP_DIST1
:
2458 case VARYING_SLOT_CLIP_VERTEX
:
2461 if (slot
>= VARYING_SLOT_VAR0
)
2463 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2465 compile_error(ctx
, "unknown VS output name: %s\n",
2466 gl_varying_slot_name(slot
));
2469 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2472 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2474 so
->outputs
[n
].slot
= slot
;
2475 so
->outputs
[n
].regid
= regid(n
, comp
);
2476 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2478 for (int i
= 0; i
< ncomp
; i
++) {
2479 unsigned idx
= (n
* 4) + i
;
2480 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
2481 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2486 max_drvloc(struct exec_list
*vars
)
2489 nir_foreach_variable(var
, vars
) {
2490 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2495 static const unsigned max_sysvals
[SHADER_MAX
] = {
2496 [SHADER_VERTEX
] = 16,
2497 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
2501 emit_instructions(struct ir3_compile
*ctx
)
2503 unsigned ninputs
, noutputs
;
2504 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2506 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2507 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2509 /* we need to leave room for sysvals:
2511 ninputs
+= max_sysvals
[ctx
->so
->type
];
2513 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2515 /* Create inputs in first block: */
2516 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2517 ctx
->in_block
= ctx
->block
;
2518 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2520 ninputs
-= max_sysvals
[ctx
->so
->type
];
2522 /* for fragment shader, we have a single input register (usually
2523 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2525 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2526 // TODO maybe a helper for fi since we need it a few places..
2527 struct ir3_instruction
*instr
;
2528 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
2529 ir3_reg_create(instr
, 0, 0);
2530 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2531 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2532 ctx
->frag_pos
= instr
;
2536 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2537 setup_input(ctx
, var
);
2540 /* Setup outputs: */
2541 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2542 setup_output(ctx
, var
);
2545 /* Setup registers (which should only be arrays): */
2546 nir_foreach_register(reg
, &ctx
->s
->registers
) {
2547 declare_array(ctx
, reg
);
2550 /* NOTE: need to do something more clever when we support >1 fxn */
2551 nir_foreach_register(reg
, &fxn
->registers
) {
2552 declare_array(ctx
, reg
);
2554 /* And emit the body: */
2556 emit_function(ctx
, fxn
);
2558 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2559 resolve_phis(ctx
, block
);
2563 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2564 * for a fragment shader are just bary.f instructions. The *actual* inputs
2565 * from the hw perspective are the frag_pos and optionally frag_coord and
2569 fixup_frag_inputs(struct ir3_compile
*ctx
)
2571 struct ir3_shader_variant
*so
= ctx
->so
;
2572 struct ir3
*ir
= ctx
->ir
;
2573 struct ir3_instruction
**inputs
;
2574 struct ir3_instruction
*instr
;
2579 n
= 4; /* always have frag_pos */
2580 n
+= COND(so
->frag_face
, 4);
2581 n
+= COND(so
->frag_coord
, 4);
2583 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2585 if (so
->frag_face
) {
2586 /* this ultimately gets assigned to hr0.x so doesn't conflict
2587 * with frag_coord/frag_pos..
2589 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2590 ctx
->frag_face
->regs
[0]->num
= 0;
2592 /* remaining channels not used, but let's avoid confusing
2593 * other parts that expect inputs to come in groups of vec4
2595 inputs
[ir
->ninputs
++] = NULL
;
2596 inputs
[ir
->ninputs
++] = NULL
;
2597 inputs
[ir
->ninputs
++] = NULL
;
2600 /* since we don't know where to set the regid for frag_coord,
2601 * we have to use r0.x for it. But we don't want to *always*
2602 * use r1.x for frag_pos as that could increase the register
2603 * footprint on simple shaders:
2605 if (so
->frag_coord
) {
2606 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2607 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2608 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2609 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2611 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2612 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2613 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2614 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2617 /* we always have frag_pos: */
2618 so
->pos_regid
= regid
;
2621 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2622 instr
->regs
[0]->num
= regid
++;
2623 inputs
[ir
->ninputs
++] = instr
;
2624 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2627 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2628 instr
->regs
[0]->num
= regid
++;
2629 inputs
[ir
->ninputs
++] = instr
;
2630 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2632 ir
->inputs
= inputs
;
2635 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2636 * need to assign the tex state indexes for these after we know the
2640 fixup_astc_srgb(struct ir3_compile
*ctx
)
2642 struct ir3_shader_variant
*so
= ctx
->so
;
2643 /* indexed by original tex idx, value is newly assigned alpha sampler
2644 * state tex idx. Zero is invalid since there is at least one sampler
2647 unsigned alt_tex_state
[16] = {0};
2648 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2651 so
->astc_srgb
.base
= tex_idx
;
2653 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2654 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2656 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2658 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2659 /* assign new alternate/alpha tex state slot: */
2660 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2661 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2662 so
->astc_srgb
.count
++;
2665 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2670 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2671 struct ir3_shader_variant
*so
)
2673 struct ir3_compile
*ctx
;
2675 struct ir3_instruction
**inputs
;
2676 unsigned i
, j
, actual_in
, inloc
;
2677 int ret
= 0, max_bary
;
2681 ctx
= compile_init(compiler
, so
);
2683 DBG("INIT failed!");
2688 emit_instructions(ctx
);
2691 DBG("EMIT failed!");
2696 ir
= so
->ir
= ctx
->ir
;
2698 /* keep track of the inputs from TGSI perspective.. */
2699 inputs
= ir
->inputs
;
2701 /* but fixup actual inputs for frag shader: */
2702 if (so
->type
== SHADER_FRAGMENT
)
2703 fixup_frag_inputs(ctx
);
2705 /* at this point, for binning pass, throw away unneeded outputs: */
2706 if (so
->key
.binning_pass
) {
2707 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2708 unsigned slot
= so
->outputs
[i
].slot
;
2710 /* throw away everything but first position/psize */
2711 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2713 so
->outputs
[j
] = so
->outputs
[i
];
2714 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2715 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2716 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2717 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2722 so
->outputs_count
= j
;
2723 ir
->noutputs
= j
* 4;
2726 /* if we want half-precision outputs, mark the output registers
2729 if (so
->key
.half_precision
) {
2730 for (i
= 0; i
< ir
->noutputs
; i
++) {
2731 struct ir3_instruction
*out
= ir
->outputs
[i
];
2736 /* if frag shader writes z, that needs to be full precision: */
2737 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
2740 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2741 /* output could be a fanout (ie. texture fetch output)
2742 * in which case we need to propagate the half-reg flag
2743 * up to the definer so that RA sees it:
2745 if (out
->opc
== OPC_META_FO
) {
2746 out
= out
->regs
[1]->instr
;
2747 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2750 if (out
->opc
== OPC_MOV
) {
2751 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2756 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2757 printf("BEFORE CP:\n");
2763 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2764 printf("BEFORE GROUPING:\n");
2768 /* Group left/right neighbors, inserting mov's where needed to
2775 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2776 printf("AFTER DEPTH:\n");
2780 ret
= ir3_sched(ir
);
2782 DBG("SCHED failed!");
2786 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2787 printf("AFTER SCHED:\n");
2791 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2797 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2798 printf("AFTER RA:\n");
2802 /* fixup input/outputs: */
2803 for (i
= 0; i
< so
->outputs_count
; i
++) {
2804 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2807 /* Note that some or all channels of an input may be unused: */
2810 for (i
= 0; i
< so
->inputs_count
; i
++) {
2811 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
2812 so
->inputs
[i
].ncomp
= 0;
2813 so
->inputs
[i
].inloc
= inloc
;
2814 for (j
= 0; j
< 4; j
++) {
2815 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2816 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2817 compmask
|= (1 << j
);
2818 regid
= in
->regs
[0]->num
- j
;
2820 so
->inputs
[i
].ncomp
++;
2821 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2823 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2824 in
->regs
[1]->iim_val
= inloc
+ j
;
2829 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
2831 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
2834 so
->inputs
[i
].compmask
= compmask
;
2836 so
->inputs
[i
].regid
= regid
;
2840 fixup_astc_srgb(ctx
);
2842 /* We need to do legalize after (for frag shader's) the "bary.f"
2843 * offsets (inloc) have been assigned.
2845 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
2847 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2848 printf("AFTER LEGALIZE:\n");
2852 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2853 if (so
->type
== SHADER_VERTEX
)
2854 so
->total_in
= actual_in
;
2856 so
->total_in
= max_bary
+ 1;
2861 ir3_destroy(so
->ir
);