1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* mapping from nir_register to defining instruction: */
78 struct hash_table
*def_ht
;
82 /* a common pattern for indirect addressing is to request the
83 * same address register multiple times. To avoid generating
84 * duplicate instruction sequences (which our backend does not
85 * try to clean up, since that should be done as the NIR stage)
86 * we cache the address value generated for a given src value:
88 * Note that we have to cache these per alignment, since same
89 * src used for an array of vec1 cannot be also used for an
92 struct hash_table
*addr_ht
[4];
94 /* last dst array, for indirect we need to insert a var-store.
96 struct ir3_instruction
**last_dst
;
99 /* maps nir_block to ir3_block, mostly for the purposes of
100 * figuring out the blocks successors
102 struct hash_table
*block_ht
;
104 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
105 * so we need to use ldlv.u32 to load the varying directly:
109 /* on a3xx, we need to add one to # of array levels:
113 /* on a3xx, we need to scale up integer coords for isaml based
116 bool unminify_coords
;
118 /* on a4xx, for array textures we need to add 0.5 to the array
121 bool array_index_add_half
;
123 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
126 unsigned max_texture_index
;
128 /* set if we encounter something we can't handle yet, so we
129 * can bail cleanly and fallback to TGSI compiler f/e
134 /* gpu pointer size in units of 32bit registers/slots */
135 static unsigned pointer_size(struct ir3_context
*ctx
)
137 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
140 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
141 static struct ir3_block
* get_block(struct ir3_context
*ctx
, nir_block
*nblock
);
144 static struct ir3_context
*
145 compile_init(struct ir3_compiler
*compiler
,
146 struct ir3_shader_variant
*so
)
148 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
150 if (compiler
->gpu_id
>= 400) {
151 /* need special handling for "flat" */
152 ctx
->flat_bypass
= true;
153 ctx
->levels_add_one
= false;
154 ctx
->unminify_coords
= false;
155 ctx
->array_index_add_half
= true;
157 if (so
->type
== SHADER_VERTEX
)
158 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
159 else if (so
->type
== SHADER_FRAGMENT
)
160 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
163 /* no special handling for "flat" */
164 ctx
->flat_bypass
= false;
165 ctx
->levels_add_one
= true;
166 ctx
->unminify_coords
= true;
167 ctx
->array_index_add_half
= false;
170 ctx
->compiler
= compiler
;
173 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
174 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
175 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
176 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
178 /* TODO: maybe generate some sort of bitmask of what key
179 * lowers vs what shader has (ie. no need to lower
180 * texture clamp lowering if no texture sample instrs)..
181 * although should be done further up the stack to avoid
182 * creating duplicate variants..
185 if (ir3_key_lowers_nir(&so
->key
)) {
186 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
187 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
189 /* fast-path for shader key that lowers nothing in NIR: */
190 ctx
->s
= so
->shader
->nir
;
193 /* this needs to be the last pass run, so do this here instead of
194 * in ir3_optimize_nir():
196 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
198 if (fd_mesa_debug
& FD_DBG_DISASM
) {
199 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
200 so
->shader
->id
, so
->id
, so
->type
,
201 so
->key
.binning_pass
, so
->key
.color_two_side
,
202 so
->key
.half_precision
);
203 nir_print_shader(ctx
->s
, stdout
);
206 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
208 so
->num_uniforms
= ctx
->s
->num_uniforms
;
209 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
211 /* Layout of constant registers, each section aligned to vec4. Note
212 * that pointer size (ubo, etc) changes depending on generation.
217 * if (vertex shader) {
218 * driver params (IR3_DP_*)
219 * if (stream_output.num_outputs > 0)
220 * stream-out addresses
224 * Immediates go last mostly because they are inserted in the CP pass
225 * after the nir -> ir3 frontend.
227 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
228 unsigned ptrsz
= pointer_size(ctx
);
230 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
232 if (so
->num_ubos
> 0) {
233 so
->constbase
.ubo
= constoff
;
234 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
237 if (so
->const_layout
.ssbo_size
.count
> 0) {
238 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
239 so
->constbase
.ssbo_sizes
= constoff
;
240 constoff
+= align(cnt
, 4) / 4;
243 if (so
->const_layout
.image_dims
.count
> 0) {
244 unsigned cnt
= so
->const_layout
.image_dims
.count
;
245 so
->constbase
.image_dims
= constoff
;
246 constoff
+= align(cnt
, 4) / 4;
249 unsigned num_driver_params
= 0;
250 if (so
->type
== SHADER_VERTEX
) {
251 num_driver_params
= IR3_DP_VS_COUNT
;
252 } else if (so
->type
== SHADER_COMPUTE
) {
253 num_driver_params
= IR3_DP_CS_COUNT
;
256 so
->constbase
.driver_param
= constoff
;
257 constoff
+= align(num_driver_params
, 4) / 4;
259 if ((so
->type
== SHADER_VERTEX
) &&
260 (compiler
->gpu_id
< 500) &&
261 so
->shader
->stream_output
.num_outputs
> 0) {
262 so
->constbase
.tfbo
= constoff
;
263 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
266 so
->constbase
.immediate
= constoff
;
272 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
275 va_start(ap
, format
);
276 _debug_vprintf(format
, ap
);
278 nir_print_shader(ctx
->s
, stdout
);
283 #define compile_assert(ctx, cond) do { \
284 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
288 compile_free(struct ir3_context
*ctx
)
294 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
296 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
297 arr
->id
= ++ctx
->num_arrays
;
298 /* NOTE: sometimes we get non array regs, for example for arrays of
299 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
300 * treat a non-array as if it was an array of length 1.
302 * It would be nice if there was a nir pass to convert arrays of
305 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
306 compile_assert(ctx
, arr
->length
> 0);
308 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
311 static struct ir3_array
*
312 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
314 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
318 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
322 /* relative (indirect) if address!=NULL */
323 static struct ir3_instruction
*
324 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
325 struct ir3_instruction
*address
)
327 struct ir3_block
*block
= ctx
->block
;
328 struct ir3_instruction
*mov
;
329 struct ir3_register
*src
;
331 mov
= ir3_instr_create(block
, OPC_MOV
);
332 mov
->cat1
.src_type
= TYPE_U32
;
333 mov
->cat1
.dst_type
= TYPE_U32
;
334 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
335 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
336 ir3_reg_create(mov
, 0, 0);
337 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
338 COND(address
, IR3_REG_RELATIV
));
339 src
->instr
= arr
->last_write
;
340 src
->size
= arr
->length
;
341 src
->array
.id
= arr
->id
;
342 src
->array
.offset
= n
;
345 ir3_instr_set_address(mov
, address
);
350 /* relative (indirect) if address!=NULL */
351 static struct ir3_instruction
*
352 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
353 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
355 struct ir3_block
*block
= ctx
->block
;
356 struct ir3_instruction
*mov
;
357 struct ir3_register
*dst
;
359 mov
= ir3_instr_create(block
, OPC_MOV
);
360 mov
->cat1
.src_type
= TYPE_U32
;
361 mov
->cat1
.dst_type
= TYPE_U32
;
362 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
363 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
364 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
365 COND(address
, IR3_REG_RELATIV
));
366 dst
->instr
= arr
->last_write
;
367 dst
->size
= arr
->length
;
368 dst
->array
.id
= arr
->id
;
369 dst
->array
.offset
= n
;
370 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
373 ir3_instr_set_address(mov
, address
);
375 arr
->last_write
= mov
;
377 /* the array store may only matter to something in an earlier
378 * block (ie. loops), but since arrays are not in SSA, depth
379 * pass won't know this.. so keep all array stores:
381 array_insert(block
, block
->keeps
, mov
);
386 /* allocate a n element value array (to be populated by caller) and
389 static struct ir3_instruction
**
390 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
392 struct ir3_instruction
**value
=
393 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
394 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
398 static struct ir3_instruction
**
399 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
401 struct ir3_instruction
**value
;
404 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
406 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
409 /* NOTE: in non-ssa case, we don't really need to store last_dst
410 * but this helps us catch cases where put_dst() call is forgotten
412 compile_assert(ctx
, !ctx
->last_dst
);
413 ctx
->last_dst
= value
;
419 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
421 static struct ir3_instruction
* const *
422 get_src(struct ir3_context
*ctx
, nir_src
*src
)
425 struct hash_entry
*entry
;
426 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
427 compile_assert(ctx
, entry
);
430 nir_register
*reg
= src
->reg
.reg
;
431 struct ir3_array
*arr
= get_array(ctx
, reg
);
432 unsigned num_components
= arr
->r
->num_components
;
433 struct ir3_instruction
*addr
= NULL
;
434 struct ir3_instruction
**value
=
435 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
437 if (src
->reg
.indirect
)
438 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
439 reg
->num_components
);
441 for (unsigned i
= 0; i
< num_components
; i
++) {
442 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
443 compile_assert(ctx
, n
< arr
->length
);
444 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
452 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
455 nir_register
*reg
= dst
->reg
.reg
;
456 struct ir3_array
*arr
= get_array(ctx
, reg
);
457 unsigned num_components
= ctx
->last_dst_n
;
458 struct ir3_instruction
*addr
= NULL
;
460 if (dst
->reg
.indirect
)
461 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
462 reg
->num_components
);
464 for (unsigned i
= 0; i
< num_components
; i
++) {
465 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
466 compile_assert(ctx
, n
< arr
->length
);
467 if (!ctx
->last_dst
[i
])
469 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
472 ralloc_free(ctx
->last_dst
);
474 ctx
->last_dst
= NULL
;
478 static struct ir3_instruction
*
479 create_immed(struct ir3_block
*block
, uint32_t val
)
481 struct ir3_instruction
*mov
;
483 mov
= ir3_instr_create(block
, OPC_MOV
);
484 mov
->cat1
.src_type
= TYPE_U32
;
485 mov
->cat1
.dst_type
= TYPE_U32
;
486 ir3_reg_create(mov
, 0, 0);
487 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
492 static struct ir3_instruction
*
493 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
495 struct ir3_instruction
*instr
, *immed
;
497 /* TODO in at least some cases, the backend could probably be
498 * made clever enough to propagate IR3_REG_HALF..
500 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
501 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
508 /* src *= 2 => src <<= 1: */
509 immed
= create_immed(block
, 1);
510 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
512 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
513 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
514 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
518 immed
= create_immed(block
, 3);
519 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
521 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
522 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
523 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
526 /* src *= 4 => src <<= 2: */
527 immed
= create_immed(block
, 2);
528 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
530 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
531 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
532 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
535 unreachable("bad align");
539 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
540 instr
->regs
[0]->num
= regid(REG_A0
, 0);
541 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
542 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
547 /* caches addr values to avoid generating multiple cov/shl/mova
548 * sequences for each use of a given NIR level src as address
550 static struct ir3_instruction
*
551 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
553 struct ir3_instruction
*addr
;
554 unsigned idx
= align
- 1;
556 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
558 if (!ctx
->addr_ht
[idx
]) {
559 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
560 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
562 struct hash_entry
*entry
;
563 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
568 addr
= create_addr(ctx
->block
, src
, align
);
569 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
574 static struct ir3_instruction
*
575 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
577 struct ir3_block
*b
= ctx
->block
;
578 struct ir3_instruction
*cond
;
580 /* NOTE: only cmps.*.* can write p0.x: */
581 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
582 cond
->cat2
.condition
= IR3_COND_NE
;
584 /* condition always goes in predicate register: */
585 cond
->regs
[0]->num
= regid(REG_P0
, 0);
590 static struct ir3_instruction
*
591 create_uniform(struct ir3_context
*ctx
, unsigned n
)
593 struct ir3_instruction
*mov
;
595 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
596 /* TODO get types right? */
597 mov
->cat1
.src_type
= TYPE_F32
;
598 mov
->cat1
.dst_type
= TYPE_F32
;
599 ir3_reg_create(mov
, 0, 0);
600 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
605 static struct ir3_instruction
*
606 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
607 struct ir3_instruction
*address
)
609 struct ir3_instruction
*mov
;
611 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
612 mov
->cat1
.src_type
= TYPE_U32
;
613 mov
->cat1
.dst_type
= TYPE_U32
;
614 ir3_reg_create(mov
, 0, 0);
615 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
617 ir3_instr_set_address(mov
, address
);
622 static struct ir3_instruction
*
623 create_collect(struct ir3_block
*block
, struct ir3_instruction
*const *arr
,
626 struct ir3_instruction
*collect
;
631 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
632 ir3_reg_create(collect
, 0, 0); /* dst */
633 for (unsigned i
= 0; i
< arrsz
; i
++)
634 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
639 static struct ir3_instruction
*
640 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
641 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
643 struct ir3_block
*block
= ctx
->block
;
644 struct ir3_instruction
*mov
;
645 struct ir3_register
*src
;
647 mov
= ir3_instr_create(block
, OPC_MOV
);
648 mov
->cat1
.src_type
= TYPE_U32
;
649 mov
->cat1
.dst_type
= TYPE_U32
;
650 ir3_reg_create(mov
, 0, 0);
651 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
652 src
->instr
= collect
;
654 src
->array
.offset
= n
;
656 ir3_instr_set_address(mov
, address
);
661 static struct ir3_instruction
*
662 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
664 struct ir3_instruction
*in
;
666 in
= ir3_instr_create(block
, OPC_META_INPUT
);
667 in
->inout
.block
= block
;
668 ir3_reg_create(in
, n
, 0);
670 in
->regs
[0]->wrmask
= compmask
;
675 static struct ir3_instruction
*
676 create_input(struct ir3_block
*block
, unsigned n
)
678 return create_input_compmask(block
, n
, 0x1);
681 static struct ir3_instruction
*
682 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
684 struct ir3_block
*block
= ctx
->block
;
685 struct ir3_instruction
*instr
;
686 /* actual inloc is assigned and fixed up later: */
687 struct ir3_instruction
*inloc
= create_immed(block
, 0);
690 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
691 instr
->cat6
.type
= TYPE_U32
;
692 instr
->cat6
.iim_val
= 1;
694 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
695 instr
->regs
[2]->wrmask
= 0x3;
701 static struct ir3_instruction
*
702 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
704 struct ir3_block
*block
= ctx
->block
;
705 struct ir3_instruction
*instr
;
707 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
709 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
714 /* for frag_coord, we get unsigned values.. we need
715 * to subtract (integer) 8 and divide by 16 (right-
716 * shift by 4) then convert to float:
720 * mov.u32f32 dst, tmp
723 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
724 create_immed(block
, 8), 0);
725 instr
= ir3_SHR_B(block
, instr
, 0,
726 create_immed(block
, 4), 0);
727 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
733 /* seems that we can use these as-is: */
734 return ctx
->frag_coord
[comp
];
738 static struct ir3_instruction
*
739 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
741 /* first four vec4 sysval's reserved for UBOs: */
742 /* NOTE: dp is in scalar, but there can be >4 dp components: */
743 unsigned n
= ctx
->so
->constbase
.driver_param
;
744 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
745 return create_uniform(ctx
, r
);
748 /* helper for instructions that produce multiple consecutive scalar
749 * outputs which need to have a split/fanout meta instruction inserted
752 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
753 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
755 struct ir3_instruction
*prev
= NULL
;
757 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
762 for (int i
= 0, j
= 0; i
< n
; i
++) {
763 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
764 ir3_reg_create(split
, 0, IR3_REG_SSA
);
765 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
766 split
->fo
.off
= i
+ base
;
769 split
->cp
.left
= prev
;
770 split
->cp
.left_cnt
++;
771 prev
->cp
.right
= split
;
772 prev
->cp
.right_cnt
++;
776 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
782 * Adreno uses uint rather than having dedicated bool type,
783 * which (potentially) requires some conversion, in particular
784 * when using output of an bool instr to int input, or visa
788 * -------+---------+-------+-
792 * To convert from an adreno bool (uint) to nir, use:
794 * absneg.s dst, (neg)src
796 * To convert back in the other direction:
798 * absneg.s dst, (abs)arc
800 * The CP step can clean up the absneg.s that cancel each other
801 * out, and with a slight bit of extra cleverness (to recognize
802 * the instructions which produce either a 0 or 1) can eliminate
803 * the absneg.s's completely when an instruction that wants
804 * 0/1 consumes the result. For example, when a nir 'bcsel'
805 * consumes the result of 'feq'. So we should be able to get by
806 * without a boolean resolve step, and without incuring any
807 * extra penalty in instruction count.
810 /* NIR bool -> native (adreno): */
811 static struct ir3_instruction
*
812 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
814 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
817 /* native (adreno) -> NIR bool: */
818 static struct ir3_instruction
*
819 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
821 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
825 * alu/sfu instructions:
829 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
831 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
832 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
833 struct ir3_block
*b
= ctx
->block
;
834 unsigned dst_sz
, wrmask
;
836 if (alu
->dest
.dest
.is_ssa
) {
837 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
838 wrmask
= (1 << dst_sz
) - 1;
840 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
841 wrmask
= alu
->dest
.write_mask
;
844 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
846 /* Vectors are special in that they have non-scalarized writemasks,
847 * and just take the first swizzle channel for each argument in
848 * order into each writemask channel.
850 if ((alu
->op
== nir_op_vec2
) ||
851 (alu
->op
== nir_op_vec3
) ||
852 (alu
->op
== nir_op_vec4
)) {
854 for (int i
= 0; i
< info
->num_inputs
; i
++) {
855 nir_alu_src
*asrc
= &alu
->src
[i
];
857 compile_assert(ctx
, !asrc
->abs
);
858 compile_assert(ctx
, !asrc
->negate
);
860 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
862 src
[i
] = create_immed(ctx
->block
, 0);
863 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
866 put_dst(ctx
, &alu
->dest
.dest
);
870 /* We also get mov's with more than one component for mov's so
871 * handle those specially:
873 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
874 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
875 nir_alu_src
*asrc
= &alu
->src
[0];
876 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
878 for (unsigned i
= 0; i
< dst_sz
; i
++) {
879 if (wrmask
& (1 << i
)) {
880 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
886 put_dst(ctx
, &alu
->dest
.dest
);
890 compile_assert(ctx
, alu
->dest
.dest
.is_ssa
);
892 /* General case: We can just grab the one used channel per src. */
893 for (int i
= 0; i
< info
->num_inputs
; i
++) {
894 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
895 nir_alu_src
*asrc
= &alu
->src
[i
];
897 compile_assert(ctx
, !asrc
->abs
);
898 compile_assert(ctx
, !asrc
->negate
);
900 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
902 compile_assert(ctx
, src
[i
]);
907 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
910 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
913 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
916 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
919 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
920 dst
[0]->cat2
.condition
= IR3_COND_NE
;
921 dst
[0] = ir3_n2b(b
, dst
[0]);
924 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
927 dst
[0] = ir3_b2n(b
, src
[0]);
930 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
931 dst
[0]->cat2
.condition
= IR3_COND_NE
;
932 dst
[0] = ir3_n2b(b
, dst
[0]);
936 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
939 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
942 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
945 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
948 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
951 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
954 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
957 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
960 dst
[0] = ir3_DSX(b
, src
[0], 0);
961 dst
[0]->cat5
.type
= TYPE_F32
;
964 dst
[0] = ir3_DSY(b
, src
[0], 0);
965 dst
[0]->cat5
.type
= TYPE_F32
;
969 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
970 dst
[0]->cat2
.condition
= IR3_COND_LT
;
971 dst
[0] = ir3_n2b(b
, dst
[0]);
974 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
975 dst
[0]->cat2
.condition
= IR3_COND_GE
;
976 dst
[0] = ir3_n2b(b
, dst
[0]);
979 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
980 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
981 dst
[0] = ir3_n2b(b
, dst
[0]);
984 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
985 dst
[0]->cat2
.condition
= IR3_COND_NE
;
986 dst
[0] = ir3_n2b(b
, dst
[0]);
989 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
992 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
995 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
997 case nir_op_fround_even
:
998 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1001 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1005 dst
[0] = ir3_SIN(b
, src
[0], 0);
1008 dst
[0] = ir3_COS(b
, src
[0], 0);
1011 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1014 dst
[0] = ir3_RCP(b
, src
[0], 0);
1017 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1020 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1023 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1027 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1030 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1033 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1036 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1039 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1042 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1045 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1049 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1050 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1051 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1052 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1054 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1055 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1056 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1059 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1062 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1065 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1068 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1071 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1073 case nir_op_isign
: {
1074 /* maybe this would be sane to lower in nir.. */
1075 struct ir3_instruction
*neg
, *pos
;
1077 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1078 neg
->cat2
.condition
= IR3_COND_LT
;
1080 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1081 pos
->cat2
.condition
= IR3_COND_GT
;
1083 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1088 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1094 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1097 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1098 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1099 dst
[0] = ir3_n2b(b
, dst
[0]);
1102 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1103 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1104 dst
[0] = ir3_n2b(b
, dst
[0]);
1107 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1108 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1109 dst
[0] = ir3_n2b(b
, dst
[0]);
1112 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1113 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1114 dst
[0] = ir3_n2b(b
, dst
[0]);
1117 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1118 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1119 dst
[0] = ir3_n2b(b
, dst
[0]);
1122 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1123 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1124 dst
[0] = ir3_n2b(b
, dst
[0]);
1128 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1131 case nir_op_bit_count
:
1132 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1134 case nir_op_ifind_msb
: {
1135 struct ir3_instruction
*cmp
;
1136 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1137 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1138 cmp
->cat2
.condition
= IR3_COND_GE
;
1139 dst
[0] = ir3_SEL_B32(b
,
1140 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1144 case nir_op_ufind_msb
:
1145 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1146 dst
[0] = ir3_SEL_B32(b
,
1147 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1148 src
[0], 0, dst
[0], 0);
1150 case nir_op_find_lsb
:
1151 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1152 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1154 case nir_op_bitfield_reverse
:
1155 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1159 compile_error(ctx
, "Unhandled ALU op: %s\n",
1160 nir_op_infos
[alu
->op
].name
);
1164 put_dst(ctx
, &alu
->dest
.dest
);
1167 /* handles direct/indirect UBO reads: */
1169 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1170 struct ir3_instruction
**dst
)
1172 struct ir3_block
*b
= ctx
->block
;
1173 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1174 nir_const_value
*const_offset
;
1175 /* UBO addresses are the first driver params: */
1176 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1177 const unsigned ptrsz
= pointer_size(ctx
);
1181 /* First src is ubo index, which could either be an immed or not: */
1182 src0
= get_src(ctx
, &intr
->src
[0])[0];
1183 if (is_same_type_mov(src0
) &&
1184 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1185 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1186 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1188 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1189 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1192 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1195 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1197 off
+= const_offset
->u32
[0];
1199 /* For load_ubo_indirect, second src is indirect offset: */
1200 src1
= get_src(ctx
, &intr
->src
[1])[0];
1202 /* and add offset to addr: */
1203 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1206 /* if offset is to large to encode in the ldg, split it out: */
1207 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1208 /* split out the minimal amount to improve the odds that
1209 * cp can fit the immediate in the add.s instruction:
1211 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1212 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1217 struct ir3_instruction
*carry
;
1219 /* handle 32b rollover, ie:
1220 * if (addr < base_lo)
1223 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1224 carry
->cat2
.condition
= IR3_COND_LT
;
1225 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1227 addr
= create_collect(b
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1230 for (int i
= 0; i
< intr
->num_components
; i
++) {
1231 struct ir3_instruction
*load
=
1232 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1233 load
->cat6
.type
= TYPE_U32
;
1234 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1239 /* src[] = { buffer_index, offset }. No const_index */
1241 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1242 struct ir3_instruction
**dst
)
1244 struct ir3_block
*b
= ctx
->block
;
1245 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1246 nir_const_value
*const_offset
;
1248 /* can this be non-const buffer_index? how do we handle that? */
1249 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1250 compile_assert(ctx
, const_offset
);
1252 offset
= get_src(ctx
, &intr
->src
[1])[0];
1254 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1255 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1259 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1261 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1263 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1264 ldgb
->cat6
.iim_val
= intr
->num_components
;
1266 ldgb
->cat6
.type
= TYPE_U32
;
1267 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1268 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1270 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1273 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1275 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1277 struct ir3_block
*b
= ctx
->block
;
1278 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1279 nir_const_value
*const_offset
;
1280 /* TODO handle wrmask properly, see _store_shared().. but I think
1281 * it is more a PITA than that, since blob ends up loading the
1282 * masked components and writing them back out.
1284 unsigned wrmask
= intr
->const_index
[0];
1285 unsigned ncomp
= ffs(~wrmask
) - 1;
1287 /* can this be non-const buffer_index? how do we handle that? */
1288 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1289 compile_assert(ctx
, const_offset
);
1291 offset
= get_src(ctx
, &intr
->src
[2])[0];
1293 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1296 src0
= create_collect(b
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1297 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1298 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1303 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1304 src0
, 0, src1
, 0, src2
, 0);
1305 stgb
->cat6
.iim_val
= ncomp
;
1307 stgb
->cat6
.type
= TYPE_U32
;
1308 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1309 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1311 array_insert(b
, b
->keeps
, stgb
);
1314 /* src[] = { block_index } */
1316 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1317 struct ir3_instruction
**dst
)
1319 /* SSBO size stored as a const starting at ssbo_sizes: */
1320 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1321 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1322 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1324 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1326 dst
[0] = create_uniform(ctx
, idx
);
1330 * SSBO atomic intrinsics
1332 * All of the SSBO atomic memory operations read a value from memory,
1333 * compute a new value using one of the operations below, write the new
1334 * value to memory, and return the original value read.
1336 * All operations take 3 sources except CompSwap that takes 4. These
1337 * sources represent:
1339 * 0: The SSBO buffer index.
1340 * 1: The offset into the SSBO buffer of the variable that the atomic
1341 * operation will operate on.
1342 * 2: The data parameter to the atomic function (i.e. the value to add
1343 * in ssbo_atomic_add, etc).
1344 * 3: For CompSwap only: the second data parameter.
1346 static struct ir3_instruction
*
1347 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1349 struct ir3_block
*b
= ctx
->block
;
1350 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1351 nir_const_value
*const_offset
;
1352 type_t type
= TYPE_U32
;
1354 /* can this be non-const buffer_index? how do we handle that? */
1355 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1356 compile_assert(ctx
, const_offset
);
1357 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1359 offset
= get_src(ctx
, &intr
->src
[1])[0];
1361 /* src0 is data (or uvec2(data, compare))
1363 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1365 * Note that nir already multiplies the offset by four
1367 src0
= get_src(ctx
, &intr
->src
[2])[0];
1368 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1369 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1374 switch (intr
->intrinsic
) {
1375 case nir_intrinsic_ssbo_atomic_add
:
1376 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1378 case nir_intrinsic_ssbo_atomic_imin
:
1379 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1382 case nir_intrinsic_ssbo_atomic_umin
:
1383 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1385 case nir_intrinsic_ssbo_atomic_imax
:
1386 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1389 case nir_intrinsic_ssbo_atomic_umax
:
1390 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1392 case nir_intrinsic_ssbo_atomic_and
:
1393 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1395 case nir_intrinsic_ssbo_atomic_or
:
1396 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1398 case nir_intrinsic_ssbo_atomic_xor
:
1399 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1401 case nir_intrinsic_ssbo_atomic_exchange
:
1402 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1404 case nir_intrinsic_ssbo_atomic_comp_swap
:
1405 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1406 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1408 get_src(ctx
, &intr
->src
[3])[0],
1410 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1416 atomic
->cat6
.iim_val
= 1;
1418 atomic
->cat6
.type
= type
;
1419 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1420 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1422 /* even if nothing consume the result, we can't DCE the instruction: */
1423 array_insert(b
, b
->keeps
, atomic
);
1428 /* src[] = { offset }. const_index[] = { base } */
1430 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1431 struct ir3_instruction
**dst
)
1433 struct ir3_block
*b
= ctx
->block
;
1434 struct ir3_instruction
*ldl
, *offset
;
1437 offset
= get_src(ctx
, &intr
->src
[0])[0];
1438 base
= intr
->const_index
[0];
1440 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1441 ldl
->cat6
.src_offset
= base
;
1442 ldl
->cat6
.type
= TYPE_U32
;
1443 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1445 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1446 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1448 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1451 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1453 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1455 struct ir3_block
*b
= ctx
->block
;
1456 struct ir3_instruction
*stl
, *offset
;
1457 struct ir3_instruction
* const *value
;
1458 unsigned base
, wrmask
;
1460 value
= get_src(ctx
, &intr
->src
[0]);
1461 offset
= get_src(ctx
, &intr
->src
[1])[0];
1463 base
= intr
->const_index
[0];
1464 wrmask
= intr
->const_index
[1];
1466 /* Combine groups of consecutive enabled channels in one write
1467 * message. We use ffs to find the first enabled channel and then ffs on
1468 * the bit-inverse, down-shifted writemask to determine the length of
1469 * the block of enabled bits.
1471 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1474 unsigned first_component
= ffs(wrmask
) - 1;
1475 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1477 stl
= ir3_STL(b
, offset
, 0,
1478 create_collect(b
, &value
[first_component
], length
), 0,
1479 create_immed(b
, length
), 0);
1480 stl
->cat6
.dst_offset
= first_component
+ base
;
1481 stl
->cat6
.type
= TYPE_U32
;
1482 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1483 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1485 array_insert(b
, b
->keeps
, stl
);
1487 /* Clear the bits in the writemask that we just wrote, then try
1488 * again to see if more channels are left.
1490 wrmask
&= (15 << (first_component
+ length
));
1495 * CS shared variable atomic intrinsics
1497 * All of the shared variable atomic memory operations read a value from
1498 * memory, compute a new value using one of the operations below, write the
1499 * new value to memory, and return the original value read.
1501 * All operations take 2 sources except CompSwap that takes 3. These
1502 * sources represent:
1504 * 0: The offset into the shared variable storage region that the atomic
1505 * operation will operate on.
1506 * 1: The data parameter to the atomic function (i.e. the value to add
1507 * in shared_atomic_add, etc).
1508 * 2: For CompSwap only: the second data parameter.
1510 static struct ir3_instruction
*
1511 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1513 struct ir3_block
*b
= ctx
->block
;
1514 struct ir3_instruction
*atomic
, *src0
, *src1
;
1515 type_t type
= TYPE_U32
;
1517 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1518 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1520 switch (intr
->intrinsic
) {
1521 case nir_intrinsic_shared_atomic_add
:
1522 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1524 case nir_intrinsic_shared_atomic_imin
:
1525 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1528 case nir_intrinsic_shared_atomic_umin
:
1529 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1531 case nir_intrinsic_shared_atomic_imax
:
1532 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1535 case nir_intrinsic_shared_atomic_umax
:
1536 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1538 case nir_intrinsic_shared_atomic_and
:
1539 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1541 case nir_intrinsic_shared_atomic_or
:
1542 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1544 case nir_intrinsic_shared_atomic_xor
:
1545 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1547 case nir_intrinsic_shared_atomic_exchange
:
1548 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1550 case nir_intrinsic_shared_atomic_comp_swap
:
1551 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1552 src1
= create_collect(b
, (struct ir3_instruction
*[]){
1553 get_src(ctx
, &intr
->src
[2])[0],
1556 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1562 atomic
->cat6
.iim_val
= 1;
1564 atomic
->cat6
.type
= type
;
1565 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1566 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1568 /* even if nothing consume the result, we can't DCE the instruction: */
1569 array_insert(b
, b
->keeps
, atomic
);
1574 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1575 * state block (for load). To simplify things, invert the image id and
1576 * map it from end of state block, ie. image 0 becomes num-1, image 1
1577 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1578 * state when switching shaders.
1580 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1581 * coded. Also, since all the gl shader stages (ie. everything but CS)
1582 * share the same SSBO/image state block, this might require some more
1583 * logic if we supported images in anything other than FS..
1586 get_image_slot(struct ir3_context
*ctx
, const nir_variable
*var
)
1588 /* TODO figure out real limit per generation, and don't hardcode: */
1589 const unsigned max_samplers
= 16;
1590 return max_samplers
- var
->data
.driver_location
- 1;
1594 get_image_coords(const nir_variable
*var
)
1596 switch (glsl_get_sampler_dim(glsl_without_array(var
->type
))) {
1597 case GLSL_SAMPLER_DIM_1D
:
1598 case GLSL_SAMPLER_DIM_BUF
:
1601 case GLSL_SAMPLER_DIM_2D
:
1602 case GLSL_SAMPLER_DIM_RECT
:
1603 case GLSL_SAMPLER_DIM_EXTERNAL
:
1604 case GLSL_SAMPLER_DIM_MS
:
1606 case GLSL_SAMPLER_DIM_3D
:
1607 case GLSL_SAMPLER_DIM_CUBE
:
1610 unreachable("bad sampler dim");
1616 get_image_type(const nir_variable
*var
)
1618 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1619 case GLSL_TYPE_UINT
:
1623 case GLSL_TYPE_FLOAT
:
1626 unreachable("bad sampler type.");
1631 static struct ir3_instruction
*
1632 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1633 struct ir3_instruction
* const *coords
, bool byteoff
)
1635 struct ir3_block
*b
= ctx
->block
;
1636 struct ir3_instruction
*offset
;
1637 unsigned ncoords
= get_image_coords(var
);
1639 /* to calculate the byte offset (yes, uggg) we need (up to) three
1640 * const values to know the bytes per pixel, and y and z stride:
1642 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1643 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1645 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1646 (1 << var
->data
.driver_location
));
1648 /* offset = coords.x * bytes_per_pixel: */
1649 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1651 /* offset += coords.y * y_pitch: */
1652 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1653 coords
[1], 0, offset
, 0);
1656 /* offset += coords.z * z_pitch: */
1657 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1658 coords
[2], 0, offset
, 0);
1662 /* Some cases, like atomics, seem to use dword offset instead
1663 * of byte offsets.. blob just puts an extra shr.b in there
1666 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1669 return create_collect(b
, (struct ir3_instruction
*[]){
1675 /* src[] = { coord, sample_index }. const_index[] = {} */
1677 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1678 struct ir3_instruction
**dst
)
1680 struct ir3_block
*b
= ctx
->block
;
1681 const nir_variable
*var
= intr
->variables
[0]->var
;
1682 struct ir3_instruction
*sam
;
1683 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1684 unsigned ncoords
= get_image_coords(var
);
1685 unsigned tex_idx
= get_image_slot(ctx
, var
);
1686 type_t type
= get_image_type(var
);
1690 flags
|= IR3_INSTR_3D
;
1692 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1693 tex_idx
, tex_idx
, create_collect(b
, coords
, ncoords
), NULL
);
1695 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1696 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1698 split_dest(b
, dst
, sam
, 0, 4);
1701 /* src[] = { coord, sample_index, value }. const_index[] = {} */
1703 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1705 struct ir3_block
*b
= ctx
->block
;
1706 const nir_variable
*var
= intr
->variables
[0]->var
;
1707 struct ir3_instruction
*stib
, *offset
;
1708 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
1709 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1710 unsigned ncoords
= get_image_coords(var
);
1711 unsigned tex_idx
= get_image_slot(ctx
, var
);
1715 * src2 is 64b byte offset
1718 offset
= get_image_offset(ctx
, var
, coords
, true);
1720 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1721 * too and takes a dword offset.. not quite sure yet why blob uses
1722 * one over the other in various cases.
1725 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
1726 create_collect(b
, value
, 4), 0,
1727 create_collect(b
, coords
, ncoords
), 0,
1729 stib
->cat6
.iim_val
= 4;
1730 stib
->cat6
.d
= ncoords
;
1731 stib
->cat6
.type
= get_image_type(var
);
1732 stib
->cat6
.typed
= true;
1733 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1734 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1736 array_insert(b
, b
->keeps
, stib
);
1740 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1741 struct ir3_instruction
**dst
)
1743 struct ir3_block
*b
= ctx
->block
;
1744 const nir_variable
*var
= intr
->variables
[0]->var
;
1745 unsigned ncoords
= get_image_coords(var
);
1746 unsigned tex_idx
= get_image_slot(ctx
, var
);
1747 struct ir3_instruction
*sam
, *lod
;
1751 flags
= IR3_INSTR_3D
;
1753 lod
= create_immed(b
, 0);
1754 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1755 tex_idx
, tex_idx
, lod
, NULL
);
1757 split_dest(b
, dst
, sam
, 0, ncoords
);
1760 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
1761 static struct ir3_instruction
*
1762 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1764 struct ir3_block
*b
= ctx
->block
;
1765 const nir_variable
*var
= intr
->variables
[0]->var
;
1766 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
1767 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1768 unsigned ncoords
= get_image_coords(var
);
1770 image
= create_immed(b
, get_image_slot(ctx
, var
));
1772 /* src0 is value (or uvec2(value, compare))
1774 * src2 is 64b byte offset
1776 src0
= get_src(ctx
, &intr
->src
[2])[0];
1777 src1
= create_collect(b
, coords
, ncoords
);
1778 src2
= get_image_offset(ctx
, var
, coords
, false);
1780 switch (intr
->intrinsic
) {
1781 case nir_intrinsic_image_atomic_add
:
1782 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1784 case nir_intrinsic_image_atomic_min
:
1785 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1787 case nir_intrinsic_image_atomic_max
:
1788 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1790 case nir_intrinsic_image_atomic_and
:
1791 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1793 case nir_intrinsic_image_atomic_or
:
1794 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1796 case nir_intrinsic_image_atomic_xor
:
1797 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1799 case nir_intrinsic_image_atomic_exchange
:
1800 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1802 case nir_intrinsic_image_atomic_comp_swap
:
1803 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1804 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1806 get_src(ctx
, &intr
->src
[3])[0],
1808 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1814 atomic
->cat6
.iim_val
= 1;
1815 atomic
->cat6
.d
= ncoords
;
1816 atomic
->cat6
.type
= get_image_type(var
);
1817 atomic
->cat6
.typed
= true;
1818 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1819 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1821 /* even if nothing consume the result, we can't DCE the instruction: */
1822 array_insert(b
, b
->keeps
, atomic
);
1828 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1830 struct ir3_block
*b
= ctx
->block
;
1831 struct ir3_instruction
*barrier
;
1833 switch (intr
->intrinsic
) {
1834 case nir_intrinsic_barrier
:
1835 barrier
= ir3_BAR(b
);
1836 barrier
->cat7
.g
= true;
1837 barrier
->cat7
.l
= true;
1838 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1839 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1841 case nir_intrinsic_memory_barrier
:
1842 barrier
= ir3_FENCE(b
);
1843 barrier
->cat7
.g
= true;
1844 barrier
->cat7
.r
= true;
1845 barrier
->cat7
.w
= true;
1846 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1847 IR3_BARRIER_BUFFER_W
;
1848 barrier
->barrier_conflict
=
1849 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1850 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1852 case nir_intrinsic_memory_barrier_atomic_counter
:
1853 case nir_intrinsic_memory_barrier_buffer
:
1854 barrier
= ir3_FENCE(b
);
1855 barrier
->cat7
.g
= true;
1856 barrier
->cat7
.r
= true;
1857 barrier
->cat7
.w
= true;
1858 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1859 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1860 IR3_BARRIER_BUFFER_W
;
1862 case nir_intrinsic_memory_barrier_image
:
1863 // TODO double check if this should have .g set
1864 barrier
= ir3_FENCE(b
);
1865 barrier
->cat7
.g
= true;
1866 barrier
->cat7
.r
= true;
1867 barrier
->cat7
.w
= true;
1868 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1869 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1870 IR3_BARRIER_IMAGE_W
;
1872 case nir_intrinsic_memory_barrier_shared
:
1873 barrier
= ir3_FENCE(b
);
1874 barrier
->cat7
.g
= true;
1875 barrier
->cat7
.l
= true;
1876 barrier
->cat7
.r
= true;
1877 barrier
->cat7
.w
= true;
1878 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1879 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1880 IR3_BARRIER_SHARED_W
;
1882 case nir_intrinsic_group_memory_barrier
:
1883 barrier
= ir3_FENCE(b
);
1884 barrier
->cat7
.g
= true;
1885 barrier
->cat7
.l
= true;
1886 barrier
->cat7
.r
= true;
1887 barrier
->cat7
.w
= true;
1888 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1889 IR3_BARRIER_IMAGE_W
|
1890 IR3_BARRIER_BUFFER_W
;
1891 barrier
->barrier_conflict
=
1892 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1893 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1894 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1900 /* make sure barrier doesn't get DCE'd */
1901 array_insert(b
, b
->keeps
, barrier
);
1904 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1905 gl_system_value slot
, unsigned compmask
,
1906 struct ir3_instruction
*instr
)
1908 struct ir3_shader_variant
*so
= ctx
->so
;
1909 unsigned r
= regid(so
->inputs_count
, 0);
1910 unsigned n
= so
->inputs_count
++;
1912 so
->inputs
[n
].sysval
= true;
1913 so
->inputs
[n
].slot
= slot
;
1914 so
->inputs
[n
].compmask
= compmask
;
1915 so
->inputs
[n
].regid
= r
;
1916 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1919 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1920 ctx
->ir
->inputs
[r
] = instr
;
1923 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1924 struct ir3_instruction
*instr
)
1926 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1930 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1932 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1933 struct ir3_instruction
**dst
;
1934 struct ir3_instruction
* const *src
;
1935 struct ir3_block
*b
= ctx
->block
;
1936 nir_const_value
*const_offset
;
1939 if (info
->has_dest
) {
1941 if (info
->dest_components
)
1942 n
= info
->dest_components
;
1944 n
= intr
->num_components
;
1945 dst
= get_dst(ctx
, &intr
->dest
, n
);
1950 switch (intr
->intrinsic
) {
1951 case nir_intrinsic_load_uniform
:
1952 idx
= nir_intrinsic_base(intr
);
1953 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1955 idx
+= const_offset
->u32
[0];
1956 for (int i
= 0; i
< intr
->num_components
; i
++) {
1957 unsigned n
= idx
* 4 + i
;
1958 dst
[i
] = create_uniform(ctx
, n
);
1961 src
= get_src(ctx
, &intr
->src
[0]);
1962 for (int i
= 0; i
< intr
->num_components
; i
++) {
1963 int n
= idx
* 4 + i
;
1964 dst
[i
] = create_uniform_indirect(ctx
, n
,
1965 get_addr(ctx
, src
[0], 4));
1967 /* NOTE: if relative addressing is used, we set
1968 * constlen in the compiler (to worst-case value)
1969 * since we don't know in the assembler what the max
1970 * addr reg value can be:
1972 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1975 case nir_intrinsic_load_ubo
:
1976 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1978 case nir_intrinsic_load_input
:
1979 idx
= nir_intrinsic_base(intr
);
1980 comp
= nir_intrinsic_component(intr
);
1981 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1983 idx
+= const_offset
->u32
[0];
1984 for (int i
= 0; i
< intr
->num_components
; i
++) {
1985 unsigned n
= idx
* 4 + i
+ comp
;
1986 dst
[i
] = ctx
->ir
->inputs
[n
];
1989 src
= get_src(ctx
, &intr
->src
[0]);
1990 struct ir3_instruction
*collect
=
1991 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1992 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
1993 for (int i
= 0; i
< intr
->num_components
; i
++) {
1994 unsigned n
= idx
* 4 + i
+ comp
;
1995 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2000 case nir_intrinsic_load_ssbo
:
2001 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2003 case nir_intrinsic_store_ssbo
:
2004 emit_intrinsic_store_ssbo(ctx
, intr
);
2006 case nir_intrinsic_get_buffer_size
:
2007 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2009 case nir_intrinsic_ssbo_atomic_add
:
2010 case nir_intrinsic_ssbo_atomic_imin
:
2011 case nir_intrinsic_ssbo_atomic_umin
:
2012 case nir_intrinsic_ssbo_atomic_imax
:
2013 case nir_intrinsic_ssbo_atomic_umax
:
2014 case nir_intrinsic_ssbo_atomic_and
:
2015 case nir_intrinsic_ssbo_atomic_or
:
2016 case nir_intrinsic_ssbo_atomic_xor
:
2017 case nir_intrinsic_ssbo_atomic_exchange
:
2018 case nir_intrinsic_ssbo_atomic_comp_swap
:
2019 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2021 case nir_intrinsic_load_shared
:
2022 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2024 case nir_intrinsic_store_shared
:
2025 emit_intrinsic_store_shared(ctx
, intr
);
2027 case nir_intrinsic_shared_atomic_add
:
2028 case nir_intrinsic_shared_atomic_imin
:
2029 case nir_intrinsic_shared_atomic_umin
:
2030 case nir_intrinsic_shared_atomic_imax
:
2031 case nir_intrinsic_shared_atomic_umax
:
2032 case nir_intrinsic_shared_atomic_and
:
2033 case nir_intrinsic_shared_atomic_or
:
2034 case nir_intrinsic_shared_atomic_xor
:
2035 case nir_intrinsic_shared_atomic_exchange
:
2036 case nir_intrinsic_shared_atomic_comp_swap
:
2037 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2039 case nir_intrinsic_image_load
:
2040 emit_intrinsic_load_image(ctx
, intr
, dst
);
2042 case nir_intrinsic_image_store
:
2043 emit_intrinsic_store_image(ctx
, intr
);
2045 case nir_intrinsic_image_size
:
2046 emit_intrinsic_image_size(ctx
, intr
, dst
);
2048 case nir_intrinsic_image_atomic_add
:
2049 case nir_intrinsic_image_atomic_min
:
2050 case nir_intrinsic_image_atomic_max
:
2051 case nir_intrinsic_image_atomic_and
:
2052 case nir_intrinsic_image_atomic_or
:
2053 case nir_intrinsic_image_atomic_xor
:
2054 case nir_intrinsic_image_atomic_exchange
:
2055 case nir_intrinsic_image_atomic_comp_swap
:
2056 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2058 case nir_intrinsic_barrier
:
2059 case nir_intrinsic_memory_barrier
:
2060 case nir_intrinsic_group_memory_barrier
:
2061 case nir_intrinsic_memory_barrier_atomic_counter
:
2062 case nir_intrinsic_memory_barrier_buffer
:
2063 case nir_intrinsic_memory_barrier_image
:
2064 case nir_intrinsic_memory_barrier_shared
:
2065 emit_intrinsic_barrier(ctx
, intr
);
2066 /* note that blk ptr no longer valid, make that obvious: */
2069 case nir_intrinsic_store_output
:
2070 idx
= nir_intrinsic_base(intr
);
2071 comp
= nir_intrinsic_component(intr
);
2072 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2073 compile_assert(ctx
, const_offset
!= NULL
);
2074 idx
+= const_offset
->u32
[0];
2076 src
= get_src(ctx
, &intr
->src
[0]);
2077 for (int i
= 0; i
< intr
->num_components
; i
++) {
2078 unsigned n
= idx
* 4 + i
+ comp
;
2079 ctx
->ir
->outputs
[n
] = src
[i
];
2082 case nir_intrinsic_load_base_vertex
:
2083 if (!ctx
->basevertex
) {
2084 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2085 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
2088 dst
[0] = ctx
->basevertex
;
2090 case nir_intrinsic_load_vertex_id_zero_base
:
2091 case nir_intrinsic_load_vertex_id
:
2092 if (!ctx
->vertex_id
) {
2093 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2094 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2095 ctx
->vertex_id
= create_input(b
, 0);
2096 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2098 dst
[0] = ctx
->vertex_id
;
2100 case nir_intrinsic_load_instance_id
:
2101 if (!ctx
->instance_id
) {
2102 ctx
->instance_id
= create_input(b
, 0);
2103 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2106 dst
[0] = ctx
->instance_id
;
2108 case nir_intrinsic_load_user_clip_plane
:
2109 idx
= nir_intrinsic_ucp_id(intr
);
2110 for (int i
= 0; i
< intr
->num_components
; i
++) {
2111 unsigned n
= idx
* 4 + i
;
2112 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2115 case nir_intrinsic_load_front_face
:
2116 if (!ctx
->frag_face
) {
2117 ctx
->so
->frag_face
= true;
2118 ctx
->frag_face
= create_input(b
, 0);
2119 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2121 /* for fragface, we get -1 for back and 0 for front. However this is
2122 * the inverse of what nir expects (where ~0 is true).
2124 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2125 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2127 case nir_intrinsic_load_local_invocation_id
:
2128 if (!ctx
->local_invocation_id
) {
2129 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2130 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2131 0x7, ctx
->local_invocation_id
);
2133 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2135 case nir_intrinsic_load_work_group_id
:
2136 if (!ctx
->work_group_id
) {
2137 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2138 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2139 0x7, ctx
->work_group_id
);
2140 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2142 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2144 case nir_intrinsic_load_num_work_groups
:
2145 for (int i
= 0; i
< intr
->num_components
; i
++) {
2146 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2149 case nir_intrinsic_discard_if
:
2150 case nir_intrinsic_discard
: {
2151 struct ir3_instruction
*cond
, *kill
;
2153 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2154 /* conditional discard: */
2155 src
= get_src(ctx
, &intr
->src
[0]);
2156 cond
= ir3_b2n(b
, src
[0]);
2158 /* unconditional discard: */
2159 cond
= create_immed(b
, 1);
2162 /* NOTE: only cmps.*.* can write p0.x: */
2163 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2164 cond
->cat2
.condition
= IR3_COND_NE
;
2166 /* condition always goes in predicate register: */
2167 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2169 kill
= ir3_KILL(b
, cond
, 0);
2170 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2172 array_insert(b
, b
->keeps
, kill
);
2173 ctx
->so
->has_kill
= true;
2178 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2179 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2184 put_dst(ctx
, &intr
->dest
);
2188 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2190 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2191 instr
->def
.num_components
);
2192 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2193 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
2197 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2199 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2200 undef
->def
.num_components
);
2201 /* backend doesn't want undefined instructions, so just plug
2204 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2205 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
2209 * texture fetch/sample instructions:
2213 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2215 unsigned coords
, flags
= 0;
2217 /* note: would use tex->coord_components.. except txs.. also,
2218 * since array index goes after shadow ref, we don't want to
2221 switch (tex
->sampler_dim
) {
2222 case GLSL_SAMPLER_DIM_1D
:
2223 case GLSL_SAMPLER_DIM_BUF
:
2226 case GLSL_SAMPLER_DIM_2D
:
2227 case GLSL_SAMPLER_DIM_RECT
:
2228 case GLSL_SAMPLER_DIM_EXTERNAL
:
2229 case GLSL_SAMPLER_DIM_MS
:
2232 case GLSL_SAMPLER_DIM_3D
:
2233 case GLSL_SAMPLER_DIM_CUBE
:
2235 flags
|= IR3_INSTR_3D
;
2238 unreachable("bad sampler_dim");
2241 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2242 flags
|= IR3_INSTR_S
;
2244 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2245 flags
|= IR3_INSTR_A
;
2252 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2254 struct ir3_block
*b
= ctx
->block
;
2255 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2256 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2257 struct ir3_instruction
*lod
, *compare
, *proj
;
2258 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2259 unsigned i
, coords
, flags
;
2260 unsigned nsrc0
= 0, nsrc1
= 0;
2264 coord
= off
= ddx
= ddy
= NULL
;
2265 lod
= proj
= compare
= NULL
;
2267 /* TODO: might just be one component for gathers? */
2268 dst
= get_dst(ctx
, &tex
->dest
, 4);
2270 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2271 switch (tex
->src
[i
].src_type
) {
2272 case nir_tex_src_coord
:
2273 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2275 case nir_tex_src_bias
:
2276 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2279 case nir_tex_src_lod
:
2280 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2283 case nir_tex_src_comparator
: /* shadow comparator */
2284 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2286 case nir_tex_src_projector
:
2287 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2290 case nir_tex_src_offset
:
2291 off
= get_src(ctx
, &tex
->src
[i
].src
);
2294 case nir_tex_src_ddx
:
2295 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2297 case nir_tex_src_ddy
:
2298 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2301 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2302 tex
->src
[i
].src_type
);
2308 case nir_texop_tex
: opc
= OPC_SAM
; break;
2309 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2310 case nir_texop_txl
: opc
= OPC_SAML
; break;
2311 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2312 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2313 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2315 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2316 * what blob does, seems gather is broken?), and a3xx did
2317 * not support it (but probably could also emulate).
2319 switch (tex
->component
) {
2320 case 0: opc
= OPC_GATHER4R
; break;
2321 case 1: opc
= OPC_GATHER4G
; break;
2322 case 2: opc
= OPC_GATHER4B
; break;
2323 case 3: opc
= OPC_GATHER4A
; break;
2326 case nir_texop_txf_ms
:
2328 case nir_texop_query_levels
:
2329 case nir_texop_texture_samples
:
2330 case nir_texop_samples_identical
:
2331 case nir_texop_txf_ms_mcs
:
2332 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2336 tex_info(tex
, &flags
, &coords
);
2339 * lay out the first argument in the proper order:
2340 * - actual coordinates first
2341 * - shadow reference
2344 * - starting at offset 4, dpdx.xy, dpdy.xy
2346 * bias/lod go into the second arg
2349 /* insert tex coords: */
2350 for (i
= 0; i
< coords
; i
++)
2355 /* scale up integer coords for TXF based on the LOD */
2356 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2358 for (i
= 0; i
< coords
; i
++)
2359 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2363 /* hw doesn't do 1d, so we treat it as 2d with
2364 * height of 1, and patch up the y coord.
2365 * TODO: y coord should be (int)0 in some cases..
2367 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2370 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2371 src0
[nsrc0
++] = compare
;
2373 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2374 struct ir3_instruction
*idx
= coord
[coords
];
2376 /* the array coord for cube arrays needs 0.5 added to it */
2377 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2378 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2380 src0
[nsrc0
++] = idx
;
2384 src0
[nsrc0
++] = proj
;
2385 flags
|= IR3_INSTR_P
;
2388 /* pad to 4, then ddx/ddy: */
2389 if (tex
->op
== nir_texop_txd
) {
2391 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2392 for (i
= 0; i
< coords
; i
++)
2393 src0
[nsrc0
++] = ddx
[i
];
2395 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2396 for (i
= 0; i
< coords
; i
++)
2397 src0
[nsrc0
++] = ddy
[i
];
2399 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2403 * second argument (if applicable):
2408 if (has_off
| has_lod
| has_bias
) {
2410 unsigned off_coords
= coords
;
2411 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2413 for (i
= 0; i
< off_coords
; i
++)
2414 src1
[nsrc1
++] = off
[i
];
2416 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2417 flags
|= IR3_INSTR_O
;
2420 if (has_lod
| has_bias
)
2421 src1
[nsrc1
++] = lod
;
2424 switch (tex
->dest_type
) {
2425 case nir_type_invalid
:
2426 case nir_type_float
:
2437 unreachable("bad dest_type");
2440 if (opc
== OPC_GETLOD
)
2443 unsigned tex_idx
= tex
->texture_index
;
2445 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2447 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
2448 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
2450 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2451 tex_idx
, tex_idx
, col0
, col1
);
2453 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2454 /* only need first 3 components: */
2455 sam
->regs
[0]->wrmask
= 0x7;
2456 split_dest(b
, dst
, sam
, 0, 3);
2458 /* we need to sample the alpha separately with a non-ASTC
2461 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2462 tex_idx
, tex_idx
, col0
, col1
);
2464 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2466 /* fixup .w component: */
2467 split_dest(b
, &dst
[3], sam
, 3, 1);
2469 /* normal (non-workaround) case: */
2470 split_dest(b
, dst
, sam
, 0, 4);
2473 /* GETLOD returns results in 4.8 fixed point */
2474 if (opc
== OPC_GETLOD
) {
2475 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2477 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2478 for (i
= 0; i
< 2; i
++) {
2479 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2484 put_dst(ctx
, &tex
->dest
);
2488 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2490 struct ir3_block
*b
= ctx
->block
;
2491 struct ir3_instruction
**dst
, *sam
;
2493 dst
= get_dst(ctx
, &tex
->dest
, 1);
2495 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2496 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2498 /* even though there is only one component, since it ends
2499 * up in .z rather than .x, we need a split_dest()
2501 split_dest(b
, dst
, sam
, 0, 3);
2503 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2504 * the value in TEX_CONST_0 is zero-based.
2506 if (ctx
->levels_add_one
)
2507 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2509 put_dst(ctx
, &tex
->dest
);
2513 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2515 struct ir3_block
*b
= ctx
->block
;
2516 struct ir3_instruction
**dst
, *sam
;
2517 struct ir3_instruction
*lod
;
2518 unsigned flags
, coords
;
2520 tex_info(tex
, &flags
, &coords
);
2522 /* Actually we want the number of dimensions, not coordinates. This
2523 * distinction only matters for cubes.
2525 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2528 dst
= get_dst(ctx
, &tex
->dest
, 4);
2530 compile_assert(ctx
, tex
->num_srcs
== 1);
2531 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2533 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2535 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2536 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2538 split_dest(b
, dst
, sam
, 0, 4);
2540 /* Array size actually ends up in .w rather than .z. This doesn't
2541 * matter for miplevel 0, but for higher mips the value in z is
2542 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2543 * returned, which means that we have to add 1 to it for arrays.
2545 if (tex
->is_array
) {
2546 if (ctx
->levels_add_one
) {
2547 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2549 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2553 put_dst(ctx
, &tex
->dest
);
2557 emit_phi(struct ir3_context
*ctx
, nir_phi_instr
*nphi
)
2559 struct ir3_instruction
*phi
, **dst
;
2561 /* NOTE: phi's should be lowered to scalar at this point */
2562 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
2564 dst
= get_dst(ctx
, &nphi
->dest
, 1);
2566 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
2567 1 + exec_list_length(&nphi
->srcs
));
2568 ir3_reg_create(phi
, 0, 0); /* dst */
2569 phi
->phi
.nphi
= nphi
;
2573 put_dst(ctx
, &nphi
->dest
);
2576 /* phi instructions are left partially constructed. We don't resolve
2577 * their srcs until the end of the block, since (eg. loops) one of
2578 * the phi's srcs might be defined after the phi due to back edges in
2582 resolve_phis(struct ir3_context
*ctx
, struct ir3_block
*block
)
2584 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2585 nir_phi_instr
*nphi
;
2587 /* phi's only come at start of block: */
2588 if (instr
->opc
!= OPC_META_PHI
)
2591 if (!instr
->phi
.nphi
)
2594 nphi
= instr
->phi
.nphi
;
2595 instr
->phi
.nphi
= NULL
;
2597 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
2598 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
2600 /* NOTE: src might not be in the same block as it comes from
2601 * according to the phi.. but in the end the backend assumes
2602 * it will be able to assign the same register to each (which
2603 * only works if it is assigned in the src block), so insert
2604 * an extra mov to make sure the phi src is assigned in the
2605 * block it comes from:
2607 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
2609 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
2615 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2617 switch (jump
->type
) {
2618 case nir_jump_break
:
2619 case nir_jump_continue
:
2620 /* I *think* we can simply just ignore this, and use the
2621 * successor block link to figure out where we need to
2622 * jump to for break/continue
2626 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2632 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2634 switch (instr
->type
) {
2635 case nir_instr_type_alu
:
2636 emit_alu(ctx
, nir_instr_as_alu(instr
));
2638 case nir_instr_type_intrinsic
:
2639 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2641 case nir_instr_type_load_const
:
2642 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2644 case nir_instr_type_ssa_undef
:
2645 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2647 case nir_instr_type_tex
: {
2648 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2649 /* couple tex instructions get special-cased:
2653 emit_tex_txs(ctx
, tex
);
2655 case nir_texop_query_levels
:
2656 emit_tex_query_levels(ctx
, tex
);
2664 case nir_instr_type_phi
:
2665 emit_phi(ctx
, nir_instr_as_phi(instr
));
2667 case nir_instr_type_jump
:
2668 emit_jump(ctx
, nir_instr_as_jump(instr
));
2670 case nir_instr_type_call
:
2671 case nir_instr_type_parallel_copy
:
2672 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2677 static struct ir3_block
*
2678 get_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2680 struct ir3_block
*block
;
2681 struct hash_entry
*entry
;
2682 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2686 block
= ir3_block_create(ctx
->ir
);
2687 block
->nblock
= nblock
;
2688 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2694 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2696 struct ir3_block
*block
= get_block(ctx
, nblock
);
2698 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2699 if (nblock
->successors
[i
]) {
2700 block
->successors
[i
] =
2701 get_block(ctx
, nblock
->successors
[i
]);
2706 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2708 /* re-emit addr register in each block if needed: */
2709 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2710 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2711 ctx
->addr_ht
[i
] = NULL
;
2714 nir_foreach_instr(instr
, nblock
) {
2715 emit_instr(ctx
, instr
);
2721 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2724 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2726 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2728 ctx
->block
->condition
=
2729 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2731 emit_cf_list(ctx
, &nif
->then_list
);
2732 emit_cf_list(ctx
, &nif
->else_list
);
2736 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2738 emit_cf_list(ctx
, &nloop
->body
);
2742 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2744 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2745 switch (node
->type
) {
2746 case nir_cf_node_block
:
2747 emit_block(ctx
, nir_cf_node_as_block(node
));
2749 case nir_cf_node_if
:
2750 emit_if(ctx
, nir_cf_node_as_if(node
));
2752 case nir_cf_node_loop
:
2753 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2755 case nir_cf_node_function
:
2756 compile_error(ctx
, "TODO\n");
2762 /* emit stream-out code. At this point, the current block is the original
2763 * (nir) end block, and nir ensures that all flow control paths terminate
2764 * into the end block. We re-purpose the original end block to generate
2765 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2766 * block holding stream-out write instructions, followed by the new end
2770 * p0.x = (vtxcnt < maxvtxcnt)
2771 * // succs: blockStreamOut, blockNewEnd
2774 * ... stream-out instructions ...
2775 * // succs: blockNewEnd
2781 emit_stream_out(struct ir3_context
*ctx
)
2783 struct ir3_shader_variant
*v
= ctx
->so
;
2784 struct ir3
*ir
= ctx
->ir
;
2785 struct pipe_stream_output_info
*strmout
=
2786 &ctx
->so
->shader
->stream_output
;
2787 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2788 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2789 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2791 /* create vtxcnt input in input block at top of shader,
2792 * so that it is seen as live over the entire duration
2795 vtxcnt
= create_input(ctx
->in_block
, 0);
2796 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2798 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2800 /* at this point, we are at the original 'end' block,
2801 * re-purpose this block to stream-out condition, then
2802 * append stream-out block and new-end block
2804 orig_end_block
= ctx
->block
;
2806 stream_out_block
= ir3_block_create(ir
);
2807 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2809 new_end_block
= ir3_block_create(ir
);
2810 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2812 orig_end_block
->successors
[0] = stream_out_block
;
2813 orig_end_block
->successors
[1] = new_end_block
;
2814 stream_out_block
->successors
[0] = new_end_block
;
2816 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2817 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2818 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2819 cond
->cat2
.condition
= IR3_COND_LT
;
2821 /* condition goes on previous block to the conditional,
2822 * since it is used to pick which of the two successor
2825 orig_end_block
->condition
= cond
;
2827 /* switch to stream_out_block to generate the stream-out
2830 ctx
->block
= stream_out_block
;
2832 /* Calculate base addresses based on vtxcnt. Instructions
2833 * generated for bases not used in following loop will be
2834 * stripped out in the backend.
2836 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2837 unsigned stride
= strmout
->stride
[i
];
2838 struct ir3_instruction
*base
, *off
;
2840 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2842 /* 24-bit should be enough: */
2843 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2844 create_immed(ctx
->block
, stride
* 4), 0);
2846 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2849 /* Generate the per-output store instructions: */
2850 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2851 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2852 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2853 struct ir3_instruction
*base
, *out
, *stg
;
2855 base
= bases
[strmout
->output
[i
].output_buffer
];
2856 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2858 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2859 create_immed(ctx
->block
, 1), 0);
2860 stg
->cat6
.type
= TYPE_U32
;
2861 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2863 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2867 /* and finally switch to the new_end_block: */
2868 ctx
->block
= new_end_block
;
2872 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2874 nir_metadata_require(impl
, nir_metadata_block_index
);
2876 emit_cf_list(ctx
, &impl
->body
);
2877 emit_block(ctx
, impl
->end_block
);
2879 /* at this point, we should have a single empty block,
2880 * into which we emit the 'end' instruction.
2882 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2884 /* If stream-out (aka transform-feedback) enabled, emit the
2885 * stream-out instructions, followed by a new empty block (into
2886 * which the 'end' instruction lands).
2888 * NOTE: it is done in this order, rather than inserting before
2889 * we emit end_block, because NIR guarantees that all blocks
2890 * flow into end_block, and that end_block has no successors.
2891 * So by re-purposing end_block as the first block of stream-
2892 * out, we guarantee that all exit paths flow into the stream-
2895 if ((ctx
->compiler
->gpu_id
< 500) &&
2896 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2897 !ctx
->so
->key
.binning_pass
) {
2898 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2899 emit_stream_out(ctx
);
2902 ir3_END(ctx
->block
);
2906 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2908 struct ir3_shader_variant
*so
= ctx
->so
;
2909 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2910 unsigned ncomp
= glsl_get_components(in
->type
);
2911 unsigned n
= in
->data
.driver_location
;
2912 unsigned slot
= in
->data
.location
;
2914 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2915 slot
, array_len
, ncomp
, n
);
2917 /* let's pretend things other than vec4 don't exist: */
2918 ncomp
= MAX2(ncomp
, 4);
2919 compile_assert(ctx
, ncomp
== 4);
2921 so
->inputs
[n
].slot
= slot
;
2922 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2923 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2924 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2926 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2927 for (int i
= 0; i
< ncomp
; i
++) {
2928 struct ir3_instruction
*instr
= NULL
;
2929 unsigned idx
= (n
* 4) + i
;
2931 if (slot
== VARYING_SLOT_POS
) {
2932 so
->inputs
[n
].bary
= false;
2933 so
->frag_coord
= true;
2934 instr
= create_frag_coord(ctx
, i
);
2935 } else if (slot
== VARYING_SLOT_PNTC
) {
2936 /* see for example st_get_generic_varying_index().. this is
2937 * maybe a bit mesa/st specific. But we need things to line
2938 * up for this in fdN_program:
2939 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2940 * if (emit->sprite_coord_enable & texmask) {
2944 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2945 so
->inputs
[n
].bary
= true;
2946 instr
= create_frag_input(ctx
, false);
2948 bool use_ldlv
= false;
2950 /* detect the special case for front/back colors where
2951 * we need to do flat vs smooth shading depending on
2954 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2956 case VARYING_SLOT_COL0
:
2957 case VARYING_SLOT_COL1
:
2958 case VARYING_SLOT_BFC0
:
2959 case VARYING_SLOT_BFC1
:
2960 so
->inputs
[n
].rasterflat
= true;
2967 if (ctx
->flat_bypass
) {
2968 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2969 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2973 so
->inputs
[n
].bary
= true;
2975 instr
= create_frag_input(ctx
, use_ldlv
);
2978 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2980 ctx
->ir
->inputs
[idx
] = instr
;
2982 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2983 for (int i
= 0; i
< ncomp
; i
++) {
2984 unsigned idx
= (n
* 4) + i
;
2985 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2986 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2989 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2992 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2993 so
->total_in
+= ncomp
;
2998 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3000 struct ir3_shader_variant
*so
= ctx
->so
;
3001 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3002 unsigned ncomp
= glsl_get_components(out
->type
);
3003 unsigned n
= out
->data
.driver_location
;
3004 unsigned slot
= out
->data
.location
;
3007 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3008 slot
, array_len
, ncomp
, n
);
3010 /* let's pretend things other than vec4 don't exist: */
3011 ncomp
= MAX2(ncomp
, 4);
3012 compile_assert(ctx
, ncomp
== 4);
3014 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3016 case FRAG_RESULT_DEPTH
:
3017 comp
= 2; /* tgsi will write to .z component */
3018 so
->writes_pos
= true;
3020 case FRAG_RESULT_COLOR
:
3024 if (slot
>= FRAG_RESULT_DATA0
)
3026 compile_error(ctx
, "unknown FS output name: %s\n",
3027 gl_frag_result_name(slot
));
3029 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3031 case VARYING_SLOT_POS
:
3032 so
->writes_pos
= true;
3034 case VARYING_SLOT_PSIZ
:
3035 so
->writes_psize
= true;
3037 case VARYING_SLOT_COL0
:
3038 case VARYING_SLOT_COL1
:
3039 case VARYING_SLOT_BFC0
:
3040 case VARYING_SLOT_BFC1
:
3041 case VARYING_SLOT_FOGC
:
3042 case VARYING_SLOT_CLIP_DIST0
:
3043 case VARYING_SLOT_CLIP_DIST1
:
3044 case VARYING_SLOT_CLIP_VERTEX
:
3047 if (slot
>= VARYING_SLOT_VAR0
)
3049 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3051 compile_error(ctx
, "unknown VS output name: %s\n",
3052 gl_varying_slot_name(slot
));
3055 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3058 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3060 so
->outputs
[n
].slot
= slot
;
3061 so
->outputs
[n
].regid
= regid(n
, comp
);
3062 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3064 for (int i
= 0; i
< ncomp
; i
++) {
3065 unsigned idx
= (n
* 4) + i
;
3066 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3067 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3072 max_drvloc(struct exec_list
*vars
)
3075 nir_foreach_variable(var
, vars
) {
3076 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3081 static const unsigned max_sysvals
[SHADER_MAX
] = {
3082 [SHADER_VERTEX
] = 16,
3083 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3087 emit_instructions(struct ir3_context
*ctx
)
3089 unsigned ninputs
, noutputs
;
3090 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3092 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3093 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3095 /* we need to leave room for sysvals:
3097 ninputs
+= max_sysvals
[ctx
->so
->type
];
3099 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3101 /* Create inputs in first block: */
3102 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3103 ctx
->in_block
= ctx
->block
;
3104 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3106 ninputs
-= max_sysvals
[ctx
->so
->type
];
3108 /* for fragment shader, we have a single input register (usually
3109 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3111 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3112 // TODO maybe a helper for fi since we need it a few places..
3113 struct ir3_instruction
*instr
;
3114 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3115 ir3_reg_create(instr
, 0, 0);
3116 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3117 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3118 ctx
->frag_pos
= instr
;
3122 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3123 setup_input(ctx
, var
);
3126 /* Setup outputs: */
3127 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3128 setup_output(ctx
, var
);
3131 /* Setup registers (which should only be arrays): */
3132 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3133 declare_array(ctx
, reg
);
3136 /* NOTE: need to do something more clever when we support >1 fxn */
3137 nir_foreach_register(reg
, &fxn
->registers
) {
3138 declare_array(ctx
, reg
);
3140 /* And emit the body: */
3142 emit_function(ctx
, fxn
);
3144 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
3145 resolve_phis(ctx
, block
);
3149 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3150 * for a fragment shader are just bary.f instructions. The *actual* inputs
3151 * from the hw perspective are the frag_pos and optionally frag_coord and
3155 fixup_frag_inputs(struct ir3_context
*ctx
)
3157 struct ir3_shader_variant
*so
= ctx
->so
;
3158 struct ir3
*ir
= ctx
->ir
;
3159 struct ir3_instruction
**inputs
;
3160 struct ir3_instruction
*instr
;
3165 n
= 4; /* always have frag_pos */
3166 n
+= COND(so
->frag_face
, 4);
3167 n
+= COND(so
->frag_coord
, 4);
3169 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3171 if (so
->frag_face
) {
3172 /* this ultimately gets assigned to hr0.x so doesn't conflict
3173 * with frag_coord/frag_pos..
3175 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3176 ctx
->frag_face
->regs
[0]->num
= 0;
3178 /* remaining channels not used, but let's avoid confusing
3179 * other parts that expect inputs to come in groups of vec4
3181 inputs
[ir
->ninputs
++] = NULL
;
3182 inputs
[ir
->ninputs
++] = NULL
;
3183 inputs
[ir
->ninputs
++] = NULL
;
3186 /* since we don't know where to set the regid for frag_coord,
3187 * we have to use r0.x for it. But we don't want to *always*
3188 * use r1.x for frag_pos as that could increase the register
3189 * footprint on simple shaders:
3191 if (so
->frag_coord
) {
3192 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3193 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3194 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3195 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3197 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3198 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3199 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3200 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3203 /* we always have frag_pos: */
3204 so
->pos_regid
= regid
;
3207 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3208 instr
->regs
[0]->num
= regid
++;
3209 inputs
[ir
->ninputs
++] = instr
;
3210 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3213 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3214 instr
->regs
[0]->num
= regid
++;
3215 inputs
[ir
->ninputs
++] = instr
;
3216 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3218 ir
->inputs
= inputs
;
3221 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3222 * need to assign the tex state indexes for these after we know the
3226 fixup_astc_srgb(struct ir3_context
*ctx
)
3228 struct ir3_shader_variant
*so
= ctx
->so
;
3229 /* indexed by original tex idx, value is newly assigned alpha sampler
3230 * state tex idx. Zero is invalid since there is at least one sampler
3233 unsigned alt_tex_state
[16] = {0};
3234 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3237 so
->astc_srgb
.base
= tex_idx
;
3239 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3240 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3242 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3244 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3245 /* assign new alternate/alpha tex state slot: */
3246 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3247 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3248 so
->astc_srgb
.count
++;
3251 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3256 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3257 struct ir3_shader_variant
*so
)
3259 struct ir3_context
*ctx
;
3261 struct ir3_instruction
**inputs
;
3262 unsigned i
, j
, actual_in
, inloc
;
3263 int ret
= 0, max_bary
;
3267 ctx
= compile_init(compiler
, so
);
3269 DBG("INIT failed!");
3274 emit_instructions(ctx
);
3277 DBG("EMIT failed!");
3282 ir
= so
->ir
= ctx
->ir
;
3284 /* keep track of the inputs from TGSI perspective.. */
3285 inputs
= ir
->inputs
;
3287 /* but fixup actual inputs for frag shader: */
3288 if (so
->type
== SHADER_FRAGMENT
)
3289 fixup_frag_inputs(ctx
);
3291 /* at this point, for binning pass, throw away unneeded outputs: */
3292 if (so
->key
.binning_pass
) {
3293 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3294 unsigned slot
= so
->outputs
[i
].slot
;
3296 /* throw away everything but first position/psize */
3297 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3299 so
->outputs
[j
] = so
->outputs
[i
];
3300 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3301 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3302 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3303 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3308 so
->outputs_count
= j
;
3309 ir
->noutputs
= j
* 4;
3312 /* if we want half-precision outputs, mark the output registers
3315 if (so
->key
.half_precision
) {
3316 for (i
= 0; i
< ir
->noutputs
; i
++) {
3317 struct ir3_instruction
*out
= ir
->outputs
[i
];
3322 /* if frag shader writes z, that needs to be full precision: */
3323 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3326 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3327 /* output could be a fanout (ie. texture fetch output)
3328 * in which case we need to propagate the half-reg flag
3329 * up to the definer so that RA sees it:
3331 if (out
->opc
== OPC_META_FO
) {
3332 out
= out
->regs
[1]->instr
;
3333 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3336 if (out
->opc
== OPC_MOV
) {
3337 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3342 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3343 printf("BEFORE CP:\n");
3349 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3350 printf("BEFORE GROUPING:\n");
3354 ir3_sched_add_deps(ir
);
3356 /* Group left/right neighbors, inserting mov's where needed to
3361 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3362 printf("AFTER GROUPING:\n");
3368 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3369 printf("AFTER DEPTH:\n");
3373 ret
= ir3_sched(ir
);
3375 DBG("SCHED failed!");
3379 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3380 printf("AFTER SCHED:\n");
3384 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3390 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3391 printf("AFTER RA:\n");
3395 /* fixup input/outputs: */
3396 for (i
= 0; i
< so
->outputs_count
; i
++) {
3397 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3400 /* Note that some or all channels of an input may be unused: */
3403 for (i
= 0; i
< so
->inputs_count
; i
++) {
3404 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3405 so
->inputs
[i
].ncomp
= 0;
3406 so
->inputs
[i
].inloc
= inloc
;
3407 for (j
= 0; j
< 4; j
++) {
3408 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3409 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3410 compmask
|= (1 << j
);
3411 regid
= in
->regs
[0]->num
- j
;
3413 so
->inputs
[i
].ncomp
++;
3414 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3416 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3417 in
->regs
[1]->iim_val
= inloc
+ j
;
3422 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3424 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3427 so
->inputs
[i
].compmask
= compmask
;
3429 so
->inputs
[i
].regid
= regid
;
3433 fixup_astc_srgb(ctx
);
3435 /* We need to do legalize after (for frag shader's) the "bary.f"
3436 * offsets (inloc) have been assigned.
3438 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3440 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3441 printf("AFTER LEGALIZE:\n");
3445 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3446 if (so
->type
== SHADER_VERTEX
)
3447 so
->total_in
= actual_in
;
3449 so
->total_in
= max_bary
+ 1;
3454 ir3_destroy(so
->ir
);