1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
41 #include "freedreno_util.h"
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
47 #include "instr-a3xx.h"
52 struct ir3_compiler
*compiler
;
54 const struct tgsi_token
*tokens
;
58 struct ir3_shader_variant
*so
;
60 struct ir3_block
*block
; /* the current block */
61 struct ir3_block
*in_block
; /* block created for shader inputs */
63 nir_function_impl
*impl
;
65 /* For fragment shaders, from the hw perspective the only
66 * actual input is r0.xy position register passed to bary.f.
67 * But TGSI doesn't know that, it still declares things as
68 * IN[] registers. So we do all the input tracking normally
69 * and fix things up after compile_instructions()
71 * NOTE that frag_pos is the hardware position (possibly it
72 * is actually an index or tag or some such.. it is *not*
73 * values that can be directly used for gl_FragCoord..)
75 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
77 /* For vertex shaders, keep track of the system values sources */
78 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
83 /* mapping from nir_variable to ir3_array: */
84 struct hash_table
*var_ht
;
87 /* a common pattern for indirect addressing is to request the
88 * same address register multiple times. To avoid generating
89 * duplicate instruction sequences (which our backend does not
90 * try to clean up, since that should be done as the NIR stage)
91 * we cache the address value generated for a given src value:
93 struct hash_table
*addr_ht
;
95 /* maps nir_block to ir3_block, mostly for the purposes of
96 * figuring out the blocks successors
98 struct hash_table
*block_ht
;
100 /* for calculating input/output positions/linkages: */
103 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
104 * so we need to use ldlv.u32 to load the varying directly:
108 /* on a3xx, we need to add one to # of array levels:
112 /* on a3xx, we need to scale up integer coords for isaml based
115 bool unminify_coords
;
117 /* for looking up which system value is which */
118 unsigned sysval_semantics
[8];
120 /* set if we encounter something we can't handle yet, so we
121 * can bail cleanly and fallback to TGSI compiler f/e
127 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
128 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
130 static struct nir_shader
*to_nir(const struct tgsi_token
*tokens
)
132 struct nir_shader_compiler_options options
= {
137 .lower_ffract
= true,
138 .native_integers
= true,
142 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
144 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
145 debug_printf("----------------------\n");
146 nir_print_shader(s
, stdout
);
147 debug_printf("----------------------\n");
150 nir_opt_global_to_local(s
);
151 nir_convert_to_ssa(s
);
153 nir_lower_load_const_to_scalar(s
);
158 nir_lower_vars_to_ssa(s
);
159 nir_lower_alu_to_scalar(s
);
160 nir_lower_phis_to_scalar(s
);
162 progress
|= nir_copy_prop(s
);
163 progress
|= nir_opt_dce(s
);
164 progress
|= nir_opt_cse(s
);
165 progress
|= ir3_nir_lower_if_else(s
);
166 progress
|= nir_opt_algebraic(s
);
167 progress
|= nir_opt_constant_folding(s
);
171 nir_remove_dead_variables(s
);
172 nir_validate_shader(s
);
174 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
175 debug_printf("----------------------\n");
176 nir_print_shader(s
, stdout
);
177 debug_printf("----------------------\n");
183 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
184 static const struct tgsi_token
*
185 lower_tgsi(struct ir3_compile
*ctx
, const struct tgsi_token
*tokens
,
186 struct ir3_shader_variant
*so
)
188 struct tgsi_shader_info info
;
189 struct tgsi_lowering_config lconfig
= {
190 .color_two_side
= so
->key
.color_two_side
,
194 case SHADER_FRAGMENT
:
196 lconfig
.saturate_s
= so
->key
.fsaturate_s
;
197 lconfig
.saturate_t
= so
->key
.fsaturate_t
;
198 lconfig
.saturate_r
= so
->key
.fsaturate_r
;
201 lconfig
.saturate_s
= so
->key
.vsaturate_s
;
202 lconfig
.saturate_t
= so
->key
.vsaturate_t
;
203 lconfig
.saturate_r
= so
->key
.vsaturate_r
;
207 if (ctx
->compiler
->gpu_id
>= 400) {
208 /* a4xx seems to have *no* sam.p */
209 lconfig
.lower_TXP
= ~0; /* lower all txp */
211 /* a3xx just needs to avoid sam.p for 3d tex */
212 lconfig
.lower_TXP
= (1 << TGSI_TEXTURE_3D
);
215 return tgsi_transform_lowering(&lconfig
, tokens
, &info
);
218 static struct ir3_compile
*
219 compile_init(struct ir3_compiler
*compiler
,
220 struct ir3_shader_variant
*so
,
221 const struct tgsi_token
*tokens
)
223 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
224 const struct tgsi_token
*lowered_tokens
;
226 if (compiler
->gpu_id
>= 400) {
227 /* need special handling for "flat" */
228 ctx
->flat_bypass
= true;
229 ctx
->levels_add_one
= false;
230 ctx
->unminify_coords
= false;
232 /* no special handling for "flat" */
233 ctx
->flat_bypass
= false;
234 ctx
->levels_add_one
= true;
235 ctx
->unminify_coords
= true;
238 ctx
->compiler
= compiler
;
242 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
243 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
244 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
245 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
246 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
247 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
248 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
249 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
251 lowered_tokens
= lower_tgsi(ctx
, tokens
, so
);
253 lowered_tokens
= tokens
;
254 ctx
->s
= to_nir(lowered_tokens
);
256 if (lowered_tokens
!= tokens
)
257 free((void *)lowered_tokens
);
259 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
261 /* Layout of constant registers:
263 * num_uniform * vec4 - user consts
264 * 4 * vec4 - UBO addresses
265 * if (vertex shader) {
266 * 1 * vec4 - driver params (IR3_DP_*)
267 * 1 * vec4 - stream-out addresses
270 * TODO this could be made more dynamic, to at least skip sections
271 * that we don't need..
274 /* reserve 4 (vec4) slots for ubo base addresses: */
275 so
->first_immediate
+= 4;
277 if (so
->type
== SHADER_VERTEX
) {
278 /* one (vec4) slot for driver params (see ir3_driver_param): */
279 so
->first_immediate
++;
280 /* one (vec4) slot for stream-output base addresses: */
281 so
->first_immediate
++;
288 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
291 va_start(ap
, format
);
292 _debug_vprintf(format
, ap
);
294 nir_print_shader(ctx
->s
, stdout
);
299 #define compile_assert(ctx, cond) do { \
300 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
304 compile_free(struct ir3_compile
*ctx
)
309 /* global per-array information: */
311 unsigned length
, aid
;
314 /* per-block array state: */
315 struct ir3_array_value
{
316 /* TODO drop length/aid, and just have ptr back to ir3_array */
317 unsigned length
, aid
;
318 /* initial array element values are phi's, other than for the
319 * entry block. The phi src's get added later in a resolve step
320 * after we have visited all the blocks, to account for back
323 struct ir3_instruction
**phis
;
324 /* current array element values (as block is processed). When
325 * the array phi's are resolved, it will contain the array state
326 * at exit of block, so successor blocks can use it to add their
329 struct ir3_instruction
*arr
[];
332 /* track array assignments per basic block. When an array is read
333 * outside of the same basic block, we can use NIR's dominance-frontier
334 * information to figure out where phi nodes are needed.
336 struct ir3_nir_block_data
{
338 /* indexed by array-id (aid): */
339 struct ir3_array_value
*arrs
[];
342 static struct ir3_nir_block_data
*
343 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
346 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
347 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
354 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
356 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
357 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
358 arr
->length
= length
;
359 arr
->aid
= ++ctx
->num_arrays
;
360 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
364 nir_block_pred(nir_block
*block
)
366 assert(block
->predecessors
->entries
< 2);
367 if (block
->predecessors
->entries
== 0)
369 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
372 static struct ir3_array_value
*
373 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
375 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
376 struct ir3_block
*block
= ctx
->block
;
377 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
378 struct ir3_array
*arr
= entry
->data
;
380 if (!bd
->arrs
[arr
->aid
]) {
381 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
382 (arr
->length
* sizeof(av
->arr
[0])));
383 struct ir3_array_value
*defn
= NULL
;
384 nir_block
*pred_block
;
386 av
->length
= arr
->length
;
389 /* For loops, we have to consider that we have not visited some
390 * of the blocks who should feed into the phi (ie. back-edges in
391 * the cfg).. for example:
394 * block { load_var; ... }
395 * if then block {} else block {}
396 * block { store_var; ... }
397 * if then block {} else block {}
401 * We can skip the phi if we can chase the block predecessors
402 * until finding the block previously defining the array without
403 * crossing a block that has more than one predecessor.
405 * Otherwise create phi's and resolve them as a post-pass after
406 * all the blocks have been visited (to handle back-edges).
409 for (pred_block
= block
->nblock
;
410 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
411 pred_block
= nir_block_pred(pred_block
)) {
412 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
413 struct ir3_nir_block_data
*pbd
= pblock
->bd
;
416 defn
= pbd
->arrs
[arr
->aid
];
420 /* only one possible definer: */
421 for (unsigned i
= 0; i
< arr
->length
; i
++)
422 av
->arr
[i
] = defn
->arr
[i
];
423 } else if (pred_block
) {
424 /* not the first block, and multiple potential definers: */
425 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
427 for (unsigned i
= 0; i
< arr
->length
; i
++) {
428 struct ir3_instruction
*phi
;
430 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
431 1 + ctx
->impl
->num_blocks
);
432 ir3_reg_create(phi
, 0, 0); /* dst */
434 /* phi's should go at head of block: */
435 list_delinit(&phi
->node
);
436 list_add(&phi
->node
, &block
->instr_list
);
438 av
->phis
[i
] = av
->arr
[i
] = phi
;
441 /* Some shaders end up reading array elements without
442 * first writing.. so initialize things to prevent null
445 for (unsigned i
= 0; i
< arr
->length
; i
++)
446 av
->arr
[i
] = create_immed(block
, 0);
449 bd
->arrs
[arr
->aid
] = av
;
452 return bd
->arrs
[arr
->aid
];
456 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
457 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
459 struct ir3_block
*block
;
460 struct ir3_nir_block_data
*bd
;
462 if (BITSET_TEST(visited
, nblock
->index
))
465 BITSET_SET(visited
, nblock
->index
);
467 block
= get_block(ctx
, nblock
);
470 if (bd
&& bd
->arrs
[av
->aid
]) {
471 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
472 for (unsigned i
= 0; i
< av
->length
; i
++) {
473 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
477 /* didn't find defn, recurse predecessors: */
478 struct set_entry
*entry
;
479 set_foreach(nblock
->predecessors
, entry
) {
480 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
486 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
488 struct ir3_nir_block_data
*bd
= block
->bd
;
489 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
494 /* TODO use nir dom_frontier to help us with this? */
496 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
497 struct ir3_array_value
*av
= bd
->arrs
[i
];
498 BITSET_WORD visited
[bitset_words
];
499 struct set_entry
*entry
;
501 if (!(av
&& av
->phis
))
504 memset(visited
, 0, sizeof(visited
));
505 set_foreach(block
->nblock
->predecessors
, entry
) {
506 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
511 /* allocate a n element value array (to be populated by caller) and
514 static struct ir3_instruction
**
515 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
517 struct ir3_instruction
**value
=
518 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
519 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
523 static struct ir3_instruction
**
524 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
527 return __get_dst(ctx
, &dst
->ssa
, n
);
529 return __get_dst(ctx
, dst
->reg
.reg
, n
);
533 static struct ir3_instruction
**
534 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
536 return __get_dst(ctx
, dst
, n
);
539 static struct ir3_instruction
**
540 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
542 struct hash_entry
*entry
;
544 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
546 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
548 compile_assert(ctx
, entry
);
552 static struct ir3_instruction
*
553 create_immed(struct ir3_block
*block
, uint32_t val
)
555 struct ir3_instruction
*mov
;
557 mov
= ir3_instr_create(block
, 1, 0);
558 mov
->cat1
.src_type
= TYPE_U32
;
559 mov
->cat1
.dst_type
= TYPE_U32
;
560 ir3_reg_create(mov
, 0, 0);
561 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
566 static struct ir3_instruction
*
567 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
569 struct ir3_instruction
*instr
, *immed
;
571 /* TODO in at least some cases, the backend could probably be
572 * made clever enough to propagate IR3_REG_HALF..
574 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
575 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
577 immed
= create_immed(block
, 2);
578 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
580 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
581 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
582 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
584 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
585 instr
->regs
[0]->num
= regid(REG_A0
, 0);
586 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
587 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
592 /* caches addr values to avoid generating multiple cov/shl/mova
593 * sequences for each use of a given NIR level src as address
595 static struct ir3_instruction
*
596 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
598 struct ir3_instruction
*addr
;
599 struct hash_entry
*entry
;
600 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
604 /* TODO do we need to cache per block? */
605 addr
= create_addr(ctx
->block
, src
);
606 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
611 static struct ir3_instruction
*
612 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
614 struct ir3_block
*b
= ctx
->block
;
615 struct ir3_instruction
*cond
;
617 /* NOTE: only cmps.*.* can write p0.x: */
618 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
619 cond
->cat2
.condition
= IR3_COND_NE
;
621 /* condition always goes in predicate register: */
622 cond
->regs
[0]->num
= regid(REG_P0
, 0);
627 static struct ir3_instruction
*
628 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
630 struct ir3_instruction
*mov
;
632 mov
= ir3_instr_create(ctx
->block
, 1, 0);
633 /* TODO get types right? */
634 mov
->cat1
.src_type
= TYPE_F32
;
635 mov
->cat1
.dst_type
= TYPE_F32
;
636 ir3_reg_create(mov
, 0, 0);
637 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
642 static struct ir3_instruction
*
643 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
644 struct ir3_instruction
*address
)
646 struct ir3_instruction
*mov
;
648 mov
= ir3_instr_create(ctx
->block
, 1, 0);
649 mov
->cat1
.src_type
= TYPE_U32
;
650 mov
->cat1
.dst_type
= TYPE_U32
;
651 ir3_reg_create(mov
, 0, 0);
652 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
654 ir3_instr_set_address(mov
, address
);
659 static struct ir3_instruction
*
660 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
663 struct ir3_instruction
*collect
;
668 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
669 ir3_reg_create(collect
, 0, 0); /* dst */
670 for (unsigned i
= 0; i
< arrsz
; i
++)
671 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
676 static struct ir3_instruction
*
677 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
678 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
680 struct ir3_block
*block
= ctx
->block
;
681 struct ir3_instruction
*mov
;
682 struct ir3_register
*src
;
684 mov
= ir3_instr_create(block
, 1, 0);
685 mov
->cat1
.src_type
= TYPE_U32
;
686 mov
->cat1
.dst_type
= TYPE_U32
;
687 ir3_reg_create(mov
, 0, 0);
688 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
689 src
->instr
= collect
;
693 ir3_instr_set_address(mov
, address
);
698 static struct ir3_instruction
*
699 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
700 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
701 struct ir3_instruction
*collect
)
703 struct ir3_block
*block
= ctx
->block
;
704 struct ir3_instruction
*mov
;
705 struct ir3_register
*dst
;
707 mov
= ir3_instr_create(block
, 1, 0);
708 mov
->cat1
.src_type
= TYPE_U32
;
709 mov
->cat1
.dst_type
= TYPE_U32
;
710 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
713 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
714 mov
->fanin
= collect
;
716 ir3_instr_set_address(mov
, address
);
721 static struct ir3_instruction
*
722 create_input(struct ir3_block
*block
, unsigned n
)
724 struct ir3_instruction
*in
;
726 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
727 in
->inout
.block
= block
;
728 ir3_reg_create(in
, n
, 0);
733 static struct ir3_instruction
*
734 create_frag_input(struct ir3_compile
*ctx
, unsigned n
, bool use_ldlv
)
736 struct ir3_block
*block
= ctx
->block
;
737 struct ir3_instruction
*instr
;
738 struct ir3_instruction
*inloc
= create_immed(block
, n
);
741 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
742 instr
->cat6
.type
= TYPE_U32
;
743 instr
->cat6
.iim_val
= 1;
745 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
746 instr
->regs
[2]->wrmask
= 0x3;
752 static struct ir3_instruction
*
753 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
755 struct ir3_block
*block
= ctx
->block
;
756 struct ir3_instruction
*instr
;
758 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
760 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
765 /* for frag_coord, we get unsigned values.. we need
766 * to subtract (integer) 8 and divide by 16 (right-
767 * shift by 4) then convert to float:
771 * mov.u32f32 dst, tmp
774 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
775 create_immed(block
, 8), 0);
776 instr
= ir3_SHR_B(block
, instr
, 0,
777 create_immed(block
, 4), 0);
778 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
784 /* seems that we can use these as-is: */
785 return ctx
->frag_coord
[comp
];
789 static struct ir3_instruction
*
790 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
792 struct ir3_block
*block
= ctx
->block
;
793 struct ir3_instruction
*instr
;
797 compile_assert(ctx
, !ctx
->frag_face
);
799 ctx
->frag_face
= create_input(block
, 0);
800 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
802 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
803 * positive vs negative float.. and piglit further seems to
804 * expect -1.0 or 1.0:
806 * mul.s tmp, hr0.x, 2
808 * mov.s32f32, dst, tmp
811 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
812 create_immed(block
, 2), 0);
813 instr
= ir3_ADD_S(block
, instr
, 0,
814 create_immed(block
, 1), 0);
815 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
820 return create_immed(block
, fui(0.0));
823 return create_immed(block
, fui(1.0));
827 static struct ir3_instruction
*
828 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
830 /* first four vec4 sysval's reserved for UBOs: */
831 unsigned r
= regid(ctx
->so
->first_driver_param
+ 4, dp
);
832 return create_uniform(ctx
, r
);
835 /* helper for instructions that produce multiple consecutive scalar
836 * outputs which need to have a split/fanout meta instruction inserted
839 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
840 struct ir3_instruction
*src
, unsigned n
)
842 struct ir3_instruction
*prev
= NULL
;
843 for (int i
= 0, j
= 0; i
< n
; i
++) {
844 struct ir3_instruction
*split
=
845 ir3_instr_create(block
, -1, OPC_META_FO
);
846 ir3_reg_create(split
, 0, IR3_REG_SSA
);
847 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
851 split
->cp
.left
= prev
;
852 split
->cp
.left_cnt
++;
853 prev
->cp
.right
= split
;
854 prev
->cp
.right_cnt
++;
858 if (src
->regs
[0]->wrmask
& (1 << i
))
864 * Adreno uses uint rather than having dedicated bool type,
865 * which (potentially) requires some conversion, in particular
866 * when using output of an bool instr to int input, or visa
870 * -------+---------+-------+-
874 * To convert from an adreno bool (uint) to nir, use:
876 * absneg.s dst, (neg)src
878 * To convert back in the other direction:
880 * absneg.s dst, (abs)arc
882 * The CP step can clean up the absneg.s that cancel each other
883 * out, and with a slight bit of extra cleverness (to recognize
884 * the instructions which produce either a 0 or 1) can eliminate
885 * the absneg.s's completely when an instruction that wants
886 * 0/1 consumes the result. For example, when a nir 'bcsel'
887 * consumes the result of 'feq'. So we should be able to get by
888 * without a boolean resolve step, and without incuring any
889 * extra penalty in instruction count.
892 /* NIR bool -> native (adreno): */
893 static struct ir3_instruction
*
894 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
896 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
899 /* native (adreno) -> NIR bool: */
900 static struct ir3_instruction
*
901 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
903 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
907 * alu/sfu instructions:
911 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
913 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
914 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
915 struct ir3_block
*b
= ctx
->block
;
917 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
919 /* Vectors are special in that they have non-scalarized writemasks,
920 * and just take the first swizzle channel for each argument in
921 * order into each writemask channel.
923 if ((alu
->op
== nir_op_vec2
) ||
924 (alu
->op
== nir_op_vec3
) ||
925 (alu
->op
== nir_op_vec4
)) {
927 for (int i
= 0; i
< info
->num_inputs
; i
++) {
928 nir_alu_src
*asrc
= &alu
->src
[i
];
930 compile_assert(ctx
, !asrc
->abs
);
931 compile_assert(ctx
, !asrc
->negate
);
933 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
935 src
[i
] = create_immed(ctx
->block
, 0);
936 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
942 /* General case: We can just grab the one used channel per src. */
943 for (int i
= 0; i
< info
->num_inputs
; i
++) {
944 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
945 nir_alu_src
*asrc
= &alu
->src
[i
];
947 compile_assert(ctx
, !asrc
->abs
);
948 compile_assert(ctx
, !asrc
->negate
);
950 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
952 compile_assert(ctx
, src
[i
]);
957 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
960 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
963 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
966 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
969 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
972 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
975 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
976 dst
[0]->cat2
.condition
= IR3_COND_NE
;
977 dst
[0] = ir3_n2b(b
, dst
[0]);
980 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
983 dst
[0] = ir3_b2n(b
, src
[0]);
986 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
987 dst
[0]->cat2
.condition
= IR3_COND_NE
;
988 dst
[0] = ir3_n2b(b
, dst
[0]);
992 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
995 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
998 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1001 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1004 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1007 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1010 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1013 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1016 dst
[0] = ir3_DSX(b
, src
[0], 0);
1017 dst
[0]->cat5
.type
= TYPE_F32
;
1020 dst
[0] = ir3_DSY(b
, src
[0], 0);
1021 dst
[0]->cat5
.type
= TYPE_F32
;
1025 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1026 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1027 dst
[0] = ir3_n2b(b
, dst
[0]);
1030 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1031 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1032 dst
[0] = ir3_n2b(b
, dst
[0]);
1035 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1036 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1037 dst
[0] = ir3_n2b(b
, dst
[0]);
1040 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1041 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1042 dst
[0] = ir3_n2b(b
, dst
[0]);
1045 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1048 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1051 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1053 case nir_op_fround_even
:
1054 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1057 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1061 dst
[0] = ir3_SIN(b
, src
[0], 0);
1064 dst
[0] = ir3_COS(b
, src
[0], 0);
1067 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1070 dst
[0] = ir3_RCP(b
, src
[0], 0);
1073 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1076 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1079 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1083 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1086 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1089 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1092 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1095 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1098 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1101 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1105 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1106 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1107 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1108 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1110 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1111 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1112 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1115 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1118 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1121 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1124 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1127 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1129 case nir_op_isign
: {
1130 /* maybe this would be sane to lower in nir.. */
1131 struct ir3_instruction
*neg
, *pos
;
1133 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1134 neg
->cat2
.condition
= IR3_COND_LT
;
1136 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1137 pos
->cat2
.condition
= IR3_COND_GT
;
1139 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1144 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1147 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1150 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1153 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1154 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1155 dst
[0] = ir3_n2b(b
, dst
[0]);
1158 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1159 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1160 dst
[0] = ir3_n2b(b
, dst
[0]);
1163 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1164 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1165 dst
[0] = ir3_n2b(b
, dst
[0]);
1168 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1169 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1170 dst
[0] = ir3_n2b(b
, dst
[0]);
1173 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1174 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1175 dst
[0] = ir3_n2b(b
, dst
[0]);
1178 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1179 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1180 dst
[0] = ir3_n2b(b
, dst
[0]);
1184 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1188 compile_error(ctx
, "Unhandled ALU op: %s\n",
1189 nir_op_infos
[alu
->op
].name
);
1194 /* handles direct/indirect UBO reads: */
1196 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1197 struct ir3_instruction
**dst
)
1199 struct ir3_block
*b
= ctx
->block
;
1200 struct ir3_instruction
*addr
, *src0
, *src1
;
1201 /* UBO addresses are the first driver params: */
1202 unsigned ubo
= regid(ctx
->so
->first_driver_param
, 0);
1203 unsigned off
= intr
->const_index
[0];
1205 /* First src is ubo index, which could either be an immed or not: */
1206 src0
= get_src(ctx
, &intr
->src
[0])[0];
1207 if (is_same_type_mov(src0
) &&
1208 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1209 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1211 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1214 if (intr
->intrinsic
== nir_intrinsic_load_ubo_indirect
) {
1215 /* For load_ubo_indirect, second src is indirect offset: */
1216 src1
= get_src(ctx
, &intr
->src
[1])[0];
1218 /* and add offset to addr: */
1219 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1222 /* if offset is to large to encode in the ldg, split it out: */
1223 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1224 /* split out the minimal amount to improve the odds that
1225 * cp can fit the immediate in the add.s instruction:
1227 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1228 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1232 for (int i
= 0; i
< intr
->num_components
; i
++) {
1233 struct ir3_instruction
*load
=
1234 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1235 load
->cat6
.type
= TYPE_U32
;
1236 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1241 /* handles array reads: */
1243 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1244 struct ir3_instruction
**dst
)
1246 nir_deref_var
*dvar
= intr
->variables
[0];
1247 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1248 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1250 compile_assert(ctx
, dvar
->deref
.child
&&
1251 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1253 switch (darr
->deref_array_type
) {
1254 case nir_deref_array_type_direct
:
1255 /* direct access does not require anything special: */
1256 for (int i
= 0; i
< intr
->num_components
; i
++) {
1257 unsigned n
= darr
->base_offset
* 4 + i
;
1258 compile_assert(ctx
, n
< arr
->length
);
1259 dst
[i
] = arr
->arr
[n
];
1262 case nir_deref_array_type_indirect
: {
1263 /* for indirect, we need to collect all the array elements: */
1264 struct ir3_instruction
*collect
=
1265 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1266 struct ir3_instruction
*addr
=
1267 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1268 for (int i
= 0; i
< intr
->num_components
; i
++) {
1269 unsigned n
= darr
->base_offset
* 4 + i
;
1270 compile_assert(ctx
, n
< arr
->length
);
1271 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1276 compile_error(ctx
, "Unhandled load deref type: %u\n",
1277 darr
->deref_array_type
);
1282 /* handles array writes: */
1284 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1286 nir_deref_var
*dvar
= intr
->variables
[0];
1287 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1288 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1289 struct ir3_instruction
**src
;
1291 compile_assert(ctx
, dvar
->deref
.child
&&
1292 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1294 src
= get_src(ctx
, &intr
->src
[0]);
1296 switch (darr
->deref_array_type
) {
1297 case nir_deref_array_type_direct
:
1298 /* direct access does not require anything special: */
1299 for (int i
= 0; i
< intr
->num_components
; i
++) {
1300 unsigned n
= darr
->base_offset
* 4 + i
;
1301 compile_assert(ctx
, n
< arr
->length
);
1302 arr
->arr
[n
] = src
[i
];
1305 case nir_deref_array_type_indirect
: {
1306 /* for indirect, create indirect-store and fan that out: */
1307 struct ir3_instruction
*collect
=
1308 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1309 struct ir3_instruction
*addr
=
1310 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1311 for (int i
= 0; i
< intr
->num_components
; i
++) {
1312 struct ir3_instruction
*store
;
1313 unsigned n
= darr
->base_offset
* 4 + i
;
1314 compile_assert(ctx
, n
< arr
->length
);
1316 store
= create_indirect_store(ctx
, arr
->length
,
1317 n
, src
[i
], addr
, collect
);
1319 store
->fanin
->fi
.aid
= arr
->aid
;
1321 /* TODO: probably split this out to be used for
1322 * store_output_indirect? or move this into
1323 * create_indirect_store()?
1325 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1326 struct ir3_instruction
*split
;
1328 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1330 ir3_reg_create(split
, 0, 0);
1331 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1333 arr
->arr
[j
] = split
;
1336 /* fixup fanout/split neighbors: */
1337 for (int i
= 0; i
< arr
->length
; i
++) {
1338 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1339 arr
->arr
[i
+1] : NULL
;
1340 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1341 arr
->arr
[i
-1] : NULL
;
1346 compile_error(ctx
, "Unhandled store deref type: %u\n",
1347 darr
->deref_array_type
);
1352 static void add_sysval_input(struct ir3_compile
*ctx
, unsigned name
,
1353 struct ir3_instruction
*instr
)
1355 struct ir3_shader_variant
*so
= ctx
->so
;
1356 unsigned r
= regid(so
->inputs_count
, 0);
1357 unsigned n
= so
->inputs_count
++;
1359 so
->inputs
[n
].semantic
= ir3_semantic_name(name
, 0);
1360 so
->inputs
[n
].compmask
= 1;
1361 so
->inputs
[n
].regid
= r
;
1362 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1365 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1366 ctx
->ir
->inputs
[r
] = instr
;
1370 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1372 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1373 struct ir3_instruction
**dst
, **src
;
1374 struct ir3_block
*b
= ctx
->block
;
1375 unsigned idx
= intr
->const_index
[0];
1377 if (info
->has_dest
) {
1378 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1383 switch (intr
->intrinsic
) {
1384 case nir_intrinsic_load_uniform
:
1385 for (int i
= 0; i
< intr
->num_components
; i
++) {
1386 unsigned n
= idx
* 4 + i
;
1387 dst
[i
] = create_uniform(ctx
, n
);
1390 case nir_intrinsic_load_uniform_indirect
:
1391 src
= get_src(ctx
, &intr
->src
[0]);
1392 for (int i
= 0; i
< intr
->num_components
; i
++) {
1393 unsigned n
= idx
* 4 + i
;
1394 dst
[i
] = create_uniform_indirect(ctx
, n
,
1395 get_addr(ctx
, src
[0]));
1397 /* NOTE: if relative addressing is used, we set constlen in
1398 * the compiler (to worst-case value) since we don't know in
1399 * the assembler what the max addr reg value can be:
1401 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1403 case nir_intrinsic_load_ubo
:
1404 case nir_intrinsic_load_ubo_indirect
:
1405 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1407 case nir_intrinsic_load_input
:
1408 for (int i
= 0; i
< intr
->num_components
; i
++) {
1409 unsigned n
= idx
* 4 + i
;
1410 dst
[i
] = ctx
->ir
->inputs
[n
];
1413 case nir_intrinsic_load_input_indirect
:
1414 src
= get_src(ctx
, &intr
->src
[0]);
1415 struct ir3_instruction
*collect
=
1416 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1417 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1418 for (int i
= 0; i
< intr
->num_components
; i
++) {
1419 unsigned n
= idx
* 4 + i
;
1420 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1424 case nir_intrinsic_load_var
:
1425 emit_intrinisic_load_var(ctx
, intr
, dst
);
1427 case nir_intrinsic_store_var
:
1428 emit_intrinisic_store_var(ctx
, intr
);
1430 case nir_intrinsic_store_output
:
1431 src
= get_src(ctx
, &intr
->src
[0]);
1432 for (int i
= 0; i
< intr
->num_components
; i
++) {
1433 unsigned n
= idx
* 4 + i
;
1434 ctx
->ir
->outputs
[n
] = src
[i
];
1437 case nir_intrinsic_load_base_vertex
:
1438 if (!ctx
->basevertex
) {
1439 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1440 add_sysval_input(ctx
, TGSI_SEMANTIC_BASEVERTEX
,
1443 dst
[0] = ctx
->basevertex
;
1445 case nir_intrinsic_load_vertex_id_zero_base
:
1446 if (!ctx
->vertex_id
) {
1447 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1448 add_sysval_input(ctx
, TGSI_SEMANTIC_VERTEXID_NOBASE
,
1451 dst
[0] = ctx
->vertex_id
;
1453 case nir_intrinsic_load_instance_id
:
1454 if (!ctx
->instance_id
) {
1455 ctx
->instance_id
= create_input(ctx
->block
, 0);
1456 add_sysval_input(ctx
, TGSI_SEMANTIC_INSTANCEID
,
1459 dst
[0] = ctx
->instance_id
;
1461 case nir_intrinsic_discard_if
:
1462 case nir_intrinsic_discard
: {
1463 struct ir3_instruction
*cond
, *kill
;
1465 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1466 /* conditional discard: */
1467 src
= get_src(ctx
, &intr
->src
[0]);
1468 cond
= ir3_b2n(b
, src
[0]);
1470 /* unconditional discard: */
1471 cond
= create_immed(b
, 1);
1474 /* NOTE: only cmps.*.* can write p0.x: */
1475 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1476 cond
->cat2
.condition
= IR3_COND_NE
;
1478 /* condition always goes in predicate register: */
1479 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1481 kill
= ir3_KILL(b
, cond
, 0);
1482 array_insert(ctx
->ir
->predicates
, kill
);
1484 array_insert(ctx
->ir
->keeps
, kill
);
1485 ctx
->so
->has_kill
= true;
1490 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1491 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1497 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1499 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1500 instr
->def
.num_components
);
1501 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1502 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1506 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1508 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1509 undef
->def
.num_components
);
1510 /* backend doesn't want undefined instructions, so just plug
1513 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1514 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1518 * texture fetch/sample instructions:
1522 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1524 unsigned coords
, flags
= 0;
1526 /* note: would use tex->coord_components.. except txs.. also,
1527 * since array index goes after shadow ref, we don't want to
1530 switch (tex
->sampler_dim
) {
1531 case GLSL_SAMPLER_DIM_1D
:
1532 case GLSL_SAMPLER_DIM_BUF
:
1535 case GLSL_SAMPLER_DIM_2D
:
1536 case GLSL_SAMPLER_DIM_RECT
:
1537 case GLSL_SAMPLER_DIM_EXTERNAL
:
1538 case GLSL_SAMPLER_DIM_MS
:
1541 case GLSL_SAMPLER_DIM_3D
:
1542 case GLSL_SAMPLER_DIM_CUBE
:
1544 flags
|= IR3_INSTR_3D
;
1547 unreachable("bad sampler_dim");
1551 flags
|= IR3_INSTR_S
;
1554 flags
|= IR3_INSTR_A
;
1561 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1563 struct ir3_block
*b
= ctx
->block
;
1564 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1565 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1566 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1567 unsigned i
, coords
, flags
;
1568 unsigned nsrc0
= 0, nsrc1
= 0;
1572 coord
= off
= ddx
= ddy
= NULL
;
1573 lod
= proj
= compare
= NULL
;
1575 /* TODO: might just be one component for gathers? */
1576 dst
= get_dst(ctx
, &tex
->dest
, 4);
1578 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1579 switch (tex
->src
[i
].src_type
) {
1580 case nir_tex_src_coord
:
1581 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1583 case nir_tex_src_bias
:
1584 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1587 case nir_tex_src_lod
:
1588 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1591 case nir_tex_src_comparitor
: /* shadow comparator */
1592 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1594 case nir_tex_src_projector
:
1595 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1598 case nir_tex_src_offset
:
1599 off
= get_src(ctx
, &tex
->src
[i
].src
);
1602 case nir_tex_src_ddx
:
1603 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1605 case nir_tex_src_ddy
:
1606 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1609 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1610 tex
->src
[i
].src_type
);
1616 case nir_texop_tex
: opc
= OPC_SAM
; break;
1617 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1618 case nir_texop_txl
: opc
= OPC_SAML
; break;
1619 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1620 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1621 case nir_texop_txf_ms
:
1625 case nir_texop_query_levels
:
1626 case nir_texop_texture_samples
:
1627 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1631 tex_info(tex
, &flags
, &coords
);
1633 /* scale up integer coords for TXF based on the LOD */
1634 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1636 for (i
= 0; i
< coords
; i
++)
1637 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1640 /* the array coord for cube arrays needs 0.5 added to it */
1641 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& tex
->is_array
&&
1643 coord
[3] = ir3_ADD_F(b
, coord
[3], 0, create_immed(b
, fui(0.5)), 0);
1646 * lay out the first argument in the proper order:
1647 * - actual coordinates first
1648 * - shadow reference
1651 * - starting at offset 4, dpdx.xy, dpdy.xy
1653 * bias/lod go into the second arg
1656 /* insert tex coords: */
1657 for (i
= 0; i
< coords
; i
++)
1658 src0
[nsrc0
++] = coord
[i
];
1661 /* hw doesn't do 1d, so we treat it as 2d with
1662 * height of 1, and patch up the y coord.
1663 * TODO: y coord should be (int)0 in some cases..
1665 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1669 src0
[nsrc0
++] = compare
;
1672 src0
[nsrc0
++] = coord
[coords
];
1675 src0
[nsrc0
++] = proj
;
1676 flags
|= IR3_INSTR_P
;
1679 /* pad to 4, then ddx/ddy: */
1680 if (tex
->op
== nir_texop_txd
) {
1682 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1683 for (i
= 0; i
< coords
; i
++)
1684 src0
[nsrc0
++] = ddx
[i
];
1686 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1687 for (i
= 0; i
< coords
; i
++)
1688 src0
[nsrc0
++] = ddy
[i
];
1690 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1694 * second argument (if applicable):
1699 if (has_off
| has_lod
| has_bias
) {
1701 for (i
= 0; i
< coords
; i
++)
1702 src1
[nsrc1
++] = off
[i
];
1704 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1705 flags
|= IR3_INSTR_O
;
1708 if (has_lod
| has_bias
)
1709 src1
[nsrc1
++] = lod
;
1712 switch (tex
->dest_type
) {
1713 case nir_type_invalid
:
1714 case nir_type_float
:
1720 case nir_type_unsigned
:
1725 unreachable("bad dest_type");
1728 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1729 flags
, tex
->sampler_index
, tex
->sampler_index
,
1730 create_collect(b
, src0
, nsrc0
),
1731 create_collect(b
, src1
, nsrc1
));
1733 split_dest(b
, dst
, sam
, 4);
1737 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1739 struct ir3_block
*b
= ctx
->block
;
1740 struct ir3_instruction
**dst
, *sam
;
1742 dst
= get_dst(ctx
, &tex
->dest
, 1);
1744 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1745 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1747 /* even though there is only one component, since it ends
1748 * up in .z rather than .x, we need a split_dest()
1750 split_dest(b
, dst
, sam
, 3);
1752 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1753 * the value in TEX_CONST_0 is zero-based.
1755 if (ctx
->levels_add_one
)
1756 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1760 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1762 struct ir3_block
*b
= ctx
->block
;
1763 struct ir3_instruction
**dst
, *sam
, *lod
;
1764 unsigned flags
, coords
;
1766 tex_info(tex
, &flags
, &coords
);
1768 /* Actually we want the number of dimensions, not coordinates. This
1769 * distinction only matters for cubes.
1771 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1774 dst
= get_dst(ctx
, &tex
->dest
, 4);
1776 compile_assert(ctx
, tex
->num_srcs
== 1);
1777 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1779 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1781 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1782 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1784 split_dest(b
, dst
, sam
, 4);
1786 /* Array size actually ends up in .w rather than .z. This doesn't
1787 * matter for miplevel 0, but for higher mips the value in z is
1788 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1789 * returned, which means that we have to add 1 to it for arrays.
1791 if (tex
->is_array
) {
1792 if (ctx
->levels_add_one
) {
1793 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1795 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1801 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1803 struct ir3_instruction
*phi
, **dst
;
1805 /* NOTE: phi's should be lowered to scalar at this point */
1806 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1808 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1810 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1811 1 + exec_list_length(&nphi
->srcs
));
1812 ir3_reg_create(phi
, 0, 0); /* dst */
1813 phi
->phi
.nphi
= nphi
;
1818 /* phi instructions are left partially constructed. We don't resolve
1819 * their srcs until the end of the block, since (eg. loops) one of
1820 * the phi's srcs might be defined after the phi due to back edges in
1824 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1826 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1827 nir_phi_instr
*nphi
;
1829 /* phi's only come at start of block: */
1830 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1833 if (!instr
->phi
.nphi
)
1836 nphi
= instr
->phi
.nphi
;
1837 instr
->phi
.nphi
= NULL
;
1839 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1840 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1841 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1845 resolve_array_phis(ctx
, block
);
1849 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1851 switch (jump
->type
) {
1852 case nir_jump_break
:
1853 case nir_jump_continue
:
1854 /* I *think* we can simply just ignore this, and use the
1855 * successor block link to figure out where we need to
1856 * jump to for break/continue
1860 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1866 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1868 switch (instr
->type
) {
1869 case nir_instr_type_alu
:
1870 emit_alu(ctx
, nir_instr_as_alu(instr
));
1872 case nir_instr_type_intrinsic
:
1873 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1875 case nir_instr_type_load_const
:
1876 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1878 case nir_instr_type_ssa_undef
:
1879 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1881 case nir_instr_type_tex
: {
1882 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1883 /* couple tex instructions get special-cased:
1887 emit_tex_txs(ctx
, tex
);
1889 case nir_texop_query_levels
:
1890 emit_tex_query_levels(ctx
, tex
);
1898 case nir_instr_type_phi
:
1899 emit_phi(ctx
, nir_instr_as_phi(instr
));
1901 case nir_instr_type_jump
:
1902 emit_jump(ctx
, nir_instr_as_jump(instr
));
1904 case nir_instr_type_call
:
1905 case nir_instr_type_parallel_copy
:
1906 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1911 static struct ir3_block
*
1912 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1914 struct ir3_block
*block
;
1915 struct hash_entry
*entry
;
1916 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1920 block
= ir3_block_create(ctx
->ir
);
1921 block
->nblock
= nblock
;
1922 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1928 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1930 struct ir3_block
*block
= get_block(ctx
, nblock
);
1932 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1933 if (nblock
->successors
[i
]) {
1934 block
->successors
[i
] =
1935 get_block(ctx
, nblock
->successors
[i
]);
1940 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1942 nir_foreach_instr(nblock
, instr
) {
1943 emit_instr(ctx
, instr
);
1949 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1952 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1954 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1956 ctx
->block
->condition
=
1957 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1959 emit_cf_list(ctx
, &nif
->then_list
);
1960 emit_cf_list(ctx
, &nif
->else_list
);
1964 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1966 emit_cf_list(ctx
, &nloop
->body
);
1970 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1972 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1973 switch (node
->type
) {
1974 case nir_cf_node_block
:
1975 emit_block(ctx
, nir_cf_node_as_block(node
));
1977 case nir_cf_node_if
:
1978 emit_if(ctx
, nir_cf_node_as_if(node
));
1980 case nir_cf_node_loop
:
1981 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1983 case nir_cf_node_function
:
1984 compile_error(ctx
, "TODO\n");
1990 /* emit stream-out code. At this point, the current block is the original
1991 * (nir) end block, and nir ensures that all flow control paths terminate
1992 * into the end block. We re-purpose the original end block to generate
1993 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
1994 * block holding stream-out write instructions, followed by the new end
1998 * p0.x = (vtxcnt < maxvtxcnt)
1999 * // succs: blockStreamOut, blockNewEnd
2002 * ... stream-out instructions ...
2003 * // succs: blockNewEnd
2009 emit_stream_out(struct ir3_compile
*ctx
)
2011 struct ir3_shader_variant
*v
= ctx
->so
;
2012 struct ir3
*ir
= ctx
->ir
;
2013 struct pipe_stream_output_info
*strmout
=
2014 &ctx
->so
->shader
->stream_output
;
2015 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2016 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2017 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2019 /* create vtxcnt input in input block at top of shader,
2020 * so that it is seen as live over the entire duration
2023 vtxcnt
= create_input(ctx
->in_block
, 0);
2024 add_sysval_input(ctx
, IR3_SEMANTIC_VTXCNT
, vtxcnt
);
2026 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2028 /* at this point, we are at the original 'end' block,
2029 * re-purpose this block to stream-out condition, then
2030 * append stream-out block and new-end block
2032 orig_end_block
= ctx
->block
;
2034 stream_out_block
= ir3_block_create(ir
);
2035 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2037 new_end_block
= ir3_block_create(ir
);
2038 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2040 orig_end_block
->successors
[0] = stream_out_block
;
2041 orig_end_block
->successors
[1] = new_end_block
;
2042 stream_out_block
->successors
[0] = new_end_block
;
2044 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2045 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2046 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2047 cond
->cat2
.condition
= IR3_COND_LT
;
2049 /* condition goes on previous block to the conditional,
2050 * since it is used to pick which of the two successor
2053 orig_end_block
->condition
= cond
;
2055 /* switch to stream_out_block to generate the stream-out
2058 ctx
->block
= stream_out_block
;
2060 /* Calculate base addresses based on vtxcnt. Instructions
2061 * generated for bases not used in following loop will be
2062 * stripped out in the backend.
2064 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2065 unsigned stride
= strmout
->stride
[i
];
2066 struct ir3_instruction
*base
, *off
;
2068 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ 5, i
));
2070 /* 24-bit should be enough: */
2071 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2072 create_immed(ctx
->block
, stride
* 4), 0);
2074 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2077 /* Generate the per-output store instructions: */
2078 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2079 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2080 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2081 struct ir3_instruction
*base
, *out
, *stg
;
2083 base
= bases
[strmout
->output
[i
].output_buffer
];
2084 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2086 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2087 create_immed(ctx
->block
, 1), 0);
2088 stg
->cat6
.type
= TYPE_U32
;
2089 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2091 array_insert(ctx
->ir
->keeps
, stg
);
2095 /* and finally switch to the new_end_block: */
2096 ctx
->block
= new_end_block
;
2100 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2102 emit_cf_list(ctx
, &impl
->body
);
2103 emit_block(ctx
, impl
->end_block
);
2105 /* at this point, we should have a single empty block,
2106 * into which we emit the 'end' instruction.
2108 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2110 /* If stream-out (aka transform-feedback) enabled, emit the
2111 * stream-out instructions, followed by a new empty block (into
2112 * which the 'end' instruction lands).
2114 * NOTE: it is done in this order, rather than inserting before
2115 * we emit end_block, because NIR guarantees that all blocks
2116 * flow into end_block, and that end_block has no successors.
2117 * So by re-purposing end_block as the first block of stream-
2118 * out, we guarantee that all exit paths flow into the stream-
2121 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2122 !ctx
->so
->key
.binning_pass
) {
2123 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2124 emit_stream_out(ctx
);
2127 ir3_END(ctx
->block
);
2131 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2133 struct ir3_shader_variant
*so
= ctx
->so
;
2134 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2135 unsigned ncomp
= glsl_get_components(in
->type
);
2136 unsigned n
= in
->data
.driver_location
;
2137 unsigned slot
= in
->data
.location
;
2139 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2140 slot
, array_len
, ncomp
, n
);
2142 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2143 so
->inputs
[n
].inloc
= ctx
->next_inloc
;
2144 so
->inputs
[n
].interpolate
= 0;
2145 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2147 /* the fdN_program_emit() code expects tgsi consts here, so map
2148 * things back to tgsi for now:
2150 switch (in
->data
.interpolation
) {
2151 case INTERP_QUALIFIER_FLAT
:
2152 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
2154 case INTERP_QUALIFIER_NOPERSPECTIVE
:
2155 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_LINEAR
;
2157 case INTERP_QUALIFIER_SMOOTH
:
2158 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_PERSPECTIVE
;
2162 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2163 unsigned semantic_name
, semantic_index
;
2165 varying_slot_to_tgsi_semantic(slot
,
2166 &semantic_name
, &semantic_index
);
2168 so
->inputs
[n
].semantic
=
2169 ir3_semantic_name(semantic_name
, semantic_index
);
2171 for (int i
= 0; i
< ncomp
; i
++) {
2172 struct ir3_instruction
*instr
= NULL
;
2173 unsigned idx
= (n
* 4) + i
;
2175 if (semantic_name
== TGSI_SEMANTIC_POSITION
) {
2176 so
->inputs
[n
].bary
= false;
2177 so
->frag_coord
= true;
2178 instr
= create_frag_coord(ctx
, i
);
2179 } else if (semantic_name
== TGSI_SEMANTIC_FACE
) {
2180 so
->inputs
[n
].bary
= false;
2181 so
->frag_face
= true;
2182 instr
= create_frag_face(ctx
, i
);
2184 bool use_ldlv
= false;
2186 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2187 * from the semantic name:
2189 if ((in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) &&
2190 ((semantic_name
== TGSI_SEMANTIC_COLOR
) ||
2191 (semantic_name
== TGSI_SEMANTIC_BCOLOR
)))
2192 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_COLOR
;
2194 if (ctx
->flat_bypass
) {
2195 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2196 * from the semantic name:
2198 switch (so
->inputs
[n
].interpolate
) {
2199 case TGSI_INTERPOLATE_COLOR
:
2200 if (!ctx
->so
->key
.rasterflat
)
2203 case TGSI_INTERPOLATE_CONSTANT
:
2209 so
->inputs
[n
].bary
= true;
2211 instr
= create_frag_input(ctx
,
2212 so
->inputs
[n
].inloc
+ i
- 8, use_ldlv
);
2215 ctx
->ir
->inputs
[idx
] = instr
;
2217 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2218 so
->inputs
[n
].semantic
= 0;
2219 for (int i
= 0; i
< ncomp
; i
++) {
2220 unsigned idx
= (n
* 4) + i
;
2221 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2224 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2227 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2228 ctx
->next_inloc
+= ncomp
;
2229 so
->total_in
+= ncomp
;
2234 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2236 struct ir3_shader_variant
*so
= ctx
->so
;
2237 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2238 unsigned ncomp
= glsl_get_components(out
->type
);
2239 unsigned semantic_name
, semantic_index
;
2240 unsigned n
= out
->data
.driver_location
;
2241 unsigned slot
= out
->data
.location
;
2244 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2245 slot
, array_len
, ncomp
, n
);
2247 if (ctx
->so
->type
== SHADER_VERTEX
) {
2248 varying_slot_to_tgsi_semantic(slot
,
2249 &semantic_name
, &semantic_index
);
2251 switch (semantic_name
) {
2252 case TGSI_SEMANTIC_POSITION
:
2253 so
->writes_pos
= true;
2255 case TGSI_SEMANTIC_PSIZE
:
2256 so
->writes_psize
= true;
2258 case TGSI_SEMANTIC_COLOR
:
2259 case TGSI_SEMANTIC_BCOLOR
:
2260 case TGSI_SEMANTIC_GENERIC
:
2261 case TGSI_SEMANTIC_FOG
:
2262 case TGSI_SEMANTIC_TEXCOORD
:
2265 compile_error(ctx
, "unknown VS semantic name: %s\n",
2266 tgsi_semantic_names
[semantic_name
]);
2268 } else if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2269 frag_result_to_tgsi_semantic(slot
,
2270 &semantic_name
, &semantic_index
);
2272 switch (semantic_name
) {
2273 case TGSI_SEMANTIC_POSITION
:
2274 comp
= 2; /* tgsi will write to .z component */
2275 so
->writes_pos
= true;
2277 case TGSI_SEMANTIC_COLOR
:
2278 if (semantic_index
== -1) {
2284 compile_error(ctx
, "unknown FS semantic name: %s\n",
2285 tgsi_semantic_names
[semantic_name
]);
2288 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2291 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2293 so
->outputs
[n
].semantic
=
2294 ir3_semantic_name(semantic_name
, semantic_index
);
2295 so
->outputs
[n
].regid
= regid(n
, comp
);
2296 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2298 for (int i
= 0; i
< ncomp
; i
++) {
2299 unsigned idx
= (n
* 4) + i
;
2301 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2306 emit_instructions(struct ir3_compile
*ctx
)
2308 unsigned ninputs
, noutputs
;
2309 nir_function_impl
*fxn
= NULL
;
2311 /* Find the main function: */
2312 nir_foreach_overload(ctx
->s
, overload
) {
2313 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
2314 compile_assert(ctx
, overload
->impl
);
2315 fxn
= overload
->impl
;
2319 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2320 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2322 /* or vtx shaders, we need to leave room for sysvals:
2324 if (ctx
->so
->type
== SHADER_VERTEX
) {
2328 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2330 /* Create inputs in first block: */
2331 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2332 ctx
->in_block
= ctx
->block
;
2333 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2335 if (ctx
->so
->type
== SHADER_VERTEX
) {
2336 ctx
->ir
->ninputs
-= 8;
2339 /* for fragment shader, we have a single input register (usually
2340 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2342 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2343 // TODO maybe a helper for fi since we need it a few places..
2344 struct ir3_instruction
*instr
;
2345 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2346 ir3_reg_create(instr
, 0, 0);
2347 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2348 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2349 ctx
->frag_pos
= instr
;
2353 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->inputs
) {
2354 setup_input(ctx
, var
);
2357 /* Setup outputs: */
2358 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->outputs
) {
2359 setup_output(ctx
, var
);
2362 /* Setup variables (which should only be arrays): */
2363 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->globals
) {
2364 declare_var(ctx
, var
);
2367 /* And emit the body: */
2369 emit_function(ctx
, fxn
);
2371 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2372 resolve_phis(ctx
, block
);
2376 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2377 * for a fragment shader are just bary.f instructions. The *actual* inputs
2378 * from the hw perspective are the frag_pos and optionally frag_coord and
2382 fixup_frag_inputs(struct ir3_compile
*ctx
)
2384 struct ir3_shader_variant
*so
= ctx
->so
;
2385 struct ir3
*ir
= ctx
->ir
;
2386 struct ir3_instruction
**inputs
;
2387 struct ir3_instruction
*instr
;
2392 n
= 4; /* always have frag_pos */
2393 n
+= COND(so
->frag_face
, 4);
2394 n
+= COND(so
->frag_coord
, 4);
2396 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2398 if (so
->frag_face
) {
2399 /* this ultimately gets assigned to hr0.x so doesn't conflict
2400 * with frag_coord/frag_pos..
2402 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2403 ctx
->frag_face
->regs
[0]->num
= 0;
2405 /* remaining channels not used, but let's avoid confusing
2406 * other parts that expect inputs to come in groups of vec4
2408 inputs
[ir
->ninputs
++] = NULL
;
2409 inputs
[ir
->ninputs
++] = NULL
;
2410 inputs
[ir
->ninputs
++] = NULL
;
2413 /* since we don't know where to set the regid for frag_coord,
2414 * we have to use r0.x for it. But we don't want to *always*
2415 * use r1.x for frag_pos as that could increase the register
2416 * footprint on simple shaders:
2418 if (so
->frag_coord
) {
2419 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2420 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2421 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2422 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2424 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2425 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2426 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2427 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2430 /* we always have frag_pos: */
2431 so
->pos_regid
= regid
;
2434 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2435 instr
->regs
[0]->num
= regid
++;
2436 inputs
[ir
->ninputs
++] = instr
;
2437 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2440 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2441 instr
->regs
[0]->num
= regid
++;
2442 inputs
[ir
->ninputs
++] = instr
;
2443 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2445 ir
->inputs
= inputs
;
2449 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2450 struct ir3_shader_variant
*so
)
2452 struct ir3_compile
*ctx
;
2454 struct ir3_instruction
**inputs
;
2455 unsigned i
, j
, actual_in
;
2456 int ret
= 0, max_bary
;
2460 ctx
= compile_init(compiler
, so
, so
->shader
->tokens
);
2462 DBG("INIT failed!");
2467 emit_instructions(ctx
);
2470 DBG("EMIT failed!");
2475 ir
= so
->ir
= ctx
->ir
;
2477 /* keep track of the inputs from TGSI perspective.. */
2478 inputs
= ir
->inputs
;
2480 /* but fixup actual inputs for frag shader: */
2481 if (so
->type
== SHADER_FRAGMENT
)
2482 fixup_frag_inputs(ctx
);
2484 /* at this point, for binning pass, throw away unneeded outputs: */
2485 if (so
->key
.binning_pass
) {
2486 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2487 unsigned name
= sem2name(so
->outputs
[i
].semantic
);
2488 unsigned idx
= sem2idx(so
->outputs
[i
].semantic
);
2490 /* throw away everything but first position/psize */
2491 if ((idx
== 0) && ((name
== TGSI_SEMANTIC_POSITION
) ||
2492 (name
== TGSI_SEMANTIC_PSIZE
))) {
2494 so
->outputs
[j
] = so
->outputs
[i
];
2495 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2496 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2497 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2498 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2503 so
->outputs_count
= j
;
2504 ir
->noutputs
= j
* 4;
2507 /* if we want half-precision outputs, mark the output registers
2510 if (so
->key
.half_precision
) {
2511 for (i
= 0; i
< ir
->noutputs
; i
++) {
2512 struct ir3_instruction
*out
= ir
->outputs
[i
];
2515 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2516 /* output could be a fanout (ie. texture fetch output)
2517 * in which case we need to propagate the half-reg flag
2518 * up to the definer so that RA sees it:
2520 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2521 out
= out
->regs
[1]->instr
;
2522 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2525 if (out
->category
== 1) {
2526 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2531 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2532 printf("BEFORE CP:\n");
2538 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2539 printf("BEFORE GROUPING:\n");
2543 /* Group left/right neighbors, inserting mov's where needed to
2550 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2551 printf("AFTER DEPTH:\n");
2555 ret
= ir3_sched(ir
);
2557 DBG("SCHED failed!");
2561 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2562 printf("AFTER SCHED:\n");
2566 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2572 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2573 printf("AFTER RA:\n");
2577 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2579 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2580 printf("AFTER LEGALIZE:\n");
2584 /* fixup input/outputs: */
2585 for (i
= 0; i
< so
->outputs_count
; i
++) {
2586 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2587 /* preserve hack for depth output.. tgsi writes depth to .z,
2588 * but what we give the hw is the scalar register:
2590 if ((so
->type
== SHADER_FRAGMENT
) &&
2591 (sem2name(so
->outputs
[i
].semantic
) == TGSI_SEMANTIC_POSITION
))
2592 so
->outputs
[i
].regid
+= 2;
2595 /* Note that some or all channels of an input may be unused: */
2597 for (i
= 0; i
< so
->inputs_count
; i
++) {
2598 unsigned j
, regid
= ~0, compmask
= 0;
2599 so
->inputs
[i
].ncomp
= 0;
2600 for (j
= 0; j
< 4; j
++) {
2601 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2603 compmask
|= (1 << j
);
2604 regid
= in
->regs
[0]->num
- j
;
2606 so
->inputs
[i
].ncomp
++;
2609 so
->inputs
[i
].regid
= regid
;
2610 so
->inputs
[i
].compmask
= compmask
;
2613 /* fragment shader always gets full vec4's even if it doesn't
2614 * fetch all components, but vertex shader we need to update
2615 * with the actual number of components fetch, otherwise thing
2616 * will hang due to mismaptch between VFD_DECODE's and
2619 if (so
->type
== SHADER_VERTEX
)
2620 so
->total_in
= actual_in
;
2622 so
->total_in
= align(max_bary
+ 1, 4);
2627 ir3_destroy(so
->ir
);