1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
41 #include "freedreno_util.h"
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
47 #include "instr-a3xx.h"
52 struct ir3_compiler
*compiler
;
54 const struct tgsi_token
*tokens
;
58 struct ir3_shader_variant
*so
;
60 struct ir3_block
*block
; /* the current block */
61 struct ir3_block
*in_block
; /* block created for shader inputs */
63 nir_function_impl
*impl
;
65 /* For fragment shaders, from the hw perspective the only
66 * actual input is r0.xy position register passed to bary.f.
67 * But TGSI doesn't know that, it still declares things as
68 * IN[] registers. So we do all the input tracking normally
69 * and fix things up after compile_instructions()
71 * NOTE that frag_pos is the hardware position (possibly it
72 * is actually an index or tag or some such.. it is *not*
73 * values that can be directly used for gl_FragCoord..)
75 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
77 /* For vertex shaders, keep track of the system values sources */
78 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
83 /* mapping from nir_variable to ir3_array: */
84 struct hash_table
*var_ht
;
87 /* a common pattern for indirect addressing is to request the
88 * same address register multiple times. To avoid generating
89 * duplicate instruction sequences (which our backend does not
90 * try to clean up, since that should be done as the NIR stage)
91 * we cache the address value generated for a given src value:
93 struct hash_table
*addr_ht
;
95 /* maps nir_block to ir3_block, mostly for the purposes of
96 * figuring out the blocks successors
98 struct hash_table
*block_ht
;
100 /* for calculating input/output positions/linkages: */
103 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
104 * so we need to use ldlv.u32 to load the varying directly:
108 /* on a3xx, we need to add one to # of array levels:
112 /* on a3xx, we need to scale up integer coords for isaml based
115 bool unminify_coords
;
117 /* for looking up which system value is which */
118 unsigned sysval_semantics
[8];
120 /* set if we encounter something we can't handle yet, so we
121 * can bail cleanly and fallback to TGSI compiler f/e
127 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
128 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
130 static struct nir_shader
*to_nir(const struct tgsi_token
*tokens
,
131 struct ir3_shader_variant
*so
)
133 struct nir_shader_compiler_options options
= {
138 .lower_ffract
= true,
139 .native_integers
= true,
143 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
145 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
146 debug_printf("----------------------\n");
147 nir_print_shader(s
, stdout
);
148 debug_printf("----------------------\n");
151 nir_opt_global_to_local(s
);
152 nir_convert_to_ssa(s
);
153 if (s
->stage
== MESA_SHADER_VERTEX
) {
154 nir_lower_clip_vs(s
, so
->key
.ucp_enables
);
155 } else if (s
->stage
== MESA_SHADER_FRAGMENT
) {
156 nir_lower_clip_fs(s
, so
->key
.ucp_enables
);
159 nir_lower_load_const_to_scalar(s
);
164 nir_lower_vars_to_ssa(s
);
165 nir_lower_alu_to_scalar(s
);
166 nir_lower_phis_to_scalar(s
);
168 progress
|= nir_copy_prop(s
);
169 progress
|= nir_opt_dce(s
);
170 progress
|= nir_opt_cse(s
);
171 progress
|= ir3_nir_lower_if_else(s
);
172 progress
|= nir_opt_algebraic(s
);
173 progress
|= nir_opt_constant_folding(s
);
177 nir_remove_dead_variables(s
);
178 nir_validate_shader(s
);
180 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
181 debug_printf("----------------------\n");
182 nir_print_shader(s
, stdout
);
183 debug_printf("----------------------\n");
189 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
190 static const struct tgsi_token
*
191 lower_tgsi(struct ir3_compile
*ctx
, const struct tgsi_token
*tokens
,
192 struct ir3_shader_variant
*so
)
194 struct tgsi_shader_info info
;
195 struct tgsi_lowering_config lconfig
= {
196 .color_two_side
= so
->key
.color_two_side
,
200 case SHADER_FRAGMENT
:
202 lconfig
.saturate_s
= so
->key
.fsaturate_s
;
203 lconfig
.saturate_t
= so
->key
.fsaturate_t
;
204 lconfig
.saturate_r
= so
->key
.fsaturate_r
;
207 lconfig
.saturate_s
= so
->key
.vsaturate_s
;
208 lconfig
.saturate_t
= so
->key
.vsaturate_t
;
209 lconfig
.saturate_r
= so
->key
.vsaturate_r
;
213 if (ctx
->compiler
->gpu_id
>= 400) {
214 /* a4xx seems to have *no* sam.p */
215 lconfig
.lower_TXP
= ~0; /* lower all txp */
217 /* a3xx just needs to avoid sam.p for 3d tex */
218 lconfig
.lower_TXP
= (1 << TGSI_TEXTURE_3D
);
221 return tgsi_transform_lowering(&lconfig
, tokens
, &info
);
224 static struct ir3_compile
*
225 compile_init(struct ir3_compiler
*compiler
,
226 struct ir3_shader_variant
*so
,
227 const struct tgsi_token
*tokens
)
229 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
230 const struct tgsi_token
*lowered_tokens
;
232 if (compiler
->gpu_id
>= 400) {
233 /* need special handling for "flat" */
234 ctx
->flat_bypass
= true;
235 ctx
->levels_add_one
= false;
236 ctx
->unminify_coords
= false;
238 /* no special handling for "flat" */
239 ctx
->flat_bypass
= false;
240 ctx
->levels_add_one
= true;
241 ctx
->unminify_coords
= true;
244 ctx
->compiler
= compiler
;
248 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
249 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
250 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
251 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
252 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
253 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
254 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
255 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
257 lowered_tokens
= lower_tgsi(ctx
, tokens
, so
);
259 lowered_tokens
= tokens
;
260 ctx
->s
= to_nir(lowered_tokens
, so
);
262 if (lowered_tokens
!= tokens
)
263 free((void *)lowered_tokens
);
265 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
267 /* Layout of constant registers:
269 * num_uniform * vec4 - user consts
270 * 4 * vec4 - UBO addresses
271 * if (vertex shader) {
272 * N * vec4 - driver params (IR3_DP_*)
273 * 1 * vec4 - stream-out addresses
276 * TODO this could be made more dynamic, to at least skip sections
277 * that we don't need..
280 /* reserve 4 (vec4) slots for ubo base addresses: */
281 so
->first_immediate
+= 4;
283 if (so
->type
== SHADER_VERTEX
) {
284 /* driver params (see ir3_driver_param): */
285 so
->first_immediate
+= IR3_DP_COUNT
/4; /* convert to vec4 */
286 /* one (vec4) slot for stream-output base addresses: */
287 so
->first_immediate
++;
294 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
297 va_start(ap
, format
);
298 _debug_vprintf(format
, ap
);
300 nir_print_shader(ctx
->s
, stdout
);
305 #define compile_assert(ctx, cond) do { \
306 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
310 compile_free(struct ir3_compile
*ctx
)
315 /* global per-array information: */
317 unsigned length
, aid
;
320 /* per-block array state: */
321 struct ir3_array_value
{
322 /* TODO drop length/aid, and just have ptr back to ir3_array */
323 unsigned length
, aid
;
324 /* initial array element values are phi's, other than for the
325 * entry block. The phi src's get added later in a resolve step
326 * after we have visited all the blocks, to account for back
329 struct ir3_instruction
**phis
;
330 /* current array element values (as block is processed). When
331 * the array phi's are resolved, it will contain the array state
332 * at exit of block, so successor blocks can use it to add their
335 struct ir3_instruction
*arr
[];
338 /* track array assignments per basic block. When an array is read
339 * outside of the same basic block, we can use NIR's dominance-frontier
340 * information to figure out where phi nodes are needed.
342 struct ir3_nir_block_data
{
344 /* indexed by array-id (aid): */
345 struct ir3_array_value
*arrs
[];
348 static struct ir3_nir_block_data
*
349 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
352 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
353 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
360 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
362 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
363 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
364 arr
->length
= length
;
365 arr
->aid
= ++ctx
->num_arrays
;
366 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
370 nir_block_pred(nir_block
*block
)
372 assert(block
->predecessors
->entries
< 2);
373 if (block
->predecessors
->entries
== 0)
375 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
378 static struct ir3_array_value
*
379 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
381 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
382 struct ir3_block
*block
= ctx
->block
;
383 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
384 struct ir3_array
*arr
= entry
->data
;
386 if (!bd
->arrs
[arr
->aid
]) {
387 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
388 (arr
->length
* sizeof(av
->arr
[0])));
389 struct ir3_array_value
*defn
= NULL
;
390 nir_block
*pred_block
;
392 av
->length
= arr
->length
;
395 /* For loops, we have to consider that we have not visited some
396 * of the blocks who should feed into the phi (ie. back-edges in
397 * the cfg).. for example:
400 * block { load_var; ... }
401 * if then block {} else block {}
402 * block { store_var; ... }
403 * if then block {} else block {}
407 * We can skip the phi if we can chase the block predecessors
408 * until finding the block previously defining the array without
409 * crossing a block that has more than one predecessor.
411 * Otherwise create phi's and resolve them as a post-pass after
412 * all the blocks have been visited (to handle back-edges).
415 for (pred_block
= block
->nblock
;
416 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
417 pred_block
= nir_block_pred(pred_block
)) {
418 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
419 struct ir3_nir_block_data
*pbd
= pblock
->bd
;
422 defn
= pbd
->arrs
[arr
->aid
];
426 /* only one possible definer: */
427 for (unsigned i
= 0; i
< arr
->length
; i
++)
428 av
->arr
[i
] = defn
->arr
[i
];
429 } else if (pred_block
) {
430 /* not the first block, and multiple potential definers: */
431 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
433 for (unsigned i
= 0; i
< arr
->length
; i
++) {
434 struct ir3_instruction
*phi
;
436 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
437 1 + ctx
->impl
->num_blocks
);
438 ir3_reg_create(phi
, 0, 0); /* dst */
440 /* phi's should go at head of block: */
441 list_delinit(&phi
->node
);
442 list_add(&phi
->node
, &block
->instr_list
);
444 av
->phis
[i
] = av
->arr
[i
] = phi
;
447 /* Some shaders end up reading array elements without
448 * first writing.. so initialize things to prevent null
451 for (unsigned i
= 0; i
< arr
->length
; i
++)
452 av
->arr
[i
] = create_immed(block
, 0);
455 bd
->arrs
[arr
->aid
] = av
;
458 return bd
->arrs
[arr
->aid
];
462 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
463 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
465 struct ir3_block
*block
;
466 struct ir3_nir_block_data
*bd
;
468 if (BITSET_TEST(visited
, nblock
->index
))
471 BITSET_SET(visited
, nblock
->index
);
473 block
= get_block(ctx
, nblock
);
476 if (bd
&& bd
->arrs
[av
->aid
]) {
477 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
478 for (unsigned i
= 0; i
< av
->length
; i
++) {
479 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
483 /* didn't find defn, recurse predecessors: */
484 struct set_entry
*entry
;
485 set_foreach(nblock
->predecessors
, entry
) {
486 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
492 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
494 struct ir3_nir_block_data
*bd
= block
->bd
;
495 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
500 /* TODO use nir dom_frontier to help us with this? */
502 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
503 struct ir3_array_value
*av
= bd
->arrs
[i
];
504 BITSET_WORD visited
[bitset_words
];
505 struct set_entry
*entry
;
507 if (!(av
&& av
->phis
))
510 memset(visited
, 0, sizeof(visited
));
511 set_foreach(block
->nblock
->predecessors
, entry
) {
512 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
517 /* allocate a n element value array (to be populated by caller) and
520 static struct ir3_instruction
**
521 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
523 struct ir3_instruction
**value
=
524 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
525 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
529 static struct ir3_instruction
**
530 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
533 return __get_dst(ctx
, &dst
->ssa
, n
);
535 return __get_dst(ctx
, dst
->reg
.reg
, n
);
539 static struct ir3_instruction
**
540 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
542 return __get_dst(ctx
, dst
, n
);
545 static struct ir3_instruction
**
546 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
548 struct hash_entry
*entry
;
550 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
552 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
554 compile_assert(ctx
, entry
);
558 static struct ir3_instruction
*
559 create_immed(struct ir3_block
*block
, uint32_t val
)
561 struct ir3_instruction
*mov
;
563 mov
= ir3_instr_create(block
, 1, 0);
564 mov
->cat1
.src_type
= TYPE_U32
;
565 mov
->cat1
.dst_type
= TYPE_U32
;
566 ir3_reg_create(mov
, 0, 0);
567 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
572 static struct ir3_instruction
*
573 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
575 struct ir3_instruction
*instr
, *immed
;
577 /* TODO in at least some cases, the backend could probably be
578 * made clever enough to propagate IR3_REG_HALF..
580 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
581 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
583 immed
= create_immed(block
, 2);
584 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
586 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
587 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
588 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
590 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
591 instr
->regs
[0]->num
= regid(REG_A0
, 0);
592 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
593 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
598 /* caches addr values to avoid generating multiple cov/shl/mova
599 * sequences for each use of a given NIR level src as address
601 static struct ir3_instruction
*
602 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
604 struct ir3_instruction
*addr
;
605 struct hash_entry
*entry
;
606 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
610 /* TODO do we need to cache per block? */
611 addr
= create_addr(ctx
->block
, src
);
612 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
617 static struct ir3_instruction
*
618 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
620 struct ir3_block
*b
= ctx
->block
;
621 struct ir3_instruction
*cond
;
623 /* NOTE: only cmps.*.* can write p0.x: */
624 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
625 cond
->cat2
.condition
= IR3_COND_NE
;
627 /* condition always goes in predicate register: */
628 cond
->regs
[0]->num
= regid(REG_P0
, 0);
633 static struct ir3_instruction
*
634 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
636 struct ir3_instruction
*mov
;
638 mov
= ir3_instr_create(ctx
->block
, 1, 0);
639 /* TODO get types right? */
640 mov
->cat1
.src_type
= TYPE_F32
;
641 mov
->cat1
.dst_type
= TYPE_F32
;
642 ir3_reg_create(mov
, 0, 0);
643 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
648 static struct ir3_instruction
*
649 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
650 struct ir3_instruction
*address
)
652 struct ir3_instruction
*mov
;
654 mov
= ir3_instr_create(ctx
->block
, 1, 0);
655 mov
->cat1
.src_type
= TYPE_U32
;
656 mov
->cat1
.dst_type
= TYPE_U32
;
657 ir3_reg_create(mov
, 0, 0);
658 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
660 ir3_instr_set_address(mov
, address
);
665 static struct ir3_instruction
*
666 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
669 struct ir3_instruction
*collect
;
674 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
675 ir3_reg_create(collect
, 0, 0); /* dst */
676 for (unsigned i
= 0; i
< arrsz
; i
++)
677 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
682 static struct ir3_instruction
*
683 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
684 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
686 struct ir3_block
*block
= ctx
->block
;
687 struct ir3_instruction
*mov
;
688 struct ir3_register
*src
;
690 mov
= ir3_instr_create(block
, 1, 0);
691 mov
->cat1
.src_type
= TYPE_U32
;
692 mov
->cat1
.dst_type
= TYPE_U32
;
693 ir3_reg_create(mov
, 0, 0);
694 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
695 src
->instr
= collect
;
699 ir3_instr_set_address(mov
, address
);
704 static struct ir3_instruction
*
705 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
706 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
707 struct ir3_instruction
*collect
)
709 struct ir3_block
*block
= ctx
->block
;
710 struct ir3_instruction
*mov
;
711 struct ir3_register
*dst
;
713 mov
= ir3_instr_create(block
, 1, 0);
714 mov
->cat1
.src_type
= TYPE_U32
;
715 mov
->cat1
.dst_type
= TYPE_U32
;
716 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
719 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
720 mov
->fanin
= collect
;
722 ir3_instr_set_address(mov
, address
);
727 static struct ir3_instruction
*
728 create_input(struct ir3_block
*block
, unsigned n
)
730 struct ir3_instruction
*in
;
732 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
733 in
->inout
.block
= block
;
734 ir3_reg_create(in
, n
, 0);
739 static struct ir3_instruction
*
740 create_frag_input(struct ir3_compile
*ctx
, unsigned n
, bool use_ldlv
)
742 struct ir3_block
*block
= ctx
->block
;
743 struct ir3_instruction
*instr
;
744 struct ir3_instruction
*inloc
= create_immed(block
, n
);
747 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
748 instr
->cat6
.type
= TYPE_U32
;
749 instr
->cat6
.iim_val
= 1;
751 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
752 instr
->regs
[2]->wrmask
= 0x3;
758 static struct ir3_instruction
*
759 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
761 struct ir3_block
*block
= ctx
->block
;
762 struct ir3_instruction
*instr
;
764 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
766 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
771 /* for frag_coord, we get unsigned values.. we need
772 * to subtract (integer) 8 and divide by 16 (right-
773 * shift by 4) then convert to float:
777 * mov.u32f32 dst, tmp
780 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
781 create_immed(block
, 8), 0);
782 instr
= ir3_SHR_B(block
, instr
, 0,
783 create_immed(block
, 4), 0);
784 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
790 /* seems that we can use these as-is: */
791 return ctx
->frag_coord
[comp
];
795 static struct ir3_instruction
*
796 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
798 struct ir3_block
*block
= ctx
->block
;
799 struct ir3_instruction
*instr
;
803 compile_assert(ctx
, !ctx
->frag_face
);
805 ctx
->frag_face
= create_input(block
, 0);
806 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
808 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
809 * positive vs negative float.. and piglit further seems to
810 * expect -1.0 or 1.0:
812 * mul.s tmp, hr0.x, 2
814 * mov.s32f32, dst, tmp
817 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
818 create_immed(block
, 2), 0);
819 instr
= ir3_ADD_S(block
, instr
, 0,
820 create_immed(block
, 1), 0);
821 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
826 return create_immed(block
, fui(0.0));
829 return create_immed(block
, fui(1.0));
833 static struct ir3_instruction
*
834 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
836 /* first four vec4 sysval's reserved for UBOs: */
837 /* NOTE: dp is in scalar, but there can be >4 dp components: */
838 unsigned n
= ctx
->so
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
839 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
840 return create_uniform(ctx
, r
);
843 /* helper for instructions that produce multiple consecutive scalar
844 * outputs which need to have a split/fanout meta instruction inserted
847 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
848 struct ir3_instruction
*src
, unsigned n
)
850 struct ir3_instruction
*prev
= NULL
;
851 for (int i
= 0, j
= 0; i
< n
; i
++) {
852 struct ir3_instruction
*split
=
853 ir3_instr_create(block
, -1, OPC_META_FO
);
854 ir3_reg_create(split
, 0, IR3_REG_SSA
);
855 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
859 split
->cp
.left
= prev
;
860 split
->cp
.left_cnt
++;
861 prev
->cp
.right
= split
;
862 prev
->cp
.right_cnt
++;
866 if (src
->regs
[0]->wrmask
& (1 << i
))
872 * Adreno uses uint rather than having dedicated bool type,
873 * which (potentially) requires some conversion, in particular
874 * when using output of an bool instr to int input, or visa
878 * -------+---------+-------+-
882 * To convert from an adreno bool (uint) to nir, use:
884 * absneg.s dst, (neg)src
886 * To convert back in the other direction:
888 * absneg.s dst, (abs)arc
890 * The CP step can clean up the absneg.s that cancel each other
891 * out, and with a slight bit of extra cleverness (to recognize
892 * the instructions which produce either a 0 or 1) can eliminate
893 * the absneg.s's completely when an instruction that wants
894 * 0/1 consumes the result. For example, when a nir 'bcsel'
895 * consumes the result of 'feq'. So we should be able to get by
896 * without a boolean resolve step, and without incuring any
897 * extra penalty in instruction count.
900 /* NIR bool -> native (adreno): */
901 static struct ir3_instruction
*
902 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
904 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
907 /* native (adreno) -> NIR bool: */
908 static struct ir3_instruction
*
909 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
911 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
915 * alu/sfu instructions:
919 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
921 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
922 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
923 struct ir3_block
*b
= ctx
->block
;
925 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
927 /* Vectors are special in that they have non-scalarized writemasks,
928 * and just take the first swizzle channel for each argument in
929 * order into each writemask channel.
931 if ((alu
->op
== nir_op_vec2
) ||
932 (alu
->op
== nir_op_vec3
) ||
933 (alu
->op
== nir_op_vec4
)) {
935 for (int i
= 0; i
< info
->num_inputs
; i
++) {
936 nir_alu_src
*asrc
= &alu
->src
[i
];
938 compile_assert(ctx
, !asrc
->abs
);
939 compile_assert(ctx
, !asrc
->negate
);
941 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
943 src
[i
] = create_immed(ctx
->block
, 0);
944 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
950 /* General case: We can just grab the one used channel per src. */
951 for (int i
= 0; i
< info
->num_inputs
; i
++) {
952 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
953 nir_alu_src
*asrc
= &alu
->src
[i
];
955 compile_assert(ctx
, !asrc
->abs
);
956 compile_assert(ctx
, !asrc
->negate
);
958 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
960 compile_assert(ctx
, src
[i
]);
965 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
968 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
971 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
974 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
977 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
980 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
983 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
984 dst
[0]->cat2
.condition
= IR3_COND_NE
;
985 dst
[0] = ir3_n2b(b
, dst
[0]);
988 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
991 dst
[0] = ir3_b2n(b
, src
[0]);
994 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
995 dst
[0]->cat2
.condition
= IR3_COND_NE
;
996 dst
[0] = ir3_n2b(b
, dst
[0]);
1000 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1003 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1006 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1009 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1012 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1015 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1018 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1021 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1024 dst
[0] = ir3_DSX(b
, src
[0], 0);
1025 dst
[0]->cat5
.type
= TYPE_F32
;
1028 dst
[0] = ir3_DSY(b
, src
[0], 0);
1029 dst
[0]->cat5
.type
= TYPE_F32
;
1033 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1034 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1035 dst
[0] = ir3_n2b(b
, dst
[0]);
1038 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1039 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1040 dst
[0] = ir3_n2b(b
, dst
[0]);
1043 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1044 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1045 dst
[0] = ir3_n2b(b
, dst
[0]);
1048 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1049 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1050 dst
[0] = ir3_n2b(b
, dst
[0]);
1053 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1056 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1059 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1061 case nir_op_fround_even
:
1062 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1065 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1069 dst
[0] = ir3_SIN(b
, src
[0], 0);
1072 dst
[0] = ir3_COS(b
, src
[0], 0);
1075 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1078 dst
[0] = ir3_RCP(b
, src
[0], 0);
1081 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1084 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1087 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1091 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1094 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1097 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1100 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1103 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1106 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1109 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1113 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1114 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1115 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1116 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1118 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1119 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1120 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1123 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1126 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1129 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1132 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1135 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1137 case nir_op_isign
: {
1138 /* maybe this would be sane to lower in nir.. */
1139 struct ir3_instruction
*neg
, *pos
;
1141 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1142 neg
->cat2
.condition
= IR3_COND_LT
;
1144 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1145 pos
->cat2
.condition
= IR3_COND_GT
;
1147 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1152 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1155 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1158 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1161 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1162 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1163 dst
[0] = ir3_n2b(b
, dst
[0]);
1166 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1167 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1168 dst
[0] = ir3_n2b(b
, dst
[0]);
1171 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1172 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1173 dst
[0] = ir3_n2b(b
, dst
[0]);
1176 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1177 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1178 dst
[0] = ir3_n2b(b
, dst
[0]);
1181 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1182 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1183 dst
[0] = ir3_n2b(b
, dst
[0]);
1186 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1187 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1188 dst
[0] = ir3_n2b(b
, dst
[0]);
1192 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1196 compile_error(ctx
, "Unhandled ALU op: %s\n",
1197 nir_op_infos
[alu
->op
].name
);
1202 /* handles direct/indirect UBO reads: */
1204 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1205 struct ir3_instruction
**dst
)
1207 struct ir3_block
*b
= ctx
->block
;
1208 struct ir3_instruction
*addr
, *src0
, *src1
;
1209 /* UBO addresses are the first driver params: */
1210 unsigned ubo
= regid(ctx
->so
->first_driver_param
+ IR3_UBOS_OFF
, 0);
1211 unsigned off
= intr
->const_index
[0];
1213 /* First src is ubo index, which could either be an immed or not: */
1214 src0
= get_src(ctx
, &intr
->src
[0])[0];
1215 if (is_same_type_mov(src0
) &&
1216 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1217 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1219 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1222 if (intr
->intrinsic
== nir_intrinsic_load_ubo_indirect
) {
1223 /* For load_ubo_indirect, second src is indirect offset: */
1224 src1
= get_src(ctx
, &intr
->src
[1])[0];
1226 /* and add offset to addr: */
1227 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1230 /* if offset is to large to encode in the ldg, split it out: */
1231 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1232 /* split out the minimal amount to improve the odds that
1233 * cp can fit the immediate in the add.s instruction:
1235 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1236 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1240 for (int i
= 0; i
< intr
->num_components
; i
++) {
1241 struct ir3_instruction
*load
=
1242 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1243 load
->cat6
.type
= TYPE_U32
;
1244 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1249 /* handles array reads: */
1251 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1252 struct ir3_instruction
**dst
)
1254 nir_deref_var
*dvar
= intr
->variables
[0];
1255 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1256 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1258 compile_assert(ctx
, dvar
->deref
.child
&&
1259 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1261 switch (darr
->deref_array_type
) {
1262 case nir_deref_array_type_direct
:
1263 /* direct access does not require anything special: */
1264 for (int i
= 0; i
< intr
->num_components
; i
++) {
1265 unsigned n
= darr
->base_offset
* 4 + i
;
1266 compile_assert(ctx
, n
< arr
->length
);
1267 dst
[i
] = arr
->arr
[n
];
1270 case nir_deref_array_type_indirect
: {
1271 /* for indirect, we need to collect all the array elements: */
1272 struct ir3_instruction
*collect
=
1273 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1274 struct ir3_instruction
*addr
=
1275 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1276 for (int i
= 0; i
< intr
->num_components
; i
++) {
1277 unsigned n
= darr
->base_offset
* 4 + i
;
1278 compile_assert(ctx
, n
< arr
->length
);
1279 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1284 compile_error(ctx
, "Unhandled load deref type: %u\n",
1285 darr
->deref_array_type
);
1290 /* handles array writes: */
1292 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1294 nir_deref_var
*dvar
= intr
->variables
[0];
1295 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1296 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1297 struct ir3_instruction
**src
;
1299 compile_assert(ctx
, dvar
->deref
.child
&&
1300 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1302 src
= get_src(ctx
, &intr
->src
[0]);
1304 switch (darr
->deref_array_type
) {
1305 case nir_deref_array_type_direct
:
1306 /* direct access does not require anything special: */
1307 for (int i
= 0; i
< intr
->num_components
; i
++) {
1308 unsigned n
= darr
->base_offset
* 4 + i
;
1309 compile_assert(ctx
, n
< arr
->length
);
1310 arr
->arr
[n
] = src
[i
];
1313 case nir_deref_array_type_indirect
: {
1314 /* for indirect, create indirect-store and fan that out: */
1315 struct ir3_instruction
*collect
=
1316 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1317 struct ir3_instruction
*addr
=
1318 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1319 for (int i
= 0; i
< intr
->num_components
; i
++) {
1320 struct ir3_instruction
*store
;
1321 unsigned n
= darr
->base_offset
* 4 + i
;
1322 compile_assert(ctx
, n
< arr
->length
);
1324 store
= create_indirect_store(ctx
, arr
->length
,
1325 n
, src
[i
], addr
, collect
);
1327 store
->fanin
->fi
.aid
= arr
->aid
;
1329 /* TODO: probably split this out to be used for
1330 * store_output_indirect? or move this into
1331 * create_indirect_store()?
1333 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1334 struct ir3_instruction
*split
;
1336 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1338 ir3_reg_create(split
, 0, 0);
1339 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1341 arr
->arr
[j
] = split
;
1344 /* fixup fanout/split neighbors: */
1345 for (int i
= 0; i
< arr
->length
; i
++) {
1346 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1347 arr
->arr
[i
+1] : NULL
;
1348 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1349 arr
->arr
[i
-1] : NULL
;
1354 compile_error(ctx
, "Unhandled store deref type: %u\n",
1355 darr
->deref_array_type
);
1360 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1361 struct ir3_instruction
*instr
)
1363 struct ir3_shader_variant
*so
= ctx
->so
;
1364 unsigned r
= regid(so
->inputs_count
, 0);
1365 unsigned n
= so
->inputs_count
++;
1367 so
->inputs
[n
].sysval
= true;
1368 so
->inputs
[n
].slot
= slot
;
1369 so
->inputs
[n
].compmask
= 1;
1370 so
->inputs
[n
].regid
= r
;
1371 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_FLAT
;
1374 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1375 ctx
->ir
->inputs
[r
] = instr
;
1379 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1381 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1382 struct ir3_instruction
**dst
, **src
;
1383 struct ir3_block
*b
= ctx
->block
;
1384 unsigned idx
= intr
->const_index
[0];
1386 if (info
->has_dest
) {
1387 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1392 switch (intr
->intrinsic
) {
1393 case nir_intrinsic_load_uniform
:
1394 for (int i
= 0; i
< intr
->num_components
; i
++) {
1395 unsigned n
= idx
* 4 + i
;
1396 dst
[i
] = create_uniform(ctx
, n
);
1399 case nir_intrinsic_load_uniform_indirect
:
1400 src
= get_src(ctx
, &intr
->src
[0]);
1401 for (int i
= 0; i
< intr
->num_components
; i
++) {
1402 unsigned n
= idx
* 4 + i
;
1403 dst
[i
] = create_uniform_indirect(ctx
, n
,
1404 get_addr(ctx
, src
[0]));
1406 /* NOTE: if relative addressing is used, we set constlen in
1407 * the compiler (to worst-case value) since we don't know in
1408 * the assembler what the max addr reg value can be:
1410 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1412 case nir_intrinsic_load_ubo
:
1413 case nir_intrinsic_load_ubo_indirect
:
1414 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1416 case nir_intrinsic_load_input
:
1417 for (int i
= 0; i
< intr
->num_components
; i
++) {
1418 unsigned n
= idx
* 4 + i
;
1419 dst
[i
] = ctx
->ir
->inputs
[n
];
1422 case nir_intrinsic_load_input_indirect
:
1423 src
= get_src(ctx
, &intr
->src
[0]);
1424 struct ir3_instruction
*collect
=
1425 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1426 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1427 for (int i
= 0; i
< intr
->num_components
; i
++) {
1428 unsigned n
= idx
* 4 + i
;
1429 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1433 case nir_intrinsic_load_var
:
1434 emit_intrinisic_load_var(ctx
, intr
, dst
);
1436 case nir_intrinsic_store_var
:
1437 emit_intrinisic_store_var(ctx
, intr
);
1439 case nir_intrinsic_store_output
:
1440 src
= get_src(ctx
, &intr
->src
[0]);
1441 for (int i
= 0; i
< intr
->num_components
; i
++) {
1442 unsigned n
= idx
* 4 + i
;
1443 ctx
->ir
->outputs
[n
] = src
[i
];
1446 case nir_intrinsic_load_base_vertex
:
1447 if (!ctx
->basevertex
) {
1448 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1449 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1452 dst
[0] = ctx
->basevertex
;
1454 case nir_intrinsic_load_vertex_id_zero_base
:
1455 if (!ctx
->vertex_id
) {
1456 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1457 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
1460 dst
[0] = ctx
->vertex_id
;
1462 case nir_intrinsic_load_instance_id
:
1463 if (!ctx
->instance_id
) {
1464 ctx
->instance_id
= create_input(ctx
->block
, 0);
1465 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1468 dst
[0] = ctx
->instance_id
;
1470 case nir_intrinsic_load_user_clip_plane
:
1471 for (int i
= 0; i
< intr
->num_components
; i
++) {
1472 unsigned n
= idx
* 4 + i
;
1473 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1476 case nir_intrinsic_discard_if
:
1477 case nir_intrinsic_discard
: {
1478 struct ir3_instruction
*cond
, *kill
;
1480 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1481 /* conditional discard: */
1482 src
= get_src(ctx
, &intr
->src
[0]);
1483 cond
= ir3_b2n(b
, src
[0]);
1485 /* unconditional discard: */
1486 cond
= create_immed(b
, 1);
1489 /* NOTE: only cmps.*.* can write p0.x: */
1490 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1491 cond
->cat2
.condition
= IR3_COND_NE
;
1493 /* condition always goes in predicate register: */
1494 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1496 kill
= ir3_KILL(b
, cond
, 0);
1497 array_insert(ctx
->ir
->predicates
, kill
);
1499 array_insert(ctx
->ir
->keeps
, kill
);
1500 ctx
->so
->has_kill
= true;
1505 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1506 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1512 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1514 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1515 instr
->def
.num_components
);
1516 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1517 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1521 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1523 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1524 undef
->def
.num_components
);
1525 /* backend doesn't want undefined instructions, so just plug
1528 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1529 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1533 * texture fetch/sample instructions:
1537 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1539 unsigned coords
, flags
= 0;
1541 /* note: would use tex->coord_components.. except txs.. also,
1542 * since array index goes after shadow ref, we don't want to
1545 switch (tex
->sampler_dim
) {
1546 case GLSL_SAMPLER_DIM_1D
:
1547 case GLSL_SAMPLER_DIM_BUF
:
1550 case GLSL_SAMPLER_DIM_2D
:
1551 case GLSL_SAMPLER_DIM_RECT
:
1552 case GLSL_SAMPLER_DIM_EXTERNAL
:
1553 case GLSL_SAMPLER_DIM_MS
:
1556 case GLSL_SAMPLER_DIM_3D
:
1557 case GLSL_SAMPLER_DIM_CUBE
:
1559 flags
|= IR3_INSTR_3D
;
1562 unreachable("bad sampler_dim");
1566 flags
|= IR3_INSTR_S
;
1569 flags
|= IR3_INSTR_A
;
1576 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1578 struct ir3_block
*b
= ctx
->block
;
1579 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1580 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1581 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1582 unsigned i
, coords
, flags
;
1583 unsigned nsrc0
= 0, nsrc1
= 0;
1587 coord
= off
= ddx
= ddy
= NULL
;
1588 lod
= proj
= compare
= NULL
;
1590 /* TODO: might just be one component for gathers? */
1591 dst
= get_dst(ctx
, &tex
->dest
, 4);
1593 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1594 switch (tex
->src
[i
].src_type
) {
1595 case nir_tex_src_coord
:
1596 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1598 case nir_tex_src_bias
:
1599 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1602 case nir_tex_src_lod
:
1603 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1606 case nir_tex_src_comparitor
: /* shadow comparator */
1607 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1609 case nir_tex_src_projector
:
1610 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1613 case nir_tex_src_offset
:
1614 off
= get_src(ctx
, &tex
->src
[i
].src
);
1617 case nir_tex_src_ddx
:
1618 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1620 case nir_tex_src_ddy
:
1621 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1624 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1625 tex
->src
[i
].src_type
);
1631 case nir_texop_tex
: opc
= OPC_SAM
; break;
1632 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1633 case nir_texop_txl
: opc
= OPC_SAML
; break;
1634 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1635 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1636 case nir_texop_txf_ms
:
1640 case nir_texop_query_levels
:
1641 case nir_texop_texture_samples
:
1642 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1646 tex_info(tex
, &flags
, &coords
);
1648 /* scale up integer coords for TXF based on the LOD */
1649 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1651 for (i
= 0; i
< coords
; i
++)
1652 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1655 /* the array coord for cube arrays needs 0.5 added to it */
1656 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& tex
->is_array
&&
1658 coord
[3] = ir3_ADD_F(b
, coord
[3], 0, create_immed(b
, fui(0.5)), 0);
1661 * lay out the first argument in the proper order:
1662 * - actual coordinates first
1663 * - shadow reference
1666 * - starting at offset 4, dpdx.xy, dpdy.xy
1668 * bias/lod go into the second arg
1671 /* insert tex coords: */
1672 for (i
= 0; i
< coords
; i
++)
1673 src0
[nsrc0
++] = coord
[i
];
1676 /* hw doesn't do 1d, so we treat it as 2d with
1677 * height of 1, and patch up the y coord.
1678 * TODO: y coord should be (int)0 in some cases..
1680 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1684 src0
[nsrc0
++] = compare
;
1687 src0
[nsrc0
++] = coord
[coords
];
1690 src0
[nsrc0
++] = proj
;
1691 flags
|= IR3_INSTR_P
;
1694 /* pad to 4, then ddx/ddy: */
1695 if (tex
->op
== nir_texop_txd
) {
1697 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1698 for (i
= 0; i
< coords
; i
++)
1699 src0
[nsrc0
++] = ddx
[i
];
1701 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1702 for (i
= 0; i
< coords
; i
++)
1703 src0
[nsrc0
++] = ddy
[i
];
1705 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1709 * second argument (if applicable):
1714 if (has_off
| has_lod
| has_bias
) {
1716 for (i
= 0; i
< coords
; i
++)
1717 src1
[nsrc1
++] = off
[i
];
1719 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1720 flags
|= IR3_INSTR_O
;
1723 if (has_lod
| has_bias
)
1724 src1
[nsrc1
++] = lod
;
1727 switch (tex
->dest_type
) {
1728 case nir_type_invalid
:
1729 case nir_type_float
:
1735 case nir_type_unsigned
:
1740 unreachable("bad dest_type");
1743 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1744 flags
, tex
->sampler_index
, tex
->sampler_index
,
1745 create_collect(b
, src0
, nsrc0
),
1746 create_collect(b
, src1
, nsrc1
));
1748 split_dest(b
, dst
, sam
, 4);
1752 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1754 struct ir3_block
*b
= ctx
->block
;
1755 struct ir3_instruction
**dst
, *sam
;
1757 dst
= get_dst(ctx
, &tex
->dest
, 1);
1759 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1760 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1762 /* even though there is only one component, since it ends
1763 * up in .z rather than .x, we need a split_dest()
1765 split_dest(b
, dst
, sam
, 3);
1767 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1768 * the value in TEX_CONST_0 is zero-based.
1770 if (ctx
->levels_add_one
)
1771 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1775 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1777 struct ir3_block
*b
= ctx
->block
;
1778 struct ir3_instruction
**dst
, *sam
, *lod
;
1779 unsigned flags
, coords
;
1781 tex_info(tex
, &flags
, &coords
);
1783 /* Actually we want the number of dimensions, not coordinates. This
1784 * distinction only matters for cubes.
1786 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1789 dst
= get_dst(ctx
, &tex
->dest
, 4);
1791 compile_assert(ctx
, tex
->num_srcs
== 1);
1792 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1794 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1796 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1797 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1799 split_dest(b
, dst
, sam
, 4);
1801 /* Array size actually ends up in .w rather than .z. This doesn't
1802 * matter for miplevel 0, but for higher mips the value in z is
1803 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1804 * returned, which means that we have to add 1 to it for arrays.
1806 if (tex
->is_array
) {
1807 if (ctx
->levels_add_one
) {
1808 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1810 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1816 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1818 struct ir3_instruction
*phi
, **dst
;
1820 /* NOTE: phi's should be lowered to scalar at this point */
1821 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1823 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1825 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1826 1 + exec_list_length(&nphi
->srcs
));
1827 ir3_reg_create(phi
, 0, 0); /* dst */
1828 phi
->phi
.nphi
= nphi
;
1833 /* phi instructions are left partially constructed. We don't resolve
1834 * their srcs until the end of the block, since (eg. loops) one of
1835 * the phi's srcs might be defined after the phi due to back edges in
1839 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1841 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1842 nir_phi_instr
*nphi
;
1844 /* phi's only come at start of block: */
1845 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1848 if (!instr
->phi
.nphi
)
1851 nphi
= instr
->phi
.nphi
;
1852 instr
->phi
.nphi
= NULL
;
1854 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1855 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1856 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1860 resolve_array_phis(ctx
, block
);
1864 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1866 switch (jump
->type
) {
1867 case nir_jump_break
:
1868 case nir_jump_continue
:
1869 /* I *think* we can simply just ignore this, and use the
1870 * successor block link to figure out where we need to
1871 * jump to for break/continue
1875 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1881 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1883 switch (instr
->type
) {
1884 case nir_instr_type_alu
:
1885 emit_alu(ctx
, nir_instr_as_alu(instr
));
1887 case nir_instr_type_intrinsic
:
1888 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1890 case nir_instr_type_load_const
:
1891 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1893 case nir_instr_type_ssa_undef
:
1894 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1896 case nir_instr_type_tex
: {
1897 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1898 /* couple tex instructions get special-cased:
1902 emit_tex_txs(ctx
, tex
);
1904 case nir_texop_query_levels
:
1905 emit_tex_query_levels(ctx
, tex
);
1913 case nir_instr_type_phi
:
1914 emit_phi(ctx
, nir_instr_as_phi(instr
));
1916 case nir_instr_type_jump
:
1917 emit_jump(ctx
, nir_instr_as_jump(instr
));
1919 case nir_instr_type_call
:
1920 case nir_instr_type_parallel_copy
:
1921 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1926 static struct ir3_block
*
1927 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1929 struct ir3_block
*block
;
1930 struct hash_entry
*entry
;
1931 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1935 block
= ir3_block_create(ctx
->ir
);
1936 block
->nblock
= nblock
;
1937 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1943 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1945 struct ir3_block
*block
= get_block(ctx
, nblock
);
1947 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1948 if (nblock
->successors
[i
]) {
1949 block
->successors
[i
] =
1950 get_block(ctx
, nblock
->successors
[i
]);
1955 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1957 nir_foreach_instr(nblock
, instr
) {
1958 emit_instr(ctx
, instr
);
1964 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1967 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1969 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1971 ctx
->block
->condition
=
1972 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1974 emit_cf_list(ctx
, &nif
->then_list
);
1975 emit_cf_list(ctx
, &nif
->else_list
);
1979 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1981 emit_cf_list(ctx
, &nloop
->body
);
1985 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1987 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1988 switch (node
->type
) {
1989 case nir_cf_node_block
:
1990 emit_block(ctx
, nir_cf_node_as_block(node
));
1992 case nir_cf_node_if
:
1993 emit_if(ctx
, nir_cf_node_as_if(node
));
1995 case nir_cf_node_loop
:
1996 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1998 case nir_cf_node_function
:
1999 compile_error(ctx
, "TODO\n");
2005 /* emit stream-out code. At this point, the current block is the original
2006 * (nir) end block, and nir ensures that all flow control paths terminate
2007 * into the end block. We re-purpose the original end block to generate
2008 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2009 * block holding stream-out write instructions, followed by the new end
2013 * p0.x = (vtxcnt < maxvtxcnt)
2014 * // succs: blockStreamOut, blockNewEnd
2017 * ... stream-out instructions ...
2018 * // succs: blockNewEnd
2024 emit_stream_out(struct ir3_compile
*ctx
)
2026 struct ir3_shader_variant
*v
= ctx
->so
;
2027 struct ir3
*ir
= ctx
->ir
;
2028 struct pipe_stream_output_info
*strmout
=
2029 &ctx
->so
->shader
->stream_output
;
2030 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2031 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2032 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2034 /* create vtxcnt input in input block at top of shader,
2035 * so that it is seen as live over the entire duration
2038 vtxcnt
= create_input(ctx
->in_block
, 0);
2039 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2041 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2043 /* at this point, we are at the original 'end' block,
2044 * re-purpose this block to stream-out condition, then
2045 * append stream-out block and new-end block
2047 orig_end_block
= ctx
->block
;
2049 stream_out_block
= ir3_block_create(ir
);
2050 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2052 new_end_block
= ir3_block_create(ir
);
2053 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2055 orig_end_block
->successors
[0] = stream_out_block
;
2056 orig_end_block
->successors
[1] = new_end_block
;
2057 stream_out_block
->successors
[0] = new_end_block
;
2059 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2060 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2061 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2062 cond
->cat2
.condition
= IR3_COND_LT
;
2064 /* condition goes on previous block to the conditional,
2065 * since it is used to pick which of the two successor
2068 orig_end_block
->condition
= cond
;
2070 /* switch to stream_out_block to generate the stream-out
2073 ctx
->block
= stream_out_block
;
2075 /* Calculate base addresses based on vtxcnt. Instructions
2076 * generated for bases not used in following loop will be
2077 * stripped out in the backend.
2079 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2080 unsigned stride
= strmout
->stride
[i
];
2081 struct ir3_instruction
*base
, *off
;
2083 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ IR3_TFBOS_OFF
, i
));
2085 /* 24-bit should be enough: */
2086 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2087 create_immed(ctx
->block
, stride
* 4), 0);
2089 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2092 /* Generate the per-output store instructions: */
2093 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2094 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2095 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2096 struct ir3_instruction
*base
, *out
, *stg
;
2098 base
= bases
[strmout
->output
[i
].output_buffer
];
2099 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2101 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2102 create_immed(ctx
->block
, 1), 0);
2103 stg
->cat6
.type
= TYPE_U32
;
2104 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2106 array_insert(ctx
->ir
->keeps
, stg
);
2110 /* and finally switch to the new_end_block: */
2111 ctx
->block
= new_end_block
;
2115 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2117 emit_cf_list(ctx
, &impl
->body
);
2118 emit_block(ctx
, impl
->end_block
);
2120 /* at this point, we should have a single empty block,
2121 * into which we emit the 'end' instruction.
2123 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2125 /* If stream-out (aka transform-feedback) enabled, emit the
2126 * stream-out instructions, followed by a new empty block (into
2127 * which the 'end' instruction lands).
2129 * NOTE: it is done in this order, rather than inserting before
2130 * we emit end_block, because NIR guarantees that all blocks
2131 * flow into end_block, and that end_block has no successors.
2132 * So by re-purposing end_block as the first block of stream-
2133 * out, we guarantee that all exit paths flow into the stream-
2136 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2137 !ctx
->so
->key
.binning_pass
) {
2138 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2139 emit_stream_out(ctx
);
2142 ir3_END(ctx
->block
);
2146 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2148 struct ir3_shader_variant
*so
= ctx
->so
;
2149 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2150 unsigned ncomp
= glsl_get_components(in
->type
);
2151 unsigned n
= in
->data
.driver_location
;
2152 unsigned slot
= in
->data
.location
;
2154 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2155 slot
, array_len
, ncomp
, n
);
2157 so
->inputs
[n
].slot
= slot
;
2158 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2159 so
->inputs
[n
].inloc
= ctx
->next_inloc
;
2160 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_NONE
;
2161 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2162 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2164 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2165 for (int i
= 0; i
< ncomp
; i
++) {
2166 struct ir3_instruction
*instr
= NULL
;
2167 unsigned idx
= (n
* 4) + i
;
2169 if (slot
== VARYING_SLOT_POS
) {
2170 so
->inputs
[n
].bary
= false;
2171 so
->frag_coord
= true;
2172 instr
= create_frag_coord(ctx
, i
);
2173 } else if (slot
== VARYING_SLOT_FACE
) {
2174 so
->inputs
[n
].bary
= false;
2175 so
->frag_face
= true;
2176 instr
= create_frag_face(ctx
, i
);
2178 bool use_ldlv
= false;
2180 /* detect the special case for front/back colors where
2181 * we need to do flat vs smooth shading depending on
2184 if (in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) {
2186 case VARYING_SLOT_COL0
:
2187 case VARYING_SLOT_COL1
:
2188 case VARYING_SLOT_BFC0
:
2189 case VARYING_SLOT_BFC1
:
2190 so
->inputs
[n
].rasterflat
= true;
2197 if (ctx
->flat_bypass
) {
2198 if ((so
->inputs
[n
].interpolate
== INTERP_QUALIFIER_FLAT
) ||
2199 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2203 so
->inputs
[n
].bary
= true;
2205 instr
= create_frag_input(ctx
,
2206 so
->inputs
[n
].inloc
+ i
- 8, use_ldlv
);
2209 ctx
->ir
->inputs
[idx
] = instr
;
2211 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2212 for (int i
= 0; i
< ncomp
; i
++) {
2213 unsigned idx
= (n
* 4) + i
;
2214 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2217 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2220 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2221 ctx
->next_inloc
+= ncomp
;
2222 so
->total_in
+= ncomp
;
2227 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2229 struct ir3_shader_variant
*so
= ctx
->so
;
2230 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2231 unsigned ncomp
= glsl_get_components(out
->type
);
2232 unsigned n
= out
->data
.driver_location
;
2233 unsigned slot
= out
->data
.location
;
2236 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2237 slot
, array_len
, ncomp
, n
);
2239 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2241 case FRAG_RESULT_DEPTH
:
2242 comp
= 2; /* tgsi will write to .z component */
2243 so
->writes_pos
= true;
2245 case FRAG_RESULT_COLOR
:
2249 if (slot
>= FRAG_RESULT_DATA0
)
2251 compile_error(ctx
, "unknown FS output name: %s\n",
2252 gl_frag_result_name(slot
));
2254 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2256 case VARYING_SLOT_POS
:
2257 so
->writes_pos
= true;
2259 case VARYING_SLOT_PSIZ
:
2260 so
->writes_psize
= true;
2262 case VARYING_SLOT_COL0
:
2263 case VARYING_SLOT_COL1
:
2264 case VARYING_SLOT_BFC0
:
2265 case VARYING_SLOT_BFC1
:
2266 case VARYING_SLOT_FOGC
:
2267 case VARYING_SLOT_CLIP_DIST0
:
2268 case VARYING_SLOT_CLIP_DIST1
:
2271 if (slot
>= VARYING_SLOT_VAR0
)
2273 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2275 compile_error(ctx
, "unknown VS output name: %s\n",
2276 gl_varying_slot_name(slot
));
2279 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2282 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2284 so
->outputs
[n
].slot
= slot
;
2285 so
->outputs
[n
].regid
= regid(n
, comp
);
2286 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2288 for (int i
= 0; i
< ncomp
; i
++) {
2289 unsigned idx
= (n
* 4) + i
;
2291 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2296 emit_instructions(struct ir3_compile
*ctx
)
2298 unsigned ninputs
, noutputs
;
2299 nir_function_impl
*fxn
= NULL
;
2301 /* Find the main function: */
2302 nir_foreach_overload(ctx
->s
, overload
) {
2303 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
2304 compile_assert(ctx
, overload
->impl
);
2305 fxn
= overload
->impl
;
2309 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2310 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2312 /* or vtx shaders, we need to leave room for sysvals:
2314 if (ctx
->so
->type
== SHADER_VERTEX
) {
2318 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2320 /* Create inputs in first block: */
2321 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2322 ctx
->in_block
= ctx
->block
;
2323 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2325 if (ctx
->so
->type
== SHADER_VERTEX
) {
2326 ctx
->ir
->ninputs
-= 8;
2329 /* for fragment shader, we have a single input register (usually
2330 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2332 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2333 // TODO maybe a helper for fi since we need it a few places..
2334 struct ir3_instruction
*instr
;
2335 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2336 ir3_reg_create(instr
, 0, 0);
2337 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2338 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2339 ctx
->frag_pos
= instr
;
2343 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->inputs
) {
2344 setup_input(ctx
, var
);
2347 /* Setup outputs: */
2348 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->outputs
) {
2349 setup_output(ctx
, var
);
2352 /* Setup variables (which should only be arrays): */
2353 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->globals
) {
2354 declare_var(ctx
, var
);
2357 /* And emit the body: */
2359 emit_function(ctx
, fxn
);
2361 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2362 resolve_phis(ctx
, block
);
2366 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2367 * for a fragment shader are just bary.f instructions. The *actual* inputs
2368 * from the hw perspective are the frag_pos and optionally frag_coord and
2372 fixup_frag_inputs(struct ir3_compile
*ctx
)
2374 struct ir3_shader_variant
*so
= ctx
->so
;
2375 struct ir3
*ir
= ctx
->ir
;
2376 struct ir3_instruction
**inputs
;
2377 struct ir3_instruction
*instr
;
2382 n
= 4; /* always have frag_pos */
2383 n
+= COND(so
->frag_face
, 4);
2384 n
+= COND(so
->frag_coord
, 4);
2386 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2388 if (so
->frag_face
) {
2389 /* this ultimately gets assigned to hr0.x so doesn't conflict
2390 * with frag_coord/frag_pos..
2392 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2393 ctx
->frag_face
->regs
[0]->num
= 0;
2395 /* remaining channels not used, but let's avoid confusing
2396 * other parts that expect inputs to come in groups of vec4
2398 inputs
[ir
->ninputs
++] = NULL
;
2399 inputs
[ir
->ninputs
++] = NULL
;
2400 inputs
[ir
->ninputs
++] = NULL
;
2403 /* since we don't know where to set the regid for frag_coord,
2404 * we have to use r0.x for it. But we don't want to *always*
2405 * use r1.x for frag_pos as that could increase the register
2406 * footprint on simple shaders:
2408 if (so
->frag_coord
) {
2409 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2410 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2411 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2412 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2414 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2415 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2416 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2417 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2420 /* we always have frag_pos: */
2421 so
->pos_regid
= regid
;
2424 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2425 instr
->regs
[0]->num
= regid
++;
2426 inputs
[ir
->ninputs
++] = instr
;
2427 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2430 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2431 instr
->regs
[0]->num
= regid
++;
2432 inputs
[ir
->ninputs
++] = instr
;
2433 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2435 ir
->inputs
= inputs
;
2439 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2440 struct ir3_shader_variant
*so
)
2442 struct ir3_compile
*ctx
;
2444 struct ir3_instruction
**inputs
;
2445 unsigned i
, j
, actual_in
;
2446 int ret
= 0, max_bary
;
2450 ctx
= compile_init(compiler
, so
, so
->shader
->tokens
);
2452 DBG("INIT failed!");
2457 emit_instructions(ctx
);
2460 DBG("EMIT failed!");
2465 ir
= so
->ir
= ctx
->ir
;
2467 /* keep track of the inputs from TGSI perspective.. */
2468 inputs
= ir
->inputs
;
2470 /* but fixup actual inputs for frag shader: */
2471 if (so
->type
== SHADER_FRAGMENT
)
2472 fixup_frag_inputs(ctx
);
2474 /* at this point, for binning pass, throw away unneeded outputs: */
2475 if (so
->key
.binning_pass
) {
2476 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2477 unsigned slot
= so
->outputs
[i
].slot
;
2479 /* throw away everything but first position/psize */
2480 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2482 so
->outputs
[j
] = so
->outputs
[i
];
2483 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2484 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2485 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2486 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2491 so
->outputs_count
= j
;
2492 ir
->noutputs
= j
* 4;
2495 /* if we want half-precision outputs, mark the output registers
2498 if (so
->key
.half_precision
) {
2499 for (i
= 0; i
< ir
->noutputs
; i
++) {
2500 struct ir3_instruction
*out
= ir
->outputs
[i
];
2503 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2504 /* output could be a fanout (ie. texture fetch output)
2505 * in which case we need to propagate the half-reg flag
2506 * up to the definer so that RA sees it:
2508 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2509 out
= out
->regs
[1]->instr
;
2510 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2513 if (out
->category
== 1) {
2514 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2519 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2520 printf("BEFORE CP:\n");
2526 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2527 printf("BEFORE GROUPING:\n");
2531 /* Group left/right neighbors, inserting mov's where needed to
2538 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2539 printf("AFTER DEPTH:\n");
2543 ret
= ir3_sched(ir
);
2545 DBG("SCHED failed!");
2549 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2550 printf("AFTER SCHED:\n");
2554 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2560 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2561 printf("AFTER RA:\n");
2565 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2567 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2568 printf("AFTER LEGALIZE:\n");
2572 /* fixup input/outputs: */
2573 for (i
= 0; i
< so
->outputs_count
; i
++) {
2574 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2575 /* preserve hack for depth output.. tgsi writes depth to .z,
2576 * but what we give the hw is the scalar register:
2578 if ((so
->type
== SHADER_FRAGMENT
) &&
2579 (so
->outputs
[i
].slot
== FRAG_RESULT_DEPTH
))
2580 so
->outputs
[i
].regid
+= 2;
2583 /* Note that some or all channels of an input may be unused: */
2585 for (i
= 0; i
< so
->inputs_count
; i
++) {
2586 unsigned j
, regid
= ~0, compmask
= 0;
2587 so
->inputs
[i
].ncomp
= 0;
2588 for (j
= 0; j
< 4; j
++) {
2589 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2591 compmask
|= (1 << j
);
2592 regid
= in
->regs
[0]->num
- j
;
2594 so
->inputs
[i
].ncomp
++;
2597 so
->inputs
[i
].regid
= regid
;
2598 so
->inputs
[i
].compmask
= compmask
;
2601 /* fragment shader always gets full vec4's even if it doesn't
2602 * fetch all components, but vertex shader we need to update
2603 * with the actual number of components fetch, otherwise thing
2604 * will hang due to mismaptch between VFD_DECODE's and
2607 if (so
->type
== SHADER_VERTEX
)
2608 so
->total_in
= actual_in
;
2610 so
->total_in
= align(max_bary
+ 1, 4);
2615 ir3_destroy(so
->ir
);