1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
41 #include "freedreno_util.h"
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
47 #include "instr-a3xx.h"
52 struct ir3_compiler
*compiler
;
54 const struct tgsi_token
*tokens
;
58 struct ir3_shader_variant
*so
;
60 struct ir3_block
*block
; /* the current block */
61 struct ir3_block
*in_block
; /* block created for shader inputs */
63 nir_function_impl
*impl
;
65 /* For fragment shaders, from the hw perspective the only
66 * actual input is r0.xy position register passed to bary.f.
67 * But TGSI doesn't know that, it still declares things as
68 * IN[] registers. So we do all the input tracking normally
69 * and fix things up after compile_instructions()
71 * NOTE that frag_pos is the hardware position (possibly it
72 * is actually an index or tag or some such.. it is *not*
73 * values that can be directly used for gl_FragCoord..)
75 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
77 /* For vertex shaders, keep track of the system values sources */
78 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
83 /* mapping from nir_variable to ir3_array: */
84 struct hash_table
*var_ht
;
87 /* a common pattern for indirect addressing is to request the
88 * same address register multiple times. To avoid generating
89 * duplicate instruction sequences (which our backend does not
90 * try to clean up, since that should be done as the NIR stage)
91 * we cache the address value generated for a given src value:
93 struct hash_table
*addr_ht
;
95 /* maps nir_block to ir3_block, mostly for the purposes of
96 * figuring out the blocks successors
98 struct hash_table
*block_ht
;
100 /* for calculating input/output positions/linkages: */
103 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
104 * so we need to use ldlv.u32 to load the varying directly:
108 /* on a3xx, we need to add one to # of array levels:
112 /* on a3xx, we need to scale up integer coords for isaml based
115 bool unminify_coords
;
117 /* for looking up which system value is which */
118 unsigned sysval_semantics
[8];
120 /* set if we encounter something we can't handle yet, so we
121 * can bail cleanly and fallback to TGSI compiler f/e
127 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
128 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
130 static struct nir_shader
*to_nir(const struct tgsi_token
*tokens
)
132 struct nir_shader_compiler_options options
= {
137 .native_integers
= true,
141 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
143 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
144 debug_printf("----------------------\n");
145 nir_print_shader(s
, stdout
);
146 debug_printf("----------------------\n");
149 nir_opt_global_to_local(s
);
150 nir_convert_to_ssa(s
);
156 nir_lower_vars_to_ssa(s
);
157 nir_lower_alu_to_scalar(s
);
158 nir_lower_phis_to_scalar(s
);
160 progress
|= nir_copy_prop(s
);
161 progress
|= nir_opt_dce(s
);
162 progress
|= nir_opt_cse(s
);
163 progress
|= ir3_nir_lower_if_else(s
);
164 progress
|= nir_opt_algebraic(s
);
165 progress
|= nir_opt_constant_folding(s
);
169 nir_remove_dead_variables(s
);
170 nir_validate_shader(s
);
172 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
173 debug_printf("----------------------\n");
174 nir_print_shader(s
, stdout
);
175 debug_printf("----------------------\n");
181 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
182 static const struct tgsi_token
*
183 lower_tgsi(struct ir3_compile
*ctx
, const struct tgsi_token
*tokens
,
184 struct ir3_shader_variant
*so
)
186 struct tgsi_shader_info info
;
187 struct tgsi_lowering_config lconfig
= {
188 .color_two_side
= so
->key
.color_two_side
,
193 case SHADER_FRAGMENT
:
195 lconfig
.saturate_s
= so
->key
.fsaturate_s
;
196 lconfig
.saturate_t
= so
->key
.fsaturate_t
;
197 lconfig
.saturate_r
= so
->key
.fsaturate_r
;
200 lconfig
.saturate_s
= so
->key
.vsaturate_s
;
201 lconfig
.saturate_t
= so
->key
.vsaturate_t
;
202 lconfig
.saturate_r
= so
->key
.vsaturate_r
;
206 if (ctx
->compiler
->gpu_id
>= 400) {
207 /* a4xx seems to have *no* sam.p */
208 lconfig
.lower_TXP
= ~0; /* lower all txp */
210 /* a3xx just needs to avoid sam.p for 3d tex */
211 lconfig
.lower_TXP
= (1 << TGSI_TEXTURE_3D
);
214 return tgsi_transform_lowering(&lconfig
, tokens
, &info
);
217 static struct ir3_compile
*
218 compile_init(struct ir3_compiler
*compiler
,
219 struct ir3_shader_variant
*so
,
220 const struct tgsi_token
*tokens
)
222 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
223 const struct tgsi_token
*lowered_tokens
;
225 if (compiler
->gpu_id
>= 400) {
226 /* need special handling for "flat" */
227 ctx
->flat_bypass
= true;
228 ctx
->levels_add_one
= false;
229 ctx
->unminify_coords
= false;
231 /* no special handling for "flat" */
232 ctx
->flat_bypass
= false;
233 ctx
->levels_add_one
= true;
234 ctx
->unminify_coords
= true;
237 ctx
->compiler
= compiler
;
241 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
242 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
243 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
244 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
245 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
246 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
247 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
248 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
250 lowered_tokens
= lower_tgsi(ctx
, tokens
, so
);
252 lowered_tokens
= tokens
;
253 ctx
->s
= to_nir(lowered_tokens
);
255 if (lowered_tokens
!= tokens
)
256 free((void *)lowered_tokens
);
258 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
260 /* Layout of constant registers:
262 * num_uniform * vec4 - user consts
263 * 4 * vec4 - UBO addresses
264 * if (vertex shader) {
265 * 1 * vec4 - driver params (IR3_DP_*)
268 * TODO this could be made more dynamic, to at least skip sections
269 * that we don't need..
272 /* reserve 4 (vec4) slots for ubo base addresses: */
273 so
->first_immediate
+= 4;
275 if (so
->type
== SHADER_VERTEX
) {
276 /* one (vec4) slot for driver params (see ir3_driver_param): */
277 so
->first_immediate
++;
284 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
287 va_start(ap
, format
);
288 _debug_vprintf(format
, ap
);
290 nir_print_shader(ctx
->s
, stdout
);
295 #define compile_assert(ctx, cond) do { \
296 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
300 compile_free(struct ir3_compile
*ctx
)
305 /* global per-array information: */
307 unsigned length
, aid
;
310 /* per-block array state: */
311 struct ir3_array_value
{
312 /* TODO drop length/aid, and just have ptr back to ir3_array */
313 unsigned length
, aid
;
314 /* initial array element values are phi's, other than for the
315 * entry block. The phi src's get added later in a resolve step
316 * after we have visited all the blocks, to account for back
319 struct ir3_instruction
**phis
;
320 /* current array element values (as block is processed). When
321 * the array phi's are resolved, it will contain the array state
322 * at exit of block, so successor blocks can use it to add their
325 struct ir3_instruction
*arr
[];
328 /* track array assignments per basic block. When an array is read
329 * outside of the same basic block, we can use NIR's dominance-frontier
330 * information to figure out where phi nodes are needed.
332 struct ir3_nir_block_data
{
334 /* indexed by array-id (aid): */
335 struct ir3_array_value
*arrs
[];
338 static struct ir3_nir_block_data
*
339 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
342 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
343 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
350 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
352 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
353 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
354 arr
->length
= length
;
355 arr
->aid
= ++ctx
->num_arrays
;
356 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
360 nir_block_pred(nir_block
*block
)
362 assert(block
->predecessors
->entries
< 2);
363 if (block
->predecessors
->entries
== 0)
365 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
368 static struct ir3_array_value
*
369 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
371 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
372 struct ir3_block
*block
= ctx
->block
;
373 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
374 struct ir3_array
*arr
= entry
->data
;
376 if (!bd
->arrs
[arr
->aid
]) {
377 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
378 (arr
->length
* sizeof(av
->arr
[0])));
379 struct ir3_array_value
*defn
= NULL
;
380 nir_block
*pred_block
;
382 av
->length
= arr
->length
;
385 /* For loops, we have to consider that we have not visited some
386 * of the blocks who should feed into the phi (ie. back-edges in
387 * the cfg).. for example:
390 * block { load_var; ... }
391 * if then block {} else block {}
392 * block { store_var; ... }
393 * if then block {} else block {}
397 * We can skip the phi if we can chase the block predecessors
398 * until finding the block previously defining the array without
399 * crossing a block that has more than one predecessor.
401 * Otherwise create phi's and resolve them as a post-pass after
402 * all the blocks have been visited (to handle back-edges).
405 for (pred_block
= block
->nblock
;
406 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
407 pred_block
= nir_block_pred(pred_block
)) {
408 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
409 struct ir3_nir_block_data
*pbd
= pblock
->bd
;
412 defn
= pbd
->arrs
[arr
->aid
];
416 /* only one possible definer: */
417 for (unsigned i
= 0; i
< arr
->length
; i
++)
418 av
->arr
[i
] = defn
->arr
[i
];
419 } else if (pred_block
) {
420 /* not the first block, and multiple potential definers: */
421 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
423 for (unsigned i
= 0; i
< arr
->length
; i
++) {
424 struct ir3_instruction
*phi
;
426 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
427 1 + ctx
->impl
->num_blocks
);
428 ir3_reg_create(phi
, 0, 0); /* dst */
430 /* phi's should go at head of block: */
431 list_delinit(&phi
->node
);
432 list_add(&phi
->node
, &block
->instr_list
);
434 av
->phis
[i
] = av
->arr
[i
] = phi
;
437 /* Some shaders end up reading array elements without
438 * first writing.. so initialize things to prevent null
441 for (unsigned i
= 0; i
< arr
->length
; i
++)
442 av
->arr
[i
] = create_immed(block
, 0);
445 bd
->arrs
[arr
->aid
] = av
;
448 return bd
->arrs
[arr
->aid
];
452 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
453 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
455 struct ir3_block
*block
;
456 struct ir3_nir_block_data
*bd
;
458 if (BITSET_TEST(visited
, nblock
->index
))
461 BITSET_SET(visited
, nblock
->index
);
463 block
= get_block(ctx
, nblock
);
466 if (bd
&& bd
->arrs
[av
->aid
]) {
467 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
468 for (unsigned i
= 0; i
< av
->length
; i
++) {
469 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
473 /* didn't find defn, recurse predecessors: */
474 struct set_entry
*entry
;
475 set_foreach(nblock
->predecessors
, entry
) {
476 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
482 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
484 struct ir3_nir_block_data
*bd
= block
->bd
;
485 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
490 /* TODO use nir dom_frontier to help us with this? */
492 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
493 struct ir3_array_value
*av
= bd
->arrs
[i
];
494 BITSET_WORD visited
[bitset_words
];
495 struct set_entry
*entry
;
497 if (!(av
&& av
->phis
))
500 memset(visited
, 0, sizeof(visited
));
501 set_foreach(block
->nblock
->predecessors
, entry
) {
502 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
507 /* allocate a n element value array (to be populated by caller) and
510 static struct ir3_instruction
**
511 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
513 struct ir3_instruction
**value
=
514 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
515 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
519 static struct ir3_instruction
**
520 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
523 return __get_dst(ctx
, &dst
->ssa
, n
);
525 return __get_dst(ctx
, dst
->reg
.reg
, n
);
529 static struct ir3_instruction
**
530 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
532 return __get_dst(ctx
, dst
, n
);
535 static struct ir3_instruction
**
536 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
538 struct hash_entry
*entry
;
540 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
542 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
544 compile_assert(ctx
, entry
);
548 static struct ir3_instruction
*
549 create_immed(struct ir3_block
*block
, uint32_t val
)
551 struct ir3_instruction
*mov
;
553 mov
= ir3_instr_create(block
, 1, 0);
554 mov
->cat1
.src_type
= TYPE_U32
;
555 mov
->cat1
.dst_type
= TYPE_U32
;
556 ir3_reg_create(mov
, 0, 0);
557 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
562 static struct ir3_instruction
*
563 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
565 struct ir3_instruction
*instr
, *immed
;
567 /* TODO in at least some cases, the backend could probably be
568 * made clever enough to propagate IR3_REG_HALF..
570 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
571 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
573 immed
= create_immed(block
, 2);
574 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
576 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
577 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
578 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
580 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
581 instr
->regs
[0]->num
= regid(REG_A0
, 0);
582 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
583 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
588 /* caches addr values to avoid generating multiple cov/shl/mova
589 * sequences for each use of a given NIR level src as address
591 static struct ir3_instruction
*
592 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
594 struct ir3_instruction
*addr
;
595 struct hash_entry
*entry
;
596 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
600 /* TODO do we need to cache per block? */
601 addr
= create_addr(ctx
->block
, src
);
602 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
607 static struct ir3_instruction
*
608 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
610 struct ir3_block
*b
= ctx
->block
;
611 struct ir3_instruction
*cond
;
613 /* NOTE: only cmps.*.* can write p0.x: */
614 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
615 cond
->cat2
.condition
= IR3_COND_NE
;
617 /* condition always goes in predicate register: */
618 cond
->regs
[0]->num
= regid(REG_P0
, 0);
623 static struct ir3_instruction
*
624 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
626 struct ir3_instruction
*mov
;
628 mov
= ir3_instr_create(ctx
->block
, 1, 0);
629 /* TODO get types right? */
630 mov
->cat1
.src_type
= TYPE_F32
;
631 mov
->cat1
.dst_type
= TYPE_F32
;
632 ir3_reg_create(mov
, 0, 0);
633 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
638 static struct ir3_instruction
*
639 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
640 struct ir3_instruction
*address
)
642 struct ir3_instruction
*mov
;
644 mov
= ir3_instr_create(ctx
->block
, 1, 0);
645 mov
->cat1
.src_type
= TYPE_U32
;
646 mov
->cat1
.dst_type
= TYPE_U32
;
647 ir3_reg_create(mov
, 0, 0);
648 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
650 ir3_instr_set_address(mov
, address
);
655 static struct ir3_instruction
*
656 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
659 struct ir3_instruction
*collect
;
664 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
665 ir3_reg_create(collect
, 0, 0); /* dst */
666 for (unsigned i
= 0; i
< arrsz
; i
++)
667 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
672 static struct ir3_instruction
*
673 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
674 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
676 struct ir3_block
*block
= ctx
->block
;
677 struct ir3_instruction
*mov
;
678 struct ir3_register
*src
;
680 mov
= ir3_instr_create(block
, 1, 0);
681 mov
->cat1
.src_type
= TYPE_U32
;
682 mov
->cat1
.dst_type
= TYPE_U32
;
683 ir3_reg_create(mov
, 0, 0);
684 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
685 src
->instr
= collect
;
689 ir3_instr_set_address(mov
, address
);
694 static struct ir3_instruction
*
695 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
696 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
697 struct ir3_instruction
*collect
)
699 struct ir3_block
*block
= ctx
->block
;
700 struct ir3_instruction
*mov
;
701 struct ir3_register
*dst
;
703 mov
= ir3_instr_create(block
, 1, 0);
704 mov
->cat1
.src_type
= TYPE_U32
;
705 mov
->cat1
.dst_type
= TYPE_U32
;
706 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
709 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
710 mov
->fanin
= collect
;
712 ir3_instr_set_address(mov
, address
);
717 static struct ir3_instruction
*
718 create_input(struct ir3_block
*block
, unsigned n
)
720 struct ir3_instruction
*in
;
722 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
723 in
->inout
.block
= block
;
724 ir3_reg_create(in
, n
, 0);
729 static struct ir3_instruction
*
730 create_frag_input(struct ir3_compile
*ctx
, unsigned n
, bool use_ldlv
)
732 struct ir3_block
*block
= ctx
->block
;
733 struct ir3_instruction
*instr
;
734 struct ir3_instruction
*inloc
= create_immed(block
, n
);
737 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
738 instr
->cat6
.type
= TYPE_U32
;
739 instr
->cat6
.iim_val
= 1;
741 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
742 instr
->regs
[2]->wrmask
= 0x3;
748 static struct ir3_instruction
*
749 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
751 struct ir3_block
*block
= ctx
->block
;
752 struct ir3_instruction
*instr
;
754 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
756 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
761 /* for frag_coord, we get unsigned values.. we need
762 * to subtract (integer) 8 and divide by 16 (right-
763 * shift by 4) then convert to float:
767 * mov.u32f32 dst, tmp
770 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
771 create_immed(block
, 8), 0);
772 instr
= ir3_SHR_B(block
, instr
, 0,
773 create_immed(block
, 4), 0);
774 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
780 /* seems that we can use these as-is: */
781 return ctx
->frag_coord
[comp
];
785 static struct ir3_instruction
*
786 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
788 struct ir3_block
*block
= ctx
->block
;
789 struct ir3_instruction
*instr
;
793 compile_assert(ctx
, !ctx
->frag_face
);
795 ctx
->frag_face
= create_input(block
, 0);
796 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
798 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
799 * positive vs negative float.. and piglit further seems to
800 * expect -1.0 or 1.0:
802 * mul.s tmp, hr0.x, 2
804 * mov.s32f32, dst, tmp
807 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
808 create_immed(block
, 2), 0);
809 instr
= ir3_ADD_S(block
, instr
, 0,
810 create_immed(block
, 1), 0);
811 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
816 return create_immed(block
, fui(0.0));
819 return create_immed(block
, fui(1.0));
823 static struct ir3_instruction
*
824 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
826 /* first four vec4 sysval's reserved for UBOs: */
827 unsigned r
= regid(ctx
->so
->first_driver_param
+ 4, dp
);
828 return create_uniform(ctx
, r
);
831 /* helper for instructions that produce multiple consecutive scalar
832 * outputs which need to have a split/fanout meta instruction inserted
835 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
836 struct ir3_instruction
*src
, unsigned n
)
838 struct ir3_instruction
*prev
= NULL
;
839 for (int i
= 0, j
= 0; i
< n
; i
++) {
840 struct ir3_instruction
*split
=
841 ir3_instr_create(block
, -1, OPC_META_FO
);
842 ir3_reg_create(split
, 0, IR3_REG_SSA
);
843 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
847 split
->cp
.left
= prev
;
848 split
->cp
.left_cnt
++;
849 prev
->cp
.right
= split
;
850 prev
->cp
.right_cnt
++;
854 if (src
->regs
[0]->wrmask
& (1 << i
))
860 * Adreno uses uint rather than having dedicated bool type,
861 * which (potentially) requires some conversion, in particular
862 * when using output of an bool instr to int input, or visa
866 * -------+---------+-------+-
870 * To convert from an adreno bool (uint) to nir, use:
872 * absneg.s dst, (neg)src
874 * To convert back in the other direction:
876 * absneg.s dst, (abs)arc
878 * The CP step can clean up the absneg.s that cancel each other
879 * out, and with a slight bit of extra cleverness (to recognize
880 * the instructions which produce either a 0 or 1) can eliminate
881 * the absneg.s's completely when an instruction that wants
882 * 0/1 consumes the result. For example, when a nir 'bcsel'
883 * consumes the result of 'feq'. So we should be able to get by
884 * without a boolean resolve step, and without incuring any
885 * extra penalty in instruction count.
888 /* NIR bool -> native (adreno): */
889 static struct ir3_instruction
*
890 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
892 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
895 /* native (adreno) -> NIR bool: */
896 static struct ir3_instruction
*
897 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
899 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
903 * alu/sfu instructions:
907 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
909 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
910 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
911 struct ir3_block
*b
= ctx
->block
;
913 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
915 /* Vectors are special in that they have non-scalarized writemasks,
916 * and just take the first swizzle channel for each argument in
917 * order into each writemask channel.
919 if ((alu
->op
== nir_op_vec2
) ||
920 (alu
->op
== nir_op_vec3
) ||
921 (alu
->op
== nir_op_vec4
)) {
923 for (int i
= 0; i
< info
->num_inputs
; i
++) {
924 nir_alu_src
*asrc
= &alu
->src
[i
];
926 compile_assert(ctx
, !asrc
->abs
);
927 compile_assert(ctx
, !asrc
->negate
);
929 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
931 src
[i
] = create_immed(ctx
->block
, 0);
932 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
938 /* General case: We can just grab the one used channel per src. */
939 for (int i
= 0; i
< info
->num_inputs
; i
++) {
940 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
941 nir_alu_src
*asrc
= &alu
->src
[i
];
943 compile_assert(ctx
, !asrc
->abs
);
944 compile_assert(ctx
, !asrc
->negate
);
946 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
948 compile_assert(ctx
, src
[i
]);
953 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
956 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
959 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
962 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
965 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
968 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
971 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
972 dst
[0]->cat2
.condition
= IR3_COND_NE
;
973 dst
[0] = ir3_n2b(b
, dst
[0]);
976 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
979 dst
[0] = ir3_b2n(b
, src
[0]);
982 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
983 dst
[0]->cat2
.condition
= IR3_COND_NE
;
984 dst
[0] = ir3_n2b(b
, dst
[0]);
988 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
991 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
994 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
997 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1000 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1003 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1006 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1009 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1012 dst
[0] = ir3_DSX(b
, src
[0], 0);
1013 dst
[0]->cat5
.type
= TYPE_F32
;
1016 dst
[0] = ir3_DSY(b
, src
[0], 0);
1017 dst
[0]->cat5
.type
= TYPE_F32
;
1021 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1022 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1023 dst
[0] = ir3_n2b(b
, dst
[0]);
1026 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1027 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1028 dst
[0] = ir3_n2b(b
, dst
[0]);
1031 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1032 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1033 dst
[0] = ir3_n2b(b
, dst
[0]);
1036 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1037 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1038 dst
[0] = ir3_n2b(b
, dst
[0]);
1041 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1044 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1047 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1049 case nir_op_fround_even
:
1050 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1053 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1057 dst
[0] = ir3_SIN(b
, src
[0], 0);
1060 dst
[0] = ir3_COS(b
, src
[0], 0);
1063 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1066 dst
[0] = ir3_RCP(b
, src
[0], 0);
1069 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1072 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1075 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1079 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1082 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1085 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1088 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1094 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1097 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1101 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1102 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1103 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1104 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1106 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1107 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1108 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1111 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1114 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1117 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1120 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1123 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1125 case nir_op_isign
: {
1126 /* maybe this would be sane to lower in nir.. */
1127 struct ir3_instruction
*neg
, *pos
;
1129 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1130 neg
->cat2
.condition
= IR3_COND_LT
;
1132 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1133 pos
->cat2
.condition
= IR3_COND_GT
;
1135 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1140 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1143 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1146 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1149 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1150 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1151 dst
[0] = ir3_n2b(b
, dst
[0]);
1154 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1155 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1156 dst
[0] = ir3_n2b(b
, dst
[0]);
1159 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1160 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1161 dst
[0] = ir3_n2b(b
, dst
[0]);
1164 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1165 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1166 dst
[0] = ir3_n2b(b
, dst
[0]);
1169 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1170 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1171 dst
[0] = ir3_n2b(b
, dst
[0]);
1174 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1175 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1176 dst
[0] = ir3_n2b(b
, dst
[0]);
1180 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1184 compile_error(ctx
, "Unhandled ALU op: %s\n",
1185 nir_op_infos
[alu
->op
].name
);
1190 /* handles direct/indirect UBO reads: */
1192 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1193 struct ir3_instruction
**dst
)
1195 struct ir3_block
*b
= ctx
->block
;
1196 struct ir3_instruction
*addr
, *src0
, *src1
;
1197 /* UBO addresses are the first driver params: */
1198 unsigned ubo
= regid(ctx
->so
->first_driver_param
, 0);
1199 unsigned off
= intr
->const_index
[0];
1201 /* First src is ubo index, which could either be an immed or not: */
1202 src0
= get_src(ctx
, &intr
->src
[0])[0];
1203 if (is_same_type_mov(src0
) &&
1204 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1205 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1207 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1210 if (intr
->intrinsic
== nir_intrinsic_load_ubo_indirect
) {
1211 /* For load_ubo_indirect, second src is indirect offset: */
1212 src1
= get_src(ctx
, &intr
->src
[1])[0];
1214 /* and add offset to addr: */
1215 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1218 /* if offset is to large to encode in the ldg, split it out: */
1219 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1220 /* split out the minimal amount to improve the odds that
1221 * cp can fit the immediate in the add.s instruction:
1223 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1224 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1228 for (int i
= 0; i
< intr
->num_components
; i
++) {
1229 struct ir3_instruction
*load
=
1230 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1231 load
->cat6
.type
= TYPE_U32
;
1232 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1237 /* handles array reads: */
1239 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1240 struct ir3_instruction
**dst
)
1242 nir_deref_var
*dvar
= intr
->variables
[0];
1243 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1244 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1246 compile_assert(ctx
, dvar
->deref
.child
&&
1247 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1249 switch (darr
->deref_array_type
) {
1250 case nir_deref_array_type_direct
:
1251 /* direct access does not require anything special: */
1252 for (int i
= 0; i
< intr
->num_components
; i
++) {
1253 unsigned n
= darr
->base_offset
* 4 + i
;
1254 compile_assert(ctx
, n
< arr
->length
);
1255 dst
[i
] = arr
->arr
[n
];
1258 case nir_deref_array_type_indirect
: {
1259 /* for indirect, we need to collect all the array elements: */
1260 struct ir3_instruction
*collect
=
1261 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1262 struct ir3_instruction
*addr
=
1263 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1264 for (int i
= 0; i
< intr
->num_components
; i
++) {
1265 unsigned n
= darr
->base_offset
* 4 + i
;
1266 compile_assert(ctx
, n
< arr
->length
);
1267 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1272 compile_error(ctx
, "Unhandled load deref type: %u\n",
1273 darr
->deref_array_type
);
1278 /* handles array writes: */
1280 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1282 nir_deref_var
*dvar
= intr
->variables
[0];
1283 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1284 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1285 struct ir3_instruction
**src
;
1287 compile_assert(ctx
, dvar
->deref
.child
&&
1288 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1290 src
= get_src(ctx
, &intr
->src
[0]);
1292 switch (darr
->deref_array_type
) {
1293 case nir_deref_array_type_direct
:
1294 /* direct access does not require anything special: */
1295 for (int i
= 0; i
< intr
->num_components
; i
++) {
1296 unsigned n
= darr
->base_offset
* 4 + i
;
1297 compile_assert(ctx
, n
< arr
->length
);
1298 arr
->arr
[n
] = src
[i
];
1301 case nir_deref_array_type_indirect
: {
1302 /* for indirect, create indirect-store and fan that out: */
1303 struct ir3_instruction
*collect
=
1304 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1305 struct ir3_instruction
*addr
=
1306 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1307 for (int i
= 0; i
< intr
->num_components
; i
++) {
1308 struct ir3_instruction
*store
;
1309 unsigned n
= darr
->base_offset
* 4 + i
;
1310 compile_assert(ctx
, n
< arr
->length
);
1312 store
= create_indirect_store(ctx
, arr
->length
,
1313 n
, src
[i
], addr
, collect
);
1315 store
->fanin
->fi
.aid
= arr
->aid
;
1317 /* TODO: probably split this out to be used for
1318 * store_output_indirect? or move this into
1319 * create_indirect_store()?
1321 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1322 struct ir3_instruction
*split
;
1324 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1326 ir3_reg_create(split
, 0, 0);
1327 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1329 arr
->arr
[j
] = split
;
1332 /* fixup fanout/split neighbors: */
1333 for (int i
= 0; i
< arr
->length
; i
++) {
1334 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1335 arr
->arr
[i
+1] : NULL
;
1336 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1337 arr
->arr
[i
-1] : NULL
;
1342 compile_error(ctx
, "Unhandled store deref type: %u\n",
1343 darr
->deref_array_type
);
1348 static void add_sysval_input(struct ir3_compile
*ctx
, unsigned name
,
1349 struct ir3_instruction
*instr
)
1351 struct ir3_shader_variant
*so
= ctx
->so
;
1352 unsigned r
= regid(so
->inputs_count
, 0);
1353 unsigned n
= so
->inputs_count
++;
1355 so
->inputs
[n
].semantic
= ir3_semantic_name(name
, 0);
1356 so
->inputs
[n
].compmask
= 1;
1357 so
->inputs
[n
].regid
= r
;
1358 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1361 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1362 ctx
->ir
->inputs
[r
] = instr
;
1366 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1368 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1369 struct ir3_instruction
**dst
, **src
;
1370 struct ir3_block
*b
= ctx
->block
;
1371 unsigned idx
= intr
->const_index
[0];
1373 if (info
->has_dest
) {
1374 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1379 switch (intr
->intrinsic
) {
1380 case nir_intrinsic_load_uniform
:
1381 for (int i
= 0; i
< intr
->num_components
; i
++) {
1382 unsigned n
= idx
* 4 + i
;
1383 dst
[i
] = create_uniform(ctx
, n
);
1386 case nir_intrinsic_load_uniform_indirect
:
1387 src
= get_src(ctx
, &intr
->src
[0]);
1388 for (int i
= 0; i
< intr
->num_components
; i
++) {
1389 unsigned n
= idx
* 4 + i
;
1390 dst
[i
] = create_uniform_indirect(ctx
, n
,
1391 get_addr(ctx
, src
[0]));
1393 /* NOTE: if relative addressing is used, we set constlen in
1394 * the compiler (to worst-case value) since we don't know in
1395 * the assembler what the max addr reg value can be:
1397 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1399 case nir_intrinsic_load_ubo
:
1400 case nir_intrinsic_load_ubo_indirect
:
1401 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1403 case nir_intrinsic_load_input
:
1404 for (int i
= 0; i
< intr
->num_components
; i
++) {
1405 unsigned n
= idx
* 4 + i
;
1406 dst
[i
] = ctx
->ir
->inputs
[n
];
1409 case nir_intrinsic_load_input_indirect
:
1410 src
= get_src(ctx
, &intr
->src
[0]);
1411 struct ir3_instruction
*collect
=
1412 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1413 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1414 for (int i
= 0; i
< intr
->num_components
; i
++) {
1415 unsigned n
= idx
* 4 + i
;
1416 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1420 case nir_intrinsic_load_var
:
1421 emit_intrinisic_load_var(ctx
, intr
, dst
);
1423 case nir_intrinsic_store_var
:
1424 emit_intrinisic_store_var(ctx
, intr
);
1426 case nir_intrinsic_store_output
:
1427 src
= get_src(ctx
, &intr
->src
[0]);
1428 for (int i
= 0; i
< intr
->num_components
; i
++) {
1429 unsigned n
= idx
* 4 + i
;
1430 ctx
->ir
->outputs
[n
] = src
[i
];
1433 case nir_intrinsic_load_base_vertex
:
1434 if (!ctx
->basevertex
) {
1435 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1436 add_sysval_input(ctx
, TGSI_SEMANTIC_BASEVERTEX
,
1439 dst
[0] = ctx
->basevertex
;
1441 case nir_intrinsic_load_vertex_id_zero_base
:
1442 if (!ctx
->vertex_id
) {
1443 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1444 add_sysval_input(ctx
, TGSI_SEMANTIC_VERTEXID_NOBASE
,
1447 dst
[0] = ctx
->vertex_id
;
1449 case nir_intrinsic_load_instance_id
:
1450 if (!ctx
->instance_id
) {
1451 ctx
->instance_id
= create_input(ctx
->block
, 0);
1452 add_sysval_input(ctx
, TGSI_SEMANTIC_INSTANCEID
,
1455 dst
[0] = ctx
->instance_id
;
1457 case nir_intrinsic_discard_if
:
1458 case nir_intrinsic_discard
: {
1459 struct ir3_instruction
*cond
, *kill
;
1461 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1462 /* conditional discard: */
1463 src
= get_src(ctx
, &intr
->src
[0]);
1464 cond
= ir3_b2n(b
, src
[0]);
1466 /* unconditional discard: */
1467 cond
= create_immed(b
, 1);
1470 /* NOTE: only cmps.*.* can write p0.x: */
1471 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1472 cond
->cat2
.condition
= IR3_COND_NE
;
1474 /* condition always goes in predicate register: */
1475 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1477 kill
= ir3_KILL(b
, cond
, 0);
1478 array_insert(ctx
->ir
->predicates
, kill
);
1480 array_insert(ctx
->ir
->keeps
, kill
);
1481 ctx
->so
->has_kill
= true;
1486 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1487 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1493 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1495 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1496 instr
->def
.num_components
);
1497 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1498 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1502 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1504 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1505 undef
->def
.num_components
);
1506 /* backend doesn't want undefined instructions, so just plug
1509 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1510 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1514 * texture fetch/sample instructions:
1518 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1520 unsigned coords
, flags
= 0;
1522 /* note: would use tex->coord_components.. except txs.. also,
1523 * since array index goes after shadow ref, we don't want to
1526 switch (tex
->sampler_dim
) {
1527 case GLSL_SAMPLER_DIM_1D
:
1528 case GLSL_SAMPLER_DIM_BUF
:
1531 case GLSL_SAMPLER_DIM_2D
:
1532 case GLSL_SAMPLER_DIM_RECT
:
1533 case GLSL_SAMPLER_DIM_EXTERNAL
:
1534 case GLSL_SAMPLER_DIM_MS
:
1537 case GLSL_SAMPLER_DIM_3D
:
1538 case GLSL_SAMPLER_DIM_CUBE
:
1540 flags
|= IR3_INSTR_3D
;
1543 unreachable("bad sampler_dim");
1547 flags
|= IR3_INSTR_S
;
1550 flags
|= IR3_INSTR_A
;
1557 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1559 struct ir3_block
*b
= ctx
->block
;
1560 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1561 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1562 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1563 unsigned i
, coords
, flags
;
1564 unsigned nsrc0
= 0, nsrc1
= 0;
1568 coord
= off
= ddx
= ddy
= NULL
;
1569 lod
= proj
= compare
= NULL
;
1571 /* TODO: might just be one component for gathers? */
1572 dst
= get_dst(ctx
, &tex
->dest
, 4);
1574 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1575 switch (tex
->src
[i
].src_type
) {
1576 case nir_tex_src_coord
:
1577 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1579 case nir_tex_src_bias
:
1580 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1583 case nir_tex_src_lod
:
1584 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1587 case nir_tex_src_comparitor
: /* shadow comparator */
1588 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1590 case nir_tex_src_projector
:
1591 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1594 case nir_tex_src_offset
:
1595 off
= get_src(ctx
, &tex
->src
[i
].src
);
1598 case nir_tex_src_ddx
:
1599 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1601 case nir_tex_src_ddy
:
1602 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1605 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1606 tex
->src
[i
].src_type
);
1612 case nir_texop_tex
: opc
= OPC_SAM
; break;
1613 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1614 case nir_texop_txl
: opc
= OPC_SAML
; break;
1615 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1616 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1617 case nir_texop_txf_ms
:
1621 case nir_texop_query_levels
:
1622 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1626 tex_info(tex
, &flags
, &coords
);
1628 /* scale up integer coords for TXF based on the LOD */
1629 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1631 for (i
= 0; i
< coords
; i
++)
1632 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1636 * lay out the first argument in the proper order:
1637 * - actual coordinates first
1638 * - shadow reference
1641 * - starting at offset 4, dpdx.xy, dpdy.xy
1643 * bias/lod go into the second arg
1646 /* insert tex coords: */
1647 for (i
= 0; i
< coords
; i
++)
1648 src0
[nsrc0
++] = coord
[i
];
1651 /* hw doesn't do 1d, so we treat it as 2d with
1652 * height of 1, and patch up the y coord.
1653 * TODO: y coord should be (int)0 in some cases..
1655 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1659 src0
[nsrc0
++] = compare
;
1662 src0
[nsrc0
++] = coord
[coords
];
1665 src0
[nsrc0
++] = proj
;
1666 flags
|= IR3_INSTR_P
;
1669 /* pad to 4, then ddx/ddy: */
1670 if (tex
->op
== nir_texop_txd
) {
1672 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1673 for (i
= 0; i
< coords
; i
++)
1674 src0
[nsrc0
++] = ddx
[i
];
1676 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1677 for (i
= 0; i
< coords
; i
++)
1678 src0
[nsrc0
++] = ddy
[i
];
1680 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1684 * second argument (if applicable):
1689 if (has_off
| has_lod
| has_bias
) {
1691 for (i
= 0; i
< coords
; i
++)
1692 src1
[nsrc1
++] = off
[i
];
1694 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1695 flags
|= IR3_INSTR_O
;
1698 if (has_lod
| has_bias
)
1699 src1
[nsrc1
++] = lod
;
1702 switch (tex
->dest_type
) {
1703 case nir_type_invalid
:
1704 case nir_type_float
:
1710 case nir_type_unsigned
:
1715 unreachable("bad dest_type");
1718 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1719 flags
, tex
->sampler_index
, tex
->sampler_index
,
1720 create_collect(b
, src0
, nsrc0
),
1721 create_collect(b
, src1
, nsrc1
));
1723 split_dest(b
, dst
, sam
, 4);
1727 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1729 struct ir3_block
*b
= ctx
->block
;
1730 struct ir3_instruction
**dst
, *sam
;
1732 dst
= get_dst(ctx
, &tex
->dest
, 1);
1734 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1735 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1737 /* even though there is only one component, since it ends
1738 * up in .z rather than .x, we need a split_dest()
1740 split_dest(b
, dst
, sam
, 3);
1742 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1743 * the value in TEX_CONST_0 is zero-based.
1745 if (ctx
->levels_add_one
)
1746 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1750 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1752 struct ir3_block
*b
= ctx
->block
;
1753 struct ir3_instruction
**dst
, *sam
, *lod
;
1754 unsigned flags
, coords
;
1756 tex_info(tex
, &flags
, &coords
);
1758 dst
= get_dst(ctx
, &tex
->dest
, 4);
1760 compile_assert(ctx
, tex
->num_srcs
== 1);
1761 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1763 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1765 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1766 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1768 split_dest(b
, dst
, sam
, 4);
1770 /* Array size actually ends up in .w rather than .z. This doesn't
1771 * matter for miplevel 0, but for higher mips the value in z is
1772 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1773 * returned, which means that we have to add 1 to it for arrays.
1775 if (tex
->is_array
) {
1776 if (ctx
->levels_add_one
) {
1777 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1779 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1785 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1787 struct ir3_instruction
*phi
, **dst
;
1789 /* NOTE: phi's should be lowered to scalar at this point */
1790 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1792 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1794 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1795 1 + exec_list_length(&nphi
->srcs
));
1796 ir3_reg_create(phi
, 0, 0); /* dst */
1797 phi
->phi
.nphi
= nphi
;
1802 /* phi instructions are left partially constructed. We don't resolve
1803 * their srcs until the end of the block, since (eg. loops) one of
1804 * the phi's srcs might be defined after the phi due to back edges in
1808 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1810 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1811 nir_phi_instr
*nphi
;
1813 /* phi's only come at start of block: */
1814 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1817 if (!instr
->phi
.nphi
)
1820 nphi
= instr
->phi
.nphi
;
1821 instr
->phi
.nphi
= NULL
;
1823 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1824 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1825 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1829 resolve_array_phis(ctx
, block
);
1833 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1835 switch (jump
->type
) {
1836 case nir_jump_break
:
1837 case nir_jump_continue
:
1838 /* I *think* we can simply just ignore this, and use the
1839 * successor block link to figure out where we need to
1840 * jump to for break/continue
1844 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1850 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1852 switch (instr
->type
) {
1853 case nir_instr_type_alu
:
1854 emit_alu(ctx
, nir_instr_as_alu(instr
));
1856 case nir_instr_type_intrinsic
:
1857 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1859 case nir_instr_type_load_const
:
1860 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1862 case nir_instr_type_ssa_undef
:
1863 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1865 case nir_instr_type_tex
: {
1866 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1867 /* couple tex instructions get special-cased:
1871 emit_tex_txs(ctx
, tex
);
1873 case nir_texop_query_levels
:
1874 emit_tex_query_levels(ctx
, tex
);
1882 case nir_instr_type_phi
:
1883 emit_phi(ctx
, nir_instr_as_phi(instr
));
1885 case nir_instr_type_jump
:
1886 emit_jump(ctx
, nir_instr_as_jump(instr
));
1888 case nir_instr_type_call
:
1889 case nir_instr_type_parallel_copy
:
1890 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1895 static struct ir3_block
*
1896 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1898 struct ir3_block
*block
;
1899 struct hash_entry
*entry
;
1900 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1904 block
= ir3_block_create(ctx
->ir
);
1905 block
->nblock
= nblock
;
1906 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1912 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1914 struct ir3_block
*block
= get_block(ctx
, nblock
);
1916 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1917 if (nblock
->successors
[i
]) {
1918 block
->successors
[i
] =
1919 get_block(ctx
, nblock
->successors
[i
]);
1924 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1926 nir_foreach_instr(nblock
, instr
) {
1927 emit_instr(ctx
, instr
);
1933 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1936 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1938 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1940 ctx
->block
->condition
=
1941 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1943 emit_cf_list(ctx
, &nif
->then_list
);
1944 emit_cf_list(ctx
, &nif
->else_list
);
1948 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1950 emit_cf_list(ctx
, &nloop
->body
);
1954 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1956 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1957 switch (node
->type
) {
1958 case nir_cf_node_block
:
1959 emit_block(ctx
, nir_cf_node_as_block(node
));
1961 case nir_cf_node_if
:
1962 emit_if(ctx
, nir_cf_node_as_if(node
));
1964 case nir_cf_node_loop
:
1965 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1967 case nir_cf_node_function
:
1968 compile_error(ctx
, "TODO\n");
1975 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
1977 emit_cf_list(ctx
, &impl
->body
);
1978 emit_block(ctx
, impl
->end_block
);
1980 /* at this point, we should have a single empty block,
1981 * into which we emit the 'end' instruction.
1983 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
1984 ir3_END(ctx
->block
);
1988 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
1990 struct ir3_shader_variant
*so
= ctx
->so
;
1991 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
1992 unsigned ncomp
= glsl_get_components(in
->type
);
1993 /* XXX: map loc slots to semantics */
1994 unsigned semantic_name
= in
->data
.location
;
1995 unsigned semantic_index
= in
->data
.index
;
1996 unsigned n
= in
->data
.driver_location
;
1998 DBG("; in: %u:%u, len=%ux%u, loc=%u",
1999 semantic_name
, semantic_index
, array_len
,
2002 so
->inputs
[n
].semantic
=
2003 ir3_semantic_name(semantic_name
, semantic_index
);
2004 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2005 so
->inputs
[n
].inloc
= ctx
->next_inloc
;
2006 so
->inputs
[n
].interpolate
= 0;
2007 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2009 /* the fdN_program_emit() code expects tgsi consts here, so map
2010 * things back to tgsi for now:
2012 switch (in
->data
.interpolation
) {
2013 case INTERP_QUALIFIER_FLAT
:
2014 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
2016 case INTERP_QUALIFIER_NOPERSPECTIVE
:
2017 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_LINEAR
;
2019 case INTERP_QUALIFIER_SMOOTH
:
2020 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_PERSPECTIVE
;
2024 for (int i
= 0; i
< ncomp
; i
++) {
2025 struct ir3_instruction
*instr
= NULL
;
2026 unsigned idx
= (n
* 4) + i
;
2028 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2029 if (semantic_name
== TGSI_SEMANTIC_POSITION
) {
2030 so
->inputs
[n
].bary
= false;
2031 so
->frag_coord
= true;
2032 instr
= create_frag_coord(ctx
, i
);
2033 } else if (semantic_name
== TGSI_SEMANTIC_FACE
) {
2034 so
->inputs
[n
].bary
= false;
2035 so
->frag_face
= true;
2036 instr
= create_frag_face(ctx
, i
);
2038 bool use_ldlv
= false;
2040 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2041 * from the semantic name:
2043 if ((in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) &&
2044 ((semantic_name
== TGSI_SEMANTIC_COLOR
) ||
2045 (semantic_name
== TGSI_SEMANTIC_BCOLOR
)))
2046 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_COLOR
;
2048 if (ctx
->flat_bypass
) {
2049 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2050 * from the semantic name:
2052 switch (so
->inputs
[n
].interpolate
) {
2053 case TGSI_INTERPOLATE_COLOR
:
2054 if (!ctx
->so
->key
.rasterflat
)
2057 case TGSI_INTERPOLATE_CONSTANT
:
2063 so
->inputs
[n
].bary
= true;
2065 instr
= create_frag_input(ctx
,
2066 so
->inputs
[n
].inloc
+ i
- 8, use_ldlv
);
2069 instr
= create_input(ctx
->block
, idx
);
2072 ctx
->ir
->inputs
[idx
] = instr
;
2075 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2076 ctx
->next_inloc
+= ncomp
;
2077 so
->total_in
+= ncomp
;
2082 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2084 struct ir3_shader_variant
*so
= ctx
->so
;
2085 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2086 unsigned ncomp
= glsl_get_components(out
->type
);
2087 /* XXX: map loc slots to semantics */
2088 unsigned semantic_name
= out
->data
.location
;
2089 unsigned semantic_index
= out
->data
.index
;
2090 unsigned n
= out
->data
.driver_location
;
2093 DBG("; out: %u:%u, len=%ux%u, loc=%u",
2094 semantic_name
, semantic_index
, array_len
,
2097 if (ctx
->so
->type
== SHADER_VERTEX
) {
2098 switch (semantic_name
) {
2099 case TGSI_SEMANTIC_POSITION
:
2100 so
->writes_pos
= true;
2102 case TGSI_SEMANTIC_PSIZE
:
2103 so
->writes_psize
= true;
2105 case TGSI_SEMANTIC_COLOR
:
2106 case TGSI_SEMANTIC_BCOLOR
:
2107 case TGSI_SEMANTIC_GENERIC
:
2108 case TGSI_SEMANTIC_FOG
:
2109 case TGSI_SEMANTIC_TEXCOORD
:
2112 compile_error(ctx
, "unknown VS semantic name: %s\n",
2113 tgsi_semantic_names
[semantic_name
]);
2116 switch (semantic_name
) {
2117 case TGSI_SEMANTIC_POSITION
:
2118 comp
= 2; /* tgsi will write to .z component */
2119 so
->writes_pos
= true;
2121 case TGSI_SEMANTIC_COLOR
:
2122 if (semantic_index
== -1) {
2128 compile_error(ctx
, "unknown FS semantic name: %s\n",
2129 tgsi_semantic_names
[semantic_name
]);
2133 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2135 so
->outputs
[n
].semantic
=
2136 ir3_semantic_name(semantic_name
, semantic_index
);
2137 so
->outputs
[n
].regid
= regid(n
, comp
);
2138 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2140 for (int i
= 0; i
< ncomp
; i
++) {
2141 unsigned idx
= (n
* 4) + i
;
2143 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2148 emit_instructions(struct ir3_compile
*ctx
)
2150 unsigned ninputs
, noutputs
;
2151 nir_function_impl
*fxn
= NULL
;
2153 /* Find the main function: */
2154 nir_foreach_overload(ctx
->s
, overload
) {
2155 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
2156 compile_assert(ctx
, overload
->impl
);
2157 fxn
= overload
->impl
;
2161 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2162 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2164 /* or vtx shaders, we need to leave room for sysvals:
2166 if (ctx
->so
->type
== SHADER_VERTEX
) {
2170 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2172 /* Create inputs in first block: */
2173 ctx
->block
= get_block(ctx
, fxn
->start_block
);
2174 ctx
->in_block
= ctx
->block
;
2175 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2177 if (ctx
->so
->type
== SHADER_VERTEX
) {
2178 ctx
->ir
->ninputs
-= 8;
2181 /* for fragment shader, we have a single input register (usually
2182 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2184 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2185 // TODO maybe a helper for fi since we need it a few places..
2186 struct ir3_instruction
*instr
;
2187 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2188 ir3_reg_create(instr
, 0, 0);
2189 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2190 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2191 ctx
->frag_pos
= instr
;
2195 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->inputs
) {
2196 setup_input(ctx
, var
);
2199 /* Setup outputs: */
2200 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->outputs
) {
2201 setup_output(ctx
, var
);
2204 /* Setup variables (which should only be arrays): */
2205 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->globals
) {
2206 declare_var(ctx
, var
);
2209 /* And emit the body: */
2211 emit_function(ctx
, fxn
);
2213 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2214 resolve_phis(ctx
, block
);
2218 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2219 * for a fragment shader are just bary.f instructions. The *actual* inputs
2220 * from the hw perspective are the frag_pos and optionally frag_coord and
2224 fixup_frag_inputs(struct ir3_compile
*ctx
)
2226 struct ir3_shader_variant
*so
= ctx
->so
;
2227 struct ir3
*ir
= ctx
->ir
;
2228 struct ir3_instruction
**inputs
;
2229 struct ir3_instruction
*instr
;
2234 n
= 4; /* always have frag_pos */
2235 n
+= COND(so
->frag_face
, 4);
2236 n
+= COND(so
->frag_coord
, 4);
2238 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2240 if (so
->frag_face
) {
2241 /* this ultimately gets assigned to hr0.x so doesn't conflict
2242 * with frag_coord/frag_pos..
2244 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2245 ctx
->frag_face
->regs
[0]->num
= 0;
2247 /* remaining channels not used, but let's avoid confusing
2248 * other parts that expect inputs to come in groups of vec4
2250 inputs
[ir
->ninputs
++] = NULL
;
2251 inputs
[ir
->ninputs
++] = NULL
;
2252 inputs
[ir
->ninputs
++] = NULL
;
2255 /* since we don't know where to set the regid for frag_coord,
2256 * we have to use r0.x for it. But we don't want to *always*
2257 * use r1.x for frag_pos as that could increase the register
2258 * footprint on simple shaders:
2260 if (so
->frag_coord
) {
2261 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2262 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2263 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2264 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2266 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2267 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2268 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2269 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2272 /* we always have frag_pos: */
2273 so
->pos_regid
= regid
;
2276 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2277 instr
->regs
[0]->num
= regid
++;
2278 inputs
[ir
->ninputs
++] = instr
;
2279 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2282 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2283 instr
->regs
[0]->num
= regid
++;
2284 inputs
[ir
->ninputs
++] = instr
;
2285 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2287 ir
->inputs
= inputs
;
2291 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2292 struct ir3_shader_variant
*so
)
2294 struct ir3_compile
*ctx
;
2296 struct ir3_instruction
**inputs
;
2297 unsigned i
, j
, actual_in
;
2298 int ret
= 0, max_bary
;
2302 ctx
= compile_init(compiler
, so
, so
->shader
->tokens
);
2304 DBG("INIT failed!");
2309 emit_instructions(ctx
);
2312 DBG("EMIT failed!");
2317 ir
= so
->ir
= ctx
->ir
;
2319 /* keep track of the inputs from TGSI perspective.. */
2320 inputs
= ir
->inputs
;
2322 /* but fixup actual inputs for frag shader: */
2323 if (so
->type
== SHADER_FRAGMENT
)
2324 fixup_frag_inputs(ctx
);
2326 /* at this point, for binning pass, throw away unneeded outputs: */
2327 if (so
->key
.binning_pass
) {
2328 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2329 unsigned name
= sem2name(so
->outputs
[i
].semantic
);
2330 unsigned idx
= sem2idx(so
->outputs
[i
].semantic
);
2332 /* throw away everything but first position/psize */
2333 if ((idx
== 0) && ((name
== TGSI_SEMANTIC_POSITION
) ||
2334 (name
== TGSI_SEMANTIC_PSIZE
))) {
2336 so
->outputs
[j
] = so
->outputs
[i
];
2337 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2338 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2339 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2340 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2345 so
->outputs_count
= j
;
2346 ir
->noutputs
= j
* 4;
2349 /* if we want half-precision outputs, mark the output registers
2352 if (so
->key
.half_precision
) {
2353 for (i
= 0; i
< ir
->noutputs
; i
++) {
2354 struct ir3_instruction
*out
= ir
->outputs
[i
];
2357 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2358 /* output could be a fanout (ie. texture fetch output)
2359 * in which case we need to propagate the half-reg flag
2360 * up to the definer so that RA sees it:
2362 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2363 out
= out
->regs
[1]->instr
;
2364 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2367 if (out
->category
== 1) {
2368 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2373 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2374 printf("BEFORE CP:\n");
2380 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2381 printf("BEFORE GROUPING:\n");
2385 /* Group left/right neighbors, inserting mov's where needed to
2392 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2393 printf("AFTER DEPTH:\n");
2397 ret
= ir3_sched(ir
);
2399 DBG("SCHED failed!");
2403 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2404 printf("AFTER SCHED:\n");
2408 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2414 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2415 printf("AFTER RA:\n");
2419 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2421 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2422 printf("AFTER LEGALIZE:\n");
2426 /* fixup input/outputs: */
2427 for (i
= 0; i
< so
->outputs_count
; i
++) {
2428 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2429 /* preserve hack for depth output.. tgsi writes depth to .z,
2430 * but what we give the hw is the scalar register:
2432 if ((so
->type
== SHADER_FRAGMENT
) &&
2433 (sem2name(so
->outputs
[i
].semantic
) == TGSI_SEMANTIC_POSITION
))
2434 so
->outputs
[i
].regid
+= 2;
2437 /* Note that some or all channels of an input may be unused: */
2439 for (i
= 0; i
< so
->inputs_count
; i
++) {
2440 unsigned j
, regid
= ~0, compmask
= 0;
2441 so
->inputs
[i
].ncomp
= 0;
2442 for (j
= 0; j
< 4; j
++) {
2443 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2445 compmask
|= (1 << j
);
2446 regid
= in
->regs
[0]->num
- j
;
2448 so
->inputs
[i
].ncomp
++;
2451 so
->inputs
[i
].regid
= regid
;
2452 so
->inputs
[i
].compmask
= compmask
;
2455 /* fragment shader always gets full vec4's even if it doesn't
2456 * fetch all components, but vertex shader we need to update
2457 * with the actual number of components fetch, otherwise thing
2458 * will hang due to mismaptch between VFD_DECODE's and
2461 if (so
->type
== SHADER_VERTEX
)
2462 so
->total_in
= actual_in
;
2464 so
->total_in
= align(max_bary
+ 1, 4);
2469 ir3_destroy(so
->ir
);