1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
41 #include "freedreno_util.h"
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
47 #include "instr-a3xx.h"
52 struct ir3_compiler
*compiler
;
54 const struct tgsi_token
*tokens
;
58 struct ir3_shader_variant
*so
;
60 struct ir3_block
*block
; /* the current block */
61 struct ir3_block
*in_block
; /* block created for shader inputs */
63 nir_function_impl
*impl
;
65 /* For fragment shaders, from the hw perspective the only
66 * actual input is r0.xy position register passed to bary.f.
67 * But TGSI doesn't know that, it still declares things as
68 * IN[] registers. So we do all the input tracking normally
69 * and fix things up after compile_instructions()
71 * NOTE that frag_pos is the hardware position (possibly it
72 * is actually an index or tag or some such.. it is *not*
73 * values that can be directly used for gl_FragCoord..)
75 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
77 /* For vertex shaders, keep track of the system values sources */
78 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
83 /* mapping from nir_variable to ir3_array: */
84 struct hash_table
*var_ht
;
87 /* a common pattern for indirect addressing is to request the
88 * same address register multiple times. To avoid generating
89 * duplicate instruction sequences (which our backend does not
90 * try to clean up, since that should be done as the NIR stage)
91 * we cache the address value generated for a given src value:
93 struct hash_table
*addr_ht
;
95 /* maps nir_block to ir3_block, mostly for the purposes of
96 * figuring out the blocks successors
98 struct hash_table
*block_ht
;
100 /* for calculating input/output positions/linkages: */
103 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
104 * so we need to use ldlv.u32 to load the varying directly:
108 /* on a3xx, we need to add one to # of array levels:
112 /* on a3xx, we need to scale up integer coords for isaml based
115 bool unminify_coords
;
117 /* for looking up which system value is which */
118 unsigned sysval_semantics
[8];
120 /* set if we encounter something we can't handle yet, so we
121 * can bail cleanly and fallback to TGSI compiler f/e
127 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
128 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
130 static struct nir_shader
*to_nir(const struct tgsi_token
*tokens
)
132 struct nir_shader_compiler_options options
= {
137 .native_integers
= true,
141 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
143 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
144 debug_printf("----------------------\n");
145 nir_print_shader(s
, stdout
);
146 debug_printf("----------------------\n");
149 nir_opt_global_to_local(s
);
150 nir_convert_to_ssa(s
);
156 nir_lower_vars_to_ssa(s
);
157 nir_lower_alu_to_scalar(s
);
158 nir_lower_phis_to_scalar(s
);
160 progress
|= nir_copy_prop(s
);
161 progress
|= nir_opt_dce(s
);
162 progress
|= nir_opt_cse(s
);
163 progress
|= ir3_nir_lower_if_else(s
);
164 progress
|= nir_opt_algebraic(s
);
165 progress
|= nir_opt_constant_folding(s
);
169 nir_remove_dead_variables(s
);
170 nir_validate_shader(s
);
172 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
173 debug_printf("----------------------\n");
174 nir_print_shader(s
, stdout
);
175 debug_printf("----------------------\n");
181 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
182 static const struct tgsi_token
*
183 lower_tgsi(struct ir3_compile
*ctx
, const struct tgsi_token
*tokens
,
184 struct ir3_shader_variant
*so
)
186 struct tgsi_shader_info info
;
187 struct tgsi_lowering_config lconfig
= {
188 .color_two_side
= so
->key
.color_two_side
,
193 case SHADER_FRAGMENT
:
195 lconfig
.saturate_s
= so
->key
.fsaturate_s
;
196 lconfig
.saturate_t
= so
->key
.fsaturate_t
;
197 lconfig
.saturate_r
= so
->key
.fsaturate_r
;
200 lconfig
.saturate_s
= so
->key
.vsaturate_s
;
201 lconfig
.saturate_t
= so
->key
.vsaturate_t
;
202 lconfig
.saturate_r
= so
->key
.vsaturate_r
;
206 if (ctx
->compiler
->gpu_id
>= 400) {
207 /* a4xx seems to have *no* sam.p */
208 lconfig
.lower_TXP
= ~0; /* lower all txp */
210 /* a3xx just needs to avoid sam.p for 3d tex */
211 lconfig
.lower_TXP
= (1 << TGSI_TEXTURE_3D
);
214 return tgsi_transform_lowering(&lconfig
, tokens
, &info
);
217 static struct ir3_compile
*
218 compile_init(struct ir3_compiler
*compiler
,
219 struct ir3_shader_variant
*so
,
220 const struct tgsi_token
*tokens
)
222 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
223 const struct tgsi_token
*lowered_tokens
;
225 if (compiler
->gpu_id
>= 400) {
226 /* need special handling for "flat" */
227 ctx
->flat_bypass
= true;
228 ctx
->levels_add_one
= false;
229 ctx
->unminify_coords
= false;
231 /* no special handling for "flat" */
232 ctx
->flat_bypass
= false;
233 ctx
->levels_add_one
= true;
234 ctx
->unminify_coords
= true;
237 ctx
->compiler
= compiler
;
241 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
242 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
243 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
244 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
245 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
246 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
247 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
248 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
250 lowered_tokens
= lower_tgsi(ctx
, tokens
, so
);
252 lowered_tokens
= tokens
;
253 ctx
->s
= to_nir(lowered_tokens
);
255 if (lowered_tokens
!= tokens
)
256 free((void *)lowered_tokens
);
258 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
260 /* Layout of constant registers:
262 * num_uniform * vec4 - user consts
263 * 4 * vec4 - UBO addresses
264 * if (vertex shader) {
265 * 1 * vec4 - driver params (IR3_DP_*)
266 * 1 * vec4 - stream-out addresses
269 * TODO this could be made more dynamic, to at least skip sections
270 * that we don't need..
273 /* reserve 4 (vec4) slots for ubo base addresses: */
274 so
->first_immediate
+= 4;
276 if (so
->type
== SHADER_VERTEX
) {
277 /* one (vec4) slot for driver params (see ir3_driver_param): */
278 so
->first_immediate
++;
279 /* one (vec4) slot for stream-output base addresses: */
280 so
->first_immediate
++;
287 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
290 va_start(ap
, format
);
291 _debug_vprintf(format
, ap
);
293 nir_print_shader(ctx
->s
, stdout
);
298 #define compile_assert(ctx, cond) do { \
299 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
303 compile_free(struct ir3_compile
*ctx
)
308 /* global per-array information: */
310 unsigned length
, aid
;
313 /* per-block array state: */
314 struct ir3_array_value
{
315 /* TODO drop length/aid, and just have ptr back to ir3_array */
316 unsigned length
, aid
;
317 /* initial array element values are phi's, other than for the
318 * entry block. The phi src's get added later in a resolve step
319 * after we have visited all the blocks, to account for back
322 struct ir3_instruction
**phis
;
323 /* current array element values (as block is processed). When
324 * the array phi's are resolved, it will contain the array state
325 * at exit of block, so successor blocks can use it to add their
328 struct ir3_instruction
*arr
[];
331 /* track array assignments per basic block. When an array is read
332 * outside of the same basic block, we can use NIR's dominance-frontier
333 * information to figure out where phi nodes are needed.
335 struct ir3_nir_block_data
{
337 /* indexed by array-id (aid): */
338 struct ir3_array_value
*arrs
[];
341 static struct ir3_nir_block_data
*
342 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
345 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
346 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
353 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
355 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
356 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
357 arr
->length
= length
;
358 arr
->aid
= ++ctx
->num_arrays
;
359 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
363 nir_block_pred(nir_block
*block
)
365 assert(block
->predecessors
->entries
< 2);
366 if (block
->predecessors
->entries
== 0)
368 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
371 static struct ir3_array_value
*
372 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
374 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
375 struct ir3_block
*block
= ctx
->block
;
376 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
377 struct ir3_array
*arr
= entry
->data
;
379 if (!bd
->arrs
[arr
->aid
]) {
380 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
381 (arr
->length
* sizeof(av
->arr
[0])));
382 struct ir3_array_value
*defn
= NULL
;
383 nir_block
*pred_block
;
385 av
->length
= arr
->length
;
388 /* For loops, we have to consider that we have not visited some
389 * of the blocks who should feed into the phi (ie. back-edges in
390 * the cfg).. for example:
393 * block { load_var; ... }
394 * if then block {} else block {}
395 * block { store_var; ... }
396 * if then block {} else block {}
400 * We can skip the phi if we can chase the block predecessors
401 * until finding the block previously defining the array without
402 * crossing a block that has more than one predecessor.
404 * Otherwise create phi's and resolve them as a post-pass after
405 * all the blocks have been visited (to handle back-edges).
408 for (pred_block
= block
->nblock
;
409 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
410 pred_block
= nir_block_pred(pred_block
)) {
411 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
412 struct ir3_nir_block_data
*pbd
= pblock
->bd
;
415 defn
= pbd
->arrs
[arr
->aid
];
419 /* only one possible definer: */
420 for (unsigned i
= 0; i
< arr
->length
; i
++)
421 av
->arr
[i
] = defn
->arr
[i
];
422 } else if (pred_block
) {
423 /* not the first block, and multiple potential definers: */
424 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
426 for (unsigned i
= 0; i
< arr
->length
; i
++) {
427 struct ir3_instruction
*phi
;
429 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
430 1 + ctx
->impl
->num_blocks
);
431 ir3_reg_create(phi
, 0, 0); /* dst */
433 /* phi's should go at head of block: */
434 list_delinit(&phi
->node
);
435 list_add(&phi
->node
, &block
->instr_list
);
437 av
->phis
[i
] = av
->arr
[i
] = phi
;
440 /* Some shaders end up reading array elements without
441 * first writing.. so initialize things to prevent null
444 for (unsigned i
= 0; i
< arr
->length
; i
++)
445 av
->arr
[i
] = create_immed(block
, 0);
448 bd
->arrs
[arr
->aid
] = av
;
451 return bd
->arrs
[arr
->aid
];
455 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
456 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
458 struct ir3_block
*block
;
459 struct ir3_nir_block_data
*bd
;
461 if (BITSET_TEST(visited
, nblock
->index
))
464 BITSET_SET(visited
, nblock
->index
);
466 block
= get_block(ctx
, nblock
);
469 if (bd
&& bd
->arrs
[av
->aid
]) {
470 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
471 for (unsigned i
= 0; i
< av
->length
; i
++) {
472 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
476 /* didn't find defn, recurse predecessors: */
477 struct set_entry
*entry
;
478 set_foreach(nblock
->predecessors
, entry
) {
479 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
485 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
487 struct ir3_nir_block_data
*bd
= block
->bd
;
488 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
493 /* TODO use nir dom_frontier to help us with this? */
495 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
496 struct ir3_array_value
*av
= bd
->arrs
[i
];
497 BITSET_WORD visited
[bitset_words
];
498 struct set_entry
*entry
;
500 if (!(av
&& av
->phis
))
503 memset(visited
, 0, sizeof(visited
));
504 set_foreach(block
->nblock
->predecessors
, entry
) {
505 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
510 /* allocate a n element value array (to be populated by caller) and
513 static struct ir3_instruction
**
514 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
516 struct ir3_instruction
**value
=
517 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
518 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
522 static struct ir3_instruction
**
523 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
526 return __get_dst(ctx
, &dst
->ssa
, n
);
528 return __get_dst(ctx
, dst
->reg
.reg
, n
);
532 static struct ir3_instruction
**
533 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
535 return __get_dst(ctx
, dst
, n
);
538 static struct ir3_instruction
**
539 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
541 struct hash_entry
*entry
;
543 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
545 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
547 compile_assert(ctx
, entry
);
551 static struct ir3_instruction
*
552 create_immed(struct ir3_block
*block
, uint32_t val
)
554 struct ir3_instruction
*mov
;
556 mov
= ir3_instr_create(block
, 1, 0);
557 mov
->cat1
.src_type
= TYPE_U32
;
558 mov
->cat1
.dst_type
= TYPE_U32
;
559 ir3_reg_create(mov
, 0, 0);
560 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
565 static struct ir3_instruction
*
566 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
568 struct ir3_instruction
*instr
, *immed
;
570 /* TODO in at least some cases, the backend could probably be
571 * made clever enough to propagate IR3_REG_HALF..
573 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
574 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
576 immed
= create_immed(block
, 2);
577 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
579 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
580 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
581 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
583 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
584 instr
->regs
[0]->num
= regid(REG_A0
, 0);
585 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
586 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
591 /* caches addr values to avoid generating multiple cov/shl/mova
592 * sequences for each use of a given NIR level src as address
594 static struct ir3_instruction
*
595 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
597 struct ir3_instruction
*addr
;
598 struct hash_entry
*entry
;
599 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
603 /* TODO do we need to cache per block? */
604 addr
= create_addr(ctx
->block
, src
);
605 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
610 static struct ir3_instruction
*
611 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
613 struct ir3_block
*b
= ctx
->block
;
614 struct ir3_instruction
*cond
;
616 /* NOTE: only cmps.*.* can write p0.x: */
617 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
618 cond
->cat2
.condition
= IR3_COND_NE
;
620 /* condition always goes in predicate register: */
621 cond
->regs
[0]->num
= regid(REG_P0
, 0);
626 static struct ir3_instruction
*
627 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
629 struct ir3_instruction
*mov
;
631 mov
= ir3_instr_create(ctx
->block
, 1, 0);
632 /* TODO get types right? */
633 mov
->cat1
.src_type
= TYPE_F32
;
634 mov
->cat1
.dst_type
= TYPE_F32
;
635 ir3_reg_create(mov
, 0, 0);
636 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
641 static struct ir3_instruction
*
642 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
643 struct ir3_instruction
*address
)
645 struct ir3_instruction
*mov
;
647 mov
= ir3_instr_create(ctx
->block
, 1, 0);
648 mov
->cat1
.src_type
= TYPE_U32
;
649 mov
->cat1
.dst_type
= TYPE_U32
;
650 ir3_reg_create(mov
, 0, 0);
651 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
653 ir3_instr_set_address(mov
, address
);
658 static struct ir3_instruction
*
659 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
662 struct ir3_instruction
*collect
;
667 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
668 ir3_reg_create(collect
, 0, 0); /* dst */
669 for (unsigned i
= 0; i
< arrsz
; i
++)
670 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
675 static struct ir3_instruction
*
676 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
677 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
679 struct ir3_block
*block
= ctx
->block
;
680 struct ir3_instruction
*mov
;
681 struct ir3_register
*src
;
683 mov
= ir3_instr_create(block
, 1, 0);
684 mov
->cat1
.src_type
= TYPE_U32
;
685 mov
->cat1
.dst_type
= TYPE_U32
;
686 ir3_reg_create(mov
, 0, 0);
687 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
688 src
->instr
= collect
;
692 ir3_instr_set_address(mov
, address
);
697 static struct ir3_instruction
*
698 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
699 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
700 struct ir3_instruction
*collect
)
702 struct ir3_block
*block
= ctx
->block
;
703 struct ir3_instruction
*mov
;
704 struct ir3_register
*dst
;
706 mov
= ir3_instr_create(block
, 1, 0);
707 mov
->cat1
.src_type
= TYPE_U32
;
708 mov
->cat1
.dst_type
= TYPE_U32
;
709 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
712 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
713 mov
->fanin
= collect
;
715 ir3_instr_set_address(mov
, address
);
720 static struct ir3_instruction
*
721 create_input(struct ir3_block
*block
, unsigned n
)
723 struct ir3_instruction
*in
;
725 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
726 in
->inout
.block
= block
;
727 ir3_reg_create(in
, n
, 0);
732 static struct ir3_instruction
*
733 create_frag_input(struct ir3_compile
*ctx
, unsigned n
, bool use_ldlv
)
735 struct ir3_block
*block
= ctx
->block
;
736 struct ir3_instruction
*instr
;
737 struct ir3_instruction
*inloc
= create_immed(block
, n
);
740 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
741 instr
->cat6
.type
= TYPE_U32
;
742 instr
->cat6
.iim_val
= 1;
744 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
745 instr
->regs
[2]->wrmask
= 0x3;
751 static struct ir3_instruction
*
752 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
754 struct ir3_block
*block
= ctx
->block
;
755 struct ir3_instruction
*instr
;
757 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
759 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
764 /* for frag_coord, we get unsigned values.. we need
765 * to subtract (integer) 8 and divide by 16 (right-
766 * shift by 4) then convert to float:
770 * mov.u32f32 dst, tmp
773 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
774 create_immed(block
, 8), 0);
775 instr
= ir3_SHR_B(block
, instr
, 0,
776 create_immed(block
, 4), 0);
777 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
783 /* seems that we can use these as-is: */
784 return ctx
->frag_coord
[comp
];
788 static struct ir3_instruction
*
789 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
791 struct ir3_block
*block
= ctx
->block
;
792 struct ir3_instruction
*instr
;
796 compile_assert(ctx
, !ctx
->frag_face
);
798 ctx
->frag_face
= create_input(block
, 0);
799 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
801 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
802 * positive vs negative float.. and piglit further seems to
803 * expect -1.0 or 1.0:
805 * mul.s tmp, hr0.x, 2
807 * mov.s32f32, dst, tmp
810 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
811 create_immed(block
, 2), 0);
812 instr
= ir3_ADD_S(block
, instr
, 0,
813 create_immed(block
, 1), 0);
814 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
819 return create_immed(block
, fui(0.0));
822 return create_immed(block
, fui(1.0));
826 static struct ir3_instruction
*
827 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
829 /* first four vec4 sysval's reserved for UBOs: */
830 unsigned r
= regid(ctx
->so
->first_driver_param
+ 4, dp
);
831 return create_uniform(ctx
, r
);
834 /* helper for instructions that produce multiple consecutive scalar
835 * outputs which need to have a split/fanout meta instruction inserted
838 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
839 struct ir3_instruction
*src
, unsigned n
)
841 struct ir3_instruction
*prev
= NULL
;
842 for (int i
= 0, j
= 0; i
< n
; i
++) {
843 struct ir3_instruction
*split
=
844 ir3_instr_create(block
, -1, OPC_META_FO
);
845 ir3_reg_create(split
, 0, IR3_REG_SSA
);
846 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
850 split
->cp
.left
= prev
;
851 split
->cp
.left_cnt
++;
852 prev
->cp
.right
= split
;
853 prev
->cp
.right_cnt
++;
857 if (src
->regs
[0]->wrmask
& (1 << i
))
863 * Adreno uses uint rather than having dedicated bool type,
864 * which (potentially) requires some conversion, in particular
865 * when using output of an bool instr to int input, or visa
869 * -------+---------+-------+-
873 * To convert from an adreno bool (uint) to nir, use:
875 * absneg.s dst, (neg)src
877 * To convert back in the other direction:
879 * absneg.s dst, (abs)arc
881 * The CP step can clean up the absneg.s that cancel each other
882 * out, and with a slight bit of extra cleverness (to recognize
883 * the instructions which produce either a 0 or 1) can eliminate
884 * the absneg.s's completely when an instruction that wants
885 * 0/1 consumes the result. For example, when a nir 'bcsel'
886 * consumes the result of 'feq'. So we should be able to get by
887 * without a boolean resolve step, and without incuring any
888 * extra penalty in instruction count.
891 /* NIR bool -> native (adreno): */
892 static struct ir3_instruction
*
893 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
895 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
898 /* native (adreno) -> NIR bool: */
899 static struct ir3_instruction
*
900 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
902 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
906 * alu/sfu instructions:
910 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
912 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
913 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
914 struct ir3_block
*b
= ctx
->block
;
916 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
918 /* Vectors are special in that they have non-scalarized writemasks,
919 * and just take the first swizzle channel for each argument in
920 * order into each writemask channel.
922 if ((alu
->op
== nir_op_vec2
) ||
923 (alu
->op
== nir_op_vec3
) ||
924 (alu
->op
== nir_op_vec4
)) {
926 for (int i
= 0; i
< info
->num_inputs
; i
++) {
927 nir_alu_src
*asrc
= &alu
->src
[i
];
929 compile_assert(ctx
, !asrc
->abs
);
930 compile_assert(ctx
, !asrc
->negate
);
932 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
934 src
[i
] = create_immed(ctx
->block
, 0);
935 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
941 /* General case: We can just grab the one used channel per src. */
942 for (int i
= 0; i
< info
->num_inputs
; i
++) {
943 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
944 nir_alu_src
*asrc
= &alu
->src
[i
];
946 compile_assert(ctx
, !asrc
->abs
);
947 compile_assert(ctx
, !asrc
->negate
);
949 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
951 compile_assert(ctx
, src
[i
]);
956 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
959 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
962 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
965 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
968 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
971 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
974 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
975 dst
[0]->cat2
.condition
= IR3_COND_NE
;
976 dst
[0] = ir3_n2b(b
, dst
[0]);
979 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
982 dst
[0] = ir3_b2n(b
, src
[0]);
985 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
986 dst
[0]->cat2
.condition
= IR3_COND_NE
;
987 dst
[0] = ir3_n2b(b
, dst
[0]);
991 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
994 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
997 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1000 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1003 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1006 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1009 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1012 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1015 dst
[0] = ir3_DSX(b
, src
[0], 0);
1016 dst
[0]->cat5
.type
= TYPE_F32
;
1019 dst
[0] = ir3_DSY(b
, src
[0], 0);
1020 dst
[0]->cat5
.type
= TYPE_F32
;
1024 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1025 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1026 dst
[0] = ir3_n2b(b
, dst
[0]);
1029 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1030 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1031 dst
[0] = ir3_n2b(b
, dst
[0]);
1034 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1035 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1036 dst
[0] = ir3_n2b(b
, dst
[0]);
1039 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1040 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1041 dst
[0] = ir3_n2b(b
, dst
[0]);
1044 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1047 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1050 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1052 case nir_op_fround_even
:
1053 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1056 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1060 dst
[0] = ir3_SIN(b
, src
[0], 0);
1063 dst
[0] = ir3_COS(b
, src
[0], 0);
1066 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1069 dst
[0] = ir3_RCP(b
, src
[0], 0);
1072 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1075 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1078 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1082 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1085 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1088 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1094 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1097 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1100 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1104 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1105 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1106 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1107 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1109 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1110 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1111 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1114 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1117 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1120 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1123 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1126 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1128 case nir_op_isign
: {
1129 /* maybe this would be sane to lower in nir.. */
1130 struct ir3_instruction
*neg
, *pos
;
1132 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1133 neg
->cat2
.condition
= IR3_COND_LT
;
1135 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1136 pos
->cat2
.condition
= IR3_COND_GT
;
1138 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1143 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1146 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1149 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1152 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1153 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1154 dst
[0] = ir3_n2b(b
, dst
[0]);
1157 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1158 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1159 dst
[0] = ir3_n2b(b
, dst
[0]);
1162 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1163 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1164 dst
[0] = ir3_n2b(b
, dst
[0]);
1167 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1168 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1169 dst
[0] = ir3_n2b(b
, dst
[0]);
1172 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1173 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1174 dst
[0] = ir3_n2b(b
, dst
[0]);
1177 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1178 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1179 dst
[0] = ir3_n2b(b
, dst
[0]);
1183 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1187 compile_error(ctx
, "Unhandled ALU op: %s\n",
1188 nir_op_infos
[alu
->op
].name
);
1193 /* handles direct/indirect UBO reads: */
1195 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1196 struct ir3_instruction
**dst
)
1198 struct ir3_block
*b
= ctx
->block
;
1199 struct ir3_instruction
*addr
, *src0
, *src1
;
1200 /* UBO addresses are the first driver params: */
1201 unsigned ubo
= regid(ctx
->so
->first_driver_param
, 0);
1202 unsigned off
= intr
->const_index
[0];
1204 /* First src is ubo index, which could either be an immed or not: */
1205 src0
= get_src(ctx
, &intr
->src
[0])[0];
1206 if (is_same_type_mov(src0
) &&
1207 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1208 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1210 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1213 if (intr
->intrinsic
== nir_intrinsic_load_ubo_indirect
) {
1214 /* For load_ubo_indirect, second src is indirect offset: */
1215 src1
= get_src(ctx
, &intr
->src
[1])[0];
1217 /* and add offset to addr: */
1218 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1221 /* if offset is to large to encode in the ldg, split it out: */
1222 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1223 /* split out the minimal amount to improve the odds that
1224 * cp can fit the immediate in the add.s instruction:
1226 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1227 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1231 for (int i
= 0; i
< intr
->num_components
; i
++) {
1232 struct ir3_instruction
*load
=
1233 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1234 load
->cat6
.type
= TYPE_U32
;
1235 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1240 /* handles array reads: */
1242 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1243 struct ir3_instruction
**dst
)
1245 nir_deref_var
*dvar
= intr
->variables
[0];
1246 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1247 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1249 compile_assert(ctx
, dvar
->deref
.child
&&
1250 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1252 switch (darr
->deref_array_type
) {
1253 case nir_deref_array_type_direct
:
1254 /* direct access does not require anything special: */
1255 for (int i
= 0; i
< intr
->num_components
; i
++) {
1256 unsigned n
= darr
->base_offset
* 4 + i
;
1257 compile_assert(ctx
, n
< arr
->length
);
1258 dst
[i
] = arr
->arr
[n
];
1261 case nir_deref_array_type_indirect
: {
1262 /* for indirect, we need to collect all the array elements: */
1263 struct ir3_instruction
*collect
=
1264 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1265 struct ir3_instruction
*addr
=
1266 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1267 for (int i
= 0; i
< intr
->num_components
; i
++) {
1268 unsigned n
= darr
->base_offset
* 4 + i
;
1269 compile_assert(ctx
, n
< arr
->length
);
1270 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1275 compile_error(ctx
, "Unhandled load deref type: %u\n",
1276 darr
->deref_array_type
);
1281 /* handles array writes: */
1283 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1285 nir_deref_var
*dvar
= intr
->variables
[0];
1286 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1287 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1288 struct ir3_instruction
**src
;
1290 compile_assert(ctx
, dvar
->deref
.child
&&
1291 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1293 src
= get_src(ctx
, &intr
->src
[0]);
1295 switch (darr
->deref_array_type
) {
1296 case nir_deref_array_type_direct
:
1297 /* direct access does not require anything special: */
1298 for (int i
= 0; i
< intr
->num_components
; i
++) {
1299 unsigned n
= darr
->base_offset
* 4 + i
;
1300 compile_assert(ctx
, n
< arr
->length
);
1301 arr
->arr
[n
] = src
[i
];
1304 case nir_deref_array_type_indirect
: {
1305 /* for indirect, create indirect-store and fan that out: */
1306 struct ir3_instruction
*collect
=
1307 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1308 struct ir3_instruction
*addr
=
1309 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1310 for (int i
= 0; i
< intr
->num_components
; i
++) {
1311 struct ir3_instruction
*store
;
1312 unsigned n
= darr
->base_offset
* 4 + i
;
1313 compile_assert(ctx
, n
< arr
->length
);
1315 store
= create_indirect_store(ctx
, arr
->length
,
1316 n
, src
[i
], addr
, collect
);
1318 store
->fanin
->fi
.aid
= arr
->aid
;
1320 /* TODO: probably split this out to be used for
1321 * store_output_indirect? or move this into
1322 * create_indirect_store()?
1324 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1325 struct ir3_instruction
*split
;
1327 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1329 ir3_reg_create(split
, 0, 0);
1330 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1332 arr
->arr
[j
] = split
;
1335 /* fixup fanout/split neighbors: */
1336 for (int i
= 0; i
< arr
->length
; i
++) {
1337 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1338 arr
->arr
[i
+1] : NULL
;
1339 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1340 arr
->arr
[i
-1] : NULL
;
1345 compile_error(ctx
, "Unhandled store deref type: %u\n",
1346 darr
->deref_array_type
);
1351 static void add_sysval_input(struct ir3_compile
*ctx
, unsigned name
,
1352 struct ir3_instruction
*instr
)
1354 struct ir3_shader_variant
*so
= ctx
->so
;
1355 unsigned r
= regid(so
->inputs_count
, 0);
1356 unsigned n
= so
->inputs_count
++;
1358 so
->inputs
[n
].semantic
= ir3_semantic_name(name
, 0);
1359 so
->inputs
[n
].compmask
= 1;
1360 so
->inputs
[n
].regid
= r
;
1361 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1364 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1365 ctx
->ir
->inputs
[r
] = instr
;
1369 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1371 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1372 struct ir3_instruction
**dst
, **src
;
1373 struct ir3_block
*b
= ctx
->block
;
1374 unsigned idx
= intr
->const_index
[0];
1376 if (info
->has_dest
) {
1377 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1382 switch (intr
->intrinsic
) {
1383 case nir_intrinsic_load_uniform
:
1384 for (int i
= 0; i
< intr
->num_components
; i
++) {
1385 unsigned n
= idx
* 4 + i
;
1386 dst
[i
] = create_uniform(ctx
, n
);
1389 case nir_intrinsic_load_uniform_indirect
:
1390 src
= get_src(ctx
, &intr
->src
[0]);
1391 for (int i
= 0; i
< intr
->num_components
; i
++) {
1392 unsigned n
= idx
* 4 + i
;
1393 dst
[i
] = create_uniform_indirect(ctx
, n
,
1394 get_addr(ctx
, src
[0]));
1396 /* NOTE: if relative addressing is used, we set constlen in
1397 * the compiler (to worst-case value) since we don't know in
1398 * the assembler what the max addr reg value can be:
1400 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1402 case nir_intrinsic_load_ubo
:
1403 case nir_intrinsic_load_ubo_indirect
:
1404 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1406 case nir_intrinsic_load_input
:
1407 for (int i
= 0; i
< intr
->num_components
; i
++) {
1408 unsigned n
= idx
* 4 + i
;
1409 dst
[i
] = ctx
->ir
->inputs
[n
];
1412 case nir_intrinsic_load_input_indirect
:
1413 src
= get_src(ctx
, &intr
->src
[0]);
1414 struct ir3_instruction
*collect
=
1415 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1416 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1417 for (int i
= 0; i
< intr
->num_components
; i
++) {
1418 unsigned n
= idx
* 4 + i
;
1419 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1423 case nir_intrinsic_load_var
:
1424 emit_intrinisic_load_var(ctx
, intr
, dst
);
1426 case nir_intrinsic_store_var
:
1427 emit_intrinisic_store_var(ctx
, intr
);
1429 case nir_intrinsic_store_output
:
1430 src
= get_src(ctx
, &intr
->src
[0]);
1431 for (int i
= 0; i
< intr
->num_components
; i
++) {
1432 unsigned n
= idx
* 4 + i
;
1433 ctx
->ir
->outputs
[n
] = src
[i
];
1436 case nir_intrinsic_load_base_vertex
:
1437 if (!ctx
->basevertex
) {
1438 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1439 add_sysval_input(ctx
, TGSI_SEMANTIC_BASEVERTEX
,
1442 dst
[0] = ctx
->basevertex
;
1444 case nir_intrinsic_load_vertex_id_zero_base
:
1445 if (!ctx
->vertex_id
) {
1446 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1447 add_sysval_input(ctx
, TGSI_SEMANTIC_VERTEXID_NOBASE
,
1450 dst
[0] = ctx
->vertex_id
;
1452 case nir_intrinsic_load_instance_id
:
1453 if (!ctx
->instance_id
) {
1454 ctx
->instance_id
= create_input(ctx
->block
, 0);
1455 add_sysval_input(ctx
, TGSI_SEMANTIC_INSTANCEID
,
1458 dst
[0] = ctx
->instance_id
;
1460 case nir_intrinsic_discard_if
:
1461 case nir_intrinsic_discard
: {
1462 struct ir3_instruction
*cond
, *kill
;
1464 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1465 /* conditional discard: */
1466 src
= get_src(ctx
, &intr
->src
[0]);
1467 cond
= ir3_b2n(b
, src
[0]);
1469 /* unconditional discard: */
1470 cond
= create_immed(b
, 1);
1473 /* NOTE: only cmps.*.* can write p0.x: */
1474 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1475 cond
->cat2
.condition
= IR3_COND_NE
;
1477 /* condition always goes in predicate register: */
1478 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1480 kill
= ir3_KILL(b
, cond
, 0);
1481 array_insert(ctx
->ir
->predicates
, kill
);
1483 array_insert(ctx
->ir
->keeps
, kill
);
1484 ctx
->so
->has_kill
= true;
1489 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1490 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1496 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1498 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1499 instr
->def
.num_components
);
1500 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1501 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1505 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1507 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1508 undef
->def
.num_components
);
1509 /* backend doesn't want undefined instructions, so just plug
1512 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1513 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1517 * texture fetch/sample instructions:
1521 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1523 unsigned coords
, flags
= 0;
1525 /* note: would use tex->coord_components.. except txs.. also,
1526 * since array index goes after shadow ref, we don't want to
1529 switch (tex
->sampler_dim
) {
1530 case GLSL_SAMPLER_DIM_1D
:
1531 case GLSL_SAMPLER_DIM_BUF
:
1534 case GLSL_SAMPLER_DIM_2D
:
1535 case GLSL_SAMPLER_DIM_RECT
:
1536 case GLSL_SAMPLER_DIM_EXTERNAL
:
1537 case GLSL_SAMPLER_DIM_MS
:
1540 case GLSL_SAMPLER_DIM_3D
:
1541 case GLSL_SAMPLER_DIM_CUBE
:
1543 flags
|= IR3_INSTR_3D
;
1546 unreachable("bad sampler_dim");
1550 flags
|= IR3_INSTR_S
;
1553 flags
|= IR3_INSTR_A
;
1560 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1562 struct ir3_block
*b
= ctx
->block
;
1563 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1564 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1565 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1566 unsigned i
, coords
, flags
;
1567 unsigned nsrc0
= 0, nsrc1
= 0;
1571 coord
= off
= ddx
= ddy
= NULL
;
1572 lod
= proj
= compare
= NULL
;
1574 /* TODO: might just be one component for gathers? */
1575 dst
= get_dst(ctx
, &tex
->dest
, 4);
1577 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1578 switch (tex
->src
[i
].src_type
) {
1579 case nir_tex_src_coord
:
1580 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1582 case nir_tex_src_bias
:
1583 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1586 case nir_tex_src_lod
:
1587 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1590 case nir_tex_src_comparitor
: /* shadow comparator */
1591 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1593 case nir_tex_src_projector
:
1594 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1597 case nir_tex_src_offset
:
1598 off
= get_src(ctx
, &tex
->src
[i
].src
);
1601 case nir_tex_src_ddx
:
1602 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1604 case nir_tex_src_ddy
:
1605 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1608 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1609 tex
->src
[i
].src_type
);
1615 case nir_texop_tex
: opc
= OPC_SAM
; break;
1616 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1617 case nir_texop_txl
: opc
= OPC_SAML
; break;
1618 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1619 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1620 case nir_texop_txf_ms
:
1624 case nir_texop_query_levels
:
1625 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1629 tex_info(tex
, &flags
, &coords
);
1631 /* scale up integer coords for TXF based on the LOD */
1632 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1634 for (i
= 0; i
< coords
; i
++)
1635 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1639 * lay out the first argument in the proper order:
1640 * - actual coordinates first
1641 * - shadow reference
1644 * - starting at offset 4, dpdx.xy, dpdy.xy
1646 * bias/lod go into the second arg
1649 /* insert tex coords: */
1650 for (i
= 0; i
< coords
; i
++)
1651 src0
[nsrc0
++] = coord
[i
];
1654 /* hw doesn't do 1d, so we treat it as 2d with
1655 * height of 1, and patch up the y coord.
1656 * TODO: y coord should be (int)0 in some cases..
1658 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1662 src0
[nsrc0
++] = compare
;
1665 src0
[nsrc0
++] = coord
[coords
];
1668 src0
[nsrc0
++] = proj
;
1669 flags
|= IR3_INSTR_P
;
1672 /* pad to 4, then ddx/ddy: */
1673 if (tex
->op
== nir_texop_txd
) {
1675 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1676 for (i
= 0; i
< coords
; i
++)
1677 src0
[nsrc0
++] = ddx
[i
];
1679 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1680 for (i
= 0; i
< coords
; i
++)
1681 src0
[nsrc0
++] = ddy
[i
];
1683 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1687 * second argument (if applicable):
1692 if (has_off
| has_lod
| has_bias
) {
1694 for (i
= 0; i
< coords
; i
++)
1695 src1
[nsrc1
++] = off
[i
];
1697 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1698 flags
|= IR3_INSTR_O
;
1701 if (has_lod
| has_bias
)
1702 src1
[nsrc1
++] = lod
;
1705 switch (tex
->dest_type
) {
1706 case nir_type_invalid
:
1707 case nir_type_float
:
1713 case nir_type_unsigned
:
1718 unreachable("bad dest_type");
1721 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1722 flags
, tex
->sampler_index
, tex
->sampler_index
,
1723 create_collect(b
, src0
, nsrc0
),
1724 create_collect(b
, src1
, nsrc1
));
1726 split_dest(b
, dst
, sam
, 4);
1730 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1732 struct ir3_block
*b
= ctx
->block
;
1733 struct ir3_instruction
**dst
, *sam
;
1735 dst
= get_dst(ctx
, &tex
->dest
, 1);
1737 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1738 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1740 /* even though there is only one component, since it ends
1741 * up in .z rather than .x, we need a split_dest()
1743 split_dest(b
, dst
, sam
, 3);
1745 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1746 * the value in TEX_CONST_0 is zero-based.
1748 if (ctx
->levels_add_one
)
1749 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1753 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1755 struct ir3_block
*b
= ctx
->block
;
1756 struct ir3_instruction
**dst
, *sam
, *lod
;
1757 unsigned flags
, coords
;
1759 tex_info(tex
, &flags
, &coords
);
1761 dst
= get_dst(ctx
, &tex
->dest
, 4);
1763 compile_assert(ctx
, tex
->num_srcs
== 1);
1764 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1766 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1768 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1769 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1771 split_dest(b
, dst
, sam
, 4);
1773 /* Array size actually ends up in .w rather than .z. This doesn't
1774 * matter for miplevel 0, but for higher mips the value in z is
1775 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1776 * returned, which means that we have to add 1 to it for arrays.
1778 if (tex
->is_array
) {
1779 if (ctx
->levels_add_one
) {
1780 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1782 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1788 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1790 struct ir3_instruction
*phi
, **dst
;
1792 /* NOTE: phi's should be lowered to scalar at this point */
1793 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1795 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1797 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1798 1 + exec_list_length(&nphi
->srcs
));
1799 ir3_reg_create(phi
, 0, 0); /* dst */
1800 phi
->phi
.nphi
= nphi
;
1805 /* phi instructions are left partially constructed. We don't resolve
1806 * their srcs until the end of the block, since (eg. loops) one of
1807 * the phi's srcs might be defined after the phi due to back edges in
1811 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1813 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1814 nir_phi_instr
*nphi
;
1816 /* phi's only come at start of block: */
1817 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1820 if (!instr
->phi
.nphi
)
1823 nphi
= instr
->phi
.nphi
;
1824 instr
->phi
.nphi
= NULL
;
1826 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1827 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1828 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1832 resolve_array_phis(ctx
, block
);
1836 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1838 switch (jump
->type
) {
1839 case nir_jump_break
:
1840 case nir_jump_continue
:
1841 /* I *think* we can simply just ignore this, and use the
1842 * successor block link to figure out where we need to
1843 * jump to for break/continue
1847 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1853 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1855 switch (instr
->type
) {
1856 case nir_instr_type_alu
:
1857 emit_alu(ctx
, nir_instr_as_alu(instr
));
1859 case nir_instr_type_intrinsic
:
1860 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1862 case nir_instr_type_load_const
:
1863 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1865 case nir_instr_type_ssa_undef
:
1866 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1868 case nir_instr_type_tex
: {
1869 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1870 /* couple tex instructions get special-cased:
1874 emit_tex_txs(ctx
, tex
);
1876 case nir_texop_query_levels
:
1877 emit_tex_query_levels(ctx
, tex
);
1885 case nir_instr_type_phi
:
1886 emit_phi(ctx
, nir_instr_as_phi(instr
));
1888 case nir_instr_type_jump
:
1889 emit_jump(ctx
, nir_instr_as_jump(instr
));
1891 case nir_instr_type_call
:
1892 case nir_instr_type_parallel_copy
:
1893 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1898 static struct ir3_block
*
1899 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1901 struct ir3_block
*block
;
1902 struct hash_entry
*entry
;
1903 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1907 block
= ir3_block_create(ctx
->ir
);
1908 block
->nblock
= nblock
;
1909 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1915 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1917 struct ir3_block
*block
= get_block(ctx
, nblock
);
1919 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1920 if (nblock
->successors
[i
]) {
1921 block
->successors
[i
] =
1922 get_block(ctx
, nblock
->successors
[i
]);
1927 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1929 nir_foreach_instr(nblock
, instr
) {
1930 emit_instr(ctx
, instr
);
1936 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1939 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1941 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1943 ctx
->block
->condition
=
1944 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1946 emit_cf_list(ctx
, &nif
->then_list
);
1947 emit_cf_list(ctx
, &nif
->else_list
);
1951 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1953 emit_cf_list(ctx
, &nloop
->body
);
1957 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1959 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1960 switch (node
->type
) {
1961 case nir_cf_node_block
:
1962 emit_block(ctx
, nir_cf_node_as_block(node
));
1964 case nir_cf_node_if
:
1965 emit_if(ctx
, nir_cf_node_as_if(node
));
1967 case nir_cf_node_loop
:
1968 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1970 case nir_cf_node_function
:
1971 compile_error(ctx
, "TODO\n");
1977 /* emit stream-out code. At this point, the current block is the original
1978 * (nir) end block, and nir ensures that all flow control paths terminate
1979 * into the end block. We re-purpose the original end block to generate
1980 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
1981 * block holding stream-out write instructions, followed by the new end
1985 * p0.x = (vtxcnt < maxvtxcnt)
1986 * // succs: blockStreamOut, blockNewEnd
1989 * ... stream-out instructions ...
1990 * // succs: blockNewEnd
1996 emit_stream_out(struct ir3_compile
*ctx
)
1998 struct ir3_shader_variant
*v
= ctx
->so
;
1999 struct ir3
*ir
= ctx
->ir
;
2000 struct pipe_stream_output_info
*strmout
=
2001 &ctx
->so
->shader
->stream_output
;
2002 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2003 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2004 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2006 /* create vtxcnt input in input block at top of shader,
2007 * so that it is seen as live over the entire duration
2010 vtxcnt
= create_input(ctx
->in_block
, 0);
2011 add_sysval_input(ctx
, IR3_SEMANTIC_VTXCNT
, vtxcnt
);
2013 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2015 /* at this point, we are at the original 'end' block,
2016 * re-purpose this block to stream-out condition, then
2017 * append stream-out block and new-end block
2019 orig_end_block
= ctx
->block
;
2021 stream_out_block
= ir3_block_create(ir
);
2022 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2024 new_end_block
= ir3_block_create(ir
);
2025 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2027 orig_end_block
->successors
[0] = stream_out_block
;
2028 orig_end_block
->successors
[1] = new_end_block
;
2029 stream_out_block
->successors
[0] = new_end_block
;
2031 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2032 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2033 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2034 cond
->cat2
.condition
= IR3_COND_LT
;
2036 /* condition goes on previous block to the conditional,
2037 * since it is used to pick which of the two successor
2040 orig_end_block
->condition
= cond
;
2042 /* switch to stream_out_block to generate the stream-out
2045 ctx
->block
= stream_out_block
;
2047 /* Calculate base addresses based on vtxcnt. Instructions
2048 * generated for bases not used in following loop will be
2049 * stripped out in the backend.
2051 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2052 unsigned stride
= strmout
->stride
[i
];
2053 struct ir3_instruction
*base
, *off
;
2055 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ 5, i
));
2057 /* 24-bit should be enough: */
2058 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2059 create_immed(ctx
->block
, stride
* 4), 0);
2061 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2064 /* Generate the per-output store instructions: */
2065 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2066 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2067 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2068 struct ir3_instruction
*base
, *out
, *stg
;
2070 base
= bases
[strmout
->output
[i
].output_buffer
];
2071 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2073 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2074 create_immed(ctx
->block
, 1), 0);
2075 stg
->cat6
.type
= TYPE_U32
;
2076 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2078 array_insert(ctx
->ir
->keeps
, stg
);
2082 /* and finally switch to the new_end_block: */
2083 ctx
->block
= new_end_block
;
2087 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2089 emit_cf_list(ctx
, &impl
->body
);
2090 emit_block(ctx
, impl
->end_block
);
2092 /* at this point, we should have a single empty block,
2093 * into which we emit the 'end' instruction.
2095 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2097 /* If stream-out (aka transform-feedback) enabled, emit the
2098 * stream-out instructions, followed by a new empty block (into
2099 * which the 'end' instruction lands).
2101 * NOTE: it is done in this order, rather than inserting before
2102 * we emit end_block, because NIR guarantees that all blocks
2103 * flow into end_block, and that end_block has no successors.
2104 * So by re-purposing end_block as the first block of stream-
2105 * out, we guarantee that all exit paths flow into the stream-
2108 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2109 !ctx
->so
->key
.binning_pass
) {
2110 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2111 emit_stream_out(ctx
);
2114 ir3_END(ctx
->block
);
2118 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2120 struct ir3_shader_variant
*so
= ctx
->so
;
2121 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2122 unsigned ncomp
= glsl_get_components(in
->type
);
2123 /* XXX: map loc slots to semantics */
2124 unsigned semantic_name
= in
->data
.location
;
2125 unsigned semantic_index
= in
->data
.index
;
2126 unsigned n
= in
->data
.driver_location
;
2128 DBG("; in: %u:%u, len=%ux%u, loc=%u",
2129 semantic_name
, semantic_index
, array_len
,
2132 so
->inputs
[n
].semantic
=
2133 ir3_semantic_name(semantic_name
, semantic_index
);
2134 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2135 so
->inputs
[n
].inloc
= ctx
->next_inloc
;
2136 so
->inputs
[n
].interpolate
= 0;
2137 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2139 /* the fdN_program_emit() code expects tgsi consts here, so map
2140 * things back to tgsi for now:
2142 switch (in
->data
.interpolation
) {
2143 case INTERP_QUALIFIER_FLAT
:
2144 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
2146 case INTERP_QUALIFIER_NOPERSPECTIVE
:
2147 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_LINEAR
;
2149 case INTERP_QUALIFIER_SMOOTH
:
2150 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_PERSPECTIVE
;
2154 for (int i
= 0; i
< ncomp
; i
++) {
2155 struct ir3_instruction
*instr
= NULL
;
2156 unsigned idx
= (n
* 4) + i
;
2158 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2159 if (semantic_name
== TGSI_SEMANTIC_POSITION
) {
2160 so
->inputs
[n
].bary
= false;
2161 so
->frag_coord
= true;
2162 instr
= create_frag_coord(ctx
, i
);
2163 } else if (semantic_name
== TGSI_SEMANTIC_FACE
) {
2164 so
->inputs
[n
].bary
= false;
2165 so
->frag_face
= true;
2166 instr
= create_frag_face(ctx
, i
);
2168 bool use_ldlv
= false;
2170 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2171 * from the semantic name:
2173 if ((in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) &&
2174 ((semantic_name
== TGSI_SEMANTIC_COLOR
) ||
2175 (semantic_name
== TGSI_SEMANTIC_BCOLOR
)))
2176 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_COLOR
;
2178 if (ctx
->flat_bypass
) {
2179 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2180 * from the semantic name:
2182 switch (so
->inputs
[n
].interpolate
) {
2183 case TGSI_INTERPOLATE_COLOR
:
2184 if (!ctx
->so
->key
.rasterflat
)
2187 case TGSI_INTERPOLATE_CONSTANT
:
2193 so
->inputs
[n
].bary
= true;
2195 instr
= create_frag_input(ctx
,
2196 so
->inputs
[n
].inloc
+ i
- 8, use_ldlv
);
2199 instr
= create_input(ctx
->block
, idx
);
2202 ctx
->ir
->inputs
[idx
] = instr
;
2205 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2206 ctx
->next_inloc
+= ncomp
;
2207 so
->total_in
+= ncomp
;
2212 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2214 struct ir3_shader_variant
*so
= ctx
->so
;
2215 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2216 unsigned ncomp
= glsl_get_components(out
->type
);
2217 /* XXX: map loc slots to semantics */
2218 unsigned semantic_name
= out
->data
.location
;
2219 unsigned semantic_index
= out
->data
.index
;
2220 unsigned n
= out
->data
.driver_location
;
2223 DBG("; out: %u:%u, len=%ux%u, loc=%u",
2224 semantic_name
, semantic_index
, array_len
,
2227 if (ctx
->so
->type
== SHADER_VERTEX
) {
2228 switch (semantic_name
) {
2229 case TGSI_SEMANTIC_POSITION
:
2230 so
->writes_pos
= true;
2232 case TGSI_SEMANTIC_PSIZE
:
2233 so
->writes_psize
= true;
2235 case TGSI_SEMANTIC_COLOR
:
2236 case TGSI_SEMANTIC_BCOLOR
:
2237 case TGSI_SEMANTIC_GENERIC
:
2238 case TGSI_SEMANTIC_FOG
:
2239 case TGSI_SEMANTIC_TEXCOORD
:
2242 compile_error(ctx
, "unknown VS semantic name: %s\n",
2243 tgsi_semantic_names
[semantic_name
]);
2246 switch (semantic_name
) {
2247 case TGSI_SEMANTIC_POSITION
:
2248 comp
= 2; /* tgsi will write to .z component */
2249 so
->writes_pos
= true;
2251 case TGSI_SEMANTIC_COLOR
:
2252 if (semantic_index
== -1) {
2258 compile_error(ctx
, "unknown FS semantic name: %s\n",
2259 tgsi_semantic_names
[semantic_name
]);
2263 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2265 so
->outputs
[n
].semantic
=
2266 ir3_semantic_name(semantic_name
, semantic_index
);
2267 so
->outputs
[n
].regid
= regid(n
, comp
);
2268 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2270 for (int i
= 0; i
< ncomp
; i
++) {
2271 unsigned idx
= (n
* 4) + i
;
2273 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2278 emit_instructions(struct ir3_compile
*ctx
)
2280 unsigned ninputs
, noutputs
;
2281 nir_function_impl
*fxn
= NULL
;
2283 /* Find the main function: */
2284 nir_foreach_overload(ctx
->s
, overload
) {
2285 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
2286 compile_assert(ctx
, overload
->impl
);
2287 fxn
= overload
->impl
;
2291 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2292 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2294 /* or vtx shaders, we need to leave room for sysvals:
2296 if (ctx
->so
->type
== SHADER_VERTEX
) {
2300 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2302 /* Create inputs in first block: */
2303 ctx
->block
= get_block(ctx
, fxn
->start_block
);
2304 ctx
->in_block
= ctx
->block
;
2305 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2307 if (ctx
->so
->type
== SHADER_VERTEX
) {
2308 ctx
->ir
->ninputs
-= 8;
2311 /* for fragment shader, we have a single input register (usually
2312 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2314 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2315 // TODO maybe a helper for fi since we need it a few places..
2316 struct ir3_instruction
*instr
;
2317 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2318 ir3_reg_create(instr
, 0, 0);
2319 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2320 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2321 ctx
->frag_pos
= instr
;
2325 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->inputs
) {
2326 setup_input(ctx
, var
);
2329 /* Setup outputs: */
2330 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->outputs
) {
2331 setup_output(ctx
, var
);
2334 /* Setup variables (which should only be arrays): */
2335 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->globals
) {
2336 declare_var(ctx
, var
);
2339 /* And emit the body: */
2341 emit_function(ctx
, fxn
);
2343 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2344 resolve_phis(ctx
, block
);
2348 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2349 * for a fragment shader are just bary.f instructions. The *actual* inputs
2350 * from the hw perspective are the frag_pos and optionally frag_coord and
2354 fixup_frag_inputs(struct ir3_compile
*ctx
)
2356 struct ir3_shader_variant
*so
= ctx
->so
;
2357 struct ir3
*ir
= ctx
->ir
;
2358 struct ir3_instruction
**inputs
;
2359 struct ir3_instruction
*instr
;
2364 n
= 4; /* always have frag_pos */
2365 n
+= COND(so
->frag_face
, 4);
2366 n
+= COND(so
->frag_coord
, 4);
2368 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2370 if (so
->frag_face
) {
2371 /* this ultimately gets assigned to hr0.x so doesn't conflict
2372 * with frag_coord/frag_pos..
2374 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2375 ctx
->frag_face
->regs
[0]->num
= 0;
2377 /* remaining channels not used, but let's avoid confusing
2378 * other parts that expect inputs to come in groups of vec4
2380 inputs
[ir
->ninputs
++] = NULL
;
2381 inputs
[ir
->ninputs
++] = NULL
;
2382 inputs
[ir
->ninputs
++] = NULL
;
2385 /* since we don't know where to set the regid for frag_coord,
2386 * we have to use r0.x for it. But we don't want to *always*
2387 * use r1.x for frag_pos as that could increase the register
2388 * footprint on simple shaders:
2390 if (so
->frag_coord
) {
2391 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2392 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2393 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2394 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2396 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2397 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2398 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2399 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2402 /* we always have frag_pos: */
2403 so
->pos_regid
= regid
;
2406 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2407 instr
->regs
[0]->num
= regid
++;
2408 inputs
[ir
->ninputs
++] = instr
;
2409 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2412 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2413 instr
->regs
[0]->num
= regid
++;
2414 inputs
[ir
->ninputs
++] = instr
;
2415 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2417 ir
->inputs
= inputs
;
2421 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2422 struct ir3_shader_variant
*so
)
2424 struct ir3_compile
*ctx
;
2426 struct ir3_instruction
**inputs
;
2427 unsigned i
, j
, actual_in
;
2428 int ret
= 0, max_bary
;
2432 ctx
= compile_init(compiler
, so
, so
->shader
->tokens
);
2434 DBG("INIT failed!");
2439 emit_instructions(ctx
);
2442 DBG("EMIT failed!");
2447 ir
= so
->ir
= ctx
->ir
;
2449 /* keep track of the inputs from TGSI perspective.. */
2450 inputs
= ir
->inputs
;
2452 /* but fixup actual inputs for frag shader: */
2453 if (so
->type
== SHADER_FRAGMENT
)
2454 fixup_frag_inputs(ctx
);
2456 /* at this point, for binning pass, throw away unneeded outputs: */
2457 if (so
->key
.binning_pass
) {
2458 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2459 unsigned name
= sem2name(so
->outputs
[i
].semantic
);
2460 unsigned idx
= sem2idx(so
->outputs
[i
].semantic
);
2462 /* throw away everything but first position/psize */
2463 if ((idx
== 0) && ((name
== TGSI_SEMANTIC_POSITION
) ||
2464 (name
== TGSI_SEMANTIC_PSIZE
))) {
2466 so
->outputs
[j
] = so
->outputs
[i
];
2467 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2468 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2469 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2470 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2475 so
->outputs_count
= j
;
2476 ir
->noutputs
= j
* 4;
2479 /* if we want half-precision outputs, mark the output registers
2482 if (so
->key
.half_precision
) {
2483 for (i
= 0; i
< ir
->noutputs
; i
++) {
2484 struct ir3_instruction
*out
= ir
->outputs
[i
];
2487 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2488 /* output could be a fanout (ie. texture fetch output)
2489 * in which case we need to propagate the half-reg flag
2490 * up to the definer so that RA sees it:
2492 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2493 out
= out
->regs
[1]->instr
;
2494 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2497 if (out
->category
== 1) {
2498 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2503 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2504 printf("BEFORE CP:\n");
2510 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2511 printf("BEFORE GROUPING:\n");
2515 /* Group left/right neighbors, inserting mov's where needed to
2522 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2523 printf("AFTER DEPTH:\n");
2527 ret
= ir3_sched(ir
);
2529 DBG("SCHED failed!");
2533 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2534 printf("AFTER SCHED:\n");
2538 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2544 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2545 printf("AFTER RA:\n");
2549 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2551 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2552 printf("AFTER LEGALIZE:\n");
2556 /* fixup input/outputs: */
2557 for (i
= 0; i
< so
->outputs_count
; i
++) {
2558 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2559 /* preserve hack for depth output.. tgsi writes depth to .z,
2560 * but what we give the hw is the scalar register:
2562 if ((so
->type
== SHADER_FRAGMENT
) &&
2563 (sem2name(so
->outputs
[i
].semantic
) == TGSI_SEMANTIC_POSITION
))
2564 so
->outputs
[i
].regid
+= 2;
2567 /* Note that some or all channels of an input may be unused: */
2569 for (i
= 0; i
< so
->inputs_count
; i
++) {
2570 unsigned j
, regid
= ~0, compmask
= 0;
2571 so
->inputs
[i
].ncomp
= 0;
2572 for (j
= 0; j
< 4; j
++) {
2573 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2575 compmask
|= (1 << j
);
2576 regid
= in
->regs
[0]->num
- j
;
2578 so
->inputs
[i
].ncomp
++;
2581 so
->inputs
[i
].regid
= regid
;
2582 so
->inputs
[i
].compmask
= compmask
;
2585 /* fragment shader always gets full vec4's even if it doesn't
2586 * fetch all components, but vertex shader we need to update
2587 * with the actual number of components fetch, otherwise thing
2588 * will hang due to mismaptch between VFD_DECODE's and
2591 if (so
->type
== SHADER_VERTEX
)
2592 so
->total_in
= actual_in
;
2594 so
->total_in
= align(max_bary
+ 1, 4);
2599 ir3_destroy(so
->ir
);