1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
41 #include "freedreno_util.h"
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
47 #include "instr-a3xx.h"
52 struct ir3_compiler
*compiler
;
54 const struct tgsi_token
*tokens
;
58 struct ir3_shader_variant
*so
;
60 struct ir3_block
*block
; /* the current block */
61 struct ir3_block
*in_block
; /* block created for shader inputs */
63 nir_function_impl
*impl
;
65 /* For fragment shaders, from the hw perspective the only
66 * actual input is r0.xy position register passed to bary.f.
67 * But TGSI doesn't know that, it still declares things as
68 * IN[] registers. So we do all the input tracking normally
69 * and fix things up after compile_instructions()
71 * NOTE that frag_pos is the hardware position (possibly it
72 * is actually an index or tag or some such.. it is *not*
73 * values that can be directly used for gl_FragCoord..)
75 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
77 /* For vertex shaders, keep track of the system values sources */
78 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
83 /* mapping from nir_variable to ir3_array: */
84 struct hash_table
*var_ht
;
87 /* a common pattern for indirect addressing is to request the
88 * same address register multiple times. To avoid generating
89 * duplicate instruction sequences (which our backend does not
90 * try to clean up, since that should be done as the NIR stage)
91 * we cache the address value generated for a given src value:
93 struct hash_table
*addr_ht
;
95 /* maps nir_block to ir3_block, mostly for the purposes of
96 * figuring out the blocks successors
98 struct hash_table
*block_ht
;
100 /* for calculating input/output positions/linkages: */
103 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
104 * so we need to use ldlv.u32 to load the varying directly:
108 /* on a3xx, we need to add one to # of array levels:
112 /* on a3xx, we need to scale up integer coords for isaml based
115 bool unminify_coords
;
117 /* for looking up which system value is which */
118 unsigned sysval_semantics
[8];
120 /* list of kill instructions: */
121 struct ir3_instruction
*kill
[16];
122 unsigned int kill_count
;
124 /* set if we encounter something we can't handle yet, so we
125 * can bail cleanly and fallback to TGSI compiler f/e
131 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
132 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
134 static struct nir_shader
*to_nir(const struct tgsi_token
*tokens
)
136 struct nir_shader_compiler_options options
= {
141 .native_integers
= true,
145 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
147 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
148 debug_printf("----------------------\n");
149 nir_print_shader(s
, stdout
);
150 debug_printf("----------------------\n");
153 nir_opt_global_to_local(s
);
154 nir_convert_to_ssa(s
);
160 nir_lower_vars_to_ssa(s
);
161 nir_lower_alu_to_scalar(s
);
162 nir_lower_phis_to_scalar(s
);
164 progress
|= nir_copy_prop(s
);
165 progress
|= nir_opt_dce(s
);
166 progress
|= nir_opt_cse(s
);
167 progress
|= ir3_nir_lower_if_else(s
);
168 progress
|= nir_opt_algebraic(s
);
169 progress
|= nir_opt_constant_folding(s
);
173 nir_remove_dead_variables(s
);
174 nir_validate_shader(s
);
176 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
177 debug_printf("----------------------\n");
178 nir_print_shader(s
, stdout
);
179 debug_printf("----------------------\n");
185 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
186 static const struct tgsi_token
*
187 lower_tgsi(struct ir3_compile
*ctx
, const struct tgsi_token
*tokens
,
188 struct ir3_shader_variant
*so
)
190 struct tgsi_shader_info info
;
191 struct tgsi_lowering_config lconfig
= {
192 .color_two_side
= so
->key
.color_two_side
,
197 case SHADER_FRAGMENT
:
199 lconfig
.saturate_s
= so
->key
.fsaturate_s
;
200 lconfig
.saturate_t
= so
->key
.fsaturate_t
;
201 lconfig
.saturate_r
= so
->key
.fsaturate_r
;
204 lconfig
.saturate_s
= so
->key
.vsaturate_s
;
205 lconfig
.saturate_t
= so
->key
.vsaturate_t
;
206 lconfig
.saturate_r
= so
->key
.vsaturate_r
;
210 if (ctx
->compiler
->gpu_id
>= 400) {
211 /* a4xx seems to have *no* sam.p */
212 lconfig
.lower_TXP
= ~0; /* lower all txp */
214 /* a3xx just needs to avoid sam.p for 3d tex */
215 lconfig
.lower_TXP
= (1 << TGSI_TEXTURE_3D
);
218 return tgsi_transform_lowering(&lconfig
, tokens
, &info
);
221 static struct ir3_compile
*
222 compile_init(struct ir3_compiler
*compiler
,
223 struct ir3_shader_variant
*so
,
224 const struct tgsi_token
*tokens
)
226 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
227 const struct tgsi_token
*lowered_tokens
;
229 if (compiler
->gpu_id
>= 400) {
230 /* need special handling for "flat" */
231 ctx
->flat_bypass
= true;
232 ctx
->levels_add_one
= false;
233 ctx
->unminify_coords
= false;
235 /* no special handling for "flat" */
236 ctx
->flat_bypass
= false;
237 ctx
->levels_add_one
= true;
238 ctx
->unminify_coords
= true;
241 ctx
->compiler
= compiler
;
245 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
246 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
247 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
248 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
249 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
250 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
251 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
252 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
254 lowered_tokens
= lower_tgsi(ctx
, tokens
, so
);
256 lowered_tokens
= tokens
;
257 ctx
->s
= to_nir(lowered_tokens
);
259 if (lowered_tokens
!= tokens
)
260 free((void *)lowered_tokens
);
262 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
264 /* Layout of constant registers:
266 * num_uniform * vec4 - user consts
267 * 4 * vec4 - UBO addresses
268 * if (vertex shader) {
269 * 1 * vec4 - driver params (IR3_DP_*)
272 * TODO this could be made more dynamic, to at least skip sections
273 * that we don't need..
276 /* reserve 4 (vec4) slots for ubo base addresses: */
277 so
->first_immediate
+= 4;
279 if (so
->type
== SHADER_VERTEX
) {
280 /* one (vec4) slot for driver params (see ir3_driver_param): */
281 so
->first_immediate
++;
288 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
291 va_start(ap
, format
);
292 _debug_vprintf(format
, ap
);
294 nir_print_shader(ctx
->s
, stdout
);
299 #define compile_assert(ctx, cond) do { \
300 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
304 compile_free(struct ir3_compile
*ctx
)
309 /* global per-array information: */
311 unsigned length
, aid
;
314 /* per-block array state: */
315 struct ir3_array_value
{
316 /* TODO drop length/aid, and just have ptr back to ir3_array */
317 unsigned length
, aid
;
318 /* initial array element values are phi's, other than for the
319 * entry block. The phi src's get added later in a resolve step
320 * after we have visited all the blocks, to account for back
323 struct ir3_instruction
**phis
;
324 /* current array element values (as block is processed). When
325 * the array phi's are resolved, it will contain the array state
326 * at exit of block, so successor blocks can use it to add their
329 struct ir3_instruction
*arr
[];
332 /* track array assignments per basic block. When an array is read
333 * outside of the same basic block, we can use NIR's dominance-frontier
334 * information to figure out where phi nodes are needed.
336 struct ir3_nir_block_data
{
338 /* indexed by array-id (aid): */
339 struct ir3_array_value
*arrs
[];
342 static struct ir3_nir_block_data
*
343 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
346 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
347 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
354 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
356 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
357 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
358 arr
->length
= length
;
359 arr
->aid
= ++ctx
->num_arrays
;
360 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
364 nir_block_pred(nir_block
*block
)
366 assert(block
->predecessors
->entries
< 2);
367 if (block
->predecessors
->entries
== 0)
369 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
372 static struct ir3_array_value
*
373 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
375 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
376 struct ir3_block
*block
= ctx
->block
;
377 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
378 struct ir3_array
*arr
= entry
->data
;
380 if (!bd
->arrs
[arr
->aid
]) {
381 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
382 (arr
->length
* sizeof(av
->arr
[0])));
383 struct ir3_array_value
*defn
= NULL
;
384 nir_block
*pred_block
;
386 av
->length
= arr
->length
;
389 /* For loops, we have to consider that we have not visited some
390 * of the blocks who should feed into the phi (ie. back-edges in
391 * the cfg).. for example:
394 * block { load_var; ... }
395 * if then block {} else block {}
396 * block { store_var; ... }
397 * if then block {} else block {}
401 * We can skip the phi if we can chase the block predecessors
402 * until finding the block previously defining the array without
403 * crossing a block that has more than one predecessor.
405 * Otherwise create phi's and resolve them as a post-pass after
406 * all the blocks have been visited (to handle back-edges).
409 for (pred_block
= block
->nblock
;
410 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
411 pred_block
= nir_block_pred(pred_block
)) {
412 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
413 struct ir3_nir_block_data
*pbd
= pblock
->bd
;
416 defn
= pbd
->arrs
[arr
->aid
];
420 /* only one possible definer: */
421 for (unsigned i
= 0; i
< arr
->length
; i
++)
422 av
->arr
[i
] = defn
->arr
[i
];
423 } else if (pred_block
) {
424 /* not the first block, and multiple potential definers: */
425 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
427 for (unsigned i
= 0; i
< arr
->length
; i
++) {
428 struct ir3_instruction
*phi
;
430 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
431 1 + ctx
->impl
->num_blocks
);
432 ir3_reg_create(phi
, 0, 0); /* dst */
434 /* phi's should go at head of block: */
435 list_delinit(&phi
->node
);
436 list_add(&phi
->node
, &block
->instr_list
);
438 av
->phis
[i
] = av
->arr
[i
] = phi
;
441 /* Some shaders end up reading array elements without
442 * first writing.. so initialize things to prevent null
445 for (unsigned i
= 0; i
< arr
->length
; i
++)
446 av
->arr
[i
] = create_immed(block
, 0);
449 bd
->arrs
[arr
->aid
] = av
;
452 return bd
->arrs
[arr
->aid
];
456 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
457 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
459 struct ir3_block
*block
;
460 struct ir3_nir_block_data
*bd
;
462 if (BITSET_TEST(visited
, nblock
->index
))
465 BITSET_SET(visited
, nblock
->index
);
467 block
= get_block(ctx
, nblock
);
470 if (bd
&& bd
->arrs
[av
->aid
]) {
471 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
472 for (unsigned i
= 0; i
< av
->length
; i
++) {
473 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
477 /* didn't find defn, recurse predecessors: */
478 struct set_entry
*entry
;
479 set_foreach(nblock
->predecessors
, entry
) {
480 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
486 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
488 struct ir3_nir_block_data
*bd
= block
->bd
;
489 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
494 /* TODO use nir dom_frontier to help us with this? */
496 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
497 struct ir3_array_value
*av
= bd
->arrs
[i
];
498 BITSET_WORD visited
[bitset_words
];
499 struct set_entry
*entry
;
501 if (!(av
&& av
->phis
))
504 memset(visited
, 0, sizeof(visited
));
505 set_foreach(block
->nblock
->predecessors
, entry
) {
506 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
511 /* allocate a n element value array (to be populated by caller) and
514 static struct ir3_instruction
**
515 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
517 struct ir3_instruction
**value
=
518 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
519 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
523 static struct ir3_instruction
**
524 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
527 return __get_dst(ctx
, &dst
->ssa
, n
);
529 return __get_dst(ctx
, dst
->reg
.reg
, n
);
533 static struct ir3_instruction
**
534 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
536 return __get_dst(ctx
, dst
, n
);
539 static struct ir3_instruction
**
540 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
542 struct hash_entry
*entry
;
544 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
546 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
548 compile_assert(ctx
, entry
);
552 static struct ir3_instruction
*
553 create_immed(struct ir3_block
*block
, uint32_t val
)
555 struct ir3_instruction
*mov
;
557 mov
= ir3_instr_create(block
, 1, 0);
558 mov
->cat1
.src_type
= TYPE_U32
;
559 mov
->cat1
.dst_type
= TYPE_U32
;
560 ir3_reg_create(mov
, 0, 0);
561 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
566 static struct ir3_instruction
*
567 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
569 struct ir3_instruction
*instr
, *immed
;
571 /* TODO in at least some cases, the backend could probably be
572 * made clever enough to propagate IR3_REG_HALF..
574 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
575 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
577 immed
= create_immed(block
, 2);
578 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
580 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
581 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
582 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
584 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
585 instr
->regs
[0]->num
= regid(REG_A0
, 0);
586 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
587 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
592 /* caches addr values to avoid generating multiple cov/shl/mova
593 * sequences for each use of a given NIR level src as address
595 static struct ir3_instruction
*
596 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
598 struct ir3_instruction
*addr
;
599 struct hash_entry
*entry
;
600 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
604 /* TODO do we need to cache per block? */
605 addr
= create_addr(ctx
->block
, src
);
606 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
611 static struct ir3_instruction
*
612 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
614 struct ir3_block
*b
= ctx
->block
;
615 struct ir3_instruction
*cond
;
617 /* NOTE: only cmps.*.* can write p0.x: */
618 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
619 cond
->cat2
.condition
= IR3_COND_NE
;
621 /* condition always goes in predicate register: */
622 cond
->regs
[0]->num
= regid(REG_P0
, 0);
627 static struct ir3_instruction
*
628 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
630 struct ir3_instruction
*mov
;
632 mov
= ir3_instr_create(ctx
->block
, 1, 0);
633 /* TODO get types right? */
634 mov
->cat1
.src_type
= TYPE_F32
;
635 mov
->cat1
.dst_type
= TYPE_F32
;
636 ir3_reg_create(mov
, 0, 0);
637 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
642 static struct ir3_instruction
*
643 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
644 struct ir3_instruction
*address
)
646 struct ir3_instruction
*mov
;
648 mov
= ir3_instr_create(ctx
->block
, 1, 0);
649 mov
->cat1
.src_type
= TYPE_U32
;
650 mov
->cat1
.dst_type
= TYPE_U32
;
651 ir3_reg_create(mov
, 0, 0);
652 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
654 ir3_instr_set_address(mov
, address
);
659 static struct ir3_instruction
*
660 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
663 struct ir3_instruction
*collect
;
668 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
669 ir3_reg_create(collect
, 0, 0); /* dst */
670 for (unsigned i
= 0; i
< arrsz
; i
++)
671 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
676 static struct ir3_instruction
*
677 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
678 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
680 struct ir3_block
*block
= ctx
->block
;
681 struct ir3_instruction
*mov
;
682 struct ir3_register
*src
;
684 mov
= ir3_instr_create(block
, 1, 0);
685 mov
->cat1
.src_type
= TYPE_U32
;
686 mov
->cat1
.dst_type
= TYPE_U32
;
687 ir3_reg_create(mov
, 0, 0);
688 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
689 src
->instr
= collect
;
693 ir3_instr_set_address(mov
, address
);
698 static struct ir3_instruction
*
699 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
700 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
701 struct ir3_instruction
*collect
)
703 struct ir3_block
*block
= ctx
->block
;
704 struct ir3_instruction
*mov
;
705 struct ir3_register
*dst
;
707 mov
= ir3_instr_create(block
, 1, 0);
708 mov
->cat1
.src_type
= TYPE_U32
;
709 mov
->cat1
.dst_type
= TYPE_U32
;
710 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
713 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
714 mov
->fanin
= collect
;
716 ir3_instr_set_address(mov
, address
);
721 static struct ir3_instruction
*
722 create_input(struct ir3_block
*block
, unsigned n
)
724 struct ir3_instruction
*in
;
726 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
727 in
->inout
.block
= block
;
728 ir3_reg_create(in
, n
, 0);
733 static struct ir3_instruction
*
734 create_frag_input(struct ir3_compile
*ctx
, unsigned n
, bool use_ldlv
)
736 struct ir3_block
*block
= ctx
->block
;
737 struct ir3_instruction
*instr
;
738 struct ir3_instruction
*inloc
= create_immed(block
, n
);
741 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
742 instr
->cat6
.type
= TYPE_U32
;
743 instr
->cat6
.iim_val
= 1;
745 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
746 instr
->regs
[2]->wrmask
= 0x3;
752 static struct ir3_instruction
*
753 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
755 struct ir3_block
*block
= ctx
->block
;
756 struct ir3_instruction
*instr
;
758 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
760 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
765 /* for frag_coord, we get unsigned values.. we need
766 * to subtract (integer) 8 and divide by 16 (right-
767 * shift by 4) then convert to float:
771 * mov.u32f32 dst, tmp
774 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
775 create_immed(block
, 8), 0);
776 instr
= ir3_SHR_B(block
, instr
, 0,
777 create_immed(block
, 4), 0);
778 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
784 /* seems that we can use these as-is: */
785 return ctx
->frag_coord
[comp
];
789 static struct ir3_instruction
*
790 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
792 struct ir3_block
*block
= ctx
->block
;
793 struct ir3_instruction
*instr
;
797 compile_assert(ctx
, !ctx
->frag_face
);
799 ctx
->frag_face
= create_input(block
, 0);
800 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
802 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
803 * positive vs negative float.. and piglit further seems to
804 * expect -1.0 or 1.0:
806 * mul.s tmp, hr0.x, 2
808 * mov.s32f32, dst, tmp
811 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
812 create_immed(block
, 2), 0);
813 instr
= ir3_ADD_S(block
, instr
, 0,
814 create_immed(block
, 1), 0);
815 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
820 return create_immed(block
, fui(0.0));
823 return create_immed(block
, fui(1.0));
827 static struct ir3_instruction
*
828 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
830 /* first four vec4 sysval's reserved for UBOs: */
831 unsigned r
= regid(ctx
->so
->first_driver_param
+ 4, dp
);
832 return create_uniform(ctx
, r
);
835 /* helper for instructions that produce multiple consecutive scalar
836 * outputs which need to have a split/fanout meta instruction inserted
839 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
840 struct ir3_instruction
*src
, unsigned n
)
842 struct ir3_instruction
*prev
= NULL
;
843 for (int i
= 0, j
= 0; i
< n
; i
++) {
844 struct ir3_instruction
*split
=
845 ir3_instr_create(block
, -1, OPC_META_FO
);
846 ir3_reg_create(split
, 0, IR3_REG_SSA
);
847 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
851 split
->cp
.left
= prev
;
852 split
->cp
.left_cnt
++;
853 prev
->cp
.right
= split
;
854 prev
->cp
.right_cnt
++;
858 if (src
->regs
[0]->wrmask
& (1 << i
))
864 * Adreno uses uint rather than having dedicated bool type,
865 * which (potentially) requires some conversion, in particular
866 * when using output of an bool instr to int input, or visa
870 * -------+---------+-------+-
874 * To convert from an adreno bool (uint) to nir, use:
876 * absneg.s dst, (neg)src
878 * To convert back in the other direction:
880 * absneg.s dst, (abs)arc
882 * The CP step can clean up the absneg.s that cancel each other
883 * out, and with a slight bit of extra cleverness (to recognize
884 * the instructions which produce either a 0 or 1) can eliminate
885 * the absneg.s's completely when an instruction that wants
886 * 0/1 consumes the result. For example, when a nir 'bcsel'
887 * consumes the result of 'feq'. So we should be able to get by
888 * without a boolean resolve step, and without incuring any
889 * extra penalty in instruction count.
892 /* NIR bool -> native (adreno): */
893 static struct ir3_instruction
*
894 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
896 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
899 /* native (adreno) -> NIR bool: */
900 static struct ir3_instruction
*
901 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
903 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
907 * alu/sfu instructions:
911 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
913 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
914 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
915 struct ir3_block
*b
= ctx
->block
;
917 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
919 /* Vectors are special in that they have non-scalarized writemasks,
920 * and just take the first swizzle channel for each argument in
921 * order into each writemask channel.
923 if ((alu
->op
== nir_op_vec2
) ||
924 (alu
->op
== nir_op_vec3
) ||
925 (alu
->op
== nir_op_vec4
)) {
927 for (int i
= 0; i
< info
->num_inputs
; i
++) {
928 nir_alu_src
*asrc
= &alu
->src
[i
];
930 compile_assert(ctx
, !asrc
->abs
);
931 compile_assert(ctx
, !asrc
->negate
);
933 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
935 src
[i
] = create_immed(ctx
->block
, 0);
936 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
942 /* General case: We can just grab the one used channel per src. */
943 for (int i
= 0; i
< info
->num_inputs
; i
++) {
944 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
945 nir_alu_src
*asrc
= &alu
->src
[i
];
947 compile_assert(ctx
, !asrc
->abs
);
948 compile_assert(ctx
, !asrc
->negate
);
950 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
952 compile_assert(ctx
, src
[i
]);
957 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
960 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
963 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
966 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
969 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
972 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
975 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
976 dst
[0]->cat2
.condition
= IR3_COND_NE
;
977 dst
[0] = ir3_n2b(b
, dst
[0]);
980 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
983 dst
[0] = ir3_b2n(b
, src
[0]);
986 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
987 dst
[0]->cat2
.condition
= IR3_COND_NE
;
988 dst
[0] = ir3_n2b(b
, dst
[0]);
992 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
995 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
998 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1001 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1004 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1007 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1010 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1013 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1016 dst
[0] = ir3_DSX(b
, src
[0], 0);
1017 dst
[0]->cat5
.type
= TYPE_F32
;
1020 dst
[0] = ir3_DSY(b
, src
[0], 0);
1021 dst
[0]->cat5
.type
= TYPE_F32
;
1025 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1026 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1027 dst
[0] = ir3_n2b(b
, dst
[0]);
1030 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1031 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1032 dst
[0] = ir3_n2b(b
, dst
[0]);
1035 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1036 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1037 dst
[0] = ir3_n2b(b
, dst
[0]);
1040 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1041 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1042 dst
[0] = ir3_n2b(b
, dst
[0]);
1045 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1048 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1051 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1053 case nir_op_fround_even
:
1054 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1057 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1061 dst
[0] = ir3_SIN(b
, src
[0], 0);
1064 dst
[0] = ir3_COS(b
, src
[0], 0);
1067 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1070 dst
[0] = ir3_RCP(b
, src
[0], 0);
1073 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1076 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1079 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1083 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1086 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1089 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1092 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1095 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1098 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1101 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1105 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1106 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1107 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1108 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1110 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1111 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1112 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1115 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1118 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1121 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1124 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1127 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1129 case nir_op_isign
: {
1130 /* maybe this would be sane to lower in nir.. */
1131 struct ir3_instruction
*neg
, *pos
;
1133 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1134 neg
->cat2
.condition
= IR3_COND_LT
;
1136 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1137 pos
->cat2
.condition
= IR3_COND_GT
;
1139 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1144 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1147 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1150 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1153 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1154 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1155 dst
[0] = ir3_n2b(b
, dst
[0]);
1158 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1159 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1160 dst
[0] = ir3_n2b(b
, dst
[0]);
1163 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1164 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1165 dst
[0] = ir3_n2b(b
, dst
[0]);
1168 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1169 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1170 dst
[0] = ir3_n2b(b
, dst
[0]);
1173 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1174 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1175 dst
[0] = ir3_n2b(b
, dst
[0]);
1178 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1179 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1180 dst
[0] = ir3_n2b(b
, dst
[0]);
1184 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1188 compile_error(ctx
, "Unhandled ALU op: %s\n",
1189 nir_op_infos
[alu
->op
].name
);
1194 /* handles direct/indirect UBO reads: */
1196 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1197 struct ir3_instruction
**dst
)
1199 struct ir3_block
*b
= ctx
->block
;
1200 struct ir3_instruction
*addr
, *src0
, *src1
;
1201 /* UBO addresses are the first driver params: */
1202 unsigned ubo
= regid(ctx
->so
->first_driver_param
, 0);
1203 unsigned off
= intr
->const_index
[0];
1205 /* First src is ubo index, which could either be an immed or not: */
1206 src0
= get_src(ctx
, &intr
->src
[0])[0];
1207 if (is_same_type_mov(src0
) &&
1208 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1209 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1211 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1214 if (intr
->intrinsic
== nir_intrinsic_load_ubo_indirect
) {
1215 /* For load_ubo_indirect, second src is indirect offset: */
1216 src1
= get_src(ctx
, &intr
->src
[1])[0];
1218 /* and add offset to addr: */
1219 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1222 /* if offset is to large to encode in the ldg, split it out: */
1223 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1224 /* split out the minimal amount to improve the odds that
1225 * cp can fit the immediate in the add.s instruction:
1227 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1228 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1232 for (int i
= 0; i
< intr
->num_components
; i
++) {
1233 struct ir3_instruction
*load
=
1234 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1235 load
->cat6
.type
= TYPE_U32
;
1236 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1241 /* handles array reads: */
1243 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1244 struct ir3_instruction
**dst
)
1246 nir_deref_var
*dvar
= intr
->variables
[0];
1247 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1248 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1250 compile_assert(ctx
, dvar
->deref
.child
&&
1251 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1253 switch (darr
->deref_array_type
) {
1254 case nir_deref_array_type_direct
:
1255 /* direct access does not require anything special: */
1256 for (int i
= 0; i
< intr
->num_components
; i
++) {
1257 unsigned n
= darr
->base_offset
* 4 + i
;
1258 compile_assert(ctx
, n
< arr
->length
);
1259 dst
[i
] = arr
->arr
[n
];
1262 case nir_deref_array_type_indirect
: {
1263 /* for indirect, we need to collect all the array elements: */
1264 struct ir3_instruction
*collect
=
1265 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1266 struct ir3_instruction
*addr
=
1267 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1268 for (int i
= 0; i
< intr
->num_components
; i
++) {
1269 unsigned n
= darr
->base_offset
* 4 + i
;
1270 compile_assert(ctx
, n
< arr
->length
);
1271 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1276 compile_error(ctx
, "Unhandled load deref type: %u\n",
1277 darr
->deref_array_type
);
1282 /* handles array writes: */
1284 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1286 nir_deref_var
*dvar
= intr
->variables
[0];
1287 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1288 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1289 struct ir3_instruction
**src
;
1291 compile_assert(ctx
, dvar
->deref
.child
&&
1292 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1294 src
= get_src(ctx
, &intr
->src
[0]);
1296 switch (darr
->deref_array_type
) {
1297 case nir_deref_array_type_direct
:
1298 /* direct access does not require anything special: */
1299 for (int i
= 0; i
< intr
->num_components
; i
++) {
1300 unsigned n
= darr
->base_offset
* 4 + i
;
1301 compile_assert(ctx
, n
< arr
->length
);
1302 arr
->arr
[n
] = src
[i
];
1305 case nir_deref_array_type_indirect
: {
1306 /* for indirect, create indirect-store and fan that out: */
1307 struct ir3_instruction
*collect
=
1308 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1309 struct ir3_instruction
*addr
=
1310 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1311 for (int i
= 0; i
< intr
->num_components
; i
++) {
1312 struct ir3_instruction
*store
;
1313 unsigned n
= darr
->base_offset
* 4 + i
;
1314 compile_assert(ctx
, n
< arr
->length
);
1316 store
= create_indirect_store(ctx
, arr
->length
,
1317 n
, src
[i
], addr
, collect
);
1319 store
->fanin
->fi
.aid
= arr
->aid
;
1321 /* TODO: probably split this out to be used for
1322 * store_output_indirect? or move this into
1323 * create_indirect_store()?
1325 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1326 struct ir3_instruction
*split
;
1328 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1330 ir3_reg_create(split
, 0, 0);
1331 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1333 arr
->arr
[j
] = split
;
1336 /* fixup fanout/split neighbors: */
1337 for (int i
= 0; i
< arr
->length
; i
++) {
1338 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1339 arr
->arr
[i
+1] : NULL
;
1340 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1341 arr
->arr
[i
-1] : NULL
;
1346 compile_error(ctx
, "Unhandled store deref type: %u\n",
1347 darr
->deref_array_type
);
1352 static void add_sysval_input(struct ir3_compile
*ctx
, unsigned name
,
1353 struct ir3_instruction
*instr
)
1355 struct ir3_shader_variant
*so
= ctx
->so
;
1356 unsigned r
= regid(so
->inputs_count
, 0);
1357 unsigned n
= so
->inputs_count
++;
1359 so
->inputs
[n
].semantic
= ir3_semantic_name(name
, 0);
1360 so
->inputs
[n
].compmask
= 1;
1361 so
->inputs
[n
].regid
= r
;
1362 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1365 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1366 ctx
->ir
->inputs
[r
] = instr
;
1370 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1372 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1373 struct ir3_instruction
**dst
, **src
;
1374 struct ir3_block
*b
= ctx
->block
;
1375 unsigned idx
= intr
->const_index
[0];
1377 if (info
->has_dest
) {
1378 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1383 switch (intr
->intrinsic
) {
1384 case nir_intrinsic_load_uniform
:
1385 for (int i
= 0; i
< intr
->num_components
; i
++) {
1386 unsigned n
= idx
* 4 + i
;
1387 dst
[i
] = create_uniform(ctx
, n
);
1390 case nir_intrinsic_load_uniform_indirect
:
1391 src
= get_src(ctx
, &intr
->src
[0]);
1392 for (int i
= 0; i
< intr
->num_components
; i
++) {
1393 unsigned n
= idx
* 4 + i
;
1394 dst
[i
] = create_uniform_indirect(ctx
, n
,
1395 get_addr(ctx
, src
[0]));
1397 /* NOTE: if relative addressing is used, we set constlen in
1398 * the compiler (to worst-case value) since we don't know in
1399 * the assembler what the max addr reg value can be:
1401 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1403 case nir_intrinsic_load_ubo
:
1404 case nir_intrinsic_load_ubo_indirect
:
1405 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1407 case nir_intrinsic_load_input
:
1408 for (int i
= 0; i
< intr
->num_components
; i
++) {
1409 unsigned n
= idx
* 4 + i
;
1410 dst
[i
] = ctx
->ir
->inputs
[n
];
1413 case nir_intrinsic_load_input_indirect
:
1414 src
= get_src(ctx
, &intr
->src
[0]);
1415 struct ir3_instruction
*collect
=
1416 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1417 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1418 for (int i
= 0; i
< intr
->num_components
; i
++) {
1419 unsigned n
= idx
* 4 + i
;
1420 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1424 case nir_intrinsic_load_var
:
1425 emit_intrinisic_load_var(ctx
, intr
, dst
);
1427 case nir_intrinsic_store_var
:
1428 emit_intrinisic_store_var(ctx
, intr
);
1430 case nir_intrinsic_store_output
:
1431 src
= get_src(ctx
, &intr
->src
[0]);
1432 for (int i
= 0; i
< intr
->num_components
; i
++) {
1433 unsigned n
= idx
* 4 + i
;
1434 ctx
->ir
->outputs
[n
] = src
[i
];
1437 case nir_intrinsic_load_base_vertex
:
1438 if (!ctx
->basevertex
) {
1439 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1440 add_sysval_input(ctx
, TGSI_SEMANTIC_BASEVERTEX
,
1443 dst
[0] = ctx
->basevertex
;
1445 case nir_intrinsic_load_vertex_id_zero_base
:
1446 if (!ctx
->vertex_id
) {
1447 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1448 add_sysval_input(ctx
, TGSI_SEMANTIC_VERTEXID_NOBASE
,
1451 dst
[0] = ctx
->vertex_id
;
1453 case nir_intrinsic_load_instance_id
:
1454 if (!ctx
->instance_id
) {
1455 ctx
->instance_id
= create_input(ctx
->block
, 0);
1456 add_sysval_input(ctx
, TGSI_SEMANTIC_INSTANCEID
,
1459 dst
[0] = ctx
->instance_id
;
1461 case nir_intrinsic_discard_if
:
1462 case nir_intrinsic_discard
: {
1463 struct ir3_instruction
*cond
, *kill
;
1465 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1466 /* conditional discard: */
1467 src
= get_src(ctx
, &intr
->src
[0]);
1468 cond
= ir3_b2n(b
, src
[0]);
1470 /* unconditional discard: */
1471 cond
= create_immed(b
, 1);
1474 /* NOTE: only cmps.*.* can write p0.x: */
1475 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1476 cond
->cat2
.condition
= IR3_COND_NE
;
1478 /* condition always goes in predicate register: */
1479 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1481 kill
= ir3_KILL(b
, cond
, 0);
1482 array_insert(ctx
->ir
->predicates
, kill
);
1484 ctx
->kill
[ctx
->kill_count
++] = kill
;
1485 ctx
->so
->has_kill
= true;
1490 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1491 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1497 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1499 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1500 instr
->def
.num_components
);
1501 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1502 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1506 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1508 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1509 undef
->def
.num_components
);
1510 /* backend doesn't want undefined instructions, so just plug
1513 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1514 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1518 * texture fetch/sample instructions:
1522 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1524 unsigned coords
, flags
= 0;
1526 /* note: would use tex->coord_components.. except txs.. also,
1527 * since array index goes after shadow ref, we don't want to
1530 switch (tex
->sampler_dim
) {
1531 case GLSL_SAMPLER_DIM_1D
:
1532 case GLSL_SAMPLER_DIM_BUF
:
1535 case GLSL_SAMPLER_DIM_2D
:
1536 case GLSL_SAMPLER_DIM_RECT
:
1537 case GLSL_SAMPLER_DIM_EXTERNAL
:
1538 case GLSL_SAMPLER_DIM_MS
:
1541 case GLSL_SAMPLER_DIM_3D
:
1542 case GLSL_SAMPLER_DIM_CUBE
:
1544 flags
|= IR3_INSTR_3D
;
1547 unreachable("bad sampler_dim");
1551 flags
|= IR3_INSTR_S
;
1554 flags
|= IR3_INSTR_A
;
1561 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1563 struct ir3_block
*b
= ctx
->block
;
1564 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1565 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1566 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1567 unsigned i
, coords
, flags
;
1568 unsigned nsrc0
= 0, nsrc1
= 0;
1572 coord
= off
= ddx
= ddy
= NULL
;
1573 lod
= proj
= compare
= NULL
;
1575 /* TODO: might just be one component for gathers? */
1576 dst
= get_dst(ctx
, &tex
->dest
, 4);
1578 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1579 switch (tex
->src
[i
].src_type
) {
1580 case nir_tex_src_coord
:
1581 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1583 case nir_tex_src_bias
:
1584 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1587 case nir_tex_src_lod
:
1588 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1591 case nir_tex_src_comparitor
: /* shadow comparator */
1592 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1594 case nir_tex_src_projector
:
1595 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1598 case nir_tex_src_offset
:
1599 off
= get_src(ctx
, &tex
->src
[i
].src
);
1602 case nir_tex_src_ddx
:
1603 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1605 case nir_tex_src_ddy
:
1606 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1609 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1610 tex
->src
[i
].src_type
);
1616 case nir_texop_tex
: opc
= OPC_SAM
; break;
1617 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1618 case nir_texop_txl
: opc
= OPC_SAML
; break;
1619 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1620 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1621 case nir_texop_txf_ms
:
1625 case nir_texop_query_levels
:
1626 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1630 tex_info(tex
, &flags
, &coords
);
1632 /* scale up integer coords for TXF based on the LOD */
1633 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1635 for (i
= 0; i
< coords
; i
++)
1636 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1640 * lay out the first argument in the proper order:
1641 * - actual coordinates first
1642 * - shadow reference
1645 * - starting at offset 4, dpdx.xy, dpdy.xy
1647 * bias/lod go into the second arg
1650 /* insert tex coords: */
1651 for (i
= 0; i
< coords
; i
++)
1652 src0
[nsrc0
++] = coord
[i
];
1655 /* hw doesn't do 1d, so we treat it as 2d with
1656 * height of 1, and patch up the y coord.
1657 * TODO: y coord should be (int)0 in some cases..
1659 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1663 src0
[nsrc0
++] = compare
;
1666 src0
[nsrc0
++] = coord
[coords
];
1669 src0
[nsrc0
++] = proj
;
1670 flags
|= IR3_INSTR_P
;
1673 /* pad to 4, then ddx/ddy: */
1674 if (tex
->op
== nir_texop_txd
) {
1676 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1677 for (i
= 0; i
< coords
; i
++)
1678 src0
[nsrc0
++] = ddx
[i
];
1680 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1681 for (i
= 0; i
< coords
; i
++)
1682 src0
[nsrc0
++] = ddy
[i
];
1684 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1688 * second argument (if applicable):
1693 if (has_off
| has_lod
| has_bias
) {
1695 for (i
= 0; i
< coords
; i
++)
1696 src1
[nsrc1
++] = off
[i
];
1698 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1699 flags
|= IR3_INSTR_O
;
1702 if (has_lod
| has_bias
)
1703 src1
[nsrc1
++] = lod
;
1706 switch (tex
->dest_type
) {
1707 case nir_type_invalid
:
1708 case nir_type_float
:
1714 case nir_type_unsigned
:
1719 unreachable("bad dest_type");
1722 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1723 flags
, tex
->sampler_index
, tex
->sampler_index
,
1724 create_collect(b
, src0
, nsrc0
),
1725 create_collect(b
, src1
, nsrc1
));
1727 split_dest(b
, dst
, sam
, 4);
1731 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1733 struct ir3_block
*b
= ctx
->block
;
1734 struct ir3_instruction
**dst
, *sam
;
1736 dst
= get_dst(ctx
, &tex
->dest
, 1);
1738 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1739 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1741 /* even though there is only one component, since it ends
1742 * up in .z rather than .x, we need a split_dest()
1744 split_dest(b
, dst
, sam
, 3);
1746 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1747 * the value in TEX_CONST_0 is zero-based.
1749 if (ctx
->levels_add_one
)
1750 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1754 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1756 struct ir3_block
*b
= ctx
->block
;
1757 struct ir3_instruction
**dst
, *sam
, *lod
;
1758 unsigned flags
, coords
;
1760 tex_info(tex
, &flags
, &coords
);
1762 dst
= get_dst(ctx
, &tex
->dest
, 4);
1764 compile_assert(ctx
, tex
->num_srcs
== 1);
1765 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1767 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1769 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1770 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1772 split_dest(b
, dst
, sam
, 4);
1774 /* Array size actually ends up in .w rather than .z. This doesn't
1775 * matter for miplevel 0, but for higher mips the value in z is
1776 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1777 * returned, which means that we have to add 1 to it for arrays.
1779 if (tex
->is_array
) {
1780 if (ctx
->levels_add_one
) {
1781 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1783 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1789 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1791 struct ir3_instruction
*phi
, **dst
;
1793 /* NOTE: phi's should be lowered to scalar at this point */
1794 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1796 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1798 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1799 1 + exec_list_length(&nphi
->srcs
));
1800 ir3_reg_create(phi
, 0, 0); /* dst */
1801 phi
->phi
.nphi
= nphi
;
1806 /* phi instructions are left partially constructed. We don't resolve
1807 * their srcs until the end of the block, since (eg. loops) one of
1808 * the phi's srcs might be defined after the phi due to back edges in
1812 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1814 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1815 nir_phi_instr
*nphi
;
1817 /* phi's only come at start of block: */
1818 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1821 if (!instr
->phi
.nphi
)
1824 nphi
= instr
->phi
.nphi
;
1825 instr
->phi
.nphi
= NULL
;
1827 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1828 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1829 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1833 resolve_array_phis(ctx
, block
);
1837 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1839 switch (jump
->type
) {
1840 case nir_jump_break
:
1841 case nir_jump_continue
:
1842 /* I *think* we can simply just ignore this, and use the
1843 * successor block link to figure out where we need to
1844 * jump to for break/continue
1848 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1854 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1856 switch (instr
->type
) {
1857 case nir_instr_type_alu
:
1858 emit_alu(ctx
, nir_instr_as_alu(instr
));
1860 case nir_instr_type_intrinsic
:
1861 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1863 case nir_instr_type_load_const
:
1864 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1866 case nir_instr_type_ssa_undef
:
1867 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1869 case nir_instr_type_tex
: {
1870 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1871 /* couple tex instructions get special-cased:
1875 emit_tex_txs(ctx
, tex
);
1877 case nir_texop_query_levels
:
1878 emit_tex_query_levels(ctx
, tex
);
1886 case nir_instr_type_phi
:
1887 emit_phi(ctx
, nir_instr_as_phi(instr
));
1889 case nir_instr_type_jump
:
1890 emit_jump(ctx
, nir_instr_as_jump(instr
));
1892 case nir_instr_type_call
:
1893 case nir_instr_type_parallel_copy
:
1894 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1899 static struct ir3_block
*
1900 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1902 struct ir3_block
*block
;
1903 struct hash_entry
*entry
;
1904 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1908 block
= ir3_block_create(ctx
->ir
);
1909 block
->nblock
= nblock
;
1910 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1916 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1918 struct ir3_block
*block
= get_block(ctx
, nblock
);
1920 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1921 if (nblock
->successors
[i
]) {
1922 block
->successors
[i
] =
1923 get_block(ctx
, nblock
->successors
[i
]);
1928 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1930 nir_foreach_instr(nblock
, instr
) {
1931 emit_instr(ctx
, instr
);
1937 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1940 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1942 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1944 ctx
->block
->condition
=
1945 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1947 emit_cf_list(ctx
, &nif
->then_list
);
1948 emit_cf_list(ctx
, &nif
->else_list
);
1952 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1954 emit_cf_list(ctx
, &nloop
->body
);
1958 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1960 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1961 switch (node
->type
) {
1962 case nir_cf_node_block
:
1963 emit_block(ctx
, nir_cf_node_as_block(node
));
1965 case nir_cf_node_if
:
1966 emit_if(ctx
, nir_cf_node_as_if(node
));
1968 case nir_cf_node_loop
:
1969 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1971 case nir_cf_node_function
:
1972 compile_error(ctx
, "TODO\n");
1979 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
1981 emit_cf_list(ctx
, &impl
->body
);
1982 emit_block(ctx
, impl
->end_block
);
1984 /* at this point, we should have a single empty block,
1985 * into which we emit the 'end' instruction.
1987 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
1988 ir3_END(ctx
->block
);
1992 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
1994 struct ir3_shader_variant
*so
= ctx
->so
;
1995 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
1996 unsigned ncomp
= glsl_get_components(in
->type
);
1997 /* XXX: map loc slots to semantics */
1998 unsigned semantic_name
= in
->data
.location
;
1999 unsigned semantic_index
= in
->data
.index
;
2000 unsigned n
= in
->data
.driver_location
;
2002 DBG("; in: %u:%u, len=%ux%u, loc=%u",
2003 semantic_name
, semantic_index
, array_len
,
2006 so
->inputs
[n
].semantic
=
2007 ir3_semantic_name(semantic_name
, semantic_index
);
2008 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2009 so
->inputs
[n
].inloc
= ctx
->next_inloc
;
2010 so
->inputs
[n
].interpolate
= 0;
2011 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2013 /* the fdN_program_emit() code expects tgsi consts here, so map
2014 * things back to tgsi for now:
2016 switch (in
->data
.interpolation
) {
2017 case INTERP_QUALIFIER_FLAT
:
2018 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
2020 case INTERP_QUALIFIER_NOPERSPECTIVE
:
2021 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_LINEAR
;
2023 case INTERP_QUALIFIER_SMOOTH
:
2024 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_PERSPECTIVE
;
2028 for (int i
= 0; i
< ncomp
; i
++) {
2029 struct ir3_instruction
*instr
= NULL
;
2030 unsigned idx
= (n
* 4) + i
;
2032 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2033 if (semantic_name
== TGSI_SEMANTIC_POSITION
) {
2034 so
->inputs
[n
].bary
= false;
2035 so
->frag_coord
= true;
2036 instr
= create_frag_coord(ctx
, i
);
2037 } else if (semantic_name
== TGSI_SEMANTIC_FACE
) {
2038 so
->inputs
[n
].bary
= false;
2039 so
->frag_face
= true;
2040 instr
= create_frag_face(ctx
, i
);
2042 bool use_ldlv
= false;
2044 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2045 * from the semantic name:
2047 if ((in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) &&
2048 ((semantic_name
== TGSI_SEMANTIC_COLOR
) ||
2049 (semantic_name
== TGSI_SEMANTIC_BCOLOR
)))
2050 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_COLOR
;
2052 if (ctx
->flat_bypass
) {
2053 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2054 * from the semantic name:
2056 switch (so
->inputs
[n
].interpolate
) {
2057 case TGSI_INTERPOLATE_COLOR
:
2058 if (!ctx
->so
->key
.rasterflat
)
2061 case TGSI_INTERPOLATE_CONSTANT
:
2067 so
->inputs
[n
].bary
= true;
2069 instr
= create_frag_input(ctx
,
2070 so
->inputs
[n
].inloc
+ i
- 8, use_ldlv
);
2073 instr
= create_input(ctx
->block
, idx
);
2076 ctx
->ir
->inputs
[idx
] = instr
;
2079 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2080 ctx
->next_inloc
+= ncomp
;
2081 so
->total_in
+= ncomp
;
2086 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2088 struct ir3_shader_variant
*so
= ctx
->so
;
2089 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2090 unsigned ncomp
= glsl_get_components(out
->type
);
2091 /* XXX: map loc slots to semantics */
2092 unsigned semantic_name
= out
->data
.location
;
2093 unsigned semantic_index
= out
->data
.index
;
2094 unsigned n
= out
->data
.driver_location
;
2097 DBG("; out: %u:%u, len=%ux%u, loc=%u",
2098 semantic_name
, semantic_index
, array_len
,
2101 if (ctx
->so
->type
== SHADER_VERTEX
) {
2102 switch (semantic_name
) {
2103 case TGSI_SEMANTIC_POSITION
:
2104 so
->writes_pos
= true;
2106 case TGSI_SEMANTIC_PSIZE
:
2107 so
->writes_psize
= true;
2109 case TGSI_SEMANTIC_COLOR
:
2110 case TGSI_SEMANTIC_BCOLOR
:
2111 case TGSI_SEMANTIC_GENERIC
:
2112 case TGSI_SEMANTIC_FOG
:
2113 case TGSI_SEMANTIC_TEXCOORD
:
2116 compile_error(ctx
, "unknown VS semantic name: %s\n",
2117 tgsi_semantic_names
[semantic_name
]);
2120 switch (semantic_name
) {
2121 case TGSI_SEMANTIC_POSITION
:
2122 comp
= 2; /* tgsi will write to .z component */
2123 so
->writes_pos
= true;
2125 case TGSI_SEMANTIC_COLOR
:
2126 if (semantic_index
== -1) {
2132 compile_error(ctx
, "unknown FS semantic name: %s\n",
2133 tgsi_semantic_names
[semantic_name
]);
2137 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2139 so
->outputs
[n
].semantic
=
2140 ir3_semantic_name(semantic_name
, semantic_index
);
2141 so
->outputs
[n
].regid
= regid(n
, comp
);
2142 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2144 for (int i
= 0; i
< ncomp
; i
++) {
2145 unsigned idx
= (n
* 4) + i
;
2147 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2152 emit_instructions(struct ir3_compile
*ctx
)
2154 unsigned ninputs
, noutputs
;
2155 nir_function_impl
*fxn
= NULL
;
2157 /* Find the main function: */
2158 nir_foreach_overload(ctx
->s
, overload
) {
2159 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
2160 compile_assert(ctx
, overload
->impl
);
2161 fxn
= overload
->impl
;
2165 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2166 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2168 /* we need to allocate big enough outputs array so that
2169 * we can stuff the kill's at the end. Likewise for vtx
2170 * shaders, we need to leave room for sysvals:
2172 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2173 noutputs
+= ARRAY_SIZE(ctx
->kill
);
2174 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2178 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2180 /* Create inputs in first block: */
2181 ctx
->block
= get_block(ctx
, fxn
->start_block
);
2182 ctx
->in_block
= ctx
->block
;
2183 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2185 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2186 ctx
->ir
->noutputs
-= ARRAY_SIZE(ctx
->kill
);
2187 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2188 ctx
->ir
->ninputs
-= 8;
2191 /* for fragment shader, we have a single input register (usually
2192 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2194 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2195 // TODO maybe a helper for fi since we need it a few places..
2196 struct ir3_instruction
*instr
;
2197 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2198 ir3_reg_create(instr
, 0, 0);
2199 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2200 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2201 ctx
->frag_pos
= instr
;
2205 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->inputs
) {
2206 setup_input(ctx
, var
);
2209 /* Setup outputs: */
2210 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->outputs
) {
2211 setup_output(ctx
, var
);
2214 /* Setup variables (which should only be arrays): */
2215 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->globals
) {
2216 declare_var(ctx
, var
);
2219 /* And emit the body: */
2221 emit_function(ctx
, fxn
);
2223 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2224 resolve_phis(ctx
, block
);
2228 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2229 * for a fragment shader are just bary.f instructions. The *actual* inputs
2230 * from the hw perspective are the frag_pos and optionally frag_coord and
2234 fixup_frag_inputs(struct ir3_compile
*ctx
)
2236 struct ir3_shader_variant
*so
= ctx
->so
;
2237 struct ir3
*ir
= ctx
->ir
;
2238 struct ir3_instruction
**inputs
;
2239 struct ir3_instruction
*instr
;
2244 n
= 4; /* always have frag_pos */
2245 n
+= COND(so
->frag_face
, 4);
2246 n
+= COND(so
->frag_coord
, 4);
2248 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2250 if (so
->frag_face
) {
2251 /* this ultimately gets assigned to hr0.x so doesn't conflict
2252 * with frag_coord/frag_pos..
2254 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2255 ctx
->frag_face
->regs
[0]->num
= 0;
2257 /* remaining channels not used, but let's avoid confusing
2258 * other parts that expect inputs to come in groups of vec4
2260 inputs
[ir
->ninputs
++] = NULL
;
2261 inputs
[ir
->ninputs
++] = NULL
;
2262 inputs
[ir
->ninputs
++] = NULL
;
2265 /* since we don't know where to set the regid for frag_coord,
2266 * we have to use r0.x for it. But we don't want to *always*
2267 * use r1.x for frag_pos as that could increase the register
2268 * footprint on simple shaders:
2270 if (so
->frag_coord
) {
2271 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2272 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2273 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2274 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2276 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2277 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2278 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2279 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2282 /* we always have frag_pos: */
2283 so
->pos_regid
= regid
;
2286 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2287 instr
->regs
[0]->num
= regid
++;
2288 inputs
[ir
->ninputs
++] = instr
;
2289 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2292 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2293 instr
->regs
[0]->num
= regid
++;
2294 inputs
[ir
->ninputs
++] = instr
;
2295 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2297 ir
->inputs
= inputs
;
2301 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2302 struct ir3_shader_variant
*so
)
2304 struct ir3_compile
*ctx
;
2306 struct ir3_instruction
**inputs
;
2307 unsigned i
, j
, actual_in
;
2308 int ret
= 0, max_bary
;
2312 ctx
= compile_init(compiler
, so
, so
->shader
->tokens
);
2314 DBG("INIT failed!");
2319 emit_instructions(ctx
);
2322 DBG("EMIT failed!");
2327 ir
= so
->ir
= ctx
->ir
;
2329 /* keep track of the inputs from TGSI perspective.. */
2330 inputs
= ir
->inputs
;
2332 /* but fixup actual inputs for frag shader: */
2333 if (so
->type
== SHADER_FRAGMENT
)
2334 fixup_frag_inputs(ctx
);
2336 /* at this point, for binning pass, throw away unneeded outputs: */
2337 if (so
->key
.binning_pass
) {
2338 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2339 unsigned name
= sem2name(so
->outputs
[i
].semantic
);
2340 unsigned idx
= sem2idx(so
->outputs
[i
].semantic
);
2342 /* throw away everything but first position/psize */
2343 if ((idx
== 0) && ((name
== TGSI_SEMANTIC_POSITION
) ||
2344 (name
== TGSI_SEMANTIC_PSIZE
))) {
2346 so
->outputs
[j
] = so
->outputs
[i
];
2347 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2348 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2349 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2350 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2355 so
->outputs_count
= j
;
2356 ir
->noutputs
= j
* 4;
2359 /* if we want half-precision outputs, mark the output registers
2362 if (so
->key
.half_precision
) {
2363 for (i
= 0; i
< ir
->noutputs
; i
++) {
2364 struct ir3_instruction
*out
= ir
->outputs
[i
];
2367 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2368 /* output could be a fanout (ie. texture fetch output)
2369 * in which case we need to propagate the half-reg flag
2370 * up to the definer so that RA sees it:
2372 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2373 out
= out
->regs
[1]->instr
;
2374 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2377 if (out
->category
== 1) {
2378 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2383 /* at this point, we want the kill's in the outputs array too,
2384 * so that they get scheduled (since they have no dst).. we've
2385 * already ensured that the array is big enough in push_block():
2387 if (so
->type
== SHADER_FRAGMENT
) {
2388 for (i
= 0; i
< ctx
->kill_count
; i
++)
2389 ir
->outputs
[ir
->noutputs
++] = ctx
->kill
[i
];
2392 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2393 printf("BEFORE CP:\n");
2399 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2400 printf("BEFORE GROUPING:\n");
2404 /* Group left/right neighbors, inserting mov's where needed to
2411 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2412 printf("AFTER DEPTH:\n");
2416 ret
= ir3_sched(ir
);
2418 DBG("SCHED failed!");
2422 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2423 printf("AFTER SCHED:\n");
2427 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2433 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2434 printf("AFTER RA:\n");
2438 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2440 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2441 printf("AFTER LEGALIZE:\n");
2445 /* fixup input/outputs: */
2446 for (i
= 0; i
< so
->outputs_count
; i
++) {
2447 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2448 /* preserve hack for depth output.. tgsi writes depth to .z,
2449 * but what we give the hw is the scalar register:
2451 if ((so
->type
== SHADER_FRAGMENT
) &&
2452 (sem2name(so
->outputs
[i
].semantic
) == TGSI_SEMANTIC_POSITION
))
2453 so
->outputs
[i
].regid
+= 2;
2456 /* Note that some or all channels of an input may be unused: */
2458 for (i
= 0; i
< so
->inputs_count
; i
++) {
2459 unsigned j
, regid
= ~0, compmask
= 0;
2460 so
->inputs
[i
].ncomp
= 0;
2461 for (j
= 0; j
< 4; j
++) {
2462 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2464 compmask
|= (1 << j
);
2465 regid
= in
->regs
[0]->num
- j
;
2467 so
->inputs
[i
].ncomp
++;
2470 so
->inputs
[i
].regid
= regid
;
2471 so
->inputs
[i
].compmask
= compmask
;
2474 /* fragment shader always gets full vec4's even if it doesn't
2475 * fetch all components, but vertex shader we need to update
2476 * with the actual number of components fetch, otherwise thing
2477 * will hang due to mismaptch between VFD_DECODE's and
2480 if (so
->type
== SHADER_VERTEX
)
2481 so
->total_in
= actual_in
;
2483 so
->total_in
= align(max_bary
+ 1, 4);
2488 ir3_destroy(so
->ir
);