1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* mapping from nir_register to defining instruction: */
78 struct hash_table
*def_ht
;
82 /* a common pattern for indirect addressing is to request the
83 * same address register multiple times. To avoid generating
84 * duplicate instruction sequences (which our backend does not
85 * try to clean up, since that should be done as the NIR stage)
86 * we cache the address value generated for a given src value:
88 * Note that we have to cache these per alignment, since same
89 * src used for an array of vec1 cannot be also used for an
92 struct hash_table
*addr_ht
[4];
94 /* last dst array, for indirect we need to insert a var-store.
96 struct ir3_instruction
**last_dst
;
99 /* maps nir_block to ir3_block, mostly for the purposes of
100 * figuring out the blocks successors
102 struct hash_table
*block_ht
;
104 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
105 * so we need to use ldlv.u32 to load the varying directly:
109 /* on a3xx, we need to add one to # of array levels:
113 /* on a3xx, we need to scale up integer coords for isaml based
116 bool unminify_coords
;
118 /* on a4xx, for array textures we need to add 0.5 to the array
121 bool array_index_add_half
;
123 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
126 unsigned max_texture_index
;
128 /* set if we encounter something we can't handle yet, so we
129 * can bail cleanly and fallback to TGSI compiler f/e
134 /* gpu pointer size in units of 32bit registers/slots */
135 static unsigned pointer_size(struct ir3_context
*ctx
)
137 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
140 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
141 static struct ir3_block
* get_block(struct ir3_context
*ctx
, nir_block
*nblock
);
144 static struct ir3_context
*
145 compile_init(struct ir3_compiler
*compiler
,
146 struct ir3_shader_variant
*so
)
148 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
150 if (compiler
->gpu_id
>= 400) {
151 /* need special handling for "flat" */
152 ctx
->flat_bypass
= true;
153 ctx
->levels_add_one
= false;
154 ctx
->unminify_coords
= false;
155 ctx
->array_index_add_half
= true;
157 if (so
->type
== SHADER_VERTEX
)
158 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
159 else if (so
->type
== SHADER_FRAGMENT
)
160 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
163 /* no special handling for "flat" */
164 ctx
->flat_bypass
= false;
165 ctx
->levels_add_one
= true;
166 ctx
->unminify_coords
= true;
167 ctx
->array_index_add_half
= false;
170 ctx
->compiler
= compiler
;
173 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
174 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
175 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
176 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
178 /* TODO: maybe generate some sort of bitmask of what key
179 * lowers vs what shader has (ie. no need to lower
180 * texture clamp lowering if no texture sample instrs)..
181 * although should be done further up the stack to avoid
182 * creating duplicate variants..
185 if (ir3_key_lowers_nir(&so
->key
)) {
186 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
187 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
189 /* fast-path for shader key that lowers nothing in NIR: */
190 ctx
->s
= so
->shader
->nir
;
193 /* this needs to be the last pass run, so do this here instead of
194 * in ir3_optimize_nir():
196 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
197 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
199 if (fd_mesa_debug
& FD_DBG_DISASM
) {
200 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
201 so
->shader
->id
, so
->id
, so
->type
,
202 so
->key
.binning_pass
, so
->key
.color_two_side
,
203 so
->key
.half_precision
);
204 nir_print_shader(ctx
->s
, stdout
);
207 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
209 so
->num_uniforms
= ctx
->s
->num_uniforms
;
210 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
212 /* Layout of constant registers, each section aligned to vec4. Note
213 * that pointer size (ubo, etc) changes depending on generation.
218 * if (vertex shader) {
219 * driver params (IR3_DP_*)
220 * if (stream_output.num_outputs > 0)
221 * stream-out addresses
225 * Immediates go last mostly because they are inserted in the CP pass
226 * after the nir -> ir3 frontend.
228 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
229 unsigned ptrsz
= pointer_size(ctx
);
231 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
233 if (so
->num_ubos
> 0) {
234 so
->constbase
.ubo
= constoff
;
235 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
238 if (so
->const_layout
.ssbo_size
.count
> 0) {
239 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
240 so
->constbase
.ssbo_sizes
= constoff
;
241 constoff
+= align(cnt
, 4) / 4;
244 if (so
->const_layout
.image_dims
.count
> 0) {
245 unsigned cnt
= so
->const_layout
.image_dims
.count
;
246 so
->constbase
.image_dims
= constoff
;
247 constoff
+= align(cnt
, 4) / 4;
250 unsigned num_driver_params
= 0;
251 if (so
->type
== SHADER_VERTEX
) {
252 num_driver_params
= IR3_DP_VS_COUNT
;
253 } else if (so
->type
== SHADER_COMPUTE
) {
254 num_driver_params
= IR3_DP_CS_COUNT
;
257 so
->constbase
.driver_param
= constoff
;
258 constoff
+= align(num_driver_params
, 4) / 4;
260 if ((so
->type
== SHADER_VERTEX
) &&
261 (compiler
->gpu_id
< 500) &&
262 so
->shader
->stream_output
.num_outputs
> 0) {
263 so
->constbase
.tfbo
= constoff
;
264 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
267 so
->constbase
.immediate
= constoff
;
273 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
276 va_start(ap
, format
);
277 _debug_vprintf(format
, ap
);
279 nir_print_shader(ctx
->s
, stdout
);
284 #define compile_assert(ctx, cond) do { \
285 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
289 compile_free(struct ir3_context
*ctx
)
295 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
297 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
298 arr
->id
= ++ctx
->num_arrays
;
299 /* NOTE: sometimes we get non array regs, for example for arrays of
300 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
301 * treat a non-array as if it was an array of length 1.
303 * It would be nice if there was a nir pass to convert arrays of
306 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
307 compile_assert(ctx
, arr
->length
> 0);
309 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
312 static struct ir3_array
*
313 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
315 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
319 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
323 /* relative (indirect) if address!=NULL */
324 static struct ir3_instruction
*
325 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
326 struct ir3_instruction
*address
)
328 struct ir3_block
*block
= ctx
->block
;
329 struct ir3_instruction
*mov
;
330 struct ir3_register
*src
;
332 mov
= ir3_instr_create(block
, OPC_MOV
);
333 mov
->cat1
.src_type
= TYPE_U32
;
334 mov
->cat1
.dst_type
= TYPE_U32
;
335 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
336 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
337 ir3_reg_create(mov
, 0, 0);
338 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
339 COND(address
, IR3_REG_RELATIV
));
340 src
->instr
= arr
->last_write
;
341 src
->size
= arr
->length
;
342 src
->array
.id
= arr
->id
;
343 src
->array
.offset
= n
;
346 ir3_instr_set_address(mov
, address
);
351 /* relative (indirect) if address!=NULL */
353 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
354 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
356 struct ir3_block
*block
= ctx
->block
;
357 struct ir3_instruction
*mov
;
358 struct ir3_register
*dst
;
360 /* if not relative store, don't create an extra mov, since that
361 * ends up being difficult for cp to remove.
366 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
367 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
369 dst
->flags
|= IR3_REG_ARRAY
;
370 dst
->instr
= arr
->last_write
;
371 dst
->size
= arr
->length
;
372 dst
->array
.id
= arr
->id
;
373 dst
->array
.offset
= n
;
375 arr
->last_write
= src
;
377 array_insert(block
, block
->keeps
, src
);
382 mov
= ir3_instr_create(block
, OPC_MOV
);
383 mov
->cat1
.src_type
= TYPE_U32
;
384 mov
->cat1
.dst_type
= TYPE_U32
;
385 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
386 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
387 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
388 COND(address
, IR3_REG_RELATIV
));
389 dst
->instr
= arr
->last_write
;
390 dst
->size
= arr
->length
;
391 dst
->array
.id
= arr
->id
;
392 dst
->array
.offset
= n
;
393 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
396 ir3_instr_set_address(mov
, address
);
398 arr
->last_write
= mov
;
400 /* the array store may only matter to something in an earlier
401 * block (ie. loops), but since arrays are not in SSA, depth
402 * pass won't know this.. so keep all array stores:
404 array_insert(block
, block
->keeps
, mov
);
407 /* allocate a n element value array (to be populated by caller) and
410 static struct ir3_instruction
**
411 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
413 struct ir3_instruction
**value
=
414 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
415 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
419 static struct ir3_instruction
**
420 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
422 struct ir3_instruction
**value
;
425 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
427 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
430 /* NOTE: in non-ssa case, we don't really need to store last_dst
431 * but this helps us catch cases where put_dst() call is forgotten
433 compile_assert(ctx
, !ctx
->last_dst
);
434 ctx
->last_dst
= value
;
440 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
442 static struct ir3_instruction
* const *
443 get_src(struct ir3_context
*ctx
, nir_src
*src
)
446 struct hash_entry
*entry
;
447 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
448 compile_assert(ctx
, entry
);
451 nir_register
*reg
= src
->reg
.reg
;
452 struct ir3_array
*arr
= get_array(ctx
, reg
);
453 unsigned num_components
= arr
->r
->num_components
;
454 struct ir3_instruction
*addr
= NULL
;
455 struct ir3_instruction
**value
=
456 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
458 if (src
->reg
.indirect
)
459 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
460 reg
->num_components
);
462 for (unsigned i
= 0; i
< num_components
; i
++) {
463 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
464 compile_assert(ctx
, n
< arr
->length
);
465 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
473 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
476 nir_register
*reg
= dst
->reg
.reg
;
477 struct ir3_array
*arr
= get_array(ctx
, reg
);
478 unsigned num_components
= ctx
->last_dst_n
;
479 struct ir3_instruction
*addr
= NULL
;
481 if (dst
->reg
.indirect
)
482 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
483 reg
->num_components
);
485 for (unsigned i
= 0; i
< num_components
; i
++) {
486 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
487 compile_assert(ctx
, n
< arr
->length
);
488 if (!ctx
->last_dst
[i
])
490 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
493 ralloc_free(ctx
->last_dst
);
495 ctx
->last_dst
= NULL
;
499 static struct ir3_instruction
*
500 create_immed(struct ir3_block
*block
, uint32_t val
)
502 struct ir3_instruction
*mov
;
504 mov
= ir3_instr_create(block
, OPC_MOV
);
505 mov
->cat1
.src_type
= TYPE_U32
;
506 mov
->cat1
.dst_type
= TYPE_U32
;
507 ir3_reg_create(mov
, 0, 0);
508 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
513 static struct ir3_instruction
*
514 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
516 struct ir3_instruction
*instr
, *immed
;
518 /* TODO in at least some cases, the backend could probably be
519 * made clever enough to propagate IR3_REG_HALF..
521 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
522 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
529 /* src *= 2 => src <<= 1: */
530 immed
= create_immed(block
, 1);
531 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
533 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
534 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
535 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
539 immed
= create_immed(block
, 3);
540 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
542 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
543 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
544 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
547 /* src *= 4 => src <<= 2: */
548 immed
= create_immed(block
, 2);
549 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
551 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
552 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
553 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
556 unreachable("bad align");
560 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
561 instr
->regs
[0]->num
= regid(REG_A0
, 0);
562 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
563 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
568 /* caches addr values to avoid generating multiple cov/shl/mova
569 * sequences for each use of a given NIR level src as address
571 static struct ir3_instruction
*
572 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
574 struct ir3_instruction
*addr
;
575 unsigned idx
= align
- 1;
577 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
579 if (!ctx
->addr_ht
[idx
]) {
580 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
581 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
583 struct hash_entry
*entry
;
584 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
589 addr
= create_addr(ctx
->block
, src
, align
);
590 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
595 static struct ir3_instruction
*
596 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
598 struct ir3_block
*b
= ctx
->block
;
599 struct ir3_instruction
*cond
;
601 /* NOTE: only cmps.*.* can write p0.x: */
602 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
603 cond
->cat2
.condition
= IR3_COND_NE
;
605 /* condition always goes in predicate register: */
606 cond
->regs
[0]->num
= regid(REG_P0
, 0);
611 static struct ir3_instruction
*
612 create_uniform(struct ir3_context
*ctx
, unsigned n
)
614 struct ir3_instruction
*mov
;
616 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
617 /* TODO get types right? */
618 mov
->cat1
.src_type
= TYPE_F32
;
619 mov
->cat1
.dst_type
= TYPE_F32
;
620 ir3_reg_create(mov
, 0, 0);
621 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
626 static struct ir3_instruction
*
627 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
628 struct ir3_instruction
*address
)
630 struct ir3_instruction
*mov
;
632 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
633 mov
->cat1
.src_type
= TYPE_U32
;
634 mov
->cat1
.dst_type
= TYPE_U32
;
635 ir3_reg_create(mov
, 0, 0);
636 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
638 ir3_instr_set_address(mov
, address
);
643 static struct ir3_instruction
*
644 create_collect(struct ir3_block
*block
, struct ir3_instruction
*const *arr
,
647 struct ir3_instruction
*collect
;
652 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
653 ir3_reg_create(collect
, 0, 0); /* dst */
654 for (unsigned i
= 0; i
< arrsz
; i
++)
655 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
660 static struct ir3_instruction
*
661 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
662 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
664 struct ir3_block
*block
= ctx
->block
;
665 struct ir3_instruction
*mov
;
666 struct ir3_register
*src
;
668 mov
= ir3_instr_create(block
, OPC_MOV
);
669 mov
->cat1
.src_type
= TYPE_U32
;
670 mov
->cat1
.dst_type
= TYPE_U32
;
671 ir3_reg_create(mov
, 0, 0);
672 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
673 src
->instr
= collect
;
675 src
->array
.offset
= n
;
677 ir3_instr_set_address(mov
, address
);
682 static struct ir3_instruction
*
683 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
685 struct ir3_instruction
*in
;
687 in
= ir3_instr_create(block
, OPC_META_INPUT
);
688 in
->inout
.block
= block
;
689 ir3_reg_create(in
, n
, 0);
691 in
->regs
[0]->wrmask
= compmask
;
696 static struct ir3_instruction
*
697 create_input(struct ir3_block
*block
, unsigned n
)
699 return create_input_compmask(block
, n
, 0x1);
702 static struct ir3_instruction
*
703 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
705 struct ir3_block
*block
= ctx
->block
;
706 struct ir3_instruction
*instr
;
707 /* actual inloc is assigned and fixed up later: */
708 struct ir3_instruction
*inloc
= create_immed(block
, 0);
711 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
712 instr
->cat6
.type
= TYPE_U32
;
713 instr
->cat6
.iim_val
= 1;
715 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
716 instr
->regs
[2]->wrmask
= 0x3;
722 static struct ir3_instruction
*
723 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
725 struct ir3_block
*block
= ctx
->block
;
726 struct ir3_instruction
*instr
;
728 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
730 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
735 /* for frag_coord, we get unsigned values.. we need
736 * to subtract (integer) 8 and divide by 16 (right-
737 * shift by 4) then convert to float:
741 * mov.u32f32 dst, tmp
744 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
745 create_immed(block
, 8), 0);
746 instr
= ir3_SHR_B(block
, instr
, 0,
747 create_immed(block
, 4), 0);
748 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
754 /* seems that we can use these as-is: */
755 return ctx
->frag_coord
[comp
];
759 static struct ir3_instruction
*
760 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
762 /* first four vec4 sysval's reserved for UBOs: */
763 /* NOTE: dp is in scalar, but there can be >4 dp components: */
764 unsigned n
= ctx
->so
->constbase
.driver_param
;
765 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
766 return create_uniform(ctx
, r
);
769 /* helper for instructions that produce multiple consecutive scalar
770 * outputs which need to have a split/fanout meta instruction inserted
773 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
774 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
776 struct ir3_instruction
*prev
= NULL
;
778 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
783 for (int i
= 0, j
= 0; i
< n
; i
++) {
784 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
785 ir3_reg_create(split
, 0, IR3_REG_SSA
);
786 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
787 split
->fo
.off
= i
+ base
;
790 split
->cp
.left
= prev
;
791 split
->cp
.left_cnt
++;
792 prev
->cp
.right
= split
;
793 prev
->cp
.right_cnt
++;
797 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
803 * Adreno uses uint rather than having dedicated bool type,
804 * which (potentially) requires some conversion, in particular
805 * when using output of an bool instr to int input, or visa
809 * -------+---------+-------+-
813 * To convert from an adreno bool (uint) to nir, use:
815 * absneg.s dst, (neg)src
817 * To convert back in the other direction:
819 * absneg.s dst, (abs)arc
821 * The CP step can clean up the absneg.s that cancel each other
822 * out, and with a slight bit of extra cleverness (to recognize
823 * the instructions which produce either a 0 or 1) can eliminate
824 * the absneg.s's completely when an instruction that wants
825 * 0/1 consumes the result. For example, when a nir 'bcsel'
826 * consumes the result of 'feq'. So we should be able to get by
827 * without a boolean resolve step, and without incuring any
828 * extra penalty in instruction count.
831 /* NIR bool -> native (adreno): */
832 static struct ir3_instruction
*
833 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
835 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
838 /* native (adreno) -> NIR bool: */
839 static struct ir3_instruction
*
840 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
842 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
846 * alu/sfu instructions:
850 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
852 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
853 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
854 struct ir3_block
*b
= ctx
->block
;
855 unsigned dst_sz
, wrmask
;
857 if (alu
->dest
.dest
.is_ssa
) {
858 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
859 wrmask
= (1 << dst_sz
) - 1;
861 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
862 wrmask
= alu
->dest
.write_mask
;
865 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
867 /* Vectors are special in that they have non-scalarized writemasks,
868 * and just take the first swizzle channel for each argument in
869 * order into each writemask channel.
871 if ((alu
->op
== nir_op_vec2
) ||
872 (alu
->op
== nir_op_vec3
) ||
873 (alu
->op
== nir_op_vec4
)) {
875 for (int i
= 0; i
< info
->num_inputs
; i
++) {
876 nir_alu_src
*asrc
= &alu
->src
[i
];
878 compile_assert(ctx
, !asrc
->abs
);
879 compile_assert(ctx
, !asrc
->negate
);
881 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
883 src
[i
] = create_immed(ctx
->block
, 0);
884 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
887 put_dst(ctx
, &alu
->dest
.dest
);
891 /* We also get mov's with more than one component for mov's so
892 * handle those specially:
894 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
895 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
896 nir_alu_src
*asrc
= &alu
->src
[0];
897 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
899 for (unsigned i
= 0; i
< dst_sz
; i
++) {
900 if (wrmask
& (1 << i
)) {
901 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
907 put_dst(ctx
, &alu
->dest
.dest
);
911 /* General case: We can just grab the one used channel per src. */
912 for (int i
= 0; i
< info
->num_inputs
; i
++) {
913 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
914 nir_alu_src
*asrc
= &alu
->src
[i
];
916 compile_assert(ctx
, !asrc
->abs
);
917 compile_assert(ctx
, !asrc
->negate
);
919 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
921 compile_assert(ctx
, src
[i
]);
926 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
929 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
932 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
935 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
938 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
939 dst
[0]->cat2
.condition
= IR3_COND_NE
;
940 dst
[0] = ir3_n2b(b
, dst
[0]);
943 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
946 dst
[0] = ir3_b2n(b
, src
[0]);
949 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
950 dst
[0]->cat2
.condition
= IR3_COND_NE
;
951 dst
[0] = ir3_n2b(b
, dst
[0]);
955 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
958 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
961 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
964 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
967 /* if there is just a single use of the src, and it supports
968 * (sat) bit, we can just fold the (sat) flag back to the
969 * src instruction and create a mov. This is easier for cp
972 * TODO probably opc_cat==4 is ok too
974 if (alu
->src
[0].src
.is_ssa
&&
975 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
976 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
977 src
[0]->flags
|= IR3_INSTR_SAT
;
978 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
980 /* otherwise generate a max.f that saturates.. blob does
981 * similar (generating a cat2 mov using max.f)
983 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
984 dst
[0]->flags
|= IR3_INSTR_SAT
;
988 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
991 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
994 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
997 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1000 dst
[0] = ir3_DSX(b
, src
[0], 0);
1001 dst
[0]->cat5
.type
= TYPE_F32
;
1004 dst
[0] = ir3_DSY(b
, src
[0], 0);
1005 dst
[0]->cat5
.type
= TYPE_F32
;
1009 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1010 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1011 dst
[0] = ir3_n2b(b
, dst
[0]);
1014 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1015 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1016 dst
[0] = ir3_n2b(b
, dst
[0]);
1019 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1020 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1021 dst
[0] = ir3_n2b(b
, dst
[0]);
1024 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1025 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1026 dst
[0] = ir3_n2b(b
, dst
[0]);
1029 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1032 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1035 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1037 case nir_op_fround_even
:
1038 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1041 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1045 dst
[0] = ir3_SIN(b
, src
[0], 0);
1048 dst
[0] = ir3_COS(b
, src
[0], 0);
1051 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1054 dst
[0] = ir3_RCP(b
, src
[0], 0);
1057 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1060 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1063 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1067 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1070 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1073 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1076 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1079 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1082 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1085 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1089 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1090 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1091 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1092 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1094 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1095 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1096 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1099 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1102 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1105 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1108 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1111 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1113 case nir_op_isign
: {
1114 /* maybe this would be sane to lower in nir.. */
1115 struct ir3_instruction
*neg
, *pos
;
1117 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1118 neg
->cat2
.condition
= IR3_COND_LT
;
1120 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1121 pos
->cat2
.condition
= IR3_COND_GT
;
1123 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1128 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1131 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1134 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1137 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1138 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1139 dst
[0] = ir3_n2b(b
, dst
[0]);
1142 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1143 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1144 dst
[0] = ir3_n2b(b
, dst
[0]);
1147 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1148 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1149 dst
[0] = ir3_n2b(b
, dst
[0]);
1152 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1153 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1154 dst
[0] = ir3_n2b(b
, dst
[0]);
1157 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1158 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1159 dst
[0] = ir3_n2b(b
, dst
[0]);
1162 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1163 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1164 dst
[0] = ir3_n2b(b
, dst
[0]);
1168 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1171 case nir_op_bit_count
:
1172 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1174 case nir_op_ifind_msb
: {
1175 struct ir3_instruction
*cmp
;
1176 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1177 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1178 cmp
->cat2
.condition
= IR3_COND_GE
;
1179 dst
[0] = ir3_SEL_B32(b
,
1180 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1184 case nir_op_ufind_msb
:
1185 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1186 dst
[0] = ir3_SEL_B32(b
,
1187 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1188 src
[0], 0, dst
[0], 0);
1190 case nir_op_find_lsb
:
1191 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1192 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1194 case nir_op_bitfield_reverse
:
1195 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1199 compile_error(ctx
, "Unhandled ALU op: %s\n",
1200 nir_op_infos
[alu
->op
].name
);
1204 put_dst(ctx
, &alu
->dest
.dest
);
1207 /* handles direct/indirect UBO reads: */
1209 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1210 struct ir3_instruction
**dst
)
1212 struct ir3_block
*b
= ctx
->block
;
1213 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1214 nir_const_value
*const_offset
;
1215 /* UBO addresses are the first driver params: */
1216 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1217 const unsigned ptrsz
= pointer_size(ctx
);
1221 /* First src is ubo index, which could either be an immed or not: */
1222 src0
= get_src(ctx
, &intr
->src
[0])[0];
1223 if (is_same_type_mov(src0
) &&
1224 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1225 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1226 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1228 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1229 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1232 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1235 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1237 off
+= const_offset
->u32
[0];
1239 /* For load_ubo_indirect, second src is indirect offset: */
1240 src1
= get_src(ctx
, &intr
->src
[1])[0];
1242 /* and add offset to addr: */
1243 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1246 /* if offset is to large to encode in the ldg, split it out: */
1247 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1248 /* split out the minimal amount to improve the odds that
1249 * cp can fit the immediate in the add.s instruction:
1251 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1252 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1257 struct ir3_instruction
*carry
;
1259 /* handle 32b rollover, ie:
1260 * if (addr < base_lo)
1263 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1264 carry
->cat2
.condition
= IR3_COND_LT
;
1265 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1267 addr
= create_collect(b
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1270 for (int i
= 0; i
< intr
->num_components
; i
++) {
1271 struct ir3_instruction
*load
=
1272 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1273 load
->cat6
.type
= TYPE_U32
;
1274 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1279 /* src[] = { buffer_index, offset }. No const_index */
1281 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1282 struct ir3_instruction
**dst
)
1284 struct ir3_block
*b
= ctx
->block
;
1285 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1286 nir_const_value
*const_offset
;
1288 /* can this be non-const buffer_index? how do we handle that? */
1289 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1290 compile_assert(ctx
, const_offset
);
1292 offset
= get_src(ctx
, &intr
->src
[1])[0];
1294 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1295 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1299 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1301 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1303 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1304 ldgb
->cat6
.iim_val
= intr
->num_components
;
1306 ldgb
->cat6
.type
= TYPE_U32
;
1307 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1308 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1310 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1313 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1315 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1317 struct ir3_block
*b
= ctx
->block
;
1318 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1319 nir_const_value
*const_offset
;
1320 /* TODO handle wrmask properly, see _store_shared().. but I think
1321 * it is more a PITA than that, since blob ends up loading the
1322 * masked components and writing them back out.
1324 unsigned wrmask
= intr
->const_index
[0];
1325 unsigned ncomp
= ffs(~wrmask
) - 1;
1327 /* can this be non-const buffer_index? how do we handle that? */
1328 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1329 compile_assert(ctx
, const_offset
);
1331 offset
= get_src(ctx
, &intr
->src
[2])[0];
1333 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1336 src0
= create_collect(b
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1337 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1338 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1343 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1344 src0
, 0, src1
, 0, src2
, 0);
1345 stgb
->cat6
.iim_val
= ncomp
;
1347 stgb
->cat6
.type
= TYPE_U32
;
1348 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1349 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1351 array_insert(b
, b
->keeps
, stgb
);
1354 /* src[] = { block_index } */
1356 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1357 struct ir3_instruction
**dst
)
1359 /* SSBO size stored as a const starting at ssbo_sizes: */
1360 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1361 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1362 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1364 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1366 dst
[0] = create_uniform(ctx
, idx
);
1370 * SSBO atomic intrinsics
1372 * All of the SSBO atomic memory operations read a value from memory,
1373 * compute a new value using one of the operations below, write the new
1374 * value to memory, and return the original value read.
1376 * All operations take 3 sources except CompSwap that takes 4. These
1377 * sources represent:
1379 * 0: The SSBO buffer index.
1380 * 1: The offset into the SSBO buffer of the variable that the atomic
1381 * operation will operate on.
1382 * 2: The data parameter to the atomic function (i.e. the value to add
1383 * in ssbo_atomic_add, etc).
1384 * 3: For CompSwap only: the second data parameter.
1386 static struct ir3_instruction
*
1387 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1389 struct ir3_block
*b
= ctx
->block
;
1390 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1391 nir_const_value
*const_offset
;
1392 type_t type
= TYPE_U32
;
1394 /* can this be non-const buffer_index? how do we handle that? */
1395 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1396 compile_assert(ctx
, const_offset
);
1397 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1399 offset
= get_src(ctx
, &intr
->src
[1])[0];
1401 /* src0 is data (or uvec2(data, compare))
1403 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1405 * Note that nir already multiplies the offset by four
1407 src0
= get_src(ctx
, &intr
->src
[2])[0];
1408 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1409 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1414 switch (intr
->intrinsic
) {
1415 case nir_intrinsic_ssbo_atomic_add
:
1416 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1418 case nir_intrinsic_ssbo_atomic_imin
:
1419 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1422 case nir_intrinsic_ssbo_atomic_umin
:
1423 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1425 case nir_intrinsic_ssbo_atomic_imax
:
1426 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1429 case nir_intrinsic_ssbo_atomic_umax
:
1430 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1432 case nir_intrinsic_ssbo_atomic_and
:
1433 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1435 case nir_intrinsic_ssbo_atomic_or
:
1436 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1438 case nir_intrinsic_ssbo_atomic_xor
:
1439 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1441 case nir_intrinsic_ssbo_atomic_exchange
:
1442 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1444 case nir_intrinsic_ssbo_atomic_comp_swap
:
1445 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1446 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1448 get_src(ctx
, &intr
->src
[3])[0],
1450 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1456 atomic
->cat6
.iim_val
= 1;
1458 atomic
->cat6
.type
= type
;
1459 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1460 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1462 /* even if nothing consume the result, we can't DCE the instruction: */
1463 array_insert(b
, b
->keeps
, atomic
);
1468 /* src[] = { offset }. const_index[] = { base } */
1470 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1471 struct ir3_instruction
**dst
)
1473 struct ir3_block
*b
= ctx
->block
;
1474 struct ir3_instruction
*ldl
, *offset
;
1477 offset
= get_src(ctx
, &intr
->src
[0])[0];
1478 base
= intr
->const_index
[0];
1480 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1481 ldl
->cat6
.src_offset
= base
;
1482 ldl
->cat6
.type
= TYPE_U32
;
1483 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1485 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1486 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1488 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1491 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1493 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1495 struct ir3_block
*b
= ctx
->block
;
1496 struct ir3_instruction
*stl
, *offset
;
1497 struct ir3_instruction
* const *value
;
1498 unsigned base
, wrmask
;
1500 value
= get_src(ctx
, &intr
->src
[0]);
1501 offset
= get_src(ctx
, &intr
->src
[1])[0];
1503 base
= intr
->const_index
[0];
1504 wrmask
= intr
->const_index
[1];
1506 /* Combine groups of consecutive enabled channels in one write
1507 * message. We use ffs to find the first enabled channel and then ffs on
1508 * the bit-inverse, down-shifted writemask to determine the length of
1509 * the block of enabled bits.
1511 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1514 unsigned first_component
= ffs(wrmask
) - 1;
1515 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1517 stl
= ir3_STL(b
, offset
, 0,
1518 create_collect(b
, &value
[first_component
], length
), 0,
1519 create_immed(b
, length
), 0);
1520 stl
->cat6
.dst_offset
= first_component
+ base
;
1521 stl
->cat6
.type
= TYPE_U32
;
1522 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1523 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1525 array_insert(b
, b
->keeps
, stl
);
1527 /* Clear the bits in the writemask that we just wrote, then try
1528 * again to see if more channels are left.
1530 wrmask
&= (15 << (first_component
+ length
));
1535 * CS shared variable atomic intrinsics
1537 * All of the shared variable atomic memory operations read a value from
1538 * memory, compute a new value using one of the operations below, write the
1539 * new value to memory, and return the original value read.
1541 * All operations take 2 sources except CompSwap that takes 3. These
1542 * sources represent:
1544 * 0: The offset into the shared variable storage region that the atomic
1545 * operation will operate on.
1546 * 1: The data parameter to the atomic function (i.e. the value to add
1547 * in shared_atomic_add, etc).
1548 * 2: For CompSwap only: the second data parameter.
1550 static struct ir3_instruction
*
1551 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1553 struct ir3_block
*b
= ctx
->block
;
1554 struct ir3_instruction
*atomic
, *src0
, *src1
;
1555 type_t type
= TYPE_U32
;
1557 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1558 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1560 switch (intr
->intrinsic
) {
1561 case nir_intrinsic_shared_atomic_add
:
1562 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1564 case nir_intrinsic_shared_atomic_imin
:
1565 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1568 case nir_intrinsic_shared_atomic_umin
:
1569 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1571 case nir_intrinsic_shared_atomic_imax
:
1572 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1575 case nir_intrinsic_shared_atomic_umax
:
1576 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1578 case nir_intrinsic_shared_atomic_and
:
1579 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1581 case nir_intrinsic_shared_atomic_or
:
1582 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1584 case nir_intrinsic_shared_atomic_xor
:
1585 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1587 case nir_intrinsic_shared_atomic_exchange
:
1588 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1590 case nir_intrinsic_shared_atomic_comp_swap
:
1591 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1592 src1
= create_collect(b
, (struct ir3_instruction
*[]){
1593 get_src(ctx
, &intr
->src
[2])[0],
1596 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1602 atomic
->cat6
.iim_val
= 1;
1604 atomic
->cat6
.type
= type
;
1605 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1606 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1608 /* even if nothing consume the result, we can't DCE the instruction: */
1609 array_insert(b
, b
->keeps
, atomic
);
1614 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1615 * state block (for load). To simplify things, invert the image id and
1616 * map it from end of state block, ie. image 0 becomes num-1, image 1
1617 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1618 * state when switching shaders.
1620 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1621 * coded. Also, since all the gl shader stages (ie. everything but CS)
1622 * share the same SSBO/image state block, this might require some more
1623 * logic if we supported images in anything other than FS..
1626 get_image_slot(struct ir3_context
*ctx
, const nir_variable
*var
)
1628 /* TODO figure out real limit per generation, and don't hardcode: */
1629 const unsigned max_samplers
= 16;
1630 return max_samplers
- var
->data
.driver_location
- 1;
1634 get_image_coords(const nir_variable
*var
)
1636 switch (glsl_get_sampler_dim(glsl_without_array(var
->type
))) {
1637 case GLSL_SAMPLER_DIM_1D
:
1638 case GLSL_SAMPLER_DIM_BUF
:
1641 case GLSL_SAMPLER_DIM_2D
:
1642 case GLSL_SAMPLER_DIM_RECT
:
1643 case GLSL_SAMPLER_DIM_EXTERNAL
:
1644 case GLSL_SAMPLER_DIM_MS
:
1646 case GLSL_SAMPLER_DIM_3D
:
1647 case GLSL_SAMPLER_DIM_CUBE
:
1650 unreachable("bad sampler dim");
1656 get_image_type(const nir_variable
*var
)
1658 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1659 case GLSL_TYPE_UINT
:
1663 case GLSL_TYPE_FLOAT
:
1666 unreachable("bad sampler type.");
1671 static struct ir3_instruction
*
1672 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1673 struct ir3_instruction
* const *coords
, bool byteoff
)
1675 struct ir3_block
*b
= ctx
->block
;
1676 struct ir3_instruction
*offset
;
1677 unsigned ncoords
= get_image_coords(var
);
1679 /* to calculate the byte offset (yes, uggg) we need (up to) three
1680 * const values to know the bytes per pixel, and y and z stride:
1682 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1683 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1685 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1686 (1 << var
->data
.driver_location
));
1688 /* offset = coords.x * bytes_per_pixel: */
1689 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1691 /* offset += coords.y * y_pitch: */
1692 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1693 coords
[1], 0, offset
, 0);
1696 /* offset += coords.z * z_pitch: */
1697 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1698 coords
[2], 0, offset
, 0);
1702 /* Some cases, like atomics, seem to use dword offset instead
1703 * of byte offsets.. blob just puts an extra shr.b in there
1706 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1709 return create_collect(b
, (struct ir3_instruction
*[]){
1715 /* src[] = { coord, sample_index }. const_index[] = {} */
1717 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1718 struct ir3_instruction
**dst
)
1720 struct ir3_block
*b
= ctx
->block
;
1721 const nir_variable
*var
= intr
->variables
[0]->var
;
1722 struct ir3_instruction
*sam
;
1723 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1724 unsigned ncoords
= get_image_coords(var
);
1725 unsigned tex_idx
= get_image_slot(ctx
, var
);
1726 type_t type
= get_image_type(var
);
1730 flags
|= IR3_INSTR_3D
;
1732 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1733 tex_idx
, tex_idx
, create_collect(b
, coords
, ncoords
), NULL
);
1735 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1736 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1738 split_dest(b
, dst
, sam
, 0, 4);
1741 /* src[] = { coord, sample_index, value }. const_index[] = {} */
1743 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1745 struct ir3_block
*b
= ctx
->block
;
1746 const nir_variable
*var
= intr
->variables
[0]->var
;
1747 struct ir3_instruction
*stib
, *offset
;
1748 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
1749 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1750 unsigned ncoords
= get_image_coords(var
);
1751 unsigned tex_idx
= get_image_slot(ctx
, var
);
1755 * src2 is 64b byte offset
1758 offset
= get_image_offset(ctx
, var
, coords
, true);
1760 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1761 * too and takes a dword offset.. not quite sure yet why blob uses
1762 * one over the other in various cases.
1765 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
1766 create_collect(b
, value
, 4), 0,
1767 create_collect(b
, coords
, ncoords
), 0,
1769 stib
->cat6
.iim_val
= 4;
1770 stib
->cat6
.d
= ncoords
;
1771 stib
->cat6
.type
= get_image_type(var
);
1772 stib
->cat6
.typed
= true;
1773 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1774 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1776 array_insert(b
, b
->keeps
, stib
);
1780 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1781 struct ir3_instruction
**dst
)
1783 struct ir3_block
*b
= ctx
->block
;
1784 const nir_variable
*var
= intr
->variables
[0]->var
;
1785 unsigned ncoords
= get_image_coords(var
);
1786 unsigned tex_idx
= get_image_slot(ctx
, var
);
1787 struct ir3_instruction
*sam
, *lod
;
1791 flags
= IR3_INSTR_3D
;
1793 lod
= create_immed(b
, 0);
1794 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1795 tex_idx
, tex_idx
, lod
, NULL
);
1797 split_dest(b
, dst
, sam
, 0, ncoords
);
1800 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
1801 static struct ir3_instruction
*
1802 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1804 struct ir3_block
*b
= ctx
->block
;
1805 const nir_variable
*var
= intr
->variables
[0]->var
;
1806 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
1807 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1808 unsigned ncoords
= get_image_coords(var
);
1810 image
= create_immed(b
, get_image_slot(ctx
, var
));
1812 /* src0 is value (or uvec2(value, compare))
1814 * src2 is 64b byte offset
1816 src0
= get_src(ctx
, &intr
->src
[2])[0];
1817 src1
= create_collect(b
, coords
, ncoords
);
1818 src2
= get_image_offset(ctx
, var
, coords
, false);
1820 switch (intr
->intrinsic
) {
1821 case nir_intrinsic_image_atomic_add
:
1822 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1824 case nir_intrinsic_image_atomic_min
:
1825 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1827 case nir_intrinsic_image_atomic_max
:
1828 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1830 case nir_intrinsic_image_atomic_and
:
1831 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1833 case nir_intrinsic_image_atomic_or
:
1834 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1836 case nir_intrinsic_image_atomic_xor
:
1837 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1839 case nir_intrinsic_image_atomic_exchange
:
1840 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1842 case nir_intrinsic_image_atomic_comp_swap
:
1843 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1844 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1846 get_src(ctx
, &intr
->src
[3])[0],
1848 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1854 atomic
->cat6
.iim_val
= 1;
1855 atomic
->cat6
.d
= ncoords
;
1856 atomic
->cat6
.type
= get_image_type(var
);
1857 atomic
->cat6
.typed
= true;
1858 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1859 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1861 /* even if nothing consume the result, we can't DCE the instruction: */
1862 array_insert(b
, b
->keeps
, atomic
);
1868 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1870 struct ir3_block
*b
= ctx
->block
;
1871 struct ir3_instruction
*barrier
;
1873 switch (intr
->intrinsic
) {
1874 case nir_intrinsic_barrier
:
1875 barrier
= ir3_BAR(b
);
1876 barrier
->cat7
.g
= true;
1877 barrier
->cat7
.l
= true;
1878 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1879 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1881 case nir_intrinsic_memory_barrier
:
1882 barrier
= ir3_FENCE(b
);
1883 barrier
->cat7
.g
= true;
1884 barrier
->cat7
.r
= true;
1885 barrier
->cat7
.w
= true;
1886 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1887 IR3_BARRIER_BUFFER_W
;
1888 barrier
->barrier_conflict
=
1889 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1890 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1892 case nir_intrinsic_memory_barrier_atomic_counter
:
1893 case nir_intrinsic_memory_barrier_buffer
:
1894 barrier
= ir3_FENCE(b
);
1895 barrier
->cat7
.g
= true;
1896 barrier
->cat7
.r
= true;
1897 barrier
->cat7
.w
= true;
1898 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1899 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1900 IR3_BARRIER_BUFFER_W
;
1902 case nir_intrinsic_memory_barrier_image
:
1903 // TODO double check if this should have .g set
1904 barrier
= ir3_FENCE(b
);
1905 barrier
->cat7
.g
= true;
1906 barrier
->cat7
.r
= true;
1907 barrier
->cat7
.w
= true;
1908 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1909 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1910 IR3_BARRIER_IMAGE_W
;
1912 case nir_intrinsic_memory_barrier_shared
:
1913 barrier
= ir3_FENCE(b
);
1914 barrier
->cat7
.g
= true;
1915 barrier
->cat7
.l
= true;
1916 barrier
->cat7
.r
= true;
1917 barrier
->cat7
.w
= true;
1918 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1919 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1920 IR3_BARRIER_SHARED_W
;
1922 case nir_intrinsic_group_memory_barrier
:
1923 barrier
= ir3_FENCE(b
);
1924 barrier
->cat7
.g
= true;
1925 barrier
->cat7
.l
= true;
1926 barrier
->cat7
.r
= true;
1927 barrier
->cat7
.w
= true;
1928 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1929 IR3_BARRIER_IMAGE_W
|
1930 IR3_BARRIER_BUFFER_W
;
1931 barrier
->barrier_conflict
=
1932 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1933 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1934 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1940 /* make sure barrier doesn't get DCE'd */
1941 array_insert(b
, b
->keeps
, barrier
);
1944 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1945 gl_system_value slot
, unsigned compmask
,
1946 struct ir3_instruction
*instr
)
1948 struct ir3_shader_variant
*so
= ctx
->so
;
1949 unsigned r
= regid(so
->inputs_count
, 0);
1950 unsigned n
= so
->inputs_count
++;
1952 so
->inputs
[n
].sysval
= true;
1953 so
->inputs
[n
].slot
= slot
;
1954 so
->inputs
[n
].compmask
= compmask
;
1955 so
->inputs
[n
].regid
= r
;
1956 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1959 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1960 ctx
->ir
->inputs
[r
] = instr
;
1963 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1964 struct ir3_instruction
*instr
)
1966 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1970 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1972 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1973 struct ir3_instruction
**dst
;
1974 struct ir3_instruction
* const *src
;
1975 struct ir3_block
*b
= ctx
->block
;
1976 nir_const_value
*const_offset
;
1979 if (info
->has_dest
) {
1981 if (info
->dest_components
)
1982 n
= info
->dest_components
;
1984 n
= intr
->num_components
;
1985 dst
= get_dst(ctx
, &intr
->dest
, n
);
1990 switch (intr
->intrinsic
) {
1991 case nir_intrinsic_load_uniform
:
1992 idx
= nir_intrinsic_base(intr
);
1993 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1995 idx
+= const_offset
->u32
[0];
1996 for (int i
= 0; i
< intr
->num_components
; i
++) {
1997 unsigned n
= idx
* 4 + i
;
1998 dst
[i
] = create_uniform(ctx
, n
);
2001 src
= get_src(ctx
, &intr
->src
[0]);
2002 for (int i
= 0; i
< intr
->num_components
; i
++) {
2003 int n
= idx
* 4 + i
;
2004 dst
[i
] = create_uniform_indirect(ctx
, n
,
2005 get_addr(ctx
, src
[0], 4));
2007 /* NOTE: if relative addressing is used, we set
2008 * constlen in the compiler (to worst-case value)
2009 * since we don't know in the assembler what the max
2010 * addr reg value can be:
2012 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2015 case nir_intrinsic_load_ubo
:
2016 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2018 case nir_intrinsic_load_input
:
2019 idx
= nir_intrinsic_base(intr
);
2020 comp
= nir_intrinsic_component(intr
);
2021 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2023 idx
+= const_offset
->u32
[0];
2024 for (int i
= 0; i
< intr
->num_components
; i
++) {
2025 unsigned n
= idx
* 4 + i
+ comp
;
2026 dst
[i
] = ctx
->ir
->inputs
[n
];
2029 src
= get_src(ctx
, &intr
->src
[0]);
2030 struct ir3_instruction
*collect
=
2031 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2032 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2033 for (int i
= 0; i
< intr
->num_components
; i
++) {
2034 unsigned n
= idx
* 4 + i
+ comp
;
2035 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2040 case nir_intrinsic_load_ssbo
:
2041 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2043 case nir_intrinsic_store_ssbo
:
2044 emit_intrinsic_store_ssbo(ctx
, intr
);
2046 case nir_intrinsic_get_buffer_size
:
2047 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2049 case nir_intrinsic_ssbo_atomic_add
:
2050 case nir_intrinsic_ssbo_atomic_imin
:
2051 case nir_intrinsic_ssbo_atomic_umin
:
2052 case nir_intrinsic_ssbo_atomic_imax
:
2053 case nir_intrinsic_ssbo_atomic_umax
:
2054 case nir_intrinsic_ssbo_atomic_and
:
2055 case nir_intrinsic_ssbo_atomic_or
:
2056 case nir_intrinsic_ssbo_atomic_xor
:
2057 case nir_intrinsic_ssbo_atomic_exchange
:
2058 case nir_intrinsic_ssbo_atomic_comp_swap
:
2059 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2061 case nir_intrinsic_load_shared
:
2062 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2064 case nir_intrinsic_store_shared
:
2065 emit_intrinsic_store_shared(ctx
, intr
);
2067 case nir_intrinsic_shared_atomic_add
:
2068 case nir_intrinsic_shared_atomic_imin
:
2069 case nir_intrinsic_shared_atomic_umin
:
2070 case nir_intrinsic_shared_atomic_imax
:
2071 case nir_intrinsic_shared_atomic_umax
:
2072 case nir_intrinsic_shared_atomic_and
:
2073 case nir_intrinsic_shared_atomic_or
:
2074 case nir_intrinsic_shared_atomic_xor
:
2075 case nir_intrinsic_shared_atomic_exchange
:
2076 case nir_intrinsic_shared_atomic_comp_swap
:
2077 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2079 case nir_intrinsic_image_load
:
2080 emit_intrinsic_load_image(ctx
, intr
, dst
);
2082 case nir_intrinsic_image_store
:
2083 emit_intrinsic_store_image(ctx
, intr
);
2085 case nir_intrinsic_image_size
:
2086 emit_intrinsic_image_size(ctx
, intr
, dst
);
2088 case nir_intrinsic_image_atomic_add
:
2089 case nir_intrinsic_image_atomic_min
:
2090 case nir_intrinsic_image_atomic_max
:
2091 case nir_intrinsic_image_atomic_and
:
2092 case nir_intrinsic_image_atomic_or
:
2093 case nir_intrinsic_image_atomic_xor
:
2094 case nir_intrinsic_image_atomic_exchange
:
2095 case nir_intrinsic_image_atomic_comp_swap
:
2096 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2098 case nir_intrinsic_barrier
:
2099 case nir_intrinsic_memory_barrier
:
2100 case nir_intrinsic_group_memory_barrier
:
2101 case nir_intrinsic_memory_barrier_atomic_counter
:
2102 case nir_intrinsic_memory_barrier_buffer
:
2103 case nir_intrinsic_memory_barrier_image
:
2104 case nir_intrinsic_memory_barrier_shared
:
2105 emit_intrinsic_barrier(ctx
, intr
);
2106 /* note that blk ptr no longer valid, make that obvious: */
2109 case nir_intrinsic_store_output
:
2110 idx
= nir_intrinsic_base(intr
);
2111 comp
= nir_intrinsic_component(intr
);
2112 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2113 compile_assert(ctx
, const_offset
!= NULL
);
2114 idx
+= const_offset
->u32
[0];
2116 src
= get_src(ctx
, &intr
->src
[0]);
2117 for (int i
= 0; i
< intr
->num_components
; i
++) {
2118 unsigned n
= idx
* 4 + i
+ comp
;
2119 ctx
->ir
->outputs
[n
] = src
[i
];
2122 case nir_intrinsic_load_base_vertex
:
2123 if (!ctx
->basevertex
) {
2124 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2125 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
2128 dst
[0] = ctx
->basevertex
;
2130 case nir_intrinsic_load_vertex_id_zero_base
:
2131 case nir_intrinsic_load_vertex_id
:
2132 if (!ctx
->vertex_id
) {
2133 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2134 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2135 ctx
->vertex_id
= create_input(b
, 0);
2136 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2138 dst
[0] = ctx
->vertex_id
;
2140 case nir_intrinsic_load_instance_id
:
2141 if (!ctx
->instance_id
) {
2142 ctx
->instance_id
= create_input(b
, 0);
2143 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2146 dst
[0] = ctx
->instance_id
;
2148 case nir_intrinsic_load_user_clip_plane
:
2149 idx
= nir_intrinsic_ucp_id(intr
);
2150 for (int i
= 0; i
< intr
->num_components
; i
++) {
2151 unsigned n
= idx
* 4 + i
;
2152 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2155 case nir_intrinsic_load_front_face
:
2156 if (!ctx
->frag_face
) {
2157 ctx
->so
->frag_face
= true;
2158 ctx
->frag_face
= create_input(b
, 0);
2159 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2161 /* for fragface, we get -1 for back and 0 for front. However this is
2162 * the inverse of what nir expects (where ~0 is true).
2164 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2165 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2167 case nir_intrinsic_load_local_invocation_id
:
2168 if (!ctx
->local_invocation_id
) {
2169 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2170 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2171 0x7, ctx
->local_invocation_id
);
2173 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2175 case nir_intrinsic_load_work_group_id
:
2176 if (!ctx
->work_group_id
) {
2177 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2178 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2179 0x7, ctx
->work_group_id
);
2180 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2182 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2184 case nir_intrinsic_load_num_work_groups
:
2185 for (int i
= 0; i
< intr
->num_components
; i
++) {
2186 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2189 case nir_intrinsic_discard_if
:
2190 case nir_intrinsic_discard
: {
2191 struct ir3_instruction
*cond
, *kill
;
2193 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2194 /* conditional discard: */
2195 src
= get_src(ctx
, &intr
->src
[0]);
2196 cond
= ir3_b2n(b
, src
[0]);
2198 /* unconditional discard: */
2199 cond
= create_immed(b
, 1);
2202 /* NOTE: only cmps.*.* can write p0.x: */
2203 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2204 cond
->cat2
.condition
= IR3_COND_NE
;
2206 /* condition always goes in predicate register: */
2207 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2209 kill
= ir3_KILL(b
, cond
, 0);
2210 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2212 array_insert(b
, b
->keeps
, kill
);
2213 ctx
->so
->has_kill
= true;
2218 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2219 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2224 put_dst(ctx
, &intr
->dest
);
2228 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2230 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2231 instr
->def
.num_components
);
2232 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2233 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
2237 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2239 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2240 undef
->def
.num_components
);
2241 /* backend doesn't want undefined instructions, so just plug
2244 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2245 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
2249 * texture fetch/sample instructions:
2253 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2255 unsigned coords
, flags
= 0;
2257 /* note: would use tex->coord_components.. except txs.. also,
2258 * since array index goes after shadow ref, we don't want to
2261 switch (tex
->sampler_dim
) {
2262 case GLSL_SAMPLER_DIM_1D
:
2263 case GLSL_SAMPLER_DIM_BUF
:
2266 case GLSL_SAMPLER_DIM_2D
:
2267 case GLSL_SAMPLER_DIM_RECT
:
2268 case GLSL_SAMPLER_DIM_EXTERNAL
:
2269 case GLSL_SAMPLER_DIM_MS
:
2272 case GLSL_SAMPLER_DIM_3D
:
2273 case GLSL_SAMPLER_DIM_CUBE
:
2275 flags
|= IR3_INSTR_3D
;
2278 unreachable("bad sampler_dim");
2281 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2282 flags
|= IR3_INSTR_S
;
2284 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2285 flags
|= IR3_INSTR_A
;
2292 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2294 struct ir3_block
*b
= ctx
->block
;
2295 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2296 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2297 struct ir3_instruction
*lod
, *compare
, *proj
;
2298 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2299 unsigned i
, coords
, flags
;
2300 unsigned nsrc0
= 0, nsrc1
= 0;
2304 coord
= off
= ddx
= ddy
= NULL
;
2305 lod
= proj
= compare
= NULL
;
2307 /* TODO: might just be one component for gathers? */
2308 dst
= get_dst(ctx
, &tex
->dest
, 4);
2310 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2311 switch (tex
->src
[i
].src_type
) {
2312 case nir_tex_src_coord
:
2313 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2315 case nir_tex_src_bias
:
2316 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2319 case nir_tex_src_lod
:
2320 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2323 case nir_tex_src_comparator
: /* shadow comparator */
2324 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2326 case nir_tex_src_projector
:
2327 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2330 case nir_tex_src_offset
:
2331 off
= get_src(ctx
, &tex
->src
[i
].src
);
2334 case nir_tex_src_ddx
:
2335 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2337 case nir_tex_src_ddy
:
2338 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2341 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2342 tex
->src
[i
].src_type
);
2348 case nir_texop_tex
: opc
= OPC_SAM
; break;
2349 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2350 case nir_texop_txl
: opc
= OPC_SAML
; break;
2351 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2352 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2353 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2355 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2356 * what blob does, seems gather is broken?), and a3xx did
2357 * not support it (but probably could also emulate).
2359 switch (tex
->component
) {
2360 case 0: opc
= OPC_GATHER4R
; break;
2361 case 1: opc
= OPC_GATHER4G
; break;
2362 case 2: opc
= OPC_GATHER4B
; break;
2363 case 3: opc
= OPC_GATHER4A
; break;
2366 case nir_texop_txf_ms
:
2368 case nir_texop_query_levels
:
2369 case nir_texop_texture_samples
:
2370 case nir_texop_samples_identical
:
2371 case nir_texop_txf_ms_mcs
:
2372 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2376 tex_info(tex
, &flags
, &coords
);
2379 * lay out the first argument in the proper order:
2380 * - actual coordinates first
2381 * - shadow reference
2384 * - starting at offset 4, dpdx.xy, dpdy.xy
2386 * bias/lod go into the second arg
2389 /* insert tex coords: */
2390 for (i
= 0; i
< coords
; i
++)
2395 /* scale up integer coords for TXF based on the LOD */
2396 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2398 for (i
= 0; i
< coords
; i
++)
2399 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2403 /* hw doesn't do 1d, so we treat it as 2d with
2404 * height of 1, and patch up the y coord.
2405 * TODO: y coord should be (int)0 in some cases..
2407 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2410 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2411 src0
[nsrc0
++] = compare
;
2413 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2414 struct ir3_instruction
*idx
= coord
[coords
];
2416 /* the array coord for cube arrays needs 0.5 added to it */
2417 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2418 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2420 src0
[nsrc0
++] = idx
;
2424 src0
[nsrc0
++] = proj
;
2425 flags
|= IR3_INSTR_P
;
2428 /* pad to 4, then ddx/ddy: */
2429 if (tex
->op
== nir_texop_txd
) {
2431 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2432 for (i
= 0; i
< coords
; i
++)
2433 src0
[nsrc0
++] = ddx
[i
];
2435 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2436 for (i
= 0; i
< coords
; i
++)
2437 src0
[nsrc0
++] = ddy
[i
];
2439 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2443 * second argument (if applicable):
2448 if (has_off
| has_lod
| has_bias
) {
2450 unsigned off_coords
= coords
;
2451 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2453 for (i
= 0; i
< off_coords
; i
++)
2454 src1
[nsrc1
++] = off
[i
];
2456 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2457 flags
|= IR3_INSTR_O
;
2460 if (has_lod
| has_bias
)
2461 src1
[nsrc1
++] = lod
;
2464 switch (tex
->dest_type
) {
2465 case nir_type_invalid
:
2466 case nir_type_float
:
2477 unreachable("bad dest_type");
2480 if (opc
== OPC_GETLOD
)
2483 unsigned tex_idx
= tex
->texture_index
;
2485 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2487 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
2488 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
2490 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2491 tex_idx
, tex_idx
, col0
, col1
);
2493 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2494 /* only need first 3 components: */
2495 sam
->regs
[0]->wrmask
= 0x7;
2496 split_dest(b
, dst
, sam
, 0, 3);
2498 /* we need to sample the alpha separately with a non-ASTC
2501 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2502 tex_idx
, tex_idx
, col0
, col1
);
2504 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2506 /* fixup .w component: */
2507 split_dest(b
, &dst
[3], sam
, 3, 1);
2509 /* normal (non-workaround) case: */
2510 split_dest(b
, dst
, sam
, 0, 4);
2513 /* GETLOD returns results in 4.8 fixed point */
2514 if (opc
== OPC_GETLOD
) {
2515 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2517 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2518 for (i
= 0; i
< 2; i
++) {
2519 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2524 put_dst(ctx
, &tex
->dest
);
2528 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2530 struct ir3_block
*b
= ctx
->block
;
2531 struct ir3_instruction
**dst
, *sam
;
2533 dst
= get_dst(ctx
, &tex
->dest
, 1);
2535 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2536 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2538 /* even though there is only one component, since it ends
2539 * up in .z rather than .x, we need a split_dest()
2541 split_dest(b
, dst
, sam
, 0, 3);
2543 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2544 * the value in TEX_CONST_0 is zero-based.
2546 if (ctx
->levels_add_one
)
2547 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2549 put_dst(ctx
, &tex
->dest
);
2553 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2555 struct ir3_block
*b
= ctx
->block
;
2556 struct ir3_instruction
**dst
, *sam
;
2557 struct ir3_instruction
*lod
;
2558 unsigned flags
, coords
;
2560 tex_info(tex
, &flags
, &coords
);
2562 /* Actually we want the number of dimensions, not coordinates. This
2563 * distinction only matters for cubes.
2565 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2568 dst
= get_dst(ctx
, &tex
->dest
, 4);
2570 compile_assert(ctx
, tex
->num_srcs
== 1);
2571 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2573 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2575 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2576 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2578 split_dest(b
, dst
, sam
, 0, 4);
2580 /* Array size actually ends up in .w rather than .z. This doesn't
2581 * matter for miplevel 0, but for higher mips the value in z is
2582 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2583 * returned, which means that we have to add 1 to it for arrays.
2585 if (tex
->is_array
) {
2586 if (ctx
->levels_add_one
) {
2587 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2589 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2593 put_dst(ctx
, &tex
->dest
);
2597 emit_phi(struct ir3_context
*ctx
, nir_phi_instr
*nphi
)
2599 struct ir3_instruction
*phi
, **dst
;
2601 /* NOTE: phi's should be lowered to scalar at this point */
2602 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
2604 dst
= get_dst(ctx
, &nphi
->dest
, 1);
2606 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
2607 1 + exec_list_length(&nphi
->srcs
));
2608 ir3_reg_create(phi
, 0, 0); /* dst */
2609 phi
->phi
.nphi
= nphi
;
2613 put_dst(ctx
, &nphi
->dest
);
2616 /* phi instructions are left partially constructed. We don't resolve
2617 * their srcs until the end of the block, since (eg. loops) one of
2618 * the phi's srcs might be defined after the phi due to back edges in
2622 resolve_phis(struct ir3_context
*ctx
, struct ir3_block
*block
)
2624 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2625 nir_phi_instr
*nphi
;
2627 /* phi's only come at start of block: */
2628 if (instr
->opc
!= OPC_META_PHI
)
2631 if (!instr
->phi
.nphi
)
2634 nphi
= instr
->phi
.nphi
;
2635 instr
->phi
.nphi
= NULL
;
2637 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
2638 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
2640 /* NOTE: src might not be in the same block as it comes from
2641 * according to the phi.. but in the end the backend assumes
2642 * it will be able to assign the same register to each (which
2643 * only works if it is assigned in the src block), so insert
2644 * an extra mov to make sure the phi src is assigned in the
2645 * block it comes from:
2647 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
2649 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
2655 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2657 switch (jump
->type
) {
2658 case nir_jump_break
:
2659 case nir_jump_continue
:
2660 /* I *think* we can simply just ignore this, and use the
2661 * successor block link to figure out where we need to
2662 * jump to for break/continue
2666 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2672 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2674 switch (instr
->type
) {
2675 case nir_instr_type_alu
:
2676 emit_alu(ctx
, nir_instr_as_alu(instr
));
2678 case nir_instr_type_intrinsic
:
2679 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2681 case nir_instr_type_load_const
:
2682 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2684 case nir_instr_type_ssa_undef
:
2685 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2687 case nir_instr_type_tex
: {
2688 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2689 /* couple tex instructions get special-cased:
2693 emit_tex_txs(ctx
, tex
);
2695 case nir_texop_query_levels
:
2696 emit_tex_query_levels(ctx
, tex
);
2704 case nir_instr_type_phi
:
2705 emit_phi(ctx
, nir_instr_as_phi(instr
));
2707 case nir_instr_type_jump
:
2708 emit_jump(ctx
, nir_instr_as_jump(instr
));
2710 case nir_instr_type_call
:
2711 case nir_instr_type_parallel_copy
:
2712 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2717 static struct ir3_block
*
2718 get_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2720 struct ir3_block
*block
;
2721 struct hash_entry
*entry
;
2722 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2726 block
= ir3_block_create(ctx
->ir
);
2727 block
->nblock
= nblock
;
2728 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2734 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2736 struct ir3_block
*block
= get_block(ctx
, nblock
);
2738 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2739 if (nblock
->successors
[i
]) {
2740 block
->successors
[i
] =
2741 get_block(ctx
, nblock
->successors
[i
]);
2746 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2748 /* re-emit addr register in each block if needed: */
2749 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2750 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2751 ctx
->addr_ht
[i
] = NULL
;
2754 nir_foreach_instr(instr
, nblock
) {
2755 emit_instr(ctx
, instr
);
2761 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2764 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2766 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2768 ctx
->block
->condition
=
2769 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2771 emit_cf_list(ctx
, &nif
->then_list
);
2772 emit_cf_list(ctx
, &nif
->else_list
);
2776 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2778 emit_cf_list(ctx
, &nloop
->body
);
2782 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2784 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2785 switch (node
->type
) {
2786 case nir_cf_node_block
:
2787 emit_block(ctx
, nir_cf_node_as_block(node
));
2789 case nir_cf_node_if
:
2790 emit_if(ctx
, nir_cf_node_as_if(node
));
2792 case nir_cf_node_loop
:
2793 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2795 case nir_cf_node_function
:
2796 compile_error(ctx
, "TODO\n");
2802 /* emit stream-out code. At this point, the current block is the original
2803 * (nir) end block, and nir ensures that all flow control paths terminate
2804 * into the end block. We re-purpose the original end block to generate
2805 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2806 * block holding stream-out write instructions, followed by the new end
2810 * p0.x = (vtxcnt < maxvtxcnt)
2811 * // succs: blockStreamOut, blockNewEnd
2814 * ... stream-out instructions ...
2815 * // succs: blockNewEnd
2821 emit_stream_out(struct ir3_context
*ctx
)
2823 struct ir3_shader_variant
*v
= ctx
->so
;
2824 struct ir3
*ir
= ctx
->ir
;
2825 struct pipe_stream_output_info
*strmout
=
2826 &ctx
->so
->shader
->stream_output
;
2827 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2828 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2829 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2831 /* create vtxcnt input in input block at top of shader,
2832 * so that it is seen as live over the entire duration
2835 vtxcnt
= create_input(ctx
->in_block
, 0);
2836 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2838 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2840 /* at this point, we are at the original 'end' block,
2841 * re-purpose this block to stream-out condition, then
2842 * append stream-out block and new-end block
2844 orig_end_block
= ctx
->block
;
2846 stream_out_block
= ir3_block_create(ir
);
2847 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2849 new_end_block
= ir3_block_create(ir
);
2850 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2852 orig_end_block
->successors
[0] = stream_out_block
;
2853 orig_end_block
->successors
[1] = new_end_block
;
2854 stream_out_block
->successors
[0] = new_end_block
;
2856 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2857 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2858 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2859 cond
->cat2
.condition
= IR3_COND_LT
;
2861 /* condition goes on previous block to the conditional,
2862 * since it is used to pick which of the two successor
2865 orig_end_block
->condition
= cond
;
2867 /* switch to stream_out_block to generate the stream-out
2870 ctx
->block
= stream_out_block
;
2872 /* Calculate base addresses based on vtxcnt. Instructions
2873 * generated for bases not used in following loop will be
2874 * stripped out in the backend.
2876 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2877 unsigned stride
= strmout
->stride
[i
];
2878 struct ir3_instruction
*base
, *off
;
2880 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2882 /* 24-bit should be enough: */
2883 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2884 create_immed(ctx
->block
, stride
* 4), 0);
2886 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2889 /* Generate the per-output store instructions: */
2890 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2891 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2892 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2893 struct ir3_instruction
*base
, *out
, *stg
;
2895 base
= bases
[strmout
->output
[i
].output_buffer
];
2896 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2898 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2899 create_immed(ctx
->block
, 1), 0);
2900 stg
->cat6
.type
= TYPE_U32
;
2901 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2903 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2907 /* and finally switch to the new_end_block: */
2908 ctx
->block
= new_end_block
;
2912 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2914 nir_metadata_require(impl
, nir_metadata_block_index
);
2916 emit_cf_list(ctx
, &impl
->body
);
2917 emit_block(ctx
, impl
->end_block
);
2919 /* at this point, we should have a single empty block,
2920 * into which we emit the 'end' instruction.
2922 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2924 /* If stream-out (aka transform-feedback) enabled, emit the
2925 * stream-out instructions, followed by a new empty block (into
2926 * which the 'end' instruction lands).
2928 * NOTE: it is done in this order, rather than inserting before
2929 * we emit end_block, because NIR guarantees that all blocks
2930 * flow into end_block, and that end_block has no successors.
2931 * So by re-purposing end_block as the first block of stream-
2932 * out, we guarantee that all exit paths flow into the stream-
2935 if ((ctx
->compiler
->gpu_id
< 500) &&
2936 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2937 !ctx
->so
->key
.binning_pass
) {
2938 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2939 emit_stream_out(ctx
);
2942 ir3_END(ctx
->block
);
2946 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2948 struct ir3_shader_variant
*so
= ctx
->so
;
2949 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2950 unsigned ncomp
= glsl_get_components(in
->type
);
2951 unsigned n
= in
->data
.driver_location
;
2952 unsigned slot
= in
->data
.location
;
2954 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2955 slot
, array_len
, ncomp
, n
);
2957 /* let's pretend things other than vec4 don't exist: */
2958 ncomp
= MAX2(ncomp
, 4);
2959 compile_assert(ctx
, ncomp
== 4);
2961 so
->inputs
[n
].slot
= slot
;
2962 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2963 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2964 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2966 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2967 for (int i
= 0; i
< ncomp
; i
++) {
2968 struct ir3_instruction
*instr
= NULL
;
2969 unsigned idx
= (n
* 4) + i
;
2971 if (slot
== VARYING_SLOT_POS
) {
2972 so
->inputs
[n
].bary
= false;
2973 so
->frag_coord
= true;
2974 instr
= create_frag_coord(ctx
, i
);
2975 } else if (slot
== VARYING_SLOT_PNTC
) {
2976 /* see for example st_get_generic_varying_index().. this is
2977 * maybe a bit mesa/st specific. But we need things to line
2978 * up for this in fdN_program:
2979 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2980 * if (emit->sprite_coord_enable & texmask) {
2984 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2985 so
->inputs
[n
].bary
= true;
2986 instr
= create_frag_input(ctx
, false);
2988 bool use_ldlv
= false;
2990 /* detect the special case for front/back colors where
2991 * we need to do flat vs smooth shading depending on
2994 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2996 case VARYING_SLOT_COL0
:
2997 case VARYING_SLOT_COL1
:
2998 case VARYING_SLOT_BFC0
:
2999 case VARYING_SLOT_BFC1
:
3000 so
->inputs
[n
].rasterflat
= true;
3007 if (ctx
->flat_bypass
) {
3008 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3009 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3013 so
->inputs
[n
].bary
= true;
3015 instr
= create_frag_input(ctx
, use_ldlv
);
3018 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3020 ctx
->ir
->inputs
[idx
] = instr
;
3022 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3023 for (int i
= 0; i
< ncomp
; i
++) {
3024 unsigned idx
= (n
* 4) + i
;
3025 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3026 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
3029 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3032 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3033 so
->total_in
+= ncomp
;
3038 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3040 struct ir3_shader_variant
*so
= ctx
->so
;
3041 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3042 unsigned ncomp
= glsl_get_components(out
->type
);
3043 unsigned n
= out
->data
.driver_location
;
3044 unsigned slot
= out
->data
.location
;
3047 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3048 slot
, array_len
, ncomp
, n
);
3050 /* let's pretend things other than vec4 don't exist: */
3051 ncomp
= MAX2(ncomp
, 4);
3052 compile_assert(ctx
, ncomp
== 4);
3054 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3056 case FRAG_RESULT_DEPTH
:
3057 comp
= 2; /* tgsi will write to .z component */
3058 so
->writes_pos
= true;
3060 case FRAG_RESULT_COLOR
:
3064 if (slot
>= FRAG_RESULT_DATA0
)
3066 compile_error(ctx
, "unknown FS output name: %s\n",
3067 gl_frag_result_name(slot
));
3069 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3071 case VARYING_SLOT_POS
:
3072 so
->writes_pos
= true;
3074 case VARYING_SLOT_PSIZ
:
3075 so
->writes_psize
= true;
3077 case VARYING_SLOT_COL0
:
3078 case VARYING_SLOT_COL1
:
3079 case VARYING_SLOT_BFC0
:
3080 case VARYING_SLOT_BFC1
:
3081 case VARYING_SLOT_FOGC
:
3082 case VARYING_SLOT_CLIP_DIST0
:
3083 case VARYING_SLOT_CLIP_DIST1
:
3084 case VARYING_SLOT_CLIP_VERTEX
:
3087 if (slot
>= VARYING_SLOT_VAR0
)
3089 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3091 compile_error(ctx
, "unknown VS output name: %s\n",
3092 gl_varying_slot_name(slot
));
3095 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3098 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3100 so
->outputs
[n
].slot
= slot
;
3101 so
->outputs
[n
].regid
= regid(n
, comp
);
3102 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3104 for (int i
= 0; i
< ncomp
; i
++) {
3105 unsigned idx
= (n
* 4) + i
;
3106 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3107 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3112 max_drvloc(struct exec_list
*vars
)
3115 nir_foreach_variable(var
, vars
) {
3116 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3121 static const unsigned max_sysvals
[SHADER_MAX
] = {
3122 [SHADER_VERTEX
] = 16,
3123 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3127 emit_instructions(struct ir3_context
*ctx
)
3129 unsigned ninputs
, noutputs
;
3130 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3132 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3133 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3135 /* we need to leave room for sysvals:
3137 ninputs
+= max_sysvals
[ctx
->so
->type
];
3139 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3141 /* Create inputs in first block: */
3142 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3143 ctx
->in_block
= ctx
->block
;
3144 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3146 ninputs
-= max_sysvals
[ctx
->so
->type
];
3148 /* for fragment shader, we have a single input register (usually
3149 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3151 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3152 // TODO maybe a helper for fi since we need it a few places..
3153 struct ir3_instruction
*instr
;
3154 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3155 ir3_reg_create(instr
, 0, 0);
3156 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3157 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3158 ctx
->frag_pos
= instr
;
3162 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3163 setup_input(ctx
, var
);
3166 /* Setup outputs: */
3167 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3168 setup_output(ctx
, var
);
3171 /* Setup registers (which should only be arrays): */
3172 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3173 declare_array(ctx
, reg
);
3176 /* NOTE: need to do something more clever when we support >1 fxn */
3177 nir_foreach_register(reg
, &fxn
->registers
) {
3178 declare_array(ctx
, reg
);
3180 /* And emit the body: */
3182 emit_function(ctx
, fxn
);
3184 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
3185 resolve_phis(ctx
, block
);
3189 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3190 * for a fragment shader are just bary.f instructions. The *actual* inputs
3191 * from the hw perspective are the frag_pos and optionally frag_coord and
3195 fixup_frag_inputs(struct ir3_context
*ctx
)
3197 struct ir3_shader_variant
*so
= ctx
->so
;
3198 struct ir3
*ir
= ctx
->ir
;
3199 struct ir3_instruction
**inputs
;
3200 struct ir3_instruction
*instr
;
3205 n
= 4; /* always have frag_pos */
3206 n
+= COND(so
->frag_face
, 4);
3207 n
+= COND(so
->frag_coord
, 4);
3209 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3211 if (so
->frag_face
) {
3212 /* this ultimately gets assigned to hr0.x so doesn't conflict
3213 * with frag_coord/frag_pos..
3215 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3216 ctx
->frag_face
->regs
[0]->num
= 0;
3218 /* remaining channels not used, but let's avoid confusing
3219 * other parts that expect inputs to come in groups of vec4
3221 inputs
[ir
->ninputs
++] = NULL
;
3222 inputs
[ir
->ninputs
++] = NULL
;
3223 inputs
[ir
->ninputs
++] = NULL
;
3226 /* since we don't know where to set the regid for frag_coord,
3227 * we have to use r0.x for it. But we don't want to *always*
3228 * use r1.x for frag_pos as that could increase the register
3229 * footprint on simple shaders:
3231 if (so
->frag_coord
) {
3232 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3233 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3234 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3235 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3237 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3238 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3239 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3240 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3243 /* we always have frag_pos: */
3244 so
->pos_regid
= regid
;
3247 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3248 instr
->regs
[0]->num
= regid
++;
3249 inputs
[ir
->ninputs
++] = instr
;
3250 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3253 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3254 instr
->regs
[0]->num
= regid
++;
3255 inputs
[ir
->ninputs
++] = instr
;
3256 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3258 ir
->inputs
= inputs
;
3261 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3262 * need to assign the tex state indexes for these after we know the
3266 fixup_astc_srgb(struct ir3_context
*ctx
)
3268 struct ir3_shader_variant
*so
= ctx
->so
;
3269 /* indexed by original tex idx, value is newly assigned alpha sampler
3270 * state tex idx. Zero is invalid since there is at least one sampler
3273 unsigned alt_tex_state
[16] = {0};
3274 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3277 so
->astc_srgb
.base
= tex_idx
;
3279 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3280 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3282 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3284 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3285 /* assign new alternate/alpha tex state slot: */
3286 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3287 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3288 so
->astc_srgb
.count
++;
3291 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3296 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3297 struct ir3_shader_variant
*so
)
3299 struct ir3_context
*ctx
;
3301 struct ir3_instruction
**inputs
;
3302 unsigned i
, j
, actual_in
, inloc
;
3303 int ret
= 0, max_bary
;
3307 ctx
= compile_init(compiler
, so
);
3309 DBG("INIT failed!");
3314 emit_instructions(ctx
);
3317 DBG("EMIT failed!");
3322 ir
= so
->ir
= ctx
->ir
;
3324 /* keep track of the inputs from TGSI perspective.. */
3325 inputs
= ir
->inputs
;
3327 /* but fixup actual inputs for frag shader: */
3328 if (so
->type
== SHADER_FRAGMENT
)
3329 fixup_frag_inputs(ctx
);
3331 /* at this point, for binning pass, throw away unneeded outputs: */
3332 if (so
->key
.binning_pass
) {
3333 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3334 unsigned slot
= so
->outputs
[i
].slot
;
3336 /* throw away everything but first position/psize */
3337 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3339 so
->outputs
[j
] = so
->outputs
[i
];
3340 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3341 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3342 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3343 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3348 so
->outputs_count
= j
;
3349 ir
->noutputs
= j
* 4;
3352 /* if we want half-precision outputs, mark the output registers
3355 if (so
->key
.half_precision
) {
3356 for (i
= 0; i
< ir
->noutputs
; i
++) {
3357 struct ir3_instruction
*out
= ir
->outputs
[i
];
3362 /* if frag shader writes z, that needs to be full precision: */
3363 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3366 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3367 /* output could be a fanout (ie. texture fetch output)
3368 * in which case we need to propagate the half-reg flag
3369 * up to the definer so that RA sees it:
3371 if (out
->opc
== OPC_META_FO
) {
3372 out
= out
->regs
[1]->instr
;
3373 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3376 if (out
->opc
== OPC_MOV
) {
3377 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3382 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3383 printf("BEFORE CP:\n");
3389 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3390 printf("BEFORE GROUPING:\n");
3394 ir3_sched_add_deps(ir
);
3396 /* Group left/right neighbors, inserting mov's where needed to
3401 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3402 printf("AFTER GROUPING:\n");
3408 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3409 printf("AFTER DEPTH:\n");
3413 ret
= ir3_sched(ir
);
3415 DBG("SCHED failed!");
3419 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3420 printf("AFTER SCHED:\n");
3424 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3430 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3431 printf("AFTER RA:\n");
3435 /* fixup input/outputs: */
3436 for (i
= 0; i
< so
->outputs_count
; i
++) {
3437 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3440 /* Note that some or all channels of an input may be unused: */
3443 for (i
= 0; i
< so
->inputs_count
; i
++) {
3444 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3445 so
->inputs
[i
].ncomp
= 0;
3446 so
->inputs
[i
].inloc
= inloc
;
3447 for (j
= 0; j
< 4; j
++) {
3448 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3449 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3450 compmask
|= (1 << j
);
3451 regid
= in
->regs
[0]->num
- j
;
3453 so
->inputs
[i
].ncomp
++;
3454 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3456 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3457 in
->regs
[1]->iim_val
= inloc
+ j
;
3462 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3464 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3467 so
->inputs
[i
].compmask
= compmask
;
3469 so
->inputs
[i
].regid
= regid
;
3473 fixup_astc_srgb(ctx
);
3475 /* We need to do legalize after (for frag shader's) the "bary.f"
3476 * offsets (inloc) have been assigned.
3478 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3480 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3481 printf("AFTER LEGALIZE:\n");
3485 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3486 if (so
->type
== SHADER_VERTEX
)
3487 so
->total_in
= actual_in
;
3489 so
->total_in
= max_bary
+ 1;
3494 ir3_destroy(so
->ir
);