1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* For fragment shaders: */
75 struct ir3_instruction
*samp_id
, *samp_mask_in
;
77 /* Compute shader inputs: */
78 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
85 /* a common pattern for indirect addressing is to request the
86 * same address register multiple times. To avoid generating
87 * duplicate instruction sequences (which our backend does not
88 * try to clean up, since that should be done as the NIR stage)
89 * we cache the address value generated for a given src value:
91 * Note that we have to cache these per alignment, since same
92 * src used for an array of vec1 cannot be also used for an
95 struct hash_table
*addr_ht
[4];
97 /* last dst array, for indirect we need to insert a var-store.
99 struct ir3_instruction
**last_dst
;
102 /* maps nir_block to ir3_block, mostly for the purposes of
103 * figuring out the blocks successors
105 struct hash_table
*block_ht
;
107 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
110 unsigned samples
; /* bitmask of x,y sample shifts */
112 unsigned max_texture_index
;
114 /* set if we encounter something we can't handle yet, so we
115 * can bail cleanly and fallback to TGSI compiler f/e
120 /* gpu pointer size in units of 32bit registers/slots */
121 static unsigned pointer_size(struct ir3_context
*ctx
)
123 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
126 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
127 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
130 static struct ir3_context
*
131 compile_init(struct ir3_compiler
*compiler
,
132 struct ir3_shader_variant
*so
)
134 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
136 if (compiler
->gpu_id
>= 400) {
137 if (so
->type
== SHADER_VERTEX
) {
138 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
139 } else if (so
->type
== SHADER_FRAGMENT
) {
140 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
144 if (so
->type
== SHADER_VERTEX
) {
145 ctx
->samples
= so
->key
.vsamples
;
146 } else if (so
->type
== SHADER_FRAGMENT
) {
147 ctx
->samples
= so
->key
.fsamples
;
151 ctx
->compiler
= compiler
;
153 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
154 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
155 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
156 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
158 /* TODO: maybe generate some sort of bitmask of what key
159 * lowers vs what shader has (ie. no need to lower
160 * texture clamp lowering if no texture sample instrs)..
161 * although should be done further up the stack to avoid
162 * creating duplicate variants..
165 if (ir3_key_lowers_nir(&so
->key
)) {
166 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
167 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
169 /* fast-path for shader key that lowers nothing in NIR: */
170 ctx
->s
= so
->shader
->nir
;
173 /* this needs to be the last pass run, so do this here instead of
174 * in ir3_optimize_nir():
176 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
177 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
179 if (fd_mesa_debug
& FD_DBG_DISASM
) {
180 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
181 so
->shader
->id
, so
->id
, so
->type
,
182 so
->key
.binning_pass
, so
->key
.color_two_side
,
183 so
->key
.half_precision
);
184 nir_print_shader(ctx
->s
, stdout
);
187 if (shader_debug_enabled(so
->type
)) {
188 fprintf(stderr
, "NIR (final form) for %s shader:\n",
189 shader_stage_name(so
->type
));
190 nir_print_shader(ctx
->s
, stderr
);
193 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
195 so
->num_uniforms
= ctx
->s
->num_uniforms
;
196 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
198 /* Layout of constant registers, each section aligned to vec4. Note
199 * that pointer size (ubo, etc) changes depending on generation.
204 * if (vertex shader) {
205 * driver params (IR3_DP_*)
206 * if (stream_output.num_outputs > 0)
207 * stream-out addresses
211 * Immediates go last mostly because they are inserted in the CP pass
212 * after the nir -> ir3 frontend.
214 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
215 unsigned ptrsz
= pointer_size(ctx
);
217 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
219 if (so
->num_ubos
> 0) {
220 so
->constbase
.ubo
= constoff
;
221 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
224 if (so
->const_layout
.ssbo_size
.count
> 0) {
225 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
226 so
->constbase
.ssbo_sizes
= constoff
;
227 constoff
+= align(cnt
, 4) / 4;
230 if (so
->const_layout
.image_dims
.count
> 0) {
231 unsigned cnt
= so
->const_layout
.image_dims
.count
;
232 so
->constbase
.image_dims
= constoff
;
233 constoff
+= align(cnt
, 4) / 4;
236 unsigned num_driver_params
= 0;
237 if (so
->type
== SHADER_VERTEX
) {
238 num_driver_params
= IR3_DP_VS_COUNT
;
239 } else if (so
->type
== SHADER_COMPUTE
) {
240 num_driver_params
= IR3_DP_CS_COUNT
;
243 so
->constbase
.driver_param
= constoff
;
244 constoff
+= align(num_driver_params
, 4) / 4;
246 if ((so
->type
== SHADER_VERTEX
) &&
247 (compiler
->gpu_id
< 500) &&
248 so
->shader
->stream_output
.num_outputs
> 0) {
249 so
->constbase
.tfbo
= constoff
;
250 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
253 so
->constbase
.immediate
= constoff
;
259 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
262 va_start(ap
, format
);
263 _debug_vprintf(format
, ap
);
265 nir_print_shader(ctx
->s
, stdout
);
270 #define compile_assert(ctx, cond) do { \
271 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
275 compile_free(struct ir3_context
*ctx
)
281 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
283 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
284 arr
->id
= ++ctx
->num_arrays
;
285 /* NOTE: sometimes we get non array regs, for example for arrays of
286 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
287 * treat a non-array as if it was an array of length 1.
289 * It would be nice if there was a nir pass to convert arrays of
292 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
293 compile_assert(ctx
, arr
->length
> 0);
295 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
298 static struct ir3_array
*
299 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
301 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
305 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
309 /* relative (indirect) if address!=NULL */
310 static struct ir3_instruction
*
311 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
312 struct ir3_instruction
*address
)
314 struct ir3_block
*block
= ctx
->block
;
315 struct ir3_instruction
*mov
;
316 struct ir3_register
*src
;
318 mov
= ir3_instr_create(block
, OPC_MOV
);
319 mov
->cat1
.src_type
= TYPE_U32
;
320 mov
->cat1
.dst_type
= TYPE_U32
;
321 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
322 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
323 ir3_reg_create(mov
, 0, 0);
324 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
325 COND(address
, IR3_REG_RELATIV
));
326 src
->instr
= arr
->last_write
;
327 src
->size
= arr
->length
;
328 src
->array
.id
= arr
->id
;
329 src
->array
.offset
= n
;
332 ir3_instr_set_address(mov
, address
);
337 /* relative (indirect) if address!=NULL */
339 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
340 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
342 struct ir3_block
*block
= ctx
->block
;
343 struct ir3_instruction
*mov
;
344 struct ir3_register
*dst
;
346 /* if not relative store, don't create an extra mov, since that
347 * ends up being difficult for cp to remove.
352 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
353 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
355 dst
->flags
|= IR3_REG_ARRAY
;
356 dst
->instr
= arr
->last_write
;
357 dst
->size
= arr
->length
;
358 dst
->array
.id
= arr
->id
;
359 dst
->array
.offset
= n
;
361 arr
->last_write
= src
;
363 array_insert(block
, block
->keeps
, src
);
368 mov
= ir3_instr_create(block
, OPC_MOV
);
369 mov
->cat1
.src_type
= TYPE_U32
;
370 mov
->cat1
.dst_type
= TYPE_U32
;
371 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
372 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
373 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
374 COND(address
, IR3_REG_RELATIV
));
375 dst
->instr
= arr
->last_write
;
376 dst
->size
= arr
->length
;
377 dst
->array
.id
= arr
->id
;
378 dst
->array
.offset
= n
;
379 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
382 ir3_instr_set_address(mov
, address
);
384 arr
->last_write
= mov
;
386 /* the array store may only matter to something in an earlier
387 * block (ie. loops), but since arrays are not in SSA, depth
388 * pass won't know this.. so keep all array stores:
390 array_insert(block
, block
->keeps
, mov
);
393 static inline type_t
utype_for_size(unsigned bit_size
)
396 case 32: return TYPE_U32
;
397 case 16: return TYPE_U16
;
398 case 8: return TYPE_U8
;
399 default: unreachable("bad bitsize"); return ~0;
403 static inline type_t
utype_src(nir_src src
)
404 { return utype_for_size(nir_src_bit_size(src
)); }
406 static inline type_t
utype_dst(nir_dest dst
)
407 { return utype_for_size(nir_dest_bit_size(dst
)); }
409 /* allocate a n element value array (to be populated by caller) and
412 static struct ir3_instruction
**
413 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
415 struct ir3_instruction
**value
=
416 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
417 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
421 static struct ir3_instruction
**
422 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
424 struct ir3_instruction
**value
;
427 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
429 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
432 /* NOTE: in non-ssa case, we don't really need to store last_dst
433 * but this helps us catch cases where put_dst() call is forgotten
435 compile_assert(ctx
, !ctx
->last_dst
);
436 ctx
->last_dst
= value
;
442 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
444 static struct ir3_instruction
* const *
445 get_src(struct ir3_context
*ctx
, nir_src
*src
)
448 struct hash_entry
*entry
;
449 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
450 compile_assert(ctx
, entry
);
453 nir_register
*reg
= src
->reg
.reg
;
454 struct ir3_array
*arr
= get_array(ctx
, reg
);
455 unsigned num_components
= arr
->r
->num_components
;
456 struct ir3_instruction
*addr
= NULL
;
457 struct ir3_instruction
**value
=
458 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
460 if (src
->reg
.indirect
)
461 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
462 reg
->num_components
);
464 for (unsigned i
= 0; i
< num_components
; i
++) {
465 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
466 compile_assert(ctx
, n
< arr
->length
);
467 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
475 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
477 unsigned bit_size
= nir_dest_bit_size(*dst
);
480 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
481 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
482 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
483 if (ctx
->last_dst
[i
]->opc
== OPC_META_FO
)
484 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
489 nir_register
*reg
= dst
->reg
.reg
;
490 struct ir3_array
*arr
= get_array(ctx
, reg
);
491 unsigned num_components
= ctx
->last_dst_n
;
492 struct ir3_instruction
*addr
= NULL
;
494 if (dst
->reg
.indirect
)
495 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
496 reg
->num_components
);
498 for (unsigned i
= 0; i
< num_components
; i
++) {
499 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
500 compile_assert(ctx
, n
< arr
->length
);
501 if (!ctx
->last_dst
[i
])
503 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
506 ralloc_free(ctx
->last_dst
);
508 ctx
->last_dst
= NULL
;
512 static struct ir3_instruction
*
513 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
515 struct ir3_instruction
*mov
;
516 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
518 mov
= ir3_instr_create(block
, OPC_MOV
);
519 mov
->cat1
.src_type
= type
;
520 mov
->cat1
.dst_type
= type
;
521 ir3_reg_create(mov
, 0, flags
);
522 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
527 static struct ir3_instruction
*
528 create_immed(struct ir3_block
*block
, uint32_t val
)
530 return create_immed_typed(block
, val
, TYPE_U32
);
533 static struct ir3_instruction
*
534 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
536 struct ir3_instruction
*instr
, *immed
;
538 /* TODO in at least some cases, the backend could probably be
539 * made clever enough to propagate IR3_REG_HALF..
541 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
542 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
549 /* src *= 2 => src <<= 1: */
550 immed
= create_immed(block
, 1);
551 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
553 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
554 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
555 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
559 immed
= create_immed(block
, 3);
560 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
562 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
563 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
564 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
567 /* src *= 4 => src <<= 2: */
568 immed
= create_immed(block
, 2);
569 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
571 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
572 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
573 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
576 unreachable("bad align");
580 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
581 instr
->regs
[0]->num
= regid(REG_A0
, 0);
582 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
583 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
588 /* caches addr values to avoid generating multiple cov/shl/mova
589 * sequences for each use of a given NIR level src as address
591 static struct ir3_instruction
*
592 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
594 struct ir3_instruction
*addr
;
595 unsigned idx
= align
- 1;
597 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
599 if (!ctx
->addr_ht
[idx
]) {
600 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
601 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
603 struct hash_entry
*entry
;
604 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
609 addr
= create_addr(ctx
->block
, src
, align
);
610 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
615 static struct ir3_instruction
*
616 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
618 struct ir3_block
*b
= ctx
->block
;
619 struct ir3_instruction
*cond
;
621 /* NOTE: only cmps.*.* can write p0.x: */
622 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
623 cond
->cat2
.condition
= IR3_COND_NE
;
625 /* condition always goes in predicate register: */
626 cond
->regs
[0]->num
= regid(REG_P0
, 0);
631 static struct ir3_instruction
*
632 create_uniform(struct ir3_context
*ctx
, unsigned n
)
634 struct ir3_instruction
*mov
;
636 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
637 /* TODO get types right? */
638 mov
->cat1
.src_type
= TYPE_F32
;
639 mov
->cat1
.dst_type
= TYPE_F32
;
640 ir3_reg_create(mov
, 0, 0);
641 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
646 static struct ir3_instruction
*
647 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
648 struct ir3_instruction
*address
)
650 struct ir3_instruction
*mov
;
652 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
653 mov
->cat1
.src_type
= TYPE_U32
;
654 mov
->cat1
.dst_type
= TYPE_U32
;
655 ir3_reg_create(mov
, 0, 0);
656 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
658 ir3_instr_set_address(mov
, address
);
663 static struct ir3_instruction
*
664 create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
667 struct ir3_block
*block
= ctx
->block
;
668 struct ir3_instruction
*collect
;
673 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
675 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
676 ir3_reg_create(collect
, 0, flags
); /* dst */
677 for (unsigned i
= 0; i
< arrsz
; i
++) {
678 struct ir3_instruction
*elem
= arr
[i
];
680 /* Since arrays are pre-colored in RA, we can't assume that
681 * things will end up in the right place. (Ie. if a collect
682 * joins elements from two different arrays.) So insert an
685 * We could possibly skip this if all the collected elements
686 * are contiguous elements in a single array.. not sure how
687 * likely that is to happen.
689 * Fixes a problem with glamor shaders, that in effect do
696 * color = texture2D(tex, texcoord);
698 * In this case, texcoord will end up as nir registers (which
699 * translate to ir3 array's of length 1. And we can't assume
700 * the two (or more) arrays will get allocated in consecutive
704 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
705 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
706 elem
= ir3_MOV(block
, elem
, type
);
709 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
710 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
716 static struct ir3_instruction
*
717 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
718 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
720 struct ir3_block
*block
= ctx
->block
;
721 struct ir3_instruction
*mov
;
722 struct ir3_register
*src
;
724 mov
= ir3_instr_create(block
, OPC_MOV
);
725 mov
->cat1
.src_type
= TYPE_U32
;
726 mov
->cat1
.dst_type
= TYPE_U32
;
727 ir3_reg_create(mov
, 0, 0);
728 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
729 src
->instr
= collect
;
731 src
->array
.offset
= n
;
733 ir3_instr_set_address(mov
, address
);
738 static struct ir3_instruction
*
739 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
741 struct ir3_instruction
*in
;
743 in
= ir3_instr_create(block
, OPC_META_INPUT
);
744 in
->inout
.block
= block
;
745 ir3_reg_create(in
, n
, 0);
747 in
->regs
[0]->wrmask
= compmask
;
752 static struct ir3_instruction
*
753 create_input(struct ir3_block
*block
, unsigned n
)
755 return create_input_compmask(block
, n
, 0x1);
758 static struct ir3_instruction
*
759 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
761 struct ir3_block
*block
= ctx
->block
;
762 struct ir3_instruction
*instr
;
763 /* actual inloc is assigned and fixed up later: */
764 struct ir3_instruction
*inloc
= create_immed(block
, 0);
767 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
768 instr
->cat6
.type
= TYPE_U32
;
769 instr
->cat6
.iim_val
= 1;
771 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
772 instr
->regs
[2]->wrmask
= 0x3;
778 static struct ir3_instruction
*
779 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
781 struct ir3_block
*block
= ctx
->block
;
782 struct ir3_instruction
*instr
;
784 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
786 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
791 /* for frag_coord, we get unsigned values.. we need
792 * to subtract (integer) 8 and divide by 16 (right-
793 * shift by 4) then convert to float:
797 * mov.u32f32 dst, tmp
800 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
801 create_immed(block
, 8), 0);
802 instr
= ir3_SHR_B(block
, instr
, 0,
803 create_immed(block
, 4), 0);
804 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
810 /* seems that we can use these as-is: */
811 return ctx
->frag_coord
[comp
];
815 static struct ir3_instruction
*
816 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
818 /* first four vec4 sysval's reserved for UBOs: */
819 /* NOTE: dp is in scalar, but there can be >4 dp components: */
820 unsigned n
= ctx
->so
->constbase
.driver_param
;
821 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
822 return create_uniform(ctx
, r
);
825 /* helper for instructions that produce multiple consecutive scalar
826 * outputs which need to have a split/fanout meta instruction inserted
829 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
830 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
832 struct ir3_instruction
*prev
= NULL
;
834 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
839 for (int i
= 0, j
= 0; i
< n
; i
++) {
840 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
841 ir3_reg_create(split
, 0, IR3_REG_SSA
);
842 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
843 split
->fo
.off
= i
+ base
;
846 split
->cp
.left
= prev
;
847 split
->cp
.left_cnt
++;
848 prev
->cp
.right
= split
;
849 prev
->cp
.right_cnt
++;
853 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
859 * Adreno uses uint rather than having dedicated bool type,
860 * which (potentially) requires some conversion, in particular
861 * when using output of an bool instr to int input, or visa
865 * -------+---------+-------+-
869 * To convert from an adreno bool (uint) to nir, use:
871 * absneg.s dst, (neg)src
873 * To convert back in the other direction:
875 * absneg.s dst, (abs)arc
877 * The CP step can clean up the absneg.s that cancel each other
878 * out, and with a slight bit of extra cleverness (to recognize
879 * the instructions which produce either a 0 or 1) can eliminate
880 * the absneg.s's completely when an instruction that wants
881 * 0/1 consumes the result. For example, when a nir 'bcsel'
882 * consumes the result of 'feq'. So we should be able to get by
883 * without a boolean resolve step, and without incuring any
884 * extra penalty in instruction count.
887 /* NIR bool -> native (adreno): */
888 static struct ir3_instruction
*
889 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
891 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
894 /* native (adreno) -> NIR bool: */
895 static struct ir3_instruction
*
896 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
898 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
902 * alu/sfu instructions:
905 static struct ir3_instruction
*
906 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
907 unsigned src_bitsize
, nir_op op
)
909 type_t src_type
, dst_type
;
913 case nir_op_f2f16_rtne
:
914 case nir_op_f2f16_rtz
:
922 switch (src_bitsize
) {
930 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
939 switch (src_bitsize
) {
950 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
959 switch (src_bitsize
) {
970 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
975 compile_error(ctx
, "invalid conversion op: %u", op
);
985 case nir_op_f2f16_rtne
:
986 case nir_op_f2f16_rtz
:
988 /* TODO how to handle rounding mode? */
1001 dst_type
= TYPE_S16
;
1011 dst_type
= TYPE_U32
;
1016 dst_type
= TYPE_U16
;
1025 compile_error(ctx
, "invalid conversion op: %u", op
);
1028 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
1032 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
1034 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1035 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
1036 unsigned bs
[info
->num_inputs
]; /* bit size */
1037 struct ir3_block
*b
= ctx
->block
;
1038 unsigned dst_sz
, wrmask
;
1040 if (alu
->dest
.dest
.is_ssa
) {
1041 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
1042 wrmask
= (1 << dst_sz
) - 1;
1044 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
1045 wrmask
= alu
->dest
.write_mask
;
1048 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
1050 /* Vectors are special in that they have non-scalarized writemasks,
1051 * and just take the first swizzle channel for each argument in
1052 * order into each writemask channel.
1054 if ((alu
->op
== nir_op_vec2
) ||
1055 (alu
->op
== nir_op_vec3
) ||
1056 (alu
->op
== nir_op_vec4
)) {
1058 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1059 nir_alu_src
*asrc
= &alu
->src
[i
];
1061 compile_assert(ctx
, !asrc
->abs
);
1062 compile_assert(ctx
, !asrc
->negate
);
1064 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
1066 src
[i
] = create_immed(ctx
->block
, 0);
1067 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
1070 put_dst(ctx
, &alu
->dest
.dest
);
1074 /* We also get mov's with more than one component for mov's so
1075 * handle those specially:
1077 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
1078 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
1079 nir_alu_src
*asrc
= &alu
->src
[0];
1080 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
1082 for (unsigned i
= 0; i
< dst_sz
; i
++) {
1083 if (wrmask
& (1 << i
)) {
1084 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
1090 put_dst(ctx
, &alu
->dest
.dest
);
1094 /* General case: We can just grab the one used channel per src. */
1095 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1096 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
1097 nir_alu_src
*asrc
= &alu
->src
[i
];
1099 compile_assert(ctx
, !asrc
->abs
);
1100 compile_assert(ctx
, !asrc
->negate
);
1102 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
1103 bs
[i
] = nir_src_bit_size(asrc
->src
);
1105 compile_assert(ctx
, src
[i
]);
1110 case nir_op_f2f16_rtne
:
1111 case nir_op_f2f16_rtz
:
1129 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
1132 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
1133 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1134 dst
[0] = ir3_n2b(b
, dst
[0]);
1137 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
1140 dst
[0] = ir3_b2n(b
, src
[0]);
1143 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1144 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1145 dst
[0] = ir3_n2b(b
, dst
[0]);
1149 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1152 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1155 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1158 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1161 /* if there is just a single use of the src, and it supports
1162 * (sat) bit, we can just fold the (sat) flag back to the
1163 * src instruction and create a mov. This is easier for cp
1166 * TODO probably opc_cat==4 is ok too
1168 if (alu
->src
[0].src
.is_ssa
&&
1169 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
1170 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
1171 src
[0]->flags
|= IR3_INSTR_SAT
;
1172 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
1174 /* otherwise generate a max.f that saturates.. blob does
1175 * similar (generating a cat2 mov using max.f)
1177 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
1178 dst
[0]->flags
|= IR3_INSTR_SAT
;
1182 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1185 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1188 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1191 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1194 dst
[0] = ir3_DSX(b
, src
[0], 0);
1195 dst
[0]->cat5
.type
= TYPE_F32
;
1198 dst
[0] = ir3_DSY(b
, src
[0], 0);
1199 dst
[0]->cat5
.type
= TYPE_F32
;
1203 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1204 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1205 dst
[0] = ir3_n2b(b
, dst
[0]);
1208 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1209 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1210 dst
[0] = ir3_n2b(b
, dst
[0]);
1213 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1214 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1215 dst
[0] = ir3_n2b(b
, dst
[0]);
1218 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1219 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1220 dst
[0] = ir3_n2b(b
, dst
[0]);
1223 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1226 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1229 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1231 case nir_op_fround_even
:
1232 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1235 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1239 dst
[0] = ir3_SIN(b
, src
[0], 0);
1242 dst
[0] = ir3_COS(b
, src
[0], 0);
1245 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1248 dst
[0] = ir3_RCP(b
, src
[0], 0);
1251 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1254 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1257 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1261 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1264 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1267 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1270 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1273 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1276 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1279 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1283 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1284 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1285 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1286 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1288 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1289 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1290 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1293 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1296 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1299 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1302 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1305 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1307 case nir_op_isign
: {
1308 /* maybe this would be sane to lower in nir.. */
1309 struct ir3_instruction
*neg
, *pos
;
1311 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1312 neg
->cat2
.condition
= IR3_COND_LT
;
1314 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1315 pos
->cat2
.condition
= IR3_COND_GT
;
1317 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1322 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1325 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1328 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1331 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1332 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1333 dst
[0] = ir3_n2b(b
, dst
[0]);
1336 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1337 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1338 dst
[0] = ir3_n2b(b
, dst
[0]);
1341 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1342 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1343 dst
[0] = ir3_n2b(b
, dst
[0]);
1346 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1347 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1348 dst
[0] = ir3_n2b(b
, dst
[0]);
1351 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1352 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1353 dst
[0] = ir3_n2b(b
, dst
[0]);
1356 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1357 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1358 dst
[0] = ir3_n2b(b
, dst
[0]);
1361 case nir_op_bcsel
: {
1362 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
1363 compile_assert(ctx
, bs
[1] == bs
[2]);
1364 /* the boolean condition is 32b even if src[1] and src[2] are
1365 * half-precision, but sel.b16 wants all three src's to be the
1369 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
1370 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
1373 case nir_op_bit_count
:
1374 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1376 case nir_op_ifind_msb
: {
1377 struct ir3_instruction
*cmp
;
1378 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1379 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1380 cmp
->cat2
.condition
= IR3_COND_GE
;
1381 dst
[0] = ir3_SEL_B32(b
,
1382 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1386 case nir_op_ufind_msb
:
1387 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1388 dst
[0] = ir3_SEL_B32(b
,
1389 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1390 src
[0], 0, dst
[0], 0);
1392 case nir_op_find_lsb
:
1393 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1394 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1396 case nir_op_bitfield_reverse
:
1397 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1401 compile_error(ctx
, "Unhandled ALU op: %s\n",
1402 nir_op_infos
[alu
->op
].name
);
1406 put_dst(ctx
, &alu
->dest
.dest
);
1409 /* handles direct/indirect UBO reads: */
1411 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1412 struct ir3_instruction
**dst
)
1414 struct ir3_block
*b
= ctx
->block
;
1415 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1416 nir_const_value
*const_offset
;
1417 /* UBO addresses are the first driver params: */
1418 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1419 const unsigned ptrsz
= pointer_size(ctx
);
1423 /* First src is ubo index, which could either be an immed or not: */
1424 src0
= get_src(ctx
, &intr
->src
[0])[0];
1425 if (is_same_type_mov(src0
) &&
1426 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1427 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1428 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1430 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1431 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1434 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1437 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1439 off
+= const_offset
->u32
[0];
1441 /* For load_ubo_indirect, second src is indirect offset: */
1442 src1
= get_src(ctx
, &intr
->src
[1])[0];
1444 /* and add offset to addr: */
1445 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1448 /* if offset is to large to encode in the ldg, split it out: */
1449 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1450 /* split out the minimal amount to improve the odds that
1451 * cp can fit the immediate in the add.s instruction:
1453 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1454 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1459 struct ir3_instruction
*carry
;
1461 /* handle 32b rollover, ie:
1462 * if (addr < base_lo)
1465 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1466 carry
->cat2
.condition
= IR3_COND_LT
;
1467 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1469 addr
= create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1472 for (int i
= 0; i
< intr
->num_components
; i
++) {
1473 struct ir3_instruction
*load
=
1474 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1475 load
->cat6
.type
= TYPE_U32
;
1476 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1481 /* src[] = { buffer_index, offset }. No const_index */
1483 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1484 struct ir3_instruction
**dst
)
1486 struct ir3_block
*b
= ctx
->block
;
1487 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1488 nir_const_value
*const_offset
;
1490 /* can this be non-const buffer_index? how do we handle that? */
1491 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1492 compile_assert(ctx
, const_offset
);
1494 offset
= get_src(ctx
, &intr
->src
[1])[0];
1496 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1497 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1501 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1503 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1505 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1506 ldgb
->cat6
.iim_val
= intr
->num_components
;
1508 ldgb
->cat6
.type
= TYPE_U32
;
1509 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1510 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1512 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1515 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1517 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1519 struct ir3_block
*b
= ctx
->block
;
1520 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1521 nir_const_value
*const_offset
;
1522 /* TODO handle wrmask properly, see _store_shared().. but I think
1523 * it is more a PITA than that, since blob ends up loading the
1524 * masked components and writing them back out.
1526 unsigned wrmask
= intr
->const_index
[0];
1527 unsigned ncomp
= ffs(~wrmask
) - 1;
1529 /* can this be non-const buffer_index? how do we handle that? */
1530 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1531 compile_assert(ctx
, const_offset
);
1533 offset
= get_src(ctx
, &intr
->src
[2])[0];
1535 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1538 src0
= create_collect(ctx
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1539 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1540 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1545 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1546 src0
, 0, src1
, 0, src2
, 0);
1547 stgb
->cat6
.iim_val
= ncomp
;
1549 stgb
->cat6
.type
= TYPE_U32
;
1550 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1551 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1553 array_insert(b
, b
->keeps
, stgb
);
1556 /* src[] = { block_index } */
1558 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1559 struct ir3_instruction
**dst
)
1561 /* SSBO size stored as a const starting at ssbo_sizes: */
1562 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1563 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1564 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1566 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1568 dst
[0] = create_uniform(ctx
, idx
);
1572 * SSBO atomic intrinsics
1574 * All of the SSBO atomic memory operations read a value from memory,
1575 * compute a new value using one of the operations below, write the new
1576 * value to memory, and return the original value read.
1578 * All operations take 3 sources except CompSwap that takes 4. These
1579 * sources represent:
1581 * 0: The SSBO buffer index.
1582 * 1: The offset into the SSBO buffer of the variable that the atomic
1583 * operation will operate on.
1584 * 2: The data parameter to the atomic function (i.e. the value to add
1585 * in ssbo_atomic_add, etc).
1586 * 3: For CompSwap only: the second data parameter.
1588 static struct ir3_instruction
*
1589 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1591 struct ir3_block
*b
= ctx
->block
;
1592 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1593 nir_const_value
*const_offset
;
1594 type_t type
= TYPE_U32
;
1596 /* can this be non-const buffer_index? how do we handle that? */
1597 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1598 compile_assert(ctx
, const_offset
);
1599 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1601 offset
= get_src(ctx
, &intr
->src
[1])[0];
1603 /* src0 is data (or uvec2(data, compare))
1605 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1607 * Note that nir already multiplies the offset by four
1609 src0
= get_src(ctx
, &intr
->src
[2])[0];
1610 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1611 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1616 switch (intr
->intrinsic
) {
1617 case nir_intrinsic_ssbo_atomic_add
:
1618 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1620 case nir_intrinsic_ssbo_atomic_imin
:
1621 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1624 case nir_intrinsic_ssbo_atomic_umin
:
1625 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1627 case nir_intrinsic_ssbo_atomic_imax
:
1628 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1631 case nir_intrinsic_ssbo_atomic_umax
:
1632 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1634 case nir_intrinsic_ssbo_atomic_and
:
1635 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1637 case nir_intrinsic_ssbo_atomic_or
:
1638 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1640 case nir_intrinsic_ssbo_atomic_xor
:
1641 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1643 case nir_intrinsic_ssbo_atomic_exchange
:
1644 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1646 case nir_intrinsic_ssbo_atomic_comp_swap
:
1647 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1648 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1650 get_src(ctx
, &intr
->src
[3])[0],
1652 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1658 atomic
->cat6
.iim_val
= 1;
1660 atomic
->cat6
.type
= type
;
1661 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1662 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1664 /* even if nothing consume the result, we can't DCE the instruction: */
1665 array_insert(b
, b
->keeps
, atomic
);
1670 /* src[] = { offset }. const_index[] = { base } */
1672 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1673 struct ir3_instruction
**dst
)
1675 struct ir3_block
*b
= ctx
->block
;
1676 struct ir3_instruction
*ldl
, *offset
;
1679 offset
= get_src(ctx
, &intr
->src
[0])[0];
1680 base
= nir_intrinsic_base(intr
);
1682 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1683 ldl
->cat6
.src_offset
= base
;
1684 ldl
->cat6
.type
= utype_dst(intr
->dest
);
1685 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1687 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1688 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1690 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1693 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1695 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1697 struct ir3_block
*b
= ctx
->block
;
1698 struct ir3_instruction
*stl
, *offset
;
1699 struct ir3_instruction
* const *value
;
1700 unsigned base
, wrmask
;
1702 value
= get_src(ctx
, &intr
->src
[0]);
1703 offset
= get_src(ctx
, &intr
->src
[1])[0];
1705 base
= nir_intrinsic_base(intr
);
1706 wrmask
= nir_intrinsic_write_mask(intr
);
1708 /* Combine groups of consecutive enabled channels in one write
1709 * message. We use ffs to find the first enabled channel and then ffs on
1710 * the bit-inverse, down-shifted writemask to determine the length of
1711 * the block of enabled bits.
1713 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1716 unsigned first_component
= ffs(wrmask
) - 1;
1717 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1719 stl
= ir3_STL(b
, offset
, 0,
1720 create_collect(ctx
, &value
[first_component
], length
), 0,
1721 create_immed(b
, length
), 0);
1722 stl
->cat6
.dst_offset
= first_component
+ base
;
1723 stl
->cat6
.type
= utype_src(intr
->src
[0]);
1724 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1725 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1727 array_insert(b
, b
->keeps
, stl
);
1729 /* Clear the bits in the writemask that we just wrote, then try
1730 * again to see if more channels are left.
1732 wrmask
&= (15 << (first_component
+ length
));
1737 * CS shared variable atomic intrinsics
1739 * All of the shared variable atomic memory operations read a value from
1740 * memory, compute a new value using one of the operations below, write the
1741 * new value to memory, and return the original value read.
1743 * All operations take 2 sources except CompSwap that takes 3. These
1744 * sources represent:
1746 * 0: The offset into the shared variable storage region that the atomic
1747 * operation will operate on.
1748 * 1: The data parameter to the atomic function (i.e. the value to add
1749 * in shared_atomic_add, etc).
1750 * 2: For CompSwap only: the second data parameter.
1752 static struct ir3_instruction
*
1753 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1755 struct ir3_block
*b
= ctx
->block
;
1756 struct ir3_instruction
*atomic
, *src0
, *src1
;
1757 type_t type
= TYPE_U32
;
1759 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1760 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1762 switch (intr
->intrinsic
) {
1763 case nir_intrinsic_shared_atomic_add
:
1764 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1766 case nir_intrinsic_shared_atomic_imin
:
1767 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1770 case nir_intrinsic_shared_atomic_umin
:
1771 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1773 case nir_intrinsic_shared_atomic_imax
:
1774 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1777 case nir_intrinsic_shared_atomic_umax
:
1778 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1780 case nir_intrinsic_shared_atomic_and
:
1781 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1783 case nir_intrinsic_shared_atomic_or
:
1784 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1786 case nir_intrinsic_shared_atomic_xor
:
1787 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1789 case nir_intrinsic_shared_atomic_exchange
:
1790 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1792 case nir_intrinsic_shared_atomic_comp_swap
:
1793 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1794 src1
= create_collect(ctx
, (struct ir3_instruction
*[]){
1795 get_src(ctx
, &intr
->src
[2])[0],
1798 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1804 atomic
->cat6
.iim_val
= 1;
1806 atomic
->cat6
.type
= type
;
1807 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1808 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1810 /* even if nothing consume the result, we can't DCE the instruction: */
1811 array_insert(b
, b
->keeps
, atomic
);
1816 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1817 * state block (for load). To simplify things, invert the image id and
1818 * map it from end of state block, ie. image 0 becomes num-1, image 1
1819 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1820 * state when switching shaders.
1822 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1823 * coded. Also, since all the gl shader stages (ie. everything but CS)
1824 * share the same SSBO/image state block, this might require some more
1825 * logic if we supported images in anything other than FS..
1828 get_image_slot(struct ir3_context
*ctx
, nir_deref_instr
*deref
)
1830 unsigned int loc
= 0;
1831 unsigned inner_size
= 1;
1833 while (deref
->deref_type
!= nir_deref_type_var
) {
1834 assert(deref
->deref_type
== nir_deref_type_array
);
1835 nir_const_value
*const_index
= nir_src_as_const_value(deref
->arr
.index
);
1836 assert(const_index
);
1838 /* Go to the next instruction */
1839 deref
= nir_deref_instr_parent(deref
);
1841 assert(glsl_type_is_array(deref
->type
));
1842 const unsigned array_len
= glsl_get_length(deref
->type
);
1843 loc
+= MIN2(const_index
->u32
[0], array_len
- 1) * inner_size
;
1845 /* Update the inner size */
1846 inner_size
*= array_len
;
1849 loc
+= deref
->var
->data
.driver_location
;
1851 /* TODO figure out real limit per generation, and don't hardcode: */
1852 const unsigned max_samplers
= 16;
1853 return max_samplers
- loc
- 1;
1856 /* see tex_info() for equiv logic for texture instructions.. it would be
1857 * nice if this could be better unified..
1860 get_image_coords(const nir_variable
*var
, unsigned *flagsp
)
1862 const struct glsl_type
*type
= glsl_without_array(var
->type
);
1863 unsigned coords
, flags
= 0;
1865 switch (glsl_get_sampler_dim(type
)) {
1866 case GLSL_SAMPLER_DIM_1D
:
1867 case GLSL_SAMPLER_DIM_BUF
:
1870 case GLSL_SAMPLER_DIM_2D
:
1871 case GLSL_SAMPLER_DIM_RECT
:
1872 case GLSL_SAMPLER_DIM_EXTERNAL
:
1873 case GLSL_SAMPLER_DIM_MS
:
1876 case GLSL_SAMPLER_DIM_3D
:
1877 case GLSL_SAMPLER_DIM_CUBE
:
1878 flags
|= IR3_INSTR_3D
;
1882 unreachable("bad sampler dim");
1886 if (glsl_sampler_type_is_array(type
)) {
1887 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1889 flags
|= IR3_INSTR_A
;
1899 get_image_type(const nir_variable
*var
)
1901 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1902 case GLSL_TYPE_UINT
:
1906 case GLSL_TYPE_FLOAT
:
1909 unreachable("bad sampler type.");
1914 static struct ir3_instruction
*
1915 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1916 struct ir3_instruction
* const *coords
, bool byteoff
)
1918 struct ir3_block
*b
= ctx
->block
;
1919 struct ir3_instruction
*offset
;
1920 unsigned ncoords
= get_image_coords(var
, NULL
);
1922 /* to calculate the byte offset (yes, uggg) we need (up to) three
1923 * const values to know the bytes per pixel, and y and z stride:
1925 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1926 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1928 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1929 (1 << var
->data
.driver_location
));
1931 /* offset = coords.x * bytes_per_pixel: */
1932 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1934 /* offset += coords.y * y_pitch: */
1935 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1936 coords
[1], 0, offset
, 0);
1939 /* offset += coords.z * z_pitch: */
1940 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1941 coords
[2], 0, offset
, 0);
1945 /* Some cases, like atomics, seem to use dword offset instead
1946 * of byte offsets.. blob just puts an extra shr.b in there
1949 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1952 return create_collect(ctx
, (struct ir3_instruction
*[]){
1958 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1960 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1961 struct ir3_instruction
**dst
)
1963 struct ir3_block
*b
= ctx
->block
;
1964 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1965 struct ir3_instruction
*sam
;
1966 struct ir3_instruction
* const *src0
= get_src(ctx
, &intr
->src
[1]);
1967 struct ir3_instruction
*coords
[4];
1968 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
1969 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
1970 type_t type
= get_image_type(var
);
1972 /* hmm, this seems a bit odd, but it is what blob does and (at least
1973 * a5xx) just faults on bogus addresses otherwise:
1975 if (flags
& IR3_INSTR_3D
) {
1976 flags
&= ~IR3_INSTR_3D
;
1977 flags
|= IR3_INSTR_A
;
1980 for (unsigned i
= 0; i
< ncoords
; i
++)
1981 coords
[i
] = src0
[i
];
1984 coords
[ncoords
++] = create_immed(b
, 0);
1986 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1987 tex_idx
, tex_idx
, create_collect(ctx
, coords
, ncoords
), NULL
);
1989 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1990 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1992 split_dest(b
, dst
, sam
, 0, 4);
1995 /* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
1997 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1999 struct ir3_block
*b
= ctx
->block
;
2000 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2001 struct ir3_instruction
*stib
, *offset
;
2002 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[3]);
2003 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[1]);
2004 unsigned ncoords
= get_image_coords(var
, NULL
);
2005 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
2009 * src2 is 64b byte offset
2012 offset
= get_image_offset(ctx
, var
, coords
, true);
2014 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
2015 * too and takes a dword offset.. not quite sure yet why blob uses
2016 * one over the other in various cases.
2019 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
2020 create_collect(ctx
, value
, 4), 0,
2021 create_collect(ctx
, coords
, ncoords
), 0,
2023 stib
->cat6
.iim_val
= 4;
2024 stib
->cat6
.d
= ncoords
;
2025 stib
->cat6
.type
= get_image_type(var
);
2026 stib
->cat6
.typed
= true;
2027 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2028 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2030 array_insert(b
, b
->keeps
, stib
);
2034 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
2035 struct ir3_instruction
**dst
)
2037 struct ir3_block
*b
= ctx
->block
;
2038 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2039 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
2040 struct ir3_instruction
*sam
, *lod
;
2041 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
2043 lod
= create_immed(b
, 0);
2044 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2045 tex_idx
, tex_idx
, lod
, NULL
);
2047 /* Array size actually ends up in .w rather than .z. This doesn't
2048 * matter for miplevel 0, but for higher mips the value in z is
2049 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2050 * returned, which means that we have to add 1 to it for arrays for
2053 * Note use a temporary dst and then copy, since the size of the dst
2054 * array that is passed in is based on nir's understanding of the
2055 * result size, not the hardware's
2057 struct ir3_instruction
*tmp
[4];
2059 split_dest(b
, tmp
, sam
, 0, 4);
2061 for (unsigned i
= 0; i
< ncoords
; i
++)
2064 if (flags
& IR3_INSTR_A
) {
2065 if (ctx
->compiler
->levels_add_one
) {
2066 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
2068 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
2073 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
2074 static struct ir3_instruction
*
2075 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2077 struct ir3_block
*b
= ctx
->block
;
2078 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2079 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
2080 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[1]);
2081 unsigned ncoords
= get_image_coords(var
, NULL
);
2083 image
= create_immed(b
, get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0])));
2085 /* src0 is value (or uvec2(value, compare))
2087 * src2 is 64b byte offset
2089 src0
= get_src(ctx
, &intr
->src
[3])[0];
2090 src1
= create_collect(ctx
, coords
, ncoords
);
2091 src2
= get_image_offset(ctx
, var
, coords
, false);
2093 switch (intr
->intrinsic
) {
2094 case nir_intrinsic_image_deref_atomic_add
:
2095 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2097 case nir_intrinsic_image_deref_atomic_min
:
2098 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2100 case nir_intrinsic_image_deref_atomic_max
:
2101 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2103 case nir_intrinsic_image_deref_atomic_and
:
2104 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2106 case nir_intrinsic_image_deref_atomic_or
:
2107 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2109 case nir_intrinsic_image_deref_atomic_xor
:
2110 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2112 case nir_intrinsic_image_deref_atomic_exchange
:
2113 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2115 case nir_intrinsic_image_deref_atomic_comp_swap
:
2116 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
2117 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
2119 get_src(ctx
, &intr
->src
[4])[0],
2121 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2127 atomic
->cat6
.iim_val
= 1;
2128 atomic
->cat6
.d
= ncoords
;
2129 atomic
->cat6
.type
= get_image_type(var
);
2130 atomic
->cat6
.typed
= true;
2131 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2132 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2134 /* even if nothing consume the result, we can't DCE the instruction: */
2135 array_insert(b
, b
->keeps
, atomic
);
2141 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2143 struct ir3_block
*b
= ctx
->block
;
2144 struct ir3_instruction
*barrier
;
2146 switch (intr
->intrinsic
) {
2147 case nir_intrinsic_barrier
:
2148 barrier
= ir3_BAR(b
);
2149 barrier
->cat7
.g
= true;
2150 barrier
->cat7
.l
= true;
2151 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
2152 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2154 case nir_intrinsic_memory_barrier
:
2155 barrier
= ir3_FENCE(b
);
2156 barrier
->cat7
.g
= true;
2157 barrier
->cat7
.r
= true;
2158 barrier
->cat7
.w
= true;
2159 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
2160 IR3_BARRIER_BUFFER_W
;
2161 barrier
->barrier_conflict
=
2162 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2163 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2165 case nir_intrinsic_memory_barrier_atomic_counter
:
2166 case nir_intrinsic_memory_barrier_buffer
:
2167 barrier
= ir3_FENCE(b
);
2168 barrier
->cat7
.g
= true;
2169 barrier
->cat7
.r
= true;
2170 barrier
->cat7
.w
= true;
2171 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
2172 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
2173 IR3_BARRIER_BUFFER_W
;
2175 case nir_intrinsic_memory_barrier_image
:
2176 // TODO double check if this should have .g set
2177 barrier
= ir3_FENCE(b
);
2178 barrier
->cat7
.g
= true;
2179 barrier
->cat7
.r
= true;
2180 barrier
->cat7
.w
= true;
2181 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2182 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
2183 IR3_BARRIER_IMAGE_W
;
2185 case nir_intrinsic_memory_barrier_shared
:
2186 barrier
= ir3_FENCE(b
);
2187 barrier
->cat7
.g
= true;
2188 barrier
->cat7
.l
= true;
2189 barrier
->cat7
.r
= true;
2190 barrier
->cat7
.w
= true;
2191 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
2192 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
2193 IR3_BARRIER_SHARED_W
;
2195 case nir_intrinsic_group_memory_barrier
:
2196 barrier
= ir3_FENCE(b
);
2197 barrier
->cat7
.g
= true;
2198 barrier
->cat7
.l
= true;
2199 barrier
->cat7
.r
= true;
2200 barrier
->cat7
.w
= true;
2201 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
2202 IR3_BARRIER_IMAGE_W
|
2203 IR3_BARRIER_BUFFER_W
;
2204 barrier
->barrier_conflict
=
2205 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
2206 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2207 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2213 /* make sure barrier doesn't get DCE'd */
2214 array_insert(b
, b
->keeps
, barrier
);
2217 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
2218 gl_system_value slot
, unsigned compmask
,
2219 struct ir3_instruction
*instr
)
2221 struct ir3_shader_variant
*so
= ctx
->so
;
2222 unsigned r
= regid(so
->inputs_count
, 0);
2223 unsigned n
= so
->inputs_count
++;
2225 so
->inputs
[n
].sysval
= true;
2226 so
->inputs
[n
].slot
= slot
;
2227 so
->inputs
[n
].compmask
= compmask
;
2228 so
->inputs
[n
].regid
= r
;
2229 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
2232 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
2233 ctx
->ir
->inputs
[r
] = instr
;
2236 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
2237 struct ir3_instruction
*instr
)
2239 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
2243 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2245 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
2246 struct ir3_instruction
**dst
;
2247 struct ir3_instruction
* const *src
;
2248 struct ir3_block
*b
= ctx
->block
;
2249 nir_const_value
*const_offset
;
2252 if (info
->has_dest
) {
2253 unsigned n
= nir_intrinsic_dest_components(intr
);
2254 dst
= get_dst(ctx
, &intr
->dest
, n
);
2259 switch (intr
->intrinsic
) {
2260 case nir_intrinsic_load_uniform
:
2261 idx
= nir_intrinsic_base(intr
);
2262 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2264 idx
+= const_offset
->u32
[0];
2265 for (int i
= 0; i
< intr
->num_components
; i
++) {
2266 unsigned n
= idx
* 4 + i
;
2267 dst
[i
] = create_uniform(ctx
, n
);
2270 src
= get_src(ctx
, &intr
->src
[0]);
2271 for (int i
= 0; i
< intr
->num_components
; i
++) {
2272 int n
= idx
* 4 + i
;
2273 dst
[i
] = create_uniform_indirect(ctx
, n
,
2274 get_addr(ctx
, src
[0], 4));
2276 /* NOTE: if relative addressing is used, we set
2277 * constlen in the compiler (to worst-case value)
2278 * since we don't know in the assembler what the max
2279 * addr reg value can be:
2281 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2284 case nir_intrinsic_load_ubo
:
2285 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2287 case nir_intrinsic_load_input
:
2288 idx
= nir_intrinsic_base(intr
);
2289 comp
= nir_intrinsic_component(intr
);
2290 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2292 idx
+= const_offset
->u32
[0];
2293 for (int i
= 0; i
< intr
->num_components
; i
++) {
2294 unsigned n
= idx
* 4 + i
+ comp
;
2295 dst
[i
] = ctx
->ir
->inputs
[n
];
2298 src
= get_src(ctx
, &intr
->src
[0]);
2299 struct ir3_instruction
*collect
=
2300 create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2301 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2302 for (int i
= 0; i
< intr
->num_components
; i
++) {
2303 unsigned n
= idx
* 4 + i
+ comp
;
2304 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2309 case nir_intrinsic_load_ssbo
:
2310 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2312 case nir_intrinsic_store_ssbo
:
2313 emit_intrinsic_store_ssbo(ctx
, intr
);
2315 case nir_intrinsic_get_buffer_size
:
2316 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2318 case nir_intrinsic_ssbo_atomic_add
:
2319 case nir_intrinsic_ssbo_atomic_imin
:
2320 case nir_intrinsic_ssbo_atomic_umin
:
2321 case nir_intrinsic_ssbo_atomic_imax
:
2322 case nir_intrinsic_ssbo_atomic_umax
:
2323 case nir_intrinsic_ssbo_atomic_and
:
2324 case nir_intrinsic_ssbo_atomic_or
:
2325 case nir_intrinsic_ssbo_atomic_xor
:
2326 case nir_intrinsic_ssbo_atomic_exchange
:
2327 case nir_intrinsic_ssbo_atomic_comp_swap
:
2328 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2330 case nir_intrinsic_load_shared
:
2331 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2333 case nir_intrinsic_store_shared
:
2334 emit_intrinsic_store_shared(ctx
, intr
);
2336 case nir_intrinsic_shared_atomic_add
:
2337 case nir_intrinsic_shared_atomic_imin
:
2338 case nir_intrinsic_shared_atomic_umin
:
2339 case nir_intrinsic_shared_atomic_imax
:
2340 case nir_intrinsic_shared_atomic_umax
:
2341 case nir_intrinsic_shared_atomic_and
:
2342 case nir_intrinsic_shared_atomic_or
:
2343 case nir_intrinsic_shared_atomic_xor
:
2344 case nir_intrinsic_shared_atomic_exchange
:
2345 case nir_intrinsic_shared_atomic_comp_swap
:
2346 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2348 case nir_intrinsic_image_deref_load
:
2349 emit_intrinsic_load_image(ctx
, intr
, dst
);
2351 case nir_intrinsic_image_deref_store
:
2352 emit_intrinsic_store_image(ctx
, intr
);
2354 case nir_intrinsic_image_deref_size
:
2355 emit_intrinsic_image_size(ctx
, intr
, dst
);
2357 case nir_intrinsic_image_deref_atomic_add
:
2358 case nir_intrinsic_image_deref_atomic_min
:
2359 case nir_intrinsic_image_deref_atomic_max
:
2360 case nir_intrinsic_image_deref_atomic_and
:
2361 case nir_intrinsic_image_deref_atomic_or
:
2362 case nir_intrinsic_image_deref_atomic_xor
:
2363 case nir_intrinsic_image_deref_atomic_exchange
:
2364 case nir_intrinsic_image_deref_atomic_comp_swap
:
2365 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2367 case nir_intrinsic_barrier
:
2368 case nir_intrinsic_memory_barrier
:
2369 case nir_intrinsic_group_memory_barrier
:
2370 case nir_intrinsic_memory_barrier_atomic_counter
:
2371 case nir_intrinsic_memory_barrier_buffer
:
2372 case nir_intrinsic_memory_barrier_image
:
2373 case nir_intrinsic_memory_barrier_shared
:
2374 emit_intrinsic_barrier(ctx
, intr
);
2375 /* note that blk ptr no longer valid, make that obvious: */
2378 case nir_intrinsic_store_output
:
2379 idx
= nir_intrinsic_base(intr
);
2380 comp
= nir_intrinsic_component(intr
);
2381 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2382 compile_assert(ctx
, const_offset
!= NULL
);
2383 idx
+= const_offset
->u32
[0];
2385 src
= get_src(ctx
, &intr
->src
[0]);
2386 for (int i
= 0; i
< intr
->num_components
; i
++) {
2387 unsigned n
= idx
* 4 + i
+ comp
;
2388 ctx
->ir
->outputs
[n
] = src
[i
];
2391 case nir_intrinsic_load_base_vertex
:
2392 case nir_intrinsic_load_first_vertex
:
2393 if (!ctx
->basevertex
) {
2394 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2395 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
2397 dst
[0] = ctx
->basevertex
;
2399 case nir_intrinsic_load_vertex_id_zero_base
:
2400 case nir_intrinsic_load_vertex_id
:
2401 if (!ctx
->vertex_id
) {
2402 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2403 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2404 ctx
->vertex_id
= create_input(b
, 0);
2405 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2407 dst
[0] = ctx
->vertex_id
;
2409 case nir_intrinsic_load_instance_id
:
2410 if (!ctx
->instance_id
) {
2411 ctx
->instance_id
= create_input(b
, 0);
2412 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2415 dst
[0] = ctx
->instance_id
;
2417 case nir_intrinsic_load_sample_id
:
2418 case nir_intrinsic_load_sample_id_no_per_sample
:
2419 if (!ctx
->samp_id
) {
2420 ctx
->samp_id
= create_input(b
, 0);
2421 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
2422 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
2425 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
2427 case nir_intrinsic_load_sample_mask_in
:
2428 if (!ctx
->samp_mask_in
) {
2429 ctx
->samp_mask_in
= create_input(b
, 0);
2430 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
2433 dst
[0] = ctx
->samp_mask_in
;
2435 case nir_intrinsic_load_user_clip_plane
:
2436 idx
= nir_intrinsic_ucp_id(intr
);
2437 for (int i
= 0; i
< intr
->num_components
; i
++) {
2438 unsigned n
= idx
* 4 + i
;
2439 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2442 case nir_intrinsic_load_front_face
:
2443 if (!ctx
->frag_face
) {
2444 ctx
->so
->frag_face
= true;
2445 ctx
->frag_face
= create_input(b
, 0);
2446 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2448 /* for fragface, we get -1 for back and 0 for front. However this is
2449 * the inverse of what nir expects (where ~0 is true).
2451 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2452 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2454 case nir_intrinsic_load_local_invocation_id
:
2455 if (!ctx
->local_invocation_id
) {
2456 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2457 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2458 0x7, ctx
->local_invocation_id
);
2460 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2462 case nir_intrinsic_load_work_group_id
:
2463 if (!ctx
->work_group_id
) {
2464 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2465 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2466 0x7, ctx
->work_group_id
);
2467 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2469 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2471 case nir_intrinsic_load_num_work_groups
:
2472 for (int i
= 0; i
< intr
->num_components
; i
++) {
2473 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2476 case nir_intrinsic_load_local_group_size
:
2477 for (int i
= 0; i
< intr
->num_components
; i
++) {
2478 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2481 case nir_intrinsic_discard_if
:
2482 case nir_intrinsic_discard
: {
2483 struct ir3_instruction
*cond
, *kill
;
2485 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2486 /* conditional discard: */
2487 src
= get_src(ctx
, &intr
->src
[0]);
2488 cond
= ir3_b2n(b
, src
[0]);
2490 /* unconditional discard: */
2491 cond
= create_immed(b
, 1);
2494 /* NOTE: only cmps.*.* can write p0.x: */
2495 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2496 cond
->cat2
.condition
= IR3_COND_NE
;
2498 /* condition always goes in predicate register: */
2499 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2501 kill
= ir3_KILL(b
, cond
, 0);
2502 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2504 array_insert(b
, b
->keeps
, kill
);
2505 ctx
->so
->has_kill
= true;
2510 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2511 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2516 put_dst(ctx
, &intr
->dest
);
2520 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2522 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2523 instr
->def
.num_components
);
2524 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2526 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2527 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
.u32
[i
], type
);
2531 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2533 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2534 undef
->def
.num_components
);
2535 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2537 /* backend doesn't want undefined instructions, so just plug
2540 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2541 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2545 * texture fetch/sample instructions:
2549 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2551 unsigned coords
, flags
= 0;
2553 /* note: would use tex->coord_components.. except txs.. also,
2554 * since array index goes after shadow ref, we don't want to
2557 switch (tex
->sampler_dim
) {
2558 case GLSL_SAMPLER_DIM_1D
:
2559 case GLSL_SAMPLER_DIM_BUF
:
2562 case GLSL_SAMPLER_DIM_2D
:
2563 case GLSL_SAMPLER_DIM_RECT
:
2564 case GLSL_SAMPLER_DIM_EXTERNAL
:
2565 case GLSL_SAMPLER_DIM_MS
:
2568 case GLSL_SAMPLER_DIM_3D
:
2569 case GLSL_SAMPLER_DIM_CUBE
:
2571 flags
|= IR3_INSTR_3D
;
2574 unreachable("bad sampler_dim");
2577 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2578 flags
|= IR3_INSTR_S
;
2580 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2581 flags
|= IR3_INSTR_A
;
2588 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2590 struct ir3_block
*b
= ctx
->block
;
2591 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2592 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2593 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2594 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2595 unsigned i
, coords
, flags
;
2596 unsigned nsrc0
= 0, nsrc1
= 0;
2600 coord
= off
= ddx
= ddy
= NULL
;
2601 lod
= proj
= compare
= sample_index
= NULL
;
2603 /* TODO: might just be one component for gathers? */
2604 dst
= get_dst(ctx
, &tex
->dest
, 4);
2606 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2607 switch (tex
->src
[i
].src_type
) {
2608 case nir_tex_src_coord
:
2609 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2611 case nir_tex_src_bias
:
2612 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2615 case nir_tex_src_lod
:
2616 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2619 case nir_tex_src_comparator
: /* shadow comparator */
2620 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2622 case nir_tex_src_projector
:
2623 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2626 case nir_tex_src_offset
:
2627 off
= get_src(ctx
, &tex
->src
[i
].src
);
2630 case nir_tex_src_ddx
:
2631 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2633 case nir_tex_src_ddy
:
2634 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2636 case nir_tex_src_ms_index
:
2637 sample_index
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2640 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2641 tex
->src
[i
].src_type
);
2647 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2648 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2649 case nir_texop_txl
: opc
= OPC_SAML
; break;
2650 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2651 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2652 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2654 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2655 * what blob does, seems gather is broken?), and a3xx did
2656 * not support it (but probably could also emulate).
2658 switch (tex
->component
) {
2659 case 0: opc
= OPC_GATHER4R
; break;
2660 case 1: opc
= OPC_GATHER4G
; break;
2661 case 2: opc
= OPC_GATHER4B
; break;
2662 case 3: opc
= OPC_GATHER4A
; break;
2665 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2667 case nir_texop_query_levels
:
2668 case nir_texop_texture_samples
:
2669 case nir_texop_samples_identical
:
2670 case nir_texop_txf_ms_mcs
:
2671 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2675 tex_info(tex
, &flags
, &coords
);
2678 * lay out the first argument in the proper order:
2679 * - actual coordinates first
2680 * - shadow reference
2683 * - starting at offset 4, dpdx.xy, dpdy.xy
2685 * bias/lod go into the second arg
2688 /* insert tex coords: */
2689 for (i
= 0; i
< coords
; i
++)
2694 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2695 * with scaled x coord according to requested sample:
2697 if (tex
->op
== nir_texop_txf_ms
) {
2698 if (ctx
->compiler
->txf_ms_with_isaml
) {
2699 /* the samples are laid out in x dimension as
2701 * x_ms = (x << ms) + sample_index;
2703 struct ir3_instruction
*ms
;
2704 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2706 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2707 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2711 src0
[nsrc0
++] = sample_index
;
2715 /* scale up integer coords for TXF based on the LOD */
2716 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2718 for (i
= 0; i
< coords
; i
++)
2719 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2723 /* hw doesn't do 1d, so we treat it as 2d with
2724 * height of 1, and patch up the y coord.
2725 * TODO: y coord should be (int)0 in some cases..
2727 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2730 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2731 src0
[nsrc0
++] = compare
;
2733 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2734 struct ir3_instruction
*idx
= coord
[coords
];
2736 /* the array coord for cube arrays needs 0.5 added to it */
2737 if (ctx
->compiler
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2738 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2740 src0
[nsrc0
++] = idx
;
2744 src0
[nsrc0
++] = proj
;
2745 flags
|= IR3_INSTR_P
;
2748 /* pad to 4, then ddx/ddy: */
2749 if (tex
->op
== nir_texop_txd
) {
2751 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2752 for (i
= 0; i
< coords
; i
++)
2753 src0
[nsrc0
++] = ddx
[i
];
2755 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2756 for (i
= 0; i
< coords
; i
++)
2757 src0
[nsrc0
++] = ddy
[i
];
2759 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2763 * second argument (if applicable):
2768 if (has_off
| has_lod
| has_bias
) {
2770 unsigned off_coords
= coords
;
2771 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2773 for (i
= 0; i
< off_coords
; i
++)
2774 src1
[nsrc1
++] = off
[i
];
2776 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2777 flags
|= IR3_INSTR_O
;
2780 if (has_lod
| has_bias
)
2781 src1
[nsrc1
++] = lod
;
2784 switch (tex
->dest_type
) {
2785 case nir_type_invalid
:
2786 case nir_type_float
:
2797 unreachable("bad dest_type");
2800 if (opc
== OPC_GETLOD
)
2803 unsigned tex_idx
= tex
->texture_index
;
2805 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2807 struct ir3_instruction
*col0
= create_collect(ctx
, src0
, nsrc0
);
2808 struct ir3_instruction
*col1
= create_collect(ctx
, src1
, nsrc1
);
2810 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2811 tex_idx
, tex_idx
, col0
, col1
);
2813 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2814 /* only need first 3 components: */
2815 sam
->regs
[0]->wrmask
= 0x7;
2816 split_dest(b
, dst
, sam
, 0, 3);
2818 /* we need to sample the alpha separately with a non-ASTC
2821 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2822 tex_idx
, tex_idx
, col0
, col1
);
2824 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2826 /* fixup .w component: */
2827 split_dest(b
, &dst
[3], sam
, 3, 1);
2829 /* normal (non-workaround) case: */
2830 split_dest(b
, dst
, sam
, 0, 4);
2833 /* GETLOD returns results in 4.8 fixed point */
2834 if (opc
== OPC_GETLOD
) {
2835 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2837 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2838 for (i
= 0; i
< 2; i
++) {
2839 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2844 put_dst(ctx
, &tex
->dest
);
2848 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2850 struct ir3_block
*b
= ctx
->block
;
2851 struct ir3_instruction
**dst
, *sam
;
2853 dst
= get_dst(ctx
, &tex
->dest
, 1);
2855 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2856 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2858 /* even though there is only one component, since it ends
2859 * up in .z rather than .x, we need a split_dest()
2861 split_dest(b
, dst
, sam
, 0, 3);
2863 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2864 * the value in TEX_CONST_0 is zero-based.
2866 if (ctx
->compiler
->levels_add_one
)
2867 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2869 put_dst(ctx
, &tex
->dest
);
2873 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2875 struct ir3_block
*b
= ctx
->block
;
2876 struct ir3_instruction
**dst
, *sam
;
2877 struct ir3_instruction
*lod
;
2878 unsigned flags
, coords
;
2880 tex_info(tex
, &flags
, &coords
);
2882 /* Actually we want the number of dimensions, not coordinates. This
2883 * distinction only matters for cubes.
2885 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2888 dst
= get_dst(ctx
, &tex
->dest
, 4);
2890 compile_assert(ctx
, tex
->num_srcs
== 1);
2891 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2893 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2895 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2896 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2898 split_dest(b
, dst
, sam
, 0, 4);
2900 /* Array size actually ends up in .w rather than .z. This doesn't
2901 * matter for miplevel 0, but for higher mips the value in z is
2902 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2903 * returned, which means that we have to add 1 to it for arrays.
2905 if (tex
->is_array
) {
2906 if (ctx
->compiler
->levels_add_one
) {
2907 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2909 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2913 put_dst(ctx
, &tex
->dest
);
2917 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2919 switch (jump
->type
) {
2920 case nir_jump_break
:
2921 case nir_jump_continue
:
2922 case nir_jump_return
:
2923 /* I *think* we can simply just ignore this, and use the
2924 * successor block link to figure out where we need to
2925 * jump to for break/continue
2929 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2935 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2937 switch (instr
->type
) {
2938 case nir_instr_type_alu
:
2939 emit_alu(ctx
, nir_instr_as_alu(instr
));
2941 case nir_instr_type_deref
:
2942 /* ignored, handled as part of the intrinsic they are src to */
2944 case nir_instr_type_intrinsic
:
2945 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2947 case nir_instr_type_load_const
:
2948 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2950 case nir_instr_type_ssa_undef
:
2951 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2953 case nir_instr_type_tex
: {
2954 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2955 /* couple tex instructions get special-cased:
2959 emit_tex_txs(ctx
, tex
);
2961 case nir_texop_query_levels
:
2962 emit_tex_query_levels(ctx
, tex
);
2970 case nir_instr_type_jump
:
2971 emit_jump(ctx
, nir_instr_as_jump(instr
));
2973 case nir_instr_type_phi
:
2974 /* we have converted phi webs to regs in NIR by now */
2975 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2977 case nir_instr_type_call
:
2978 case nir_instr_type_parallel_copy
:
2979 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2984 static struct ir3_block
*
2985 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2987 struct ir3_block
*block
;
2988 struct hash_entry
*hentry
;
2989 struct set_entry
*sentry
;
2992 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2994 return hentry
->data
;
2996 block
= ir3_block_create(ctx
->ir
);
2997 block
->nblock
= nblock
;
2998 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
3000 block
->predecessors_count
= nblock
->predecessors
->entries
;
3001 block
->predecessors
= ralloc_array_size(block
,
3002 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
3004 set_foreach(nblock
->predecessors
, sentry
) {
3005 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
3012 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
3014 struct ir3_block
*block
= get_block(ctx
, nblock
);
3016 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
3017 if (nblock
->successors
[i
]) {
3018 block
->successors
[i
] =
3019 get_block(ctx
, nblock
->successors
[i
]);
3024 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
3026 /* re-emit addr register in each block if needed: */
3027 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
3028 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
3029 ctx
->addr_ht
[i
] = NULL
;
3032 nir_foreach_instr(instr
, nblock
) {
3033 emit_instr(ctx
, instr
);
3039 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
3042 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
3044 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
3046 ctx
->block
->condition
=
3047 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
3049 emit_cf_list(ctx
, &nif
->then_list
);
3050 emit_cf_list(ctx
, &nif
->else_list
);
3054 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
3056 emit_cf_list(ctx
, &nloop
->body
);
3060 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
3062 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3063 switch (node
->type
) {
3064 case nir_cf_node_block
:
3065 emit_block(ctx
, nir_cf_node_as_block(node
));
3067 case nir_cf_node_if
:
3068 emit_if(ctx
, nir_cf_node_as_if(node
));
3070 case nir_cf_node_loop
:
3071 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3073 case nir_cf_node_function
:
3074 compile_error(ctx
, "TODO\n");
3080 /* emit stream-out code. At this point, the current block is the original
3081 * (nir) end block, and nir ensures that all flow control paths terminate
3082 * into the end block. We re-purpose the original end block to generate
3083 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
3084 * block holding stream-out write instructions, followed by the new end
3088 * p0.x = (vtxcnt < maxvtxcnt)
3089 * // succs: blockStreamOut, blockNewEnd
3092 * ... stream-out instructions ...
3093 * // succs: blockNewEnd
3099 emit_stream_out(struct ir3_context
*ctx
)
3101 struct ir3_shader_variant
*v
= ctx
->so
;
3102 struct ir3
*ir
= ctx
->ir
;
3103 struct pipe_stream_output_info
*strmout
=
3104 &ctx
->so
->shader
->stream_output
;
3105 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
3106 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
3107 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
3109 /* create vtxcnt input in input block at top of shader,
3110 * so that it is seen as live over the entire duration
3113 vtxcnt
= create_input(ctx
->in_block
, 0);
3114 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
3116 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
3118 /* at this point, we are at the original 'end' block,
3119 * re-purpose this block to stream-out condition, then
3120 * append stream-out block and new-end block
3122 orig_end_block
= ctx
->block
;
3124 // TODO these blocks need to update predecessors..
3125 // maybe w/ store_global intrinsic, we could do this
3126 // stuff in nir->nir pass
3128 stream_out_block
= ir3_block_create(ir
);
3129 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
3131 new_end_block
= ir3_block_create(ir
);
3132 list_addtail(&new_end_block
->node
, &ir
->block_list
);
3134 orig_end_block
->successors
[0] = stream_out_block
;
3135 orig_end_block
->successors
[1] = new_end_block
;
3136 stream_out_block
->successors
[0] = new_end_block
;
3138 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
3139 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
3140 cond
->regs
[0]->num
= regid(REG_P0
, 0);
3141 cond
->cat2
.condition
= IR3_COND_LT
;
3143 /* condition goes on previous block to the conditional,
3144 * since it is used to pick which of the two successor
3147 orig_end_block
->condition
= cond
;
3149 /* switch to stream_out_block to generate the stream-out
3152 ctx
->block
= stream_out_block
;
3154 /* Calculate base addresses based on vtxcnt. Instructions
3155 * generated for bases not used in following loop will be
3156 * stripped out in the backend.
3158 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3159 unsigned stride
= strmout
->stride
[i
];
3160 struct ir3_instruction
*base
, *off
;
3162 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
3164 /* 24-bit should be enough: */
3165 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
3166 create_immed(ctx
->block
, stride
* 4), 0);
3168 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
3171 /* Generate the per-output store instructions: */
3172 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
3173 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
3174 unsigned c
= j
+ strmout
->output
[i
].start_component
;
3175 struct ir3_instruction
*base
, *out
, *stg
;
3177 base
= bases
[strmout
->output
[i
].output_buffer
];
3178 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
3180 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
3181 create_immed(ctx
->block
, 1), 0);
3182 stg
->cat6
.type
= TYPE_U32
;
3183 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
3185 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
3189 /* and finally switch to the new_end_block: */
3190 ctx
->block
= new_end_block
;
3194 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
3196 nir_metadata_require(impl
, nir_metadata_block_index
);
3198 emit_cf_list(ctx
, &impl
->body
);
3199 emit_block(ctx
, impl
->end_block
);
3201 /* at this point, we should have a single empty block,
3202 * into which we emit the 'end' instruction.
3204 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
3206 /* If stream-out (aka transform-feedback) enabled, emit the
3207 * stream-out instructions, followed by a new empty block (into
3208 * which the 'end' instruction lands).
3210 * NOTE: it is done in this order, rather than inserting before
3211 * we emit end_block, because NIR guarantees that all blocks
3212 * flow into end_block, and that end_block has no successors.
3213 * So by re-purposing end_block as the first block of stream-
3214 * out, we guarantee that all exit paths flow into the stream-
3217 if ((ctx
->compiler
->gpu_id
< 500) &&
3218 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
3219 !ctx
->so
->key
.binning_pass
) {
3220 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
3221 emit_stream_out(ctx
);
3224 ir3_END(ctx
->block
);
3228 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
3230 struct ir3_shader_variant
*so
= ctx
->so
;
3231 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
3232 unsigned ncomp
= glsl_get_components(in
->type
);
3233 unsigned n
= in
->data
.driver_location
;
3234 unsigned slot
= in
->data
.location
;
3236 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
3237 slot
, array_len
, ncomp
, n
);
3239 /* let's pretend things other than vec4 don't exist: */
3240 ncomp
= MAX2(ncomp
, 4);
3241 compile_assert(ctx
, ncomp
== 4);
3243 so
->inputs
[n
].slot
= slot
;
3244 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
3245 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
3246 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
3248 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3249 for (int i
= 0; i
< ncomp
; i
++) {
3250 struct ir3_instruction
*instr
= NULL
;
3251 unsigned idx
= (n
* 4) + i
;
3253 if (slot
== VARYING_SLOT_POS
) {
3254 so
->inputs
[n
].bary
= false;
3255 so
->frag_coord
= true;
3256 instr
= create_frag_coord(ctx
, i
);
3257 } else if (slot
== VARYING_SLOT_PNTC
) {
3258 /* see for example st_get_generic_varying_index().. this is
3259 * maybe a bit mesa/st specific. But we need things to line
3260 * up for this in fdN_program:
3261 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
3262 * if (emit->sprite_coord_enable & texmask) {
3266 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
3267 so
->inputs
[n
].bary
= true;
3268 instr
= create_frag_input(ctx
, false);
3270 bool use_ldlv
= false;
3272 /* detect the special case for front/back colors where
3273 * we need to do flat vs smooth shading depending on
3276 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3278 case VARYING_SLOT_COL0
:
3279 case VARYING_SLOT_COL1
:
3280 case VARYING_SLOT_BFC0
:
3281 case VARYING_SLOT_BFC1
:
3282 so
->inputs
[n
].rasterflat
= true;
3289 if (ctx
->compiler
->flat_bypass
) {
3290 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3291 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3295 so
->inputs
[n
].bary
= true;
3297 instr
= create_frag_input(ctx
, use_ldlv
);
3300 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3302 ctx
->ir
->inputs
[idx
] = instr
;
3304 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3305 for (int i
= 0; i
< ncomp
; i
++) {
3306 unsigned idx
= (n
* 4) + i
;
3307 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3308 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
3311 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3314 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3315 so
->total_in
+= ncomp
;
3320 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3322 struct ir3_shader_variant
*so
= ctx
->so
;
3323 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3324 unsigned ncomp
= glsl_get_components(out
->type
);
3325 unsigned n
= out
->data
.driver_location
;
3326 unsigned slot
= out
->data
.location
;
3329 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3330 slot
, array_len
, ncomp
, n
);
3332 /* let's pretend things other than vec4 don't exist: */
3333 ncomp
= MAX2(ncomp
, 4);
3334 compile_assert(ctx
, ncomp
== 4);
3336 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3338 case FRAG_RESULT_DEPTH
:
3339 comp
= 2; /* tgsi will write to .z component */
3340 so
->writes_pos
= true;
3342 case FRAG_RESULT_COLOR
:
3346 if (slot
>= FRAG_RESULT_DATA0
)
3348 compile_error(ctx
, "unknown FS output name: %s\n",
3349 gl_frag_result_name(slot
));
3351 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3353 case VARYING_SLOT_POS
:
3354 so
->writes_pos
= true;
3356 case VARYING_SLOT_PSIZ
:
3357 so
->writes_psize
= true;
3359 case VARYING_SLOT_COL0
:
3360 case VARYING_SLOT_COL1
:
3361 case VARYING_SLOT_BFC0
:
3362 case VARYING_SLOT_BFC1
:
3363 case VARYING_SLOT_FOGC
:
3364 case VARYING_SLOT_CLIP_DIST0
:
3365 case VARYING_SLOT_CLIP_DIST1
:
3366 case VARYING_SLOT_CLIP_VERTEX
:
3369 if (slot
>= VARYING_SLOT_VAR0
)
3371 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3373 compile_error(ctx
, "unknown VS output name: %s\n",
3374 gl_varying_slot_name(slot
));
3377 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3380 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3382 so
->outputs
[n
].slot
= slot
;
3383 so
->outputs
[n
].regid
= regid(n
, comp
);
3384 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3386 for (int i
= 0; i
< ncomp
; i
++) {
3387 unsigned idx
= (n
* 4) + i
;
3388 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3389 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3394 max_drvloc(struct exec_list
*vars
)
3397 nir_foreach_variable(var
, vars
) {
3398 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3403 static const unsigned max_sysvals
[SHADER_MAX
] = {
3404 [SHADER_FRAGMENT
] = 8,
3405 [SHADER_VERTEX
] = 16,
3406 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3410 emit_instructions(struct ir3_context
*ctx
)
3412 unsigned ninputs
, noutputs
;
3413 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3415 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3416 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3418 /* we need to leave room for sysvals:
3420 ninputs
+= max_sysvals
[ctx
->so
->type
];
3422 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3424 /* Create inputs in first block: */
3425 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3426 ctx
->in_block
= ctx
->block
;
3427 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3429 ninputs
-= max_sysvals
[ctx
->so
->type
];
3431 /* for fragment shader, we have a single input register (usually
3432 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3434 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3435 // TODO maybe a helper for fi since we need it a few places..
3436 struct ir3_instruction
*instr
;
3437 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3438 ir3_reg_create(instr
, 0, 0);
3439 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3440 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3441 ctx
->frag_pos
= instr
;
3445 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3446 setup_input(ctx
, var
);
3449 /* Setup outputs: */
3450 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3451 setup_output(ctx
, var
);
3454 /* Setup registers (which should only be arrays): */
3455 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3456 declare_array(ctx
, reg
);
3459 /* NOTE: need to do something more clever when we support >1 fxn */
3460 nir_foreach_register(reg
, &fxn
->registers
) {
3461 declare_array(ctx
, reg
);
3463 /* And emit the body: */
3465 emit_function(ctx
, fxn
);
3468 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3469 * for a fragment shader are just bary.f instructions. The *actual* inputs
3470 * from the hw perspective are the frag_pos and optionally frag_coord and
3474 fixup_frag_inputs(struct ir3_context
*ctx
)
3476 struct ir3_shader_variant
*so
= ctx
->so
;
3477 struct ir3
*ir
= ctx
->ir
;
3478 struct ir3_instruction
**inputs
;
3479 struct ir3_instruction
*instr
;
3484 n
= 4; /* always have frag_pos */
3485 n
+= COND(so
->frag_face
, 4);
3486 n
+= COND(so
->frag_coord
, 4);
3488 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3490 if (so
->frag_face
) {
3491 /* this ultimately gets assigned to hr0.x so doesn't conflict
3492 * with frag_coord/frag_pos..
3494 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3495 ctx
->frag_face
->regs
[0]->num
= 0;
3497 /* remaining channels not used, but let's avoid confusing
3498 * other parts that expect inputs to come in groups of vec4
3500 inputs
[ir
->ninputs
++] = NULL
;
3501 inputs
[ir
->ninputs
++] = NULL
;
3502 inputs
[ir
->ninputs
++] = NULL
;
3505 /* since we don't know where to set the regid for frag_coord,
3506 * we have to use r0.x for it. But we don't want to *always*
3507 * use r1.x for frag_pos as that could increase the register
3508 * footprint on simple shaders:
3510 if (so
->frag_coord
) {
3511 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3512 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3513 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3514 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3516 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3517 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3518 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3519 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3522 /* we always have frag_pos: */
3523 so
->pos_regid
= regid
;
3526 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3527 instr
->regs
[0]->num
= regid
++;
3528 inputs
[ir
->ninputs
++] = instr
;
3529 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3532 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3533 instr
->regs
[0]->num
= regid
++;
3534 inputs
[ir
->ninputs
++] = instr
;
3535 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3537 ir
->inputs
= inputs
;
3540 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3541 * need to assign the tex state indexes for these after we know the
3545 fixup_astc_srgb(struct ir3_context
*ctx
)
3547 struct ir3_shader_variant
*so
= ctx
->so
;
3548 /* indexed by original tex idx, value is newly assigned alpha sampler
3549 * state tex idx. Zero is invalid since there is at least one sampler
3552 unsigned alt_tex_state
[16] = {0};
3553 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3556 so
->astc_srgb
.base
= tex_idx
;
3558 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3559 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3561 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3563 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3564 /* assign new alternate/alpha tex state slot: */
3565 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3566 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3567 so
->astc_srgb
.count
++;
3570 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3575 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3576 struct ir3_shader_variant
*so
)
3578 struct ir3_context
*ctx
;
3580 struct ir3_instruction
**inputs
;
3581 unsigned i
, j
, actual_in
, inloc
;
3582 int ret
= 0, max_bary
;
3586 ctx
= compile_init(compiler
, so
);
3588 DBG("INIT failed!");
3593 emit_instructions(ctx
);
3596 DBG("EMIT failed!");
3601 ir
= so
->ir
= ctx
->ir
;
3603 /* keep track of the inputs from TGSI perspective.. */
3604 inputs
= ir
->inputs
;
3606 /* but fixup actual inputs for frag shader: */
3607 if (so
->type
== SHADER_FRAGMENT
)
3608 fixup_frag_inputs(ctx
);
3610 /* at this point, for binning pass, throw away unneeded outputs: */
3611 if (so
->key
.binning_pass
) {
3612 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3613 unsigned slot
= so
->outputs
[i
].slot
;
3615 /* throw away everything but first position/psize */
3616 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3618 so
->outputs
[j
] = so
->outputs
[i
];
3619 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3620 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3621 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3622 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3627 so
->outputs_count
= j
;
3628 ir
->noutputs
= j
* 4;
3631 /* if we want half-precision outputs, mark the output registers
3634 if (so
->key
.half_precision
) {
3635 for (i
= 0; i
< ir
->noutputs
; i
++) {
3636 struct ir3_instruction
*out
= ir
->outputs
[i
];
3641 /* if frag shader writes z, that needs to be full precision: */
3642 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3645 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3646 /* output could be a fanout (ie. texture fetch output)
3647 * in which case we need to propagate the half-reg flag
3648 * up to the definer so that RA sees it:
3650 if (out
->opc
== OPC_META_FO
) {
3651 out
= out
->regs
[1]->instr
;
3652 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3655 if (out
->opc
== OPC_MOV
) {
3656 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3661 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3662 printf("BEFORE CP:\n");
3668 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3669 printf("BEFORE GROUPING:\n");
3673 ir3_sched_add_deps(ir
);
3675 /* Group left/right neighbors, inserting mov's where needed to
3680 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3681 printf("AFTER GROUPING:\n");
3687 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3688 printf("AFTER DEPTH:\n");
3692 ret
= ir3_sched(ir
);
3694 DBG("SCHED failed!");
3698 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3699 printf("AFTER SCHED:\n");
3703 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3709 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3710 printf("AFTER RA:\n");
3714 /* fixup input/outputs: */
3715 for (i
= 0; i
< so
->outputs_count
; i
++) {
3716 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3719 /* Note that some or all channels of an input may be unused: */
3722 for (i
= 0; i
< so
->inputs_count
; i
++) {
3723 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3724 so
->inputs
[i
].ncomp
= 0;
3725 so
->inputs
[i
].inloc
= inloc
;
3726 for (j
= 0; j
< 4; j
++) {
3727 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3728 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3729 compmask
|= (1 << j
);
3730 regid
= in
->regs
[0]->num
- j
;
3732 so
->inputs
[i
].ncomp
++;
3733 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3735 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3736 in
->regs
[1]->iim_val
= inloc
+ j
;
3741 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3743 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3745 } else if (!so
->inputs
[i
].sysval
) {
3746 so
->inputs
[i
].compmask
= compmask
;
3748 so
->inputs
[i
].regid
= regid
;
3752 fixup_astc_srgb(ctx
);
3754 /* We need to do legalize after (for frag shader's) the "bary.f"
3755 * offsets (inloc) have been assigned.
3757 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3759 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3760 printf("AFTER LEGALIZE:\n");
3764 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3765 if (so
->type
== SHADER_VERTEX
)
3766 so
->total_in
= actual_in
;
3768 so
->total_in
= max_bary
+ 1;
3773 ir3_destroy(so
->ir
);