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freedreno/ir3/nir: couple little fixes
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_compiler_nir.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include <stdarg.h>
30
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
37
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
40
41 #include "freedreno_util.h"
42
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
45
46 #include "instr-a3xx.h"
47 #include "ir3.h"
48
49
50 static struct ir3_instruction * create_immed(struct ir3_block *block, uint32_t val);
51
52 struct ir3_compile {
53 const struct tgsi_token *tokens;
54 struct nir_shader *s;
55
56 struct ir3 *ir;
57 struct ir3_shader_variant *so;
58
59 /* bitmask of which samplers are integer: */
60 uint16_t integer_s;
61
62 struct ir3_block *block;
63
64 /* For fragment shaders, from the hw perspective the only
65 * actual input is r0.xy position register passed to bary.f.
66 * But TGSI doesn't know that, it still declares things as
67 * IN[] registers. So we do all the input tracking normally
68 * and fix things up after compile_instructions()
69 *
70 * NOTE that frag_pos is the hardware position (possibly it
71 * is actually an index or tag or some such.. it is *not*
72 * values that can be directly used for gl_FragCoord..)
73 */
74 struct ir3_instruction *frag_pos, *frag_face, *frag_coord[4];
75
76 /* For vertex shaders, keep track of the system values sources */
77 struct ir3_instruction *vertex_id, *basevertex, *instance_id;
78
79 /* mapping from nir_register to defining instruction: */
80 struct hash_table *def_ht;
81
82 /* mapping from nir_variable to ir3_array: */
83 struct hash_table *var_ht;
84 unsigned num_arrays;
85
86 /* a common pattern for indirect addressing is to request the
87 * same address register multiple times. To avoid generating
88 * duplicate instruction sequences (which our backend does not
89 * try to clean up, since that should be done as the NIR stage)
90 * we cache the address value generated for a given src value:
91 */
92 struct hash_table *addr_ht;
93
94 /* for calculating input/output positions/linkages: */
95 unsigned next_inloc;
96
97 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
98 * so we need to use ldlv.u32 to load the varying directly:
99 */
100 bool flat_bypass;
101
102 /* on a3xx, we need to add one to # of array levels:
103 */
104 bool levels_add_one;
105
106 /* for looking up which system value is which */
107 unsigned sysval_semantics[8];
108
109 /* list of kill instructions: */
110 struct ir3_instruction *kill[16];
111 unsigned int kill_count;
112
113 /* set if we encounter something we can't handle yet, so we
114 * can bail cleanly and fallback to TGSI compiler f/e
115 */
116 bool error;
117 };
118
119
120 static struct nir_shader *to_nir(const struct tgsi_token *tokens)
121 {
122 struct nir_shader_compiler_options options = {
123 .lower_fpow = true,
124 .lower_fsat = true,
125 .lower_scmp = true,
126 .lower_flrp = true,
127 .native_integers = true,
128 };
129 bool progress;
130
131 struct nir_shader *s = tgsi_to_nir(tokens, &options);
132
133 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
134 debug_printf("----------------------\n");
135 nir_print_shader(s, stdout);
136 debug_printf("----------------------\n");
137 }
138
139 nir_opt_global_to_local(s);
140 nir_convert_to_ssa(s);
141 nir_lower_idiv(s);
142
143 do {
144 progress = false;
145
146 nir_lower_vars_to_ssa(s);
147 nir_lower_alu_to_scalar(s);
148
149 progress |= nir_copy_prop(s);
150 progress |= nir_opt_dce(s);
151 progress |= nir_opt_cse(s);
152 progress |= nir_opt_peephole_select(s);
153 progress |= nir_opt_algebraic(s);
154 progress |= nir_opt_constant_folding(s);
155
156 } while (progress);
157
158 nir_remove_dead_variables(s);
159 nir_validate_shader(s);
160
161 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
162 debug_printf("----------------------\n");
163 nir_print_shader(s, stdout);
164 debug_printf("----------------------\n");
165 }
166
167 return s;
168 }
169
170 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
171 static const struct tgsi_token *
172 lower_tgsi(const struct tgsi_token *tokens, struct ir3_shader_variant *so)
173 {
174 struct tgsi_shader_info info;
175 struct tgsi_lowering_config lconfig = {
176 .color_two_side = so->key.color_two_side,
177 .lower_FRC = true,
178 };
179
180 switch (so->type) {
181 case SHADER_FRAGMENT:
182 case SHADER_COMPUTE:
183 lconfig.saturate_s = so->key.fsaturate_s;
184 lconfig.saturate_t = so->key.fsaturate_t;
185 lconfig.saturate_r = so->key.fsaturate_r;
186 break;
187 case SHADER_VERTEX:
188 lconfig.saturate_s = so->key.vsaturate_s;
189 lconfig.saturate_t = so->key.vsaturate_t;
190 lconfig.saturate_r = so->key.vsaturate_r;
191 break;
192 }
193
194 if (!so->shader) {
195 /* hack for standalone compiler which does not have
196 * screen/context:
197 */
198 } else if (ir3_shader_gpuid(so->shader) >= 400) {
199 /* a4xx seems to have *no* sam.p */
200 lconfig.lower_TXP = ~0; /* lower all txp */
201 } else {
202 /* a3xx just needs to avoid sam.p for 3d tex */
203 lconfig.lower_TXP = (1 << TGSI_TEXTURE_3D);
204 }
205
206 return tgsi_transform_lowering(&lconfig, tokens, &info);
207 }
208
209 static struct ir3_compile *
210 compile_init(struct ir3_shader_variant *so,
211 const struct tgsi_token *tokens)
212 {
213 struct ir3_compile *ctx = rzalloc(NULL, struct ir3_compile);
214 const struct tgsi_token *lowered_tokens;
215
216 if (!so->shader) {
217 /* hack for standalone compiler which does not have
218 * screen/context:
219 */
220 } else if (ir3_shader_gpuid(so->shader) >= 400) {
221 /* need special handling for "flat" */
222 ctx->flat_bypass = true;
223 ctx->levels_add_one = false;
224 } else {
225 /* no special handling for "flat" */
226 ctx->flat_bypass = false;
227 ctx->levels_add_one = true;
228 }
229
230 switch (so->type) {
231 case SHADER_FRAGMENT:
232 case SHADER_COMPUTE:
233 ctx->integer_s = so->key.finteger_s;
234 break;
235 case SHADER_VERTEX:
236 ctx->integer_s = so->key.vinteger_s;
237 break;
238 }
239
240 ctx->ir = so->ir;
241 ctx->so = so;
242 ctx->next_inloc = 8;
243 ctx->def_ht = _mesa_hash_table_create(ctx,
244 _mesa_hash_pointer, _mesa_key_pointer_equal);
245 ctx->var_ht = _mesa_hash_table_create(ctx,
246 _mesa_hash_pointer, _mesa_key_pointer_equal);
247 ctx->addr_ht = _mesa_hash_table_create(ctx,
248 _mesa_hash_pointer, _mesa_key_pointer_equal);
249
250 lowered_tokens = lower_tgsi(tokens, so);
251 if (!lowered_tokens)
252 lowered_tokens = tokens;
253 ctx->s = to_nir(lowered_tokens);
254
255 if (lowered_tokens != tokens)
256 free((void *)lowered_tokens);
257
258 so->first_driver_param = so->first_immediate = ctx->s->num_uniforms;
259
260 /* one (vec4) slot for vertex id base: */
261 if (so->type == SHADER_VERTEX)
262 so->first_immediate++;
263
264 /* reserve 4 (vec4) slots for ubo base addresses: */
265 so->first_immediate += 4;
266
267 return ctx;
268 }
269
270 static void
271 compile_error(struct ir3_compile *ctx, const char *format, ...)
272 {
273 va_list ap;
274 va_start(ap, format);
275 _debug_vprintf(format, ap);
276 va_end(ap);
277 nir_print_shader(ctx->s, stdout);
278 ctx->error = true;
279 debug_assert(0);
280 }
281
282 #define compile_assert(ctx, cond) do { \
283 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
284 } while (0)
285
286 static void
287 compile_free(struct ir3_compile *ctx)
288 {
289 ralloc_free(ctx);
290 }
291
292
293 struct ir3_array {
294 unsigned length, aid;
295 struct ir3_instruction *arr[];
296 };
297
298 static void
299 declare_var(struct ir3_compile *ctx, nir_variable *var)
300 {
301 unsigned length = glsl_get_length(var->type) * 4; /* always vec4, at least with ttn */
302 struct ir3_array *arr = ralloc_size(ctx, sizeof(*arr) +
303 (length * sizeof(arr->arr[0])));
304 arr->length = length;
305 arr->aid = ++ctx->num_arrays;
306 /* Some shaders end up reading array elements without first writing..
307 * so initialize things to prevent null instr ptrs later:
308 */
309 for (unsigned i = 0; i < length; i++)
310 arr->arr[i] = create_immed(ctx->block, 0);
311 _mesa_hash_table_insert(ctx->var_ht, var, arr);
312 }
313
314 static struct ir3_array *
315 get_var(struct ir3_compile *ctx, nir_variable *var)
316 {
317 struct hash_entry *entry = _mesa_hash_table_search(ctx->var_ht, var);
318 return entry->data;
319 }
320
321 /* allocate a n element value array (to be populated by caller) and
322 * insert in def_ht
323 */
324 static struct ir3_instruction **
325 __get_dst(struct ir3_compile *ctx, void *key, unsigned n)
326 {
327 struct ir3_instruction **value =
328 ralloc_array(ctx->def_ht, struct ir3_instruction *, n);
329 _mesa_hash_table_insert(ctx->def_ht, key, value);
330 return value;
331 }
332
333 static struct ir3_instruction **
334 get_dst(struct ir3_compile *ctx, nir_dest *dst, unsigned n)
335 {
336 if (dst->is_ssa) {
337 return __get_dst(ctx, &dst->ssa, n);
338 } else {
339 return __get_dst(ctx, dst->reg.reg, n);
340 }
341 }
342
343 static struct ir3_instruction **
344 get_dst_ssa(struct ir3_compile *ctx, nir_ssa_def *dst, unsigned n)
345 {
346 return __get_dst(ctx, dst, n);
347 }
348
349 static struct ir3_instruction **
350 get_src(struct ir3_compile *ctx, nir_src *src)
351 {
352 struct hash_entry *entry;
353 if (src->is_ssa) {
354 entry = _mesa_hash_table_search(ctx->def_ht, src->ssa);
355 } else {
356 entry = _mesa_hash_table_search(ctx->def_ht, src->reg.reg);
357 }
358 compile_assert(ctx, entry);
359 return entry->data;
360 }
361
362 static struct ir3_instruction *
363 create_immed(struct ir3_block *block, uint32_t val)
364 {
365 struct ir3_instruction *mov;
366
367 mov = ir3_instr_create(block, 1, 0);
368 mov->cat1.src_type = TYPE_U32;
369 mov->cat1.dst_type = TYPE_U32;
370 ir3_reg_create(mov, 0, 0);
371 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
372
373 return mov;
374 }
375
376 static struct ir3_instruction *
377 create_addr(struct ir3_block *block, struct ir3_instruction *src)
378 {
379 struct ir3_instruction *instr, *immed;
380
381 /* TODO in at least some cases, the backend could probably be
382 * made clever enough to propagate IR3_REG_HALF..
383 */
384 instr = ir3_COV(block, src, TYPE_U32, TYPE_S16);
385 instr->regs[0]->flags |= IR3_REG_HALF;
386
387 immed = create_immed(block, 2);
388 immed->regs[0]->flags |= IR3_REG_HALF;
389
390 instr = ir3_SHL_B(block, instr, 0, immed, 0);
391 instr->regs[0]->flags |= IR3_REG_HALF;
392 instr->regs[1]->flags |= IR3_REG_HALF;
393
394 instr = ir3_MOV(block, instr, TYPE_S16);
395 instr->regs[0]->flags |= IR3_REG_ADDR | IR3_REG_HALF;
396 instr->regs[1]->flags |= IR3_REG_HALF;
397
398 return instr;
399 }
400
401 /* caches addr values to avoid generating multiple cov/shl/mova
402 * sequences for each use of a given NIR level src as address
403 */
404 static struct ir3_instruction *
405 get_addr(struct ir3_compile *ctx, struct ir3_instruction *src)
406 {
407 struct ir3_instruction *addr;
408 struct hash_entry *entry;
409 entry = _mesa_hash_table_search(ctx->addr_ht, src);
410 if (entry)
411 return entry->data;
412
413 /* TODO do we need to cache per block? */
414 addr = create_addr(ctx->block, src);
415 _mesa_hash_table_insert(ctx->addr_ht, src, addr);
416
417 return addr;
418 }
419
420 static struct ir3_instruction *
421 create_uniform(struct ir3_compile *ctx, unsigned n)
422 {
423 struct ir3_instruction *mov;
424
425 mov = ir3_instr_create(ctx->block, 1, 0);
426 /* TODO get types right? */
427 mov->cat1.src_type = TYPE_F32;
428 mov->cat1.dst_type = TYPE_F32;
429 ir3_reg_create(mov, 0, 0);
430 ir3_reg_create(mov, n, IR3_REG_CONST);
431
432 return mov;
433 }
434
435 static struct ir3_instruction *
436 create_uniform_indirect(struct ir3_compile *ctx, unsigned n,
437 struct ir3_instruction *address)
438 {
439 struct ir3_instruction *mov;
440
441 mov = ir3_instr_create(ctx->block, 1, 0);
442 mov->cat1.src_type = TYPE_U32;
443 mov->cat1.dst_type = TYPE_U32;
444 ir3_reg_create(mov, 0, 0);
445 ir3_reg_create(mov, n, IR3_REG_CONST | IR3_REG_RELATIV);
446 mov->address = address;
447
448 array_insert(ctx->ir->indirects, mov);
449
450 return mov;
451 }
452
453 static struct ir3_instruction *
454 create_collect(struct ir3_block *block, struct ir3_instruction **arr,
455 unsigned arrsz)
456 {
457 struct ir3_instruction *collect;
458
459 if (arrsz == 0)
460 return NULL;
461
462 collect = ir3_instr_create2(block, -1, OPC_META_FI, 1 + arrsz);
463 ir3_reg_create(collect, 0, 0);
464 for (unsigned i = 0; i < arrsz; i++)
465 ir3_reg_create(collect, 0, IR3_REG_SSA)->instr = arr[i];
466
467 return collect;
468 }
469
470 static struct ir3_instruction *
471 create_indirect_load(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
472 struct ir3_instruction *address, struct ir3_instruction *collect)
473 {
474 struct ir3_block *block = ctx->block;
475 struct ir3_instruction *mov;
476 struct ir3_register *src;
477
478 mov = ir3_instr_create(block, 1, 0);
479 mov->cat1.src_type = TYPE_U32;
480 mov->cat1.dst_type = TYPE_U32;
481 ir3_reg_create(mov, 0, 0);
482 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
483 src->instr = collect;
484 src->size = arrsz;
485 src->offset = n;
486 mov->address = address;
487
488 array_insert(ctx->ir->indirects, mov);
489
490 return mov;
491 }
492
493 static struct ir3_instruction *
494 create_indirect_store(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
495 struct ir3_instruction *src, struct ir3_instruction *address,
496 struct ir3_instruction *collect)
497 {
498 struct ir3_block *block = ctx->block;
499 struct ir3_instruction *mov;
500 struct ir3_register *dst;
501
502 mov = ir3_instr_create(block, 1, 0);
503 mov->cat1.src_type = TYPE_U32;
504 mov->cat1.dst_type = TYPE_U32;
505 dst = ir3_reg_create(mov, 0, IR3_REG_RELATIV);
506 dst->size = arrsz;
507 dst->offset = n;
508 ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src;
509 mov->address = address;
510 mov->fanin = collect;
511
512 array_insert(ctx->ir->indirects, mov);
513
514 return mov;
515 }
516
517 static struct ir3_instruction *
518 create_input(struct ir3_block *block, struct ir3_instruction *instr,
519 unsigned n)
520 {
521 struct ir3_instruction *in;
522
523 in = ir3_instr_create(block, -1, OPC_META_INPUT);
524 in->inout.block = block;
525 ir3_reg_create(in, n, 0);
526 if (instr)
527 ir3_reg_create(in, 0, IR3_REG_SSA)->instr = instr;
528
529 return in;
530 }
531
532 static struct ir3_instruction *
533 create_frag_input(struct ir3_compile *ctx, unsigned n, bool use_ldlv)
534 {
535 struct ir3_block *block = ctx->block;
536 struct ir3_instruction *instr;
537 struct ir3_instruction *inloc = create_immed(block, n);
538
539 if (use_ldlv) {
540 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
541 instr->cat6.type = TYPE_U32;
542 instr->cat6.iim_val = 1;
543 } else {
544 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_pos, 0);
545 instr->regs[2]->wrmask = 0x3;
546 }
547
548 return instr;
549 }
550
551 static struct ir3_instruction *
552 create_frag_coord(struct ir3_compile *ctx, unsigned comp)
553 {
554 struct ir3_block *block = ctx->block;
555 struct ir3_instruction *instr;
556
557 compile_assert(ctx, !ctx->frag_coord[comp]);
558
559 ctx->frag_coord[comp] = create_input(ctx->block, NULL, 0);
560
561 switch (comp) {
562 case 0: /* .x */
563 case 1: /* .y */
564 /* for frag_coord, we get unsigned values.. we need
565 * to subtract (integer) 8 and divide by 16 (right-
566 * shift by 4) then convert to float:
567 *
568 * add.s tmp, src, -8
569 * shr.b tmp, tmp, 4
570 * mov.u32f32 dst, tmp
571 *
572 */
573 instr = ir3_ADD_S(block, ctx->frag_coord[comp], 0,
574 create_immed(block, -8), 0);
575 instr = ir3_SHR_B(block, instr, 0,
576 create_immed(block, 4), 0);
577 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
578
579 return instr;
580 case 2: /* .z */
581 case 3: /* .w */
582 default:
583 /* seems that we can use these as-is: */
584 return ctx->frag_coord[comp];
585 }
586 }
587
588 static struct ir3_instruction *
589 create_frag_face(struct ir3_compile *ctx, unsigned comp)
590 {
591 struct ir3_block *block = ctx->block;
592 struct ir3_instruction *instr;
593
594 switch (comp) {
595 case 0: /* .x */
596 compile_assert(ctx, !ctx->frag_face);
597
598 ctx->frag_face = create_input(block, NULL, 0);
599
600 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
601 * positive vs negative float.. and piglit further seems to
602 * expect -1.0 or 1.0:
603 *
604 * mul.s tmp, hr0.x, 2
605 * add.s tmp, tmp, 1
606 * mov.s32f32, dst, tmp
607 *
608 */
609 instr = ir3_MUL_S(block, ctx->frag_face, 0,
610 create_immed(block, 2), 0);
611 instr = ir3_ADD_S(block, instr, 0,
612 create_immed(block, 1), 0);
613 instr = ir3_COV(block, instr, TYPE_S32, TYPE_F32);
614
615 return instr;
616 case 1: /* .y */
617 case 2: /* .z */
618 return create_immed(block, fui(0.0));
619 default:
620 case 3: /* .w */
621 return create_immed(block, fui(1.0));
622 }
623 }
624
625 /* helper for instructions that produce multiple consecutive scalar
626 * outputs which need to have a split/fanout meta instruction inserted
627 */
628 static void
629 split_dest(struct ir3_block *block, struct ir3_instruction **dst,
630 struct ir3_instruction *src)
631 {
632 struct ir3_instruction *prev = NULL;
633 for (int i = 0, j = 0; i < 4; i++) {
634 struct ir3_instruction *split =
635 ir3_instr_create(block, -1, OPC_META_FO);
636 ir3_reg_create(split, 0, IR3_REG_SSA);
637 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = src;
638 split->fo.off = i;
639
640 if (prev) {
641 split->cp.left = prev;
642 split->cp.left_cnt++;
643 prev->cp.right = split;
644 prev->cp.right_cnt++;
645 }
646 prev = split;
647
648 if (src->regs[0]->wrmask & (1 << i))
649 dst[j++] = split;
650 }
651 }
652
653 /*
654 * Adreno uses uint rather than having dedicated bool type,
655 * which (potentially) requires some conversion, in particular
656 * when using output of an bool instr to int input, or visa
657 * versa.
658 *
659 * | Adreno | NIR |
660 * -------+---------+-------+-
661 * true | 1 | ~0 |
662 * false | 0 | 0 |
663 *
664 * To convert from an adreno bool (uint) to nir, use:
665 *
666 * absneg.s dst, (neg)src
667 *
668 * To convert back in the other direction:
669 *
670 * absneg.s dst, (abs)arc
671 *
672 * The CP step can clean up the absneg.s that cancel each other
673 * out, and with a slight bit of extra cleverness (to recognize
674 * the instructions which produce either a 0 or 1) can eliminate
675 * the absneg.s's completely when an instruction that wants
676 * 0/1 consumes the result. For example, when a nir 'bcsel'
677 * consumes the result of 'feq'. So we should be able to get by
678 * without a boolean resolve step, and without incuring any
679 * extra penalty in instruction count.
680 */
681
682 /* NIR bool -> native (adreno): */
683 static struct ir3_instruction *
684 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
685 {
686 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
687 }
688
689 /* native (adreno) -> NIR bool: */
690 static struct ir3_instruction *
691 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
692 {
693 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
694 }
695
696 /*
697 * alu/sfu instructions:
698 */
699
700 static void
701 emit_alu(struct ir3_compile *ctx, nir_alu_instr *alu)
702 {
703 const nir_op_info *info = &nir_op_infos[alu->op];
704 struct ir3_instruction **dst, *src[info->num_inputs];
705 struct ir3_block *b = ctx->block;
706
707 dst = get_dst(ctx, &alu->dest.dest, MAX2(info->output_size, 1));
708
709 /* Vectors are special in that they have non-scalarized writemasks,
710 * and just take the first swizzle channel for each argument in
711 * order into each writemask channel.
712 */
713 if ((alu->op == nir_op_vec2) ||
714 (alu->op == nir_op_vec3) ||
715 (alu->op == nir_op_vec4)) {
716
717 for (int i = 0; i < info->num_inputs; i++) {
718 nir_alu_src *asrc = &alu->src[i];
719
720 compile_assert(ctx, !asrc->abs);
721 compile_assert(ctx, !asrc->negate);
722
723 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[0]];
724 if (!src[i])
725 src[i] = create_immed(ctx->block, 0);
726 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
727 }
728
729 return;
730 }
731
732 /* General case: We can just grab the one used channel per src. */
733 for (int i = 0; i < info->num_inputs; i++) {
734 unsigned chan = ffs(alu->dest.write_mask) - 1;
735 nir_alu_src *asrc = &alu->src[i];
736
737 compile_assert(ctx, !asrc->abs);
738 compile_assert(ctx, !asrc->negate);
739
740 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
741
742 compile_assert(ctx, src[i]);
743 }
744
745 switch (alu->op) {
746 case nir_op_f2i:
747 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_S32);
748 break;
749 case nir_op_f2u:
750 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_U32);
751 break;
752 case nir_op_i2f:
753 dst[0] = ir3_COV(b, src[0], TYPE_S32, TYPE_F32);
754 break;
755 case nir_op_u2f:
756 dst[0] = ir3_COV(b, src[0], TYPE_U32, TYPE_F32);
757 break;
758 case nir_op_imov:
759 dst[0] = ir3_MOV(b, src[0], TYPE_S32);
760 break;
761 case nir_op_fmov:
762 dst[0] = ir3_MOV(b, src[0], TYPE_F32);
763 break;
764 case nir_op_f2b:
765 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
766 dst[0]->cat2.condition = IR3_COND_NE;
767 dst[0] = ir3_n2b(b, dst[0]);
768 break;
769 case nir_op_b2f:
770 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
771 break;
772 case nir_op_b2i:
773 dst[0] = ir3_b2n(b, src[0]);
774 break;
775 case nir_op_i2b:
776 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
777 dst[0]->cat2.condition = IR3_COND_NE;
778 dst[0] = ir3_n2b(b, dst[0]);
779 break;
780
781 case nir_op_fneg:
782 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
783 break;
784 case nir_op_fabs:
785 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
786 break;
787 case nir_op_fmax:
788 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
789 break;
790 case nir_op_fmin:
791 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
792 break;
793 case nir_op_fmul:
794 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
795 break;
796 case nir_op_fadd:
797 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
798 break;
799 case nir_op_fsub:
800 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
801 break;
802 case nir_op_ffma:
803 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
804 break;
805 case nir_op_fddx:
806 dst[0] = ir3_DSX(b, src[0], 0);
807 dst[0]->cat5.type = TYPE_F32;
808 break;
809 case nir_op_fddy:
810 dst[0] = ir3_DSY(b, src[0], 0);
811 dst[0]->cat5.type = TYPE_F32;
812 break;
813 break;
814 case nir_op_flt:
815 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
816 dst[0]->cat2.condition = IR3_COND_LT;
817 dst[0] = ir3_n2b(b, dst[0]);
818 break;
819 case nir_op_fge:
820 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
821 dst[0]->cat2.condition = IR3_COND_GE;
822 dst[0] = ir3_n2b(b, dst[0]);
823 break;
824 case nir_op_feq:
825 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
826 dst[0]->cat2.condition = IR3_COND_EQ;
827 dst[0] = ir3_n2b(b, dst[0]);
828 break;
829 case nir_op_fne:
830 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
831 dst[0]->cat2.condition = IR3_COND_NE;
832 dst[0] = ir3_n2b(b, dst[0]);
833 break;
834 case nir_op_fceil:
835 dst[0] = ir3_CEIL_F(b, src[0], 0);
836 break;
837 case nir_op_ffloor:
838 dst[0] = ir3_FLOOR_F(b, src[0], 0);
839 break;
840 case nir_op_ftrunc:
841 dst[0] = ir3_TRUNC_F(b, src[0], 0);
842 break;
843 case nir_op_fround_even:
844 dst[0] = ir3_RNDNE_F(b, src[0], 0);
845 break;
846 case nir_op_fsign:
847 dst[0] = ir3_SIGN_F(b, src[0], 0);
848 break;
849
850 case nir_op_fsin:
851 dst[0] = ir3_SIN(b, src[0], 0);
852 break;
853 case nir_op_fcos:
854 dst[0] = ir3_COS(b, src[0], 0);
855 break;
856 case nir_op_frsq:
857 dst[0] = ir3_RSQ(b, src[0], 0);
858 break;
859 case nir_op_frcp:
860 dst[0] = ir3_RCP(b, src[0], 0);
861 break;
862 case nir_op_flog2:
863 dst[0] = ir3_LOG2(b, src[0], 0);
864 break;
865 case nir_op_fexp2:
866 dst[0] = ir3_EXP2(b, src[0], 0);
867 break;
868 case nir_op_fsqrt:
869 dst[0] = ir3_SQRT(b, src[0], 0);
870 break;
871
872 case nir_op_iabs:
873 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
874 break;
875 case nir_op_iadd:
876 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
877 break;
878 case nir_op_iand:
879 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
880 break;
881 case nir_op_imax:
882 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
883 break;
884 case nir_op_imin:
885 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
886 break;
887 case nir_op_imul:
888 /*
889 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
890 * mull.u tmp0, a, b ; mul low, i.e. al * bl
891 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
892 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
893 */
894 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
895 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
896 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
897 break;
898 case nir_op_ineg:
899 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
900 break;
901 case nir_op_inot:
902 dst[0] = ir3_NOT_B(b, src[0], 0);
903 break;
904 case nir_op_ior:
905 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
906 break;
907 case nir_op_ishl:
908 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
909 break;
910 case nir_op_ishr:
911 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
912 break;
913 case nir_op_isign: {
914 /* maybe this would be sane to lower in nir.. */
915 struct ir3_instruction *neg, *pos;
916
917 neg = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
918 neg->cat2.condition = IR3_COND_LT;
919
920 pos = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
921 pos->cat2.condition = IR3_COND_GT;
922
923 dst[0] = ir3_SUB_U(b, pos, 0, neg, 0);
924
925 break;
926 }
927 case nir_op_isub:
928 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
929 break;
930 case nir_op_ixor:
931 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
932 break;
933 case nir_op_ushr:
934 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
935 break;
936 case nir_op_ilt:
937 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
938 dst[0]->cat2.condition = IR3_COND_LT;
939 dst[0] = ir3_n2b(b, dst[0]);
940 break;
941 case nir_op_ige:
942 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
943 dst[0]->cat2.condition = IR3_COND_GE;
944 dst[0] = ir3_n2b(b, dst[0]);
945 break;
946 case nir_op_ieq:
947 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
948 dst[0]->cat2.condition = IR3_COND_EQ;
949 dst[0] = ir3_n2b(b, dst[0]);
950 break;
951 case nir_op_ine:
952 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
953 dst[0]->cat2.condition = IR3_COND_NE;
954 dst[0] = ir3_n2b(b, dst[0]);
955 break;
956 case nir_op_ult:
957 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
958 dst[0]->cat2.condition = IR3_COND_LT;
959 dst[0] = ir3_n2b(b, dst[0]);
960 break;
961 case nir_op_uge:
962 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
963 dst[0]->cat2.condition = IR3_COND_GE;
964 dst[0] = ir3_n2b(b, dst[0]);
965 break;
966
967 case nir_op_bcsel:
968 dst[0] = ir3_SEL_B32(b, src[1], 0, ir3_b2n(b, src[0]), 0, src[2], 0);
969 break;
970
971 default:
972 compile_error(ctx, "Unhandled ALU op: %s\n",
973 nir_op_infos[alu->op].name);
974 break;
975 }
976 }
977
978 /* handles array reads: */
979 static void
980 emit_intrinisic_load_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
981 struct ir3_instruction **dst)
982 {
983 nir_deref_var *dvar = intr->variables[0];
984 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
985 struct ir3_array *arr = get_var(ctx, dvar->var);
986
987 compile_assert(ctx, dvar->deref.child &&
988 (dvar->deref.child->deref_type == nir_deref_type_array));
989
990 switch (darr->deref_array_type) {
991 case nir_deref_array_type_direct:
992 /* direct access does not require anything special: */
993 for (int i = 0; i < intr->num_components; i++) {
994 unsigned n = darr->base_offset * 4 + i;
995 compile_assert(ctx, n < arr->length);
996 dst[i] = arr->arr[n];
997 }
998 break;
999 case nir_deref_array_type_indirect: {
1000 /* for indirect, we need to collect all the array elements: */
1001 struct ir3_instruction *collect =
1002 create_collect(ctx->block, arr->arr, arr->length);
1003 struct ir3_instruction *addr =
1004 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1005 for (int i = 0; i < intr->num_components; i++) {
1006 unsigned n = darr->base_offset * 4 + i;
1007 compile_assert(ctx, n < arr->length);
1008 dst[i] = create_indirect_load(ctx, arr->length, n, addr, collect);
1009 }
1010 break;
1011 }
1012 default:
1013 compile_error(ctx, "Unhandled load deref type: %u\n",
1014 darr->deref_array_type);
1015 break;
1016 }
1017 }
1018
1019 /* handles array writes: */
1020 static void
1021 emit_intrinisic_store_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1022 {
1023 nir_deref_var *dvar = intr->variables[0];
1024 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
1025 struct ir3_array *arr = get_var(ctx, dvar->var);
1026 struct ir3_instruction **src;
1027
1028 compile_assert(ctx, dvar->deref.child &&
1029 (dvar->deref.child->deref_type == nir_deref_type_array));
1030
1031 src = get_src(ctx, &intr->src[0]);
1032
1033 switch (darr->deref_array_type) {
1034 case nir_deref_array_type_direct:
1035 /* direct access does not require anything special: */
1036 for (int i = 0; i < intr->num_components; i++) {
1037 unsigned n = darr->base_offset * 4 + i;
1038 compile_assert(ctx, n < arr->length);
1039 arr->arr[n] = src[i];
1040 }
1041 break;
1042 case nir_deref_array_type_indirect: {
1043 /* for indirect, create indirect-store and fan that out: */
1044 struct ir3_instruction *collect =
1045 create_collect(ctx->block, arr->arr, arr->length);
1046 struct ir3_instruction *addr =
1047 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1048 for (int i = 0; i < intr->num_components; i++) {
1049 struct ir3_instruction *store;
1050 unsigned n = darr->base_offset * 4 + i;
1051 compile_assert(ctx, n < arr->length);
1052
1053 store = create_indirect_store(ctx, arr->length,
1054 n, src[i], addr, collect);
1055
1056 store->fanin->fi.aid = arr->aid;
1057
1058 /* TODO: probably split this out to be used for
1059 * store_output_indirect? or move this into
1060 * create_indirect_store()?
1061 */
1062 for (int j = i; j < arr->length; j += 4) {
1063 struct ir3_instruction *split;
1064
1065 split = ir3_instr_create(ctx->block, -1, OPC_META_FO);
1066 split->fo.off = j;
1067 ir3_reg_create(split, 0, 0);
1068 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = store;
1069
1070 arr->arr[j] = split;
1071 }
1072 }
1073 break;
1074 }
1075 default:
1076 compile_error(ctx, "Unhandled store deref type: %u\n",
1077 darr->deref_array_type);
1078 break;
1079 }
1080 }
1081
1082 static void add_sysval_input(struct ir3_compile *ctx, unsigned name,
1083 struct ir3_instruction *instr)
1084 {
1085 struct ir3_shader_variant *so = ctx->so;
1086 unsigned r = regid(so->inputs_count, 0);
1087 unsigned n = so->inputs_count++;
1088
1089 so->inputs[n].semantic = ir3_semantic_name(name, 0);
1090 so->inputs[n].compmask = 1;
1091 so->inputs[n].regid = r;
1092 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1093 so->total_in++;
1094
1095 ctx->block->inputs[r] = instr;
1096 }
1097
1098 static void
1099 emit_intrinisic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1100 {
1101 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1102 struct ir3_instruction **dst, **src;
1103 struct ir3_block *b = ctx->block;
1104 unsigned idx = intr->const_index[0];
1105
1106 if (info->has_dest) {
1107 dst = get_dst(ctx, &intr->dest, intr->num_components);
1108 }
1109
1110 switch (intr->intrinsic) {
1111 case nir_intrinsic_load_uniform:
1112 compile_assert(ctx, intr->const_index[1] == 1);
1113 for (int i = 0; i < intr->num_components; i++) {
1114 unsigned n = idx * 4 + i;
1115 dst[i] = create_uniform(ctx, n);
1116 }
1117 break;
1118 case nir_intrinsic_load_uniform_indirect:
1119 compile_assert(ctx, intr->const_index[1] == 1);
1120 src = get_src(ctx, &intr->src[0]);
1121 for (int i = 0; i < intr->num_components; i++) {
1122 unsigned n = idx * 4 + i;
1123 dst[i] = create_uniform_indirect(ctx, n,
1124 get_addr(ctx, src[0]));
1125 }
1126 break;
1127 case nir_intrinsic_load_input:
1128 compile_assert(ctx, intr->const_index[1] == 1);
1129 for (int i = 0; i < intr->num_components; i++) {
1130 unsigned n = idx * 4 + i;
1131 dst[i] = b->inputs[n];
1132 }
1133 break;
1134 case nir_intrinsic_load_input_indirect:
1135 compile_assert(ctx, intr->const_index[1] == 1);
1136 src = get_src(ctx, &intr->src[0]);
1137 struct ir3_instruction *collect =
1138 create_collect(b, b->inputs, b->ninputs);
1139 struct ir3_instruction *addr = get_addr(ctx, src[0]);
1140 for (int i = 0; i < intr->num_components; i++) {
1141 unsigned n = idx * 4 + i;
1142 dst[i] = create_indirect_load(ctx, b->ninputs, n, addr, collect);
1143 }
1144 break;
1145 case nir_intrinsic_load_var:
1146 emit_intrinisic_load_var(ctx, intr, dst);
1147 break;
1148 case nir_intrinsic_store_var:
1149 emit_intrinisic_store_var(ctx, intr);
1150 break;
1151 case nir_intrinsic_store_output:
1152 compile_assert(ctx, intr->const_index[1] == 1);
1153 src = get_src(ctx, &intr->src[0]);
1154 for (int i = 0; i < intr->num_components; i++) {
1155 unsigned n = idx * 4 + i;
1156 b->outputs[n] = src[i];
1157 }
1158 break;
1159 case nir_intrinsic_load_base_vertex:
1160 if (!ctx->basevertex) {
1161 /* first four vec4 sysval's reserved for UBOs: */
1162 unsigned r = regid(ctx->so->first_driver_param + 4, 0);
1163 ctx->basevertex = create_uniform(ctx, r);
1164 add_sysval_input(ctx, TGSI_SEMANTIC_BASEVERTEX,
1165 ctx->basevertex);
1166 }
1167 dst[0] = ctx->basevertex;
1168 break;
1169 case nir_intrinsic_load_vertex_id_zero_base:
1170 if (!ctx->vertex_id) {
1171 ctx->vertex_id = create_input(ctx->block, NULL, 0);
1172 add_sysval_input(ctx, TGSI_SEMANTIC_VERTEXID_NOBASE,
1173 ctx->vertex_id);
1174 }
1175 dst[0] = ctx->vertex_id;
1176 break;
1177 case nir_intrinsic_load_instance_id:
1178 if (!ctx->instance_id) {
1179 ctx->instance_id = create_input(ctx->block, NULL, 0);
1180 add_sysval_input(ctx, TGSI_SEMANTIC_INSTANCEID,
1181 ctx->instance_id);
1182 }
1183 dst[0] = ctx->instance_id;
1184 break;
1185 case nir_intrinsic_discard_if:
1186 case nir_intrinsic_discard: {
1187 struct ir3_instruction *cond, *kill;
1188
1189 if (intr->intrinsic == nir_intrinsic_discard_if) {
1190 /* conditional discard: */
1191 src = get_src(ctx, &intr->src[0]);
1192 cond = ir3_b2n(b, src[0]);
1193 } else {
1194 /* unconditional discard: */
1195 cond = create_immed(b, 1);
1196 }
1197
1198 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1199 cond->cat2.condition = IR3_COND_NE;
1200
1201 /* condition always goes in predicate register: */
1202 cond->regs[0]->num = regid(REG_P0, 0);
1203
1204 kill = ir3_KILL(b, cond, 0);
1205
1206 ctx->kill[ctx->kill_count++] = kill;
1207 ctx->so->has_kill = true;
1208
1209 break;
1210 }
1211 default:
1212 compile_error(ctx, "Unhandled intrinsic type: %s\n",
1213 nir_intrinsic_infos[intr->intrinsic].name);
1214 break;
1215 }
1216 }
1217
1218 static void
1219 emit_load_const(struct ir3_compile *ctx, nir_load_const_instr *instr)
1220 {
1221 struct ir3_instruction **dst = get_dst_ssa(ctx, &instr->def,
1222 instr->def.num_components);
1223 for (int i = 0; i < instr->def.num_components; i++)
1224 dst[i] = create_immed(ctx->block, instr->value.u[i]);
1225 }
1226
1227 static void
1228 emit_undef(struct ir3_compile *ctx, nir_ssa_undef_instr *undef)
1229 {
1230 struct ir3_instruction **dst = get_dst_ssa(ctx, &undef->def,
1231 undef->def.num_components);
1232 /* backend doesn't want undefined instructions, so just plug
1233 * in 0.0..
1234 */
1235 for (int i = 0; i < undef->def.num_components; i++)
1236 dst[i] = create_immed(ctx->block, fui(0.0));
1237 }
1238
1239 /*
1240 * texture fetch/sample instructions:
1241 */
1242
1243 static void
1244 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1245 {
1246 unsigned coords, flags = 0;
1247
1248 /* note: would use tex->coord_components.. except txs.. also,
1249 * since array index goes after shadow ref, we don't want to
1250 * count it:
1251 */
1252 switch (tex->sampler_dim) {
1253 case GLSL_SAMPLER_DIM_1D:
1254 case GLSL_SAMPLER_DIM_BUF:
1255 coords = 1;
1256 break;
1257 case GLSL_SAMPLER_DIM_2D:
1258 case GLSL_SAMPLER_DIM_RECT:
1259 case GLSL_SAMPLER_DIM_EXTERNAL:
1260 case GLSL_SAMPLER_DIM_MS:
1261 coords = 2;
1262 break;
1263 case GLSL_SAMPLER_DIM_3D:
1264 case GLSL_SAMPLER_DIM_CUBE:
1265 coords = 3;
1266 flags |= IR3_INSTR_3D;
1267 break;
1268 }
1269
1270 if (tex->is_shadow)
1271 flags |= IR3_INSTR_S;
1272
1273 if (tex->is_array)
1274 flags |= IR3_INSTR_A;
1275
1276 *flagsp = flags;
1277 *coordsp = coords;
1278 }
1279
1280 static void
1281 emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex)
1282 {
1283 struct ir3_block *b = ctx->block;
1284 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1285 struct ir3_instruction **coord, *lod, *compare, *proj, **off, **ddx, **ddy;
1286 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1287 unsigned i, coords, flags;
1288 unsigned nsrc0 = 0, nsrc1 = 0;
1289 type_t type;
1290 opc_t opc;
1291
1292 /* TODO: might just be one component for gathers? */
1293 dst = get_dst(ctx, &tex->dest, 4);
1294
1295 for (unsigned i = 0; i < tex->num_srcs; i++) {
1296 switch (tex->src[i].src_type) {
1297 case nir_tex_src_coord:
1298 coord = get_src(ctx, &tex->src[i].src);
1299 break;
1300 case nir_tex_src_bias:
1301 lod = get_src(ctx, &tex->src[i].src)[0];
1302 has_bias = true;
1303 break;
1304 case nir_tex_src_lod:
1305 lod = get_src(ctx, &tex->src[i].src)[0];
1306 has_lod = true;
1307 break;
1308 case nir_tex_src_comparitor: /* shadow comparator */
1309 compare = get_src(ctx, &tex->src[i].src)[0];
1310 break;
1311 case nir_tex_src_projector:
1312 proj = get_src(ctx, &tex->src[i].src)[0];
1313 has_proj = true;
1314 break;
1315 case nir_tex_src_offset:
1316 off = get_src(ctx, &tex->src[i].src);
1317 has_off = true;
1318 break;
1319 case nir_tex_src_ddx:
1320 ddx = get_src(ctx, &tex->src[i].src);
1321 break;
1322 case nir_tex_src_ddy:
1323 ddy = get_src(ctx, &tex->src[i].src);
1324 break;
1325 default:
1326 compile_error(ctx, "Unhandled NIR tex serc type: %d\n",
1327 tex->src[i].src_type);
1328 return;
1329 }
1330 }
1331
1332 /*
1333 * lay out the first argument in the proper order:
1334 * - actual coordinates first
1335 * - shadow reference
1336 * - array index
1337 * - projection w
1338 * - starting at offset 4, dpdx.xy, dpdy.xy
1339 *
1340 * bias/lod go into the second arg
1341 */
1342
1343 tex_info(tex, &flags, &coords);
1344
1345 /* insert tex coords: */
1346 for (i = 0; i < coords; i++)
1347 src0[nsrc0++] = coord[i];
1348
1349 if (coords == 1) {
1350 /* hw doesn't do 1d, so we treat it as 2d with
1351 * height of 1, and patch up the y coord.
1352 * TODO: y coord should be (int)0 in some cases..
1353 */
1354 src0[nsrc0++] = create_immed(b, fui(0.5));
1355 }
1356
1357 if (tex->is_shadow)
1358 src0[nsrc0++] = compare;
1359
1360 if (tex->is_array)
1361 src0[nsrc0++] = coord[coords];
1362
1363 if (has_proj) {
1364 src0[nsrc0++] = proj;
1365 flags |= IR3_INSTR_P;
1366 }
1367
1368 /* pad to 4, then ddx/ddy: */
1369 if (tex->op == nir_texop_txd) {
1370 while (nsrc0 < 4)
1371 src0[nsrc0++] = create_immed(b, fui(0.0));
1372 for (i = 0; i < coords; i++)
1373 src0[nsrc0++] = ddx[i];
1374 if (coords < 2)
1375 src0[nsrc0++] = create_immed(b, fui(0.0));
1376 for (i = 0; i < coords; i++)
1377 src0[nsrc0++] = ddy[i];
1378 if (coords < 2)
1379 src0[nsrc0++] = create_immed(b, fui(0.0));
1380 }
1381
1382 /*
1383 * second argument (if applicable):
1384 * - offsets
1385 * - lod
1386 * - bias
1387 */
1388 if (has_off | has_lod | has_bias) {
1389 if (has_off) {
1390 for (i = 0; i < coords; i++)
1391 src1[nsrc1++] = off[i];
1392 if (coords < 2)
1393 src1[nsrc1++] = create_immed(b, fui(0.0));
1394 flags |= IR3_INSTR_O;
1395 }
1396
1397 if (has_lod | has_bias)
1398 src1[nsrc1++] = lod;
1399 }
1400
1401 switch (tex->op) {
1402 case nir_texop_tex: opc = OPC_SAM; break;
1403 case nir_texop_txb: opc = OPC_SAMB; break;
1404 case nir_texop_txl: opc = OPC_SAML; break;
1405 case nir_texop_txd: opc = OPC_SAMGQ; break;
1406 case nir_texop_txf: opc = OPC_ISAML; break;
1407 case nir_texop_txf_ms:
1408 case nir_texop_txs:
1409 case nir_texop_lod:
1410 case nir_texop_tg4:
1411 case nir_texop_query_levels:
1412 compile_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1413 return;
1414 }
1415
1416 switch (tex->dest_type) {
1417 case nir_type_invalid:
1418 case nir_type_float:
1419 type = TYPE_F32;
1420 break;
1421 case nir_type_int:
1422 type = TYPE_S32;
1423 break;
1424 case nir_type_unsigned:
1425 case nir_type_bool:
1426 type = TYPE_U32;
1427 break;
1428 }
1429
1430 sam = ir3_SAM(b, opc, type, TGSI_WRITEMASK_XYZW,
1431 flags, tex->sampler_index, tex->sampler_index,
1432 create_collect(b, src0, nsrc0),
1433 create_collect(b, src1, nsrc1));
1434
1435 split_dest(b, dst, sam);
1436 }
1437
1438 static void
1439 emit_tex_query_levels(struct ir3_compile *ctx, nir_tex_instr *tex)
1440 {
1441 struct ir3_block *b = ctx->block;
1442 struct ir3_instruction **dst, *sam;
1443
1444 dst = get_dst(ctx, &tex->dest, 1);
1445
1446 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, TGSI_WRITEMASK_Z, 0,
1447 tex->sampler_index, tex->sampler_index, NULL, NULL);
1448
1449 /* even though there is only one component, since it ends
1450 * up in .z rather than .x, we need a split_dest()
1451 */
1452 split_dest(b, dst, sam);
1453
1454 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1455 * the value in TEX_CONST_0 is zero-based.
1456 */
1457 if (ctx->levels_add_one)
1458 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1459 }
1460
1461 static void
1462 emit_tex_txs(struct ir3_compile *ctx, nir_tex_instr *tex)
1463 {
1464 struct ir3_block *b = ctx->block;
1465 struct ir3_instruction **dst, *sam, *lod;
1466 unsigned flags, coords;
1467
1468 tex_info(tex, &flags, &coords);
1469
1470 dst = get_dst(ctx, &tex->dest, 4);
1471
1472 compile_assert(ctx, tex->num_srcs == 1);
1473 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
1474
1475 lod = get_src(ctx, &tex->src[0].src)[0];
1476
1477 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, TGSI_WRITEMASK_XYZW, flags,
1478 tex->sampler_index, tex->sampler_index, lod, NULL);
1479
1480 split_dest(b, dst, sam);
1481
1482 /* Array size actually ends up in .w rather than .z. This doesn't
1483 * matter for miplevel 0, but for higher mips the value in z is
1484 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1485 * returned, which means that we have to add 1 to it for arrays.
1486 */
1487 if (tex->is_array) {
1488 if (ctx->levels_add_one) {
1489 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
1490 } else {
1491 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
1492 }
1493 }
1494 }
1495
1496 static void
1497 emit_instr(struct ir3_compile *ctx, nir_instr *instr)
1498 {
1499 switch (instr->type) {
1500 case nir_instr_type_alu:
1501 emit_alu(ctx, nir_instr_as_alu(instr));
1502 break;
1503 case nir_instr_type_intrinsic:
1504 emit_intrinisic(ctx, nir_instr_as_intrinsic(instr));
1505 break;
1506 case nir_instr_type_load_const:
1507 emit_load_const(ctx, nir_instr_as_load_const(instr));
1508 break;
1509 case nir_instr_type_ssa_undef:
1510 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1511 break;
1512 case nir_instr_type_tex: {
1513 nir_tex_instr *tex = nir_instr_as_tex(instr);
1514 /* couple tex instructions get special-cased:
1515 */
1516 switch (tex->op) {
1517 case nir_texop_txs:
1518 emit_tex_txs(ctx, tex);
1519 break;
1520 case nir_texop_query_levels:
1521 emit_tex_query_levels(ctx, tex);
1522 break;
1523 default:
1524 emit_tex(ctx, tex);
1525 break;
1526 }
1527 break;
1528 }
1529 case nir_instr_type_call:
1530 case nir_instr_type_jump:
1531 case nir_instr_type_phi:
1532 case nir_instr_type_parallel_copy:
1533 compile_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1534 break;
1535 }
1536 }
1537
1538 static void
1539 emit_block(struct ir3_compile *ctx, nir_block *block)
1540 {
1541 nir_foreach_instr(block, instr) {
1542 emit_instr(ctx, instr);
1543 if (ctx->error)
1544 return;
1545 }
1546 }
1547
1548 static void
1549 emit_function(struct ir3_compile *ctx, nir_function_impl *impl)
1550 {
1551 foreach_list_typed(nir_cf_node, node, node, &impl->body) {
1552 switch (node->type) {
1553 case nir_cf_node_block:
1554 emit_block(ctx, nir_cf_node_as_block(node));
1555 break;
1556 case nir_cf_node_if:
1557 case nir_cf_node_loop:
1558 case nir_cf_node_function:
1559 compile_error(ctx, "TODO\n");
1560 break;
1561 }
1562 if (ctx->error)
1563 return;
1564 }
1565 }
1566
1567 static void
1568 setup_input(struct ir3_compile *ctx, nir_variable *in)
1569 {
1570 struct ir3_shader_variant *so = ctx->so;
1571 unsigned array_len = MAX2(glsl_get_length(in->type), 1);
1572 unsigned ncomp = glsl_get_components(in->type);
1573 /* XXX: map loc slots to semantics */
1574 unsigned semantic_name = in->data.location;
1575 unsigned semantic_index = in->data.index;
1576 unsigned n = in->data.driver_location;
1577
1578 DBG("; in: %u:%u, len=%ux%u, loc=%u\n",
1579 semantic_name, semantic_index, array_len,
1580 ncomp, n);
1581
1582 so->inputs[n].semantic =
1583 ir3_semantic_name(semantic_name, semantic_index);
1584 so->inputs[n].compmask = (1 << ncomp) - 1;
1585 so->inputs[n].inloc = ctx->next_inloc;
1586 so->inputs[n].interpolate = 0;
1587 so->inputs_count = MAX2(so->inputs_count, n + 1);
1588
1589 /* the fdN_program_emit() code expects tgsi consts here, so map
1590 * things back to tgsi for now:
1591 */
1592 switch (in->data.interpolation) {
1593 case INTERP_QUALIFIER_FLAT:
1594 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1595 break;
1596 case INTERP_QUALIFIER_NOPERSPECTIVE:
1597 so->inputs[n].interpolate = TGSI_INTERPOLATE_LINEAR;
1598 break;
1599 case INTERP_QUALIFIER_SMOOTH:
1600 so->inputs[n].interpolate = TGSI_INTERPOLATE_PERSPECTIVE;
1601 break;
1602 }
1603
1604 for (int i = 0; i < ncomp; i++) {
1605 struct ir3_instruction *instr = NULL;
1606 unsigned idx = (n * 4) + i;
1607
1608 if (ctx->so->type == SHADER_FRAGMENT) {
1609 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1610 so->inputs[n].bary = false;
1611 so->frag_coord = true;
1612 instr = create_frag_coord(ctx, i);
1613 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1614 so->inputs[n].bary = false;
1615 so->frag_face = true;
1616 instr = create_frag_face(ctx, i);
1617 } else {
1618 bool use_ldlv = false;
1619
1620 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1621 * from the semantic name:
1622 */
1623 if ((in->data.interpolation == INTERP_QUALIFIER_NONE) &&
1624 ((semantic_name == TGSI_SEMANTIC_COLOR) ||
1625 (semantic_name == TGSI_SEMANTIC_BCOLOR)))
1626 so->inputs[n].interpolate = TGSI_INTERPOLATE_COLOR;
1627
1628 if (ctx->flat_bypass) {
1629 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1630 * from the semantic name:
1631 */
1632 switch (so->inputs[n].interpolate) {
1633 case TGSI_INTERPOLATE_COLOR:
1634 if (!ctx->so->key.rasterflat)
1635 break;
1636 /* fallthrough */
1637 case TGSI_INTERPOLATE_CONSTANT:
1638 use_ldlv = true;
1639 break;
1640 }
1641 }
1642
1643 so->inputs[n].bary = true;
1644
1645 instr = create_frag_input(ctx, idx, use_ldlv);
1646 }
1647 } else {
1648 instr = create_input(ctx->block, NULL, idx);
1649 }
1650
1651 ctx->block->inputs[idx] = instr;
1652 }
1653
1654 if (so->inputs[n].bary || (ctx->so->type == SHADER_VERTEX)) {
1655 ctx->next_inloc += ncomp;
1656 so->total_in += ncomp;
1657 }
1658 }
1659
1660 static void
1661 setup_output(struct ir3_compile *ctx, nir_variable *out)
1662 {
1663 struct ir3_shader_variant *so = ctx->so;
1664 unsigned array_len = MAX2(glsl_get_length(out->type), 1);
1665 unsigned ncomp = glsl_get_components(out->type);
1666 /* XXX: map loc slots to semantics */
1667 unsigned semantic_name = out->data.location;
1668 unsigned semantic_index = out->data.index;
1669 unsigned n = out->data.driver_location;
1670 unsigned comp = 0;
1671
1672 DBG("; out: %u:%u, len=%ux%u, loc=%u\n",
1673 semantic_name, semantic_index, array_len,
1674 ncomp, n);
1675
1676 if (ctx->so->type == SHADER_VERTEX) {
1677 switch (semantic_name) {
1678 case TGSI_SEMANTIC_POSITION:
1679 so->writes_pos = true;
1680 break;
1681 case TGSI_SEMANTIC_PSIZE:
1682 so->writes_psize = true;
1683 break;
1684 case TGSI_SEMANTIC_COLOR:
1685 case TGSI_SEMANTIC_BCOLOR:
1686 case TGSI_SEMANTIC_GENERIC:
1687 case TGSI_SEMANTIC_FOG:
1688 case TGSI_SEMANTIC_TEXCOORD:
1689 break;
1690 default:
1691 compile_error(ctx, "unknown VS semantic name: %s\n",
1692 tgsi_semantic_names[semantic_name]);
1693 }
1694 } else {
1695 switch (semantic_name) {
1696 case TGSI_SEMANTIC_POSITION:
1697 comp = 2; /* tgsi will write to .z component */
1698 so->writes_pos = true;
1699 break;
1700 case TGSI_SEMANTIC_COLOR:
1701 break;
1702 default:
1703 compile_error(ctx, "unknown FS semantic name: %s\n",
1704 tgsi_semantic_names[semantic_name]);
1705 }
1706 }
1707
1708 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
1709
1710 so->outputs[n].semantic =
1711 ir3_semantic_name(semantic_name, semantic_index);
1712 so->outputs[n].regid = regid(n, comp);
1713 so->outputs_count = MAX2(so->outputs_count, n + 1);
1714
1715 for (int i = 0; i < ncomp; i++) {
1716 unsigned idx = (n * 4) + i;
1717
1718 ctx->block->outputs[idx] = create_immed(ctx->block, fui(0.0));
1719 }
1720 }
1721
1722 static void
1723 emit_instructions(struct ir3_compile *ctx)
1724 {
1725 unsigned ninputs = exec_list_length(&ctx->s->inputs) * 4;
1726 unsigned noutputs = exec_list_length(&ctx->s->outputs) * 4;
1727
1728 /* we need to allocate big enough outputs array so that
1729 * we can stuff the kill's at the end:
1730 */
1731 if (ctx->so->type == SHADER_FRAGMENT)
1732 noutputs += ARRAY_SIZE(ctx->kill);
1733
1734 ctx->block = ir3_block_create(ctx->ir, 0, ninputs, noutputs);
1735
1736 if (ctx->so->type == SHADER_FRAGMENT)
1737 ctx->block->noutputs -= ARRAY_SIZE(ctx->kill);
1738
1739
1740 /* for fragment shader, we have a single input register (usually
1741 * r0.xy) which is used as the base for bary.f varying fetch instrs:
1742 */
1743 if (ctx->so->type == SHADER_FRAGMENT) {
1744 // TODO maybe a helper for fi since we need it a few places..
1745 struct ir3_instruction *instr;
1746 instr = ir3_instr_create(ctx->block, -1, OPC_META_FI);
1747 ir3_reg_create(instr, 0, 0);
1748 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.x */
1749 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.y */
1750 ctx->frag_pos = instr;
1751 }
1752
1753 /* Setup inputs: */
1754 foreach_list_typed(nir_variable, var, node, &ctx->s->inputs) {
1755 setup_input(ctx, var);
1756 }
1757
1758 /* Setup outputs: */
1759 foreach_list_typed(nir_variable, var, node, &ctx->s->outputs) {
1760 setup_output(ctx, var);
1761 }
1762
1763 /* Setup variables (which should only be arrays): */
1764 foreach_list_typed(nir_variable, var, node, &ctx->s->globals) {
1765 declare_var(ctx, var);
1766 }
1767
1768 /* Find the main function and emit the body: */
1769 nir_foreach_overload(ctx->s, overload) {
1770 compile_assert(ctx, strcmp(overload->function->name, "main") == 0);
1771 compile_assert(ctx, overload->impl);
1772 emit_function(ctx, overload->impl);
1773 if (ctx->error)
1774 return;
1775 }
1776 }
1777
1778 /* from NIR perspective, we actually have inputs. But most of the "inputs"
1779 * for a fragment shader are just bary.f instructions. The *actual* inputs
1780 * from the hw perspective are the frag_pos and optionally frag_coord and
1781 * frag_face.
1782 */
1783 static void
1784 fixup_frag_inputs(struct ir3_compile *ctx)
1785 {
1786 struct ir3_shader_variant *so = ctx->so;
1787 struct ir3_block *block = ctx->block;
1788 struct ir3_instruction **inputs;
1789 struct ir3_instruction *instr;
1790 int n, regid = 0;
1791
1792 block->ninputs = 0;
1793
1794 n = 4; /* always have frag_pos */
1795 n += COND(so->frag_face, 4);
1796 n += COND(so->frag_coord, 4);
1797
1798 inputs = ir3_alloc(ctx->ir, n * (sizeof(struct ir3_instruction *)));
1799
1800 if (so->frag_face) {
1801 /* this ultimately gets assigned to hr0.x so doesn't conflict
1802 * with frag_coord/frag_pos..
1803 */
1804 inputs[block->ninputs++] = ctx->frag_face;
1805 ctx->frag_face->regs[0]->num = 0;
1806
1807 /* remaining channels not used, but let's avoid confusing
1808 * other parts that expect inputs to come in groups of vec4
1809 */
1810 inputs[block->ninputs++] = NULL;
1811 inputs[block->ninputs++] = NULL;
1812 inputs[block->ninputs++] = NULL;
1813 }
1814
1815 /* since we don't know where to set the regid for frag_coord,
1816 * we have to use r0.x for it. But we don't want to *always*
1817 * use r1.x for frag_pos as that could increase the register
1818 * footprint on simple shaders:
1819 */
1820 if (so->frag_coord) {
1821 ctx->frag_coord[0]->regs[0]->num = regid++;
1822 ctx->frag_coord[1]->regs[0]->num = regid++;
1823 ctx->frag_coord[2]->regs[0]->num = regid++;
1824 ctx->frag_coord[3]->regs[0]->num = regid++;
1825
1826 inputs[block->ninputs++] = ctx->frag_coord[0];
1827 inputs[block->ninputs++] = ctx->frag_coord[1];
1828 inputs[block->ninputs++] = ctx->frag_coord[2];
1829 inputs[block->ninputs++] = ctx->frag_coord[3];
1830 }
1831
1832 /* we always have frag_pos: */
1833 so->pos_regid = regid;
1834
1835 /* r0.x */
1836 instr = create_input(block, NULL, block->ninputs);
1837 instr->regs[0]->num = regid++;
1838 inputs[block->ninputs++] = instr;
1839 ctx->frag_pos->regs[1]->instr = instr;
1840
1841 /* r0.y */
1842 instr = create_input(block, NULL, block->ninputs);
1843 instr->regs[0]->num = regid++;
1844 inputs[block->ninputs++] = instr;
1845 ctx->frag_pos->regs[2]->instr = instr;
1846
1847 block->inputs = inputs;
1848 }
1849
1850 static void
1851 compile_dump(struct ir3_compile *ctx)
1852 {
1853 const char *name = (ctx->so->type == SHADER_VERTEX) ? "vert" : "frag";
1854 static unsigned n = 0;
1855 char fname[16];
1856 FILE *f;
1857 snprintf(fname, sizeof(fname), "%s-%04u.dot", name, n++);
1858 f = fopen(fname, "w");
1859 if (!f)
1860 return;
1861 ir3_block_depth(ctx->block);
1862 ir3_dump(ctx->ir, name, ctx->block, f);
1863 fclose(f);
1864 }
1865
1866 int
1867 ir3_compile_shader_nir(struct ir3_shader_variant *so,
1868 const struct tgsi_token *tokens, struct ir3_shader_key key)
1869 {
1870 struct ir3_compile *ctx;
1871 struct ir3_block *block;
1872 struct ir3_instruction **inputs;
1873 unsigned i, j, actual_in;
1874 int ret = 0, max_bary;
1875
1876 assert(!so->ir);
1877
1878 so->ir = ir3_create();
1879
1880 assert(so->ir);
1881
1882 ctx = compile_init(so, tokens);
1883 if (!ctx) {
1884 DBG("INIT failed!");
1885 ret = -1;
1886 goto out;
1887 }
1888
1889 emit_instructions(ctx);
1890
1891 if (ctx->error) {
1892 DBG("EMIT failed!");
1893 ret = -1;
1894 goto out;
1895 }
1896
1897 block = ctx->block;
1898 so->ir->block = block;
1899
1900 /* keep track of the inputs from TGSI perspective.. */
1901 inputs = block->inputs;
1902
1903 /* but fixup actual inputs for frag shader: */
1904 if (so->type == SHADER_FRAGMENT)
1905 fixup_frag_inputs(ctx);
1906
1907 /* at this point, for binning pass, throw away unneeded outputs: */
1908 if (key.binning_pass) {
1909 for (i = 0, j = 0; i < so->outputs_count; i++) {
1910 unsigned name = sem2name(so->outputs[i].semantic);
1911 unsigned idx = sem2idx(so->outputs[i].semantic);
1912
1913 /* throw away everything but first position/psize */
1914 if ((idx == 0) && ((name == TGSI_SEMANTIC_POSITION) ||
1915 (name == TGSI_SEMANTIC_PSIZE))) {
1916 if (i != j) {
1917 so->outputs[j] = so->outputs[i];
1918 block->outputs[(j*4)+0] = block->outputs[(i*4)+0];
1919 block->outputs[(j*4)+1] = block->outputs[(i*4)+1];
1920 block->outputs[(j*4)+2] = block->outputs[(i*4)+2];
1921 block->outputs[(j*4)+3] = block->outputs[(i*4)+3];
1922 }
1923 j++;
1924 }
1925 }
1926 so->outputs_count = j;
1927 block->noutputs = j * 4;
1928 }
1929
1930 /* if we want half-precision outputs, mark the output registers
1931 * as half:
1932 */
1933 if (key.half_precision) {
1934 for (i = 0; i < block->noutputs; i++) {
1935 if (!block->outputs[i])
1936 continue;
1937 block->outputs[i]->regs[0]->flags |= IR3_REG_HALF;
1938 }
1939 }
1940
1941 /* at this point, we want the kill's in the outputs array too,
1942 * so that they get scheduled (since they have no dst).. we've
1943 * already ensured that the array is big enough in push_block():
1944 */
1945 if (so->type == SHADER_FRAGMENT) {
1946 for (i = 0; i < ctx->kill_count; i++)
1947 block->outputs[block->noutputs++] = ctx->kill[i];
1948 }
1949
1950 if (fd_mesa_debug & FD_DBG_OPTDUMP)
1951 compile_dump(ctx);
1952
1953 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1954 printf("BEFORE CP:\n");
1955 ir3_dump_instr_list(block->head);
1956 }
1957
1958 ir3_block_depth(block);
1959
1960 ir3_block_cp(block);
1961
1962 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1963 printf("BEFORE GROUPING:\n");
1964 ir3_dump_instr_list(block->head);
1965 }
1966
1967 /* Group left/right neighbors, inserting mov's where needed to
1968 * solve conflicts:
1969 */
1970 ir3_block_group(block);
1971
1972 if (fd_mesa_debug & FD_DBG_OPTDUMP)
1973 compile_dump(ctx);
1974
1975 ir3_block_depth(block);
1976
1977 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1978 printf("AFTER DEPTH:\n");
1979 ir3_dump_instr_list(block->head);
1980 }
1981
1982 ret = ir3_block_sched(block);
1983 if (ret) {
1984 DBG("SCHED failed!");
1985 goto out;
1986 }
1987
1988 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1989 printf("AFTER SCHED:\n");
1990 ir3_dump_instr_list(block->head);
1991 }
1992
1993 ret = ir3_block_ra(block, so->type, so->frag_coord, so->frag_face);
1994 if (ret) {
1995 DBG("RA failed!");
1996 goto out;
1997 }
1998
1999 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2000 printf("AFTER RA:\n");
2001 ir3_dump_instr_list(block->head);
2002 }
2003
2004 ir3_block_legalize(block, &so->has_samp, &max_bary);
2005
2006 /* fixup input/outputs: */
2007 for (i = 0; i < so->outputs_count; i++) {
2008 so->outputs[i].regid = block->outputs[i*4]->regs[0]->num;
2009 /* preserve hack for depth output.. tgsi writes depth to .z,
2010 * but what we give the hw is the scalar register:
2011 */
2012 if ((so->type == SHADER_FRAGMENT) &&
2013 (sem2name(so->outputs[i].semantic) == TGSI_SEMANTIC_POSITION))
2014 so->outputs[i].regid += 2;
2015 }
2016
2017 /* Note that some or all channels of an input may be unused: */
2018 actual_in = 0;
2019 for (i = 0; i < so->inputs_count; i++) {
2020 unsigned j, regid = ~0, compmask = 0;
2021 so->inputs[i].ncomp = 0;
2022 for (j = 0; j < 4; j++) {
2023 struct ir3_instruction *in = inputs[(i*4) + j];
2024 if (in) {
2025 compmask |= (1 << j);
2026 regid = in->regs[0]->num - j;
2027 actual_in++;
2028 so->inputs[i].ncomp++;
2029 }
2030 }
2031 so->inputs[i].regid = regid;
2032 so->inputs[i].compmask = compmask;
2033 }
2034
2035 /* fragment shader always gets full vec4's even if it doesn't
2036 * fetch all components, but vertex shader we need to update
2037 * with the actual number of components fetch, otherwise thing
2038 * will hang due to mismaptch between VFD_DECODE's and
2039 * TOTALATTRTOVS
2040 */
2041 if (so->type == SHADER_VERTEX)
2042 so->total_in = actual_in;
2043 else
2044 so->total_in = align(max_bary + 1, 4);
2045
2046 out:
2047 if (ret) {
2048 ir3_destroy(so->ir);
2049 so->ir = NULL;
2050 }
2051 compile_free(ctx);
2052
2053 return ret;
2054 }