1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* mapping from nir_register to defining instruction: */
78 struct hash_table
*def_ht
;
82 /* a common pattern for indirect addressing is to request the
83 * same address register multiple times. To avoid generating
84 * duplicate instruction sequences (which our backend does not
85 * try to clean up, since that should be done as the NIR stage)
86 * we cache the address value generated for a given src value:
88 * Note that we have to cache these per alignment, since same
89 * src used for an array of vec1 cannot be also used for an
92 struct hash_table
*addr_ht
[4];
94 /* last dst array, for indirect we need to insert a var-store.
96 struct ir3_instruction
**last_dst
;
99 /* maps nir_block to ir3_block, mostly for the purposes of
100 * figuring out the blocks successors
102 struct hash_table
*block_ht
;
104 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
105 * so we need to use ldlv.u32 to load the varying directly:
109 /* on a3xx, we need to add one to # of array levels:
113 /* on a3xx, we need to scale up integer coords for isaml based
116 bool unminify_coords
;
118 /* on a4xx, for array textures we need to add 0.5 to the array
121 bool array_index_add_half
;
123 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
126 unsigned max_texture_index
;
128 /* set if we encounter something we can't handle yet, so we
129 * can bail cleanly and fallback to TGSI compiler f/e
134 /* gpu pointer size in units of 32bit registers/slots */
135 static unsigned pointer_size(struct ir3_context
*ctx
)
137 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
140 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
141 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
144 static struct ir3_context
*
145 compile_init(struct ir3_compiler
*compiler
,
146 struct ir3_shader_variant
*so
)
148 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
150 if (compiler
->gpu_id
>= 400) {
151 /* need special handling for "flat" */
152 ctx
->flat_bypass
= true;
153 ctx
->levels_add_one
= false;
154 ctx
->unminify_coords
= false;
155 ctx
->array_index_add_half
= true;
157 if (so
->type
== SHADER_VERTEX
)
158 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
159 else if (so
->type
== SHADER_FRAGMENT
)
160 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
163 /* no special handling for "flat" */
164 ctx
->flat_bypass
= false;
165 ctx
->levels_add_one
= true;
166 ctx
->unminify_coords
= true;
167 ctx
->array_index_add_half
= false;
170 ctx
->compiler
= compiler
;
173 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
174 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
175 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
176 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
178 /* TODO: maybe generate some sort of bitmask of what key
179 * lowers vs what shader has (ie. no need to lower
180 * texture clamp lowering if no texture sample instrs)..
181 * although should be done further up the stack to avoid
182 * creating duplicate variants..
185 if (ir3_key_lowers_nir(&so
->key
)) {
186 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
187 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
189 /* fast-path for shader key that lowers nothing in NIR: */
190 ctx
->s
= so
->shader
->nir
;
193 /* this needs to be the last pass run, so do this here instead of
194 * in ir3_optimize_nir():
196 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
197 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
199 if (fd_mesa_debug
& FD_DBG_DISASM
) {
200 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
201 so
->shader
->id
, so
->id
, so
->type
,
202 so
->key
.binning_pass
, so
->key
.color_two_side
,
203 so
->key
.half_precision
);
204 nir_print_shader(ctx
->s
, stdout
);
207 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
209 so
->num_uniforms
= ctx
->s
->num_uniforms
;
210 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
212 /* Layout of constant registers, each section aligned to vec4. Note
213 * that pointer size (ubo, etc) changes depending on generation.
218 * if (vertex shader) {
219 * driver params (IR3_DP_*)
220 * if (stream_output.num_outputs > 0)
221 * stream-out addresses
225 * Immediates go last mostly because they are inserted in the CP pass
226 * after the nir -> ir3 frontend.
228 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
229 unsigned ptrsz
= pointer_size(ctx
);
231 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
233 if (so
->num_ubos
> 0) {
234 so
->constbase
.ubo
= constoff
;
235 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
238 if (so
->const_layout
.ssbo_size
.count
> 0) {
239 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
240 so
->constbase
.ssbo_sizes
= constoff
;
241 constoff
+= align(cnt
, 4) / 4;
244 if (so
->const_layout
.image_dims
.count
> 0) {
245 unsigned cnt
= so
->const_layout
.image_dims
.count
;
246 so
->constbase
.image_dims
= constoff
;
247 constoff
+= align(cnt
, 4) / 4;
250 unsigned num_driver_params
= 0;
251 if (so
->type
== SHADER_VERTEX
) {
252 num_driver_params
= IR3_DP_VS_COUNT
;
253 } else if (so
->type
== SHADER_COMPUTE
) {
254 num_driver_params
= IR3_DP_CS_COUNT
;
257 so
->constbase
.driver_param
= constoff
;
258 constoff
+= align(num_driver_params
, 4) / 4;
260 if ((so
->type
== SHADER_VERTEX
) &&
261 (compiler
->gpu_id
< 500) &&
262 so
->shader
->stream_output
.num_outputs
> 0) {
263 so
->constbase
.tfbo
= constoff
;
264 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
267 so
->constbase
.immediate
= constoff
;
273 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
276 va_start(ap
, format
);
277 _debug_vprintf(format
, ap
);
279 nir_print_shader(ctx
->s
, stdout
);
284 #define compile_assert(ctx, cond) do { \
285 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
289 compile_free(struct ir3_context
*ctx
)
295 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
297 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
298 arr
->id
= ++ctx
->num_arrays
;
299 /* NOTE: sometimes we get non array regs, for example for arrays of
300 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
301 * treat a non-array as if it was an array of length 1.
303 * It would be nice if there was a nir pass to convert arrays of
306 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
307 compile_assert(ctx
, arr
->length
> 0);
309 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
312 static struct ir3_array
*
313 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
315 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
319 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
323 /* relative (indirect) if address!=NULL */
324 static struct ir3_instruction
*
325 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
326 struct ir3_instruction
*address
)
328 struct ir3_block
*block
= ctx
->block
;
329 struct ir3_instruction
*mov
;
330 struct ir3_register
*src
;
332 mov
= ir3_instr_create(block
, OPC_MOV
);
333 mov
->cat1
.src_type
= TYPE_U32
;
334 mov
->cat1
.dst_type
= TYPE_U32
;
335 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
336 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
337 ir3_reg_create(mov
, 0, 0);
338 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
339 COND(address
, IR3_REG_RELATIV
));
340 src
->instr
= arr
->last_write
;
341 src
->size
= arr
->length
;
342 src
->array
.id
= arr
->id
;
343 src
->array
.offset
= n
;
346 ir3_instr_set_address(mov
, address
);
351 /* relative (indirect) if address!=NULL */
353 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
354 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
356 struct ir3_block
*block
= ctx
->block
;
357 struct ir3_instruction
*mov
;
358 struct ir3_register
*dst
;
360 /* if not relative store, don't create an extra mov, since that
361 * ends up being difficult for cp to remove.
366 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
367 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
369 dst
->flags
|= IR3_REG_ARRAY
;
370 dst
->instr
= arr
->last_write
;
371 dst
->size
= arr
->length
;
372 dst
->array
.id
= arr
->id
;
373 dst
->array
.offset
= n
;
375 arr
->last_write
= src
;
377 array_insert(block
, block
->keeps
, src
);
382 mov
= ir3_instr_create(block
, OPC_MOV
);
383 mov
->cat1
.src_type
= TYPE_U32
;
384 mov
->cat1
.dst_type
= TYPE_U32
;
385 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
386 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
387 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
388 COND(address
, IR3_REG_RELATIV
));
389 dst
->instr
= arr
->last_write
;
390 dst
->size
= arr
->length
;
391 dst
->array
.id
= arr
->id
;
392 dst
->array
.offset
= n
;
393 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
396 ir3_instr_set_address(mov
, address
);
398 arr
->last_write
= mov
;
400 /* the array store may only matter to something in an earlier
401 * block (ie. loops), but since arrays are not in SSA, depth
402 * pass won't know this.. so keep all array stores:
404 array_insert(block
, block
->keeps
, mov
);
407 static inline type_t
utype_for_size(unsigned bit_size
)
410 case 32: return TYPE_U32
;
411 case 16: return TYPE_U16
;
412 case 8: return TYPE_U8
;
413 default: unreachable("bad bitsize"); return ~0;
417 static inline type_t
utype_src(nir_src src
)
418 { return utype_for_size(nir_src_bit_size(src
)); }
420 static inline type_t
utype_dst(nir_dest dst
)
421 { return utype_for_size(nir_dest_bit_size(dst
)); }
423 /* allocate a n element value array (to be populated by caller) and
426 static struct ir3_instruction
**
427 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
429 struct ir3_instruction
**value
=
430 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
431 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
435 static struct ir3_instruction
**
436 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
438 struct ir3_instruction
**value
;
441 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
443 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
446 /* NOTE: in non-ssa case, we don't really need to store last_dst
447 * but this helps us catch cases where put_dst() call is forgotten
449 compile_assert(ctx
, !ctx
->last_dst
);
450 ctx
->last_dst
= value
;
456 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
458 static struct ir3_instruction
* const *
459 get_src(struct ir3_context
*ctx
, nir_src
*src
)
462 struct hash_entry
*entry
;
463 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
464 compile_assert(ctx
, entry
);
467 nir_register
*reg
= src
->reg
.reg
;
468 struct ir3_array
*arr
= get_array(ctx
, reg
);
469 unsigned num_components
= arr
->r
->num_components
;
470 struct ir3_instruction
*addr
= NULL
;
471 struct ir3_instruction
**value
=
472 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
474 if (src
->reg
.indirect
)
475 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
476 reg
->num_components
);
478 for (unsigned i
= 0; i
< num_components
; i
++) {
479 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
480 compile_assert(ctx
, n
< arr
->length
);
481 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
489 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
491 unsigned bit_size
= nir_dest_bit_size(*dst
);
494 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
495 ctx
->last_dst
[i
]->regs
[0]->flags
|= IR3_REG_HALF
;
500 nir_register
*reg
= dst
->reg
.reg
;
501 struct ir3_array
*arr
= get_array(ctx
, reg
);
502 unsigned num_components
= ctx
->last_dst_n
;
503 struct ir3_instruction
*addr
= NULL
;
505 if (dst
->reg
.indirect
)
506 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
507 reg
->num_components
);
509 for (unsigned i
= 0; i
< num_components
; i
++) {
510 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
511 compile_assert(ctx
, n
< arr
->length
);
512 if (!ctx
->last_dst
[i
])
514 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
517 ralloc_free(ctx
->last_dst
);
519 ctx
->last_dst
= NULL
;
523 static struct ir3_instruction
*
524 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
526 struct ir3_instruction
*mov
;
527 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
529 mov
= ir3_instr_create(block
, OPC_MOV
);
530 mov
->cat1
.src_type
= type
;
531 mov
->cat1
.dst_type
= type
;
532 ir3_reg_create(mov
, 0, flags
);
533 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
538 static struct ir3_instruction
*
539 create_immed(struct ir3_block
*block
, uint32_t val
)
541 return create_immed_typed(block
, val
, TYPE_U32
);
544 static struct ir3_instruction
*
545 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
547 struct ir3_instruction
*instr
, *immed
;
549 /* TODO in at least some cases, the backend could probably be
550 * made clever enough to propagate IR3_REG_HALF..
552 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
553 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
560 /* src *= 2 => src <<= 1: */
561 immed
= create_immed(block
, 1);
562 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
564 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
565 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
566 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
570 immed
= create_immed(block
, 3);
571 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
573 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
574 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
575 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
578 /* src *= 4 => src <<= 2: */
579 immed
= create_immed(block
, 2);
580 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
582 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
583 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
584 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
587 unreachable("bad align");
591 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
592 instr
->regs
[0]->num
= regid(REG_A0
, 0);
593 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
594 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
599 /* caches addr values to avoid generating multiple cov/shl/mova
600 * sequences for each use of a given NIR level src as address
602 static struct ir3_instruction
*
603 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
605 struct ir3_instruction
*addr
;
606 unsigned idx
= align
- 1;
608 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
610 if (!ctx
->addr_ht
[idx
]) {
611 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
612 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
614 struct hash_entry
*entry
;
615 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
620 addr
= create_addr(ctx
->block
, src
, align
);
621 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
626 static struct ir3_instruction
*
627 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
629 struct ir3_block
*b
= ctx
->block
;
630 struct ir3_instruction
*cond
;
632 /* NOTE: only cmps.*.* can write p0.x: */
633 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
634 cond
->cat2
.condition
= IR3_COND_NE
;
636 /* condition always goes in predicate register: */
637 cond
->regs
[0]->num
= regid(REG_P0
, 0);
642 static struct ir3_instruction
*
643 create_uniform(struct ir3_context
*ctx
, unsigned n
)
645 struct ir3_instruction
*mov
;
647 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
648 /* TODO get types right? */
649 mov
->cat1
.src_type
= TYPE_F32
;
650 mov
->cat1
.dst_type
= TYPE_F32
;
651 ir3_reg_create(mov
, 0, 0);
652 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
657 static struct ir3_instruction
*
658 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
659 struct ir3_instruction
*address
)
661 struct ir3_instruction
*mov
;
663 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
664 mov
->cat1
.src_type
= TYPE_U32
;
665 mov
->cat1
.dst_type
= TYPE_U32
;
666 ir3_reg_create(mov
, 0, 0);
667 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
669 ir3_instr_set_address(mov
, address
);
674 static struct ir3_instruction
*
675 create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
678 struct ir3_block
*block
= ctx
->block
;
679 struct ir3_instruction
*collect
;
684 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
686 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
687 ir3_reg_create(collect
, 0, flags
); /* dst */
688 for (unsigned i
= 0; i
< arrsz
; i
++) {
689 struct ir3_instruction
*elem
= arr
[i
];
691 /* Since arrays are pre-colored in RA, we can't assume that
692 * things will end up in the right place. (Ie. if a collect
693 * joins elements from two different arrays.) So insert an
696 * We could possibly skip this if all the collected elements
697 * are contiguous elements in a single array.. not sure how
698 * likely that is to happen.
700 * Fixes a problem with glamor shaders, that in effect do
707 * color = texture2D(tex, texcoord);
709 * In this case, texcoord will end up as nir registers (which
710 * translate to ir3 array's of length 1. And we can't assume
711 * the two (or more) arrays will get allocated in consecutive
715 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
716 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
717 elem
= ir3_MOV(block
, elem
, type
);
720 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
721 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
727 static struct ir3_instruction
*
728 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
729 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
731 struct ir3_block
*block
= ctx
->block
;
732 struct ir3_instruction
*mov
;
733 struct ir3_register
*src
;
735 mov
= ir3_instr_create(block
, OPC_MOV
);
736 mov
->cat1
.src_type
= TYPE_U32
;
737 mov
->cat1
.dst_type
= TYPE_U32
;
738 ir3_reg_create(mov
, 0, 0);
739 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
740 src
->instr
= collect
;
742 src
->array
.offset
= n
;
744 ir3_instr_set_address(mov
, address
);
749 static struct ir3_instruction
*
750 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
752 struct ir3_instruction
*in
;
754 in
= ir3_instr_create(block
, OPC_META_INPUT
);
755 in
->inout
.block
= block
;
756 ir3_reg_create(in
, n
, 0);
758 in
->regs
[0]->wrmask
= compmask
;
763 static struct ir3_instruction
*
764 create_input(struct ir3_block
*block
, unsigned n
)
766 return create_input_compmask(block
, n
, 0x1);
769 static struct ir3_instruction
*
770 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
772 struct ir3_block
*block
= ctx
->block
;
773 struct ir3_instruction
*instr
;
774 /* actual inloc is assigned and fixed up later: */
775 struct ir3_instruction
*inloc
= create_immed(block
, 0);
778 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
779 instr
->cat6
.type
= TYPE_U32
;
780 instr
->cat6
.iim_val
= 1;
782 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
783 instr
->regs
[2]->wrmask
= 0x3;
789 static struct ir3_instruction
*
790 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
792 struct ir3_block
*block
= ctx
->block
;
793 struct ir3_instruction
*instr
;
795 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
797 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
802 /* for frag_coord, we get unsigned values.. we need
803 * to subtract (integer) 8 and divide by 16 (right-
804 * shift by 4) then convert to float:
808 * mov.u32f32 dst, tmp
811 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
812 create_immed(block
, 8), 0);
813 instr
= ir3_SHR_B(block
, instr
, 0,
814 create_immed(block
, 4), 0);
815 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
821 /* seems that we can use these as-is: */
822 return ctx
->frag_coord
[comp
];
826 static struct ir3_instruction
*
827 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
829 /* first four vec4 sysval's reserved for UBOs: */
830 /* NOTE: dp is in scalar, but there can be >4 dp components: */
831 unsigned n
= ctx
->so
->constbase
.driver_param
;
832 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
833 return create_uniform(ctx
, r
);
836 /* helper for instructions that produce multiple consecutive scalar
837 * outputs which need to have a split/fanout meta instruction inserted
840 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
841 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
843 struct ir3_instruction
*prev
= NULL
;
845 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
850 for (int i
= 0, j
= 0; i
< n
; i
++) {
851 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
852 ir3_reg_create(split
, 0, IR3_REG_SSA
);
853 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
854 split
->fo
.off
= i
+ base
;
857 split
->cp
.left
= prev
;
858 split
->cp
.left_cnt
++;
859 prev
->cp
.right
= split
;
860 prev
->cp
.right_cnt
++;
864 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
870 * Adreno uses uint rather than having dedicated bool type,
871 * which (potentially) requires some conversion, in particular
872 * when using output of an bool instr to int input, or visa
876 * -------+---------+-------+-
880 * To convert from an adreno bool (uint) to nir, use:
882 * absneg.s dst, (neg)src
884 * To convert back in the other direction:
886 * absneg.s dst, (abs)arc
888 * The CP step can clean up the absneg.s that cancel each other
889 * out, and with a slight bit of extra cleverness (to recognize
890 * the instructions which produce either a 0 or 1) can eliminate
891 * the absneg.s's completely when an instruction that wants
892 * 0/1 consumes the result. For example, when a nir 'bcsel'
893 * consumes the result of 'feq'. So we should be able to get by
894 * without a boolean resolve step, and without incuring any
895 * extra penalty in instruction count.
898 /* NIR bool -> native (adreno): */
899 static struct ir3_instruction
*
900 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
902 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
905 /* native (adreno) -> NIR bool: */
906 static struct ir3_instruction
*
907 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
909 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
913 * alu/sfu instructions:
917 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
919 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
920 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
921 struct ir3_block
*b
= ctx
->block
;
922 unsigned dst_sz
, wrmask
;
924 if (alu
->dest
.dest
.is_ssa
) {
925 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
926 wrmask
= (1 << dst_sz
) - 1;
928 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
929 wrmask
= alu
->dest
.write_mask
;
932 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
934 /* Vectors are special in that they have non-scalarized writemasks,
935 * and just take the first swizzle channel for each argument in
936 * order into each writemask channel.
938 if ((alu
->op
== nir_op_vec2
) ||
939 (alu
->op
== nir_op_vec3
) ||
940 (alu
->op
== nir_op_vec4
)) {
942 for (int i
= 0; i
< info
->num_inputs
; i
++) {
943 nir_alu_src
*asrc
= &alu
->src
[i
];
945 compile_assert(ctx
, !asrc
->abs
);
946 compile_assert(ctx
, !asrc
->negate
);
948 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
950 src
[i
] = create_immed(ctx
->block
, 0);
951 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
954 put_dst(ctx
, &alu
->dest
.dest
);
958 /* We also get mov's with more than one component for mov's so
959 * handle those specially:
961 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
962 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
963 nir_alu_src
*asrc
= &alu
->src
[0];
964 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
966 for (unsigned i
= 0; i
< dst_sz
; i
++) {
967 if (wrmask
& (1 << i
)) {
968 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
974 put_dst(ctx
, &alu
->dest
.dest
);
978 /* General case: We can just grab the one used channel per src. */
979 for (int i
= 0; i
< info
->num_inputs
; i
++) {
980 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
981 nir_alu_src
*asrc
= &alu
->src
[i
];
983 compile_assert(ctx
, !asrc
->abs
);
984 compile_assert(ctx
, !asrc
->negate
);
986 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
988 compile_assert(ctx
, src
[i
]);
993 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
996 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
999 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
1002 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
1005 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
1006 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1007 dst
[0] = ir3_n2b(b
, dst
[0]);
1010 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
1013 dst
[0] = ir3_b2n(b
, src
[0]);
1016 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1017 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1018 dst
[0] = ir3_n2b(b
, dst
[0]);
1022 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1025 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1028 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1031 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1034 /* if there is just a single use of the src, and it supports
1035 * (sat) bit, we can just fold the (sat) flag back to the
1036 * src instruction and create a mov. This is easier for cp
1039 * TODO probably opc_cat==4 is ok too
1041 if (alu
->src
[0].src
.is_ssa
&&
1042 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
1043 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
1044 src
[0]->flags
|= IR3_INSTR_SAT
;
1045 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
1047 /* otherwise generate a max.f that saturates.. blob does
1048 * similar (generating a cat2 mov using max.f)
1050 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
1051 dst
[0]->flags
|= IR3_INSTR_SAT
;
1055 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1058 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1061 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1064 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1067 dst
[0] = ir3_DSX(b
, src
[0], 0);
1068 dst
[0]->cat5
.type
= TYPE_F32
;
1071 dst
[0] = ir3_DSY(b
, src
[0], 0);
1072 dst
[0]->cat5
.type
= TYPE_F32
;
1076 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1077 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1078 dst
[0] = ir3_n2b(b
, dst
[0]);
1081 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1082 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1083 dst
[0] = ir3_n2b(b
, dst
[0]);
1086 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1087 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1088 dst
[0] = ir3_n2b(b
, dst
[0]);
1091 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1092 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1093 dst
[0] = ir3_n2b(b
, dst
[0]);
1096 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1099 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1102 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1104 case nir_op_fround_even
:
1105 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1108 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1112 dst
[0] = ir3_SIN(b
, src
[0], 0);
1115 dst
[0] = ir3_COS(b
, src
[0], 0);
1118 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1121 dst
[0] = ir3_RCP(b
, src
[0], 0);
1124 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1127 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1130 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1134 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1137 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1140 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1143 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1146 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1149 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1152 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1156 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1157 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1158 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1159 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1161 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1162 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1163 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1166 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1169 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1172 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1175 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1178 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1180 case nir_op_isign
: {
1181 /* maybe this would be sane to lower in nir.. */
1182 struct ir3_instruction
*neg
, *pos
;
1184 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1185 neg
->cat2
.condition
= IR3_COND_LT
;
1187 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1188 pos
->cat2
.condition
= IR3_COND_GT
;
1190 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1195 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1198 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1201 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1204 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1205 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1206 dst
[0] = ir3_n2b(b
, dst
[0]);
1209 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1210 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1211 dst
[0] = ir3_n2b(b
, dst
[0]);
1214 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1215 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1216 dst
[0] = ir3_n2b(b
, dst
[0]);
1219 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1220 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1221 dst
[0] = ir3_n2b(b
, dst
[0]);
1224 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1225 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1226 dst
[0] = ir3_n2b(b
, dst
[0]);
1229 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1230 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1231 dst
[0] = ir3_n2b(b
, dst
[0]);
1235 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1238 case nir_op_bit_count
:
1239 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1241 case nir_op_ifind_msb
: {
1242 struct ir3_instruction
*cmp
;
1243 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1244 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1245 cmp
->cat2
.condition
= IR3_COND_GE
;
1246 dst
[0] = ir3_SEL_B32(b
,
1247 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1251 case nir_op_ufind_msb
:
1252 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1253 dst
[0] = ir3_SEL_B32(b
,
1254 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1255 src
[0], 0, dst
[0], 0);
1257 case nir_op_find_lsb
:
1258 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1259 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1261 case nir_op_bitfield_reverse
:
1262 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1266 compile_error(ctx
, "Unhandled ALU op: %s\n",
1267 nir_op_infos
[alu
->op
].name
);
1271 put_dst(ctx
, &alu
->dest
.dest
);
1274 /* handles direct/indirect UBO reads: */
1276 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1277 struct ir3_instruction
**dst
)
1279 struct ir3_block
*b
= ctx
->block
;
1280 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1281 nir_const_value
*const_offset
;
1282 /* UBO addresses are the first driver params: */
1283 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1284 const unsigned ptrsz
= pointer_size(ctx
);
1288 /* First src is ubo index, which could either be an immed or not: */
1289 src0
= get_src(ctx
, &intr
->src
[0])[0];
1290 if (is_same_type_mov(src0
) &&
1291 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1292 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1293 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1295 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1296 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1299 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1302 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1304 off
+= const_offset
->u32
[0];
1306 /* For load_ubo_indirect, second src is indirect offset: */
1307 src1
= get_src(ctx
, &intr
->src
[1])[0];
1309 /* and add offset to addr: */
1310 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1313 /* if offset is to large to encode in the ldg, split it out: */
1314 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1315 /* split out the minimal amount to improve the odds that
1316 * cp can fit the immediate in the add.s instruction:
1318 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1319 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1324 struct ir3_instruction
*carry
;
1326 /* handle 32b rollover, ie:
1327 * if (addr < base_lo)
1330 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1331 carry
->cat2
.condition
= IR3_COND_LT
;
1332 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1334 addr
= create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1337 for (int i
= 0; i
< intr
->num_components
; i
++) {
1338 struct ir3_instruction
*load
=
1339 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1340 load
->cat6
.type
= TYPE_U32
;
1341 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1346 /* src[] = { buffer_index, offset }. No const_index */
1348 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1349 struct ir3_instruction
**dst
)
1351 struct ir3_block
*b
= ctx
->block
;
1352 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1353 nir_const_value
*const_offset
;
1355 /* can this be non-const buffer_index? how do we handle that? */
1356 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1357 compile_assert(ctx
, const_offset
);
1359 offset
= get_src(ctx
, &intr
->src
[1])[0];
1361 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1362 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1366 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1368 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1370 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1371 ldgb
->cat6
.iim_val
= intr
->num_components
;
1373 ldgb
->cat6
.type
= TYPE_U32
;
1374 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1375 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1377 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1380 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1382 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1384 struct ir3_block
*b
= ctx
->block
;
1385 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1386 nir_const_value
*const_offset
;
1387 /* TODO handle wrmask properly, see _store_shared().. but I think
1388 * it is more a PITA than that, since blob ends up loading the
1389 * masked components and writing them back out.
1391 unsigned wrmask
= intr
->const_index
[0];
1392 unsigned ncomp
= ffs(~wrmask
) - 1;
1394 /* can this be non-const buffer_index? how do we handle that? */
1395 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1396 compile_assert(ctx
, const_offset
);
1398 offset
= get_src(ctx
, &intr
->src
[2])[0];
1400 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1403 src0
= create_collect(ctx
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1404 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1405 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1410 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1411 src0
, 0, src1
, 0, src2
, 0);
1412 stgb
->cat6
.iim_val
= ncomp
;
1414 stgb
->cat6
.type
= TYPE_U32
;
1415 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1416 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1418 array_insert(b
, b
->keeps
, stgb
);
1421 /* src[] = { block_index } */
1423 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1424 struct ir3_instruction
**dst
)
1426 /* SSBO size stored as a const starting at ssbo_sizes: */
1427 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1428 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1429 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1431 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1433 dst
[0] = create_uniform(ctx
, idx
);
1437 * SSBO atomic intrinsics
1439 * All of the SSBO atomic memory operations read a value from memory,
1440 * compute a new value using one of the operations below, write the new
1441 * value to memory, and return the original value read.
1443 * All operations take 3 sources except CompSwap that takes 4. These
1444 * sources represent:
1446 * 0: The SSBO buffer index.
1447 * 1: The offset into the SSBO buffer of the variable that the atomic
1448 * operation will operate on.
1449 * 2: The data parameter to the atomic function (i.e. the value to add
1450 * in ssbo_atomic_add, etc).
1451 * 3: For CompSwap only: the second data parameter.
1453 static struct ir3_instruction
*
1454 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1456 struct ir3_block
*b
= ctx
->block
;
1457 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1458 nir_const_value
*const_offset
;
1459 type_t type
= TYPE_U32
;
1461 /* can this be non-const buffer_index? how do we handle that? */
1462 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1463 compile_assert(ctx
, const_offset
);
1464 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1466 offset
= get_src(ctx
, &intr
->src
[1])[0];
1468 /* src0 is data (or uvec2(data, compare))
1470 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1472 * Note that nir already multiplies the offset by four
1474 src0
= get_src(ctx
, &intr
->src
[2])[0];
1475 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1476 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1481 switch (intr
->intrinsic
) {
1482 case nir_intrinsic_ssbo_atomic_add
:
1483 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1485 case nir_intrinsic_ssbo_atomic_imin
:
1486 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1489 case nir_intrinsic_ssbo_atomic_umin
:
1490 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1492 case nir_intrinsic_ssbo_atomic_imax
:
1493 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1496 case nir_intrinsic_ssbo_atomic_umax
:
1497 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1499 case nir_intrinsic_ssbo_atomic_and
:
1500 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1502 case nir_intrinsic_ssbo_atomic_or
:
1503 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1505 case nir_intrinsic_ssbo_atomic_xor
:
1506 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1508 case nir_intrinsic_ssbo_atomic_exchange
:
1509 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1511 case nir_intrinsic_ssbo_atomic_comp_swap
:
1512 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1513 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1515 get_src(ctx
, &intr
->src
[3])[0],
1517 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1523 atomic
->cat6
.iim_val
= 1;
1525 atomic
->cat6
.type
= type
;
1526 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1527 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1529 /* even if nothing consume the result, we can't DCE the instruction: */
1530 array_insert(b
, b
->keeps
, atomic
);
1535 /* src[] = { offset }. const_index[] = { base } */
1537 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1538 struct ir3_instruction
**dst
)
1540 struct ir3_block
*b
= ctx
->block
;
1541 struct ir3_instruction
*ldl
, *offset
;
1544 offset
= get_src(ctx
, &intr
->src
[0])[0];
1545 base
= nir_intrinsic_base(intr
);
1547 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1548 ldl
->cat6
.src_offset
= base
;
1549 ldl
->cat6
.type
= utype_dst(intr
->dest
);
1550 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1552 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1553 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1555 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1558 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1560 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1562 struct ir3_block
*b
= ctx
->block
;
1563 struct ir3_instruction
*stl
, *offset
;
1564 struct ir3_instruction
* const *value
;
1565 unsigned base
, wrmask
;
1567 value
= get_src(ctx
, &intr
->src
[0]);
1568 offset
= get_src(ctx
, &intr
->src
[1])[0];
1570 base
= nir_intrinsic_base(intr
);
1571 wrmask
= nir_intrinsic_write_mask(intr
);
1573 /* Combine groups of consecutive enabled channels in one write
1574 * message. We use ffs to find the first enabled channel and then ffs on
1575 * the bit-inverse, down-shifted writemask to determine the length of
1576 * the block of enabled bits.
1578 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1581 unsigned first_component
= ffs(wrmask
) - 1;
1582 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1584 stl
= ir3_STL(b
, offset
, 0,
1585 create_collect(ctx
, &value
[first_component
], length
), 0,
1586 create_immed(b
, length
), 0);
1587 stl
->cat6
.dst_offset
= first_component
+ base
;
1588 stl
->cat6
.type
= utype_src(intr
->src
[0]);
1589 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1590 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1592 array_insert(b
, b
->keeps
, stl
);
1594 /* Clear the bits in the writemask that we just wrote, then try
1595 * again to see if more channels are left.
1597 wrmask
&= (15 << (first_component
+ length
));
1602 * CS shared variable atomic intrinsics
1604 * All of the shared variable atomic memory operations read a value from
1605 * memory, compute a new value using one of the operations below, write the
1606 * new value to memory, and return the original value read.
1608 * All operations take 2 sources except CompSwap that takes 3. These
1609 * sources represent:
1611 * 0: The offset into the shared variable storage region that the atomic
1612 * operation will operate on.
1613 * 1: The data parameter to the atomic function (i.e. the value to add
1614 * in shared_atomic_add, etc).
1615 * 2: For CompSwap only: the second data parameter.
1617 static struct ir3_instruction
*
1618 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1620 struct ir3_block
*b
= ctx
->block
;
1621 struct ir3_instruction
*atomic
, *src0
, *src1
;
1622 type_t type
= TYPE_U32
;
1624 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1625 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1627 switch (intr
->intrinsic
) {
1628 case nir_intrinsic_shared_atomic_add
:
1629 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1631 case nir_intrinsic_shared_atomic_imin
:
1632 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1635 case nir_intrinsic_shared_atomic_umin
:
1636 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1638 case nir_intrinsic_shared_atomic_imax
:
1639 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1642 case nir_intrinsic_shared_atomic_umax
:
1643 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1645 case nir_intrinsic_shared_atomic_and
:
1646 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1648 case nir_intrinsic_shared_atomic_or
:
1649 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1651 case nir_intrinsic_shared_atomic_xor
:
1652 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1654 case nir_intrinsic_shared_atomic_exchange
:
1655 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1657 case nir_intrinsic_shared_atomic_comp_swap
:
1658 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1659 src1
= create_collect(ctx
, (struct ir3_instruction
*[]){
1660 get_src(ctx
, &intr
->src
[2])[0],
1663 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1669 atomic
->cat6
.iim_val
= 1;
1671 atomic
->cat6
.type
= type
;
1672 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1673 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1675 /* even if nothing consume the result, we can't DCE the instruction: */
1676 array_insert(b
, b
->keeps
, atomic
);
1681 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1682 * state block (for load). To simplify things, invert the image id and
1683 * map it from end of state block, ie. image 0 becomes num-1, image 1
1684 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1685 * state when switching shaders.
1687 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1688 * coded. Also, since all the gl shader stages (ie. everything but CS)
1689 * share the same SSBO/image state block, this might require some more
1690 * logic if we supported images in anything other than FS..
1693 get_image_slot(struct ir3_context
*ctx
, const nir_variable
*var
)
1695 /* TODO figure out real limit per generation, and don't hardcode: */
1696 const unsigned max_samplers
= 16;
1697 return max_samplers
- var
->data
.driver_location
- 1;
1701 get_image_coords(const nir_variable
*var
)
1703 switch (glsl_get_sampler_dim(glsl_without_array(var
->type
))) {
1704 case GLSL_SAMPLER_DIM_1D
:
1705 case GLSL_SAMPLER_DIM_BUF
:
1708 case GLSL_SAMPLER_DIM_2D
:
1709 case GLSL_SAMPLER_DIM_RECT
:
1710 case GLSL_SAMPLER_DIM_EXTERNAL
:
1711 case GLSL_SAMPLER_DIM_MS
:
1713 case GLSL_SAMPLER_DIM_3D
:
1714 case GLSL_SAMPLER_DIM_CUBE
:
1717 unreachable("bad sampler dim");
1723 get_image_type(const nir_variable
*var
)
1725 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1726 case GLSL_TYPE_UINT
:
1730 case GLSL_TYPE_FLOAT
:
1733 unreachable("bad sampler type.");
1738 static struct ir3_instruction
*
1739 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1740 struct ir3_instruction
* const *coords
, bool byteoff
)
1742 struct ir3_block
*b
= ctx
->block
;
1743 struct ir3_instruction
*offset
;
1744 unsigned ncoords
= get_image_coords(var
);
1746 /* to calculate the byte offset (yes, uggg) we need (up to) three
1747 * const values to know the bytes per pixel, and y and z stride:
1749 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1750 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1752 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1753 (1 << var
->data
.driver_location
));
1755 /* offset = coords.x * bytes_per_pixel: */
1756 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1758 /* offset += coords.y * y_pitch: */
1759 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1760 coords
[1], 0, offset
, 0);
1763 /* offset += coords.z * z_pitch: */
1764 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1765 coords
[2], 0, offset
, 0);
1769 /* Some cases, like atomics, seem to use dword offset instead
1770 * of byte offsets.. blob just puts an extra shr.b in there
1773 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1776 return create_collect(ctx
, (struct ir3_instruction
*[]){
1782 /* src[] = { coord, sample_index }. const_index[] = {} */
1784 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1785 struct ir3_instruction
**dst
)
1787 struct ir3_block
*b
= ctx
->block
;
1788 const nir_variable
*var
= intr
->variables
[0]->var
;
1789 struct ir3_instruction
*sam
;
1790 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1791 unsigned ncoords
= get_image_coords(var
);
1792 unsigned tex_idx
= get_image_slot(ctx
, var
);
1793 type_t type
= get_image_type(var
);
1797 flags
|= IR3_INSTR_3D
;
1799 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1800 tex_idx
, tex_idx
, create_collect(ctx
, coords
, ncoords
), NULL
);
1802 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1803 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1805 split_dest(b
, dst
, sam
, 0, 4);
1808 /* src[] = { coord, sample_index, value }. const_index[] = {} */
1810 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1812 struct ir3_block
*b
= ctx
->block
;
1813 const nir_variable
*var
= intr
->variables
[0]->var
;
1814 struct ir3_instruction
*stib
, *offset
;
1815 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
1816 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1817 unsigned ncoords
= get_image_coords(var
);
1818 unsigned tex_idx
= get_image_slot(ctx
, var
);
1822 * src2 is 64b byte offset
1825 offset
= get_image_offset(ctx
, var
, coords
, true);
1827 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1828 * too and takes a dword offset.. not quite sure yet why blob uses
1829 * one over the other in various cases.
1832 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
1833 create_collect(ctx
, value
, 4), 0,
1834 create_collect(ctx
, coords
, ncoords
), 0,
1836 stib
->cat6
.iim_val
= 4;
1837 stib
->cat6
.d
= ncoords
;
1838 stib
->cat6
.type
= get_image_type(var
);
1839 stib
->cat6
.typed
= true;
1840 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1841 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1843 array_insert(b
, b
->keeps
, stib
);
1847 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1848 struct ir3_instruction
**dst
)
1850 struct ir3_block
*b
= ctx
->block
;
1851 const nir_variable
*var
= intr
->variables
[0]->var
;
1852 unsigned ncoords
= get_image_coords(var
);
1853 unsigned tex_idx
= get_image_slot(ctx
, var
);
1854 struct ir3_instruction
*sam
, *lod
;
1858 flags
= IR3_INSTR_3D
;
1860 lod
= create_immed(b
, 0);
1861 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1862 tex_idx
, tex_idx
, lod
, NULL
);
1864 split_dest(b
, dst
, sam
, 0, ncoords
);
1867 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
1868 static struct ir3_instruction
*
1869 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1871 struct ir3_block
*b
= ctx
->block
;
1872 const nir_variable
*var
= intr
->variables
[0]->var
;
1873 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
1874 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1875 unsigned ncoords
= get_image_coords(var
);
1877 image
= create_immed(b
, get_image_slot(ctx
, var
));
1879 /* src0 is value (or uvec2(value, compare))
1881 * src2 is 64b byte offset
1883 src0
= get_src(ctx
, &intr
->src
[2])[0];
1884 src1
= create_collect(ctx
, coords
, ncoords
);
1885 src2
= get_image_offset(ctx
, var
, coords
, false);
1887 switch (intr
->intrinsic
) {
1888 case nir_intrinsic_image_var_atomic_add
:
1889 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1891 case nir_intrinsic_image_var_atomic_min
:
1892 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1894 case nir_intrinsic_image_var_atomic_max
:
1895 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1897 case nir_intrinsic_image_var_atomic_and
:
1898 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1900 case nir_intrinsic_image_var_atomic_or
:
1901 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1903 case nir_intrinsic_image_var_atomic_xor
:
1904 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1906 case nir_intrinsic_image_var_atomic_exchange
:
1907 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1909 case nir_intrinsic_image_var_atomic_comp_swap
:
1910 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1911 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1913 get_src(ctx
, &intr
->src
[3])[0],
1915 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1921 atomic
->cat6
.iim_val
= 1;
1922 atomic
->cat6
.d
= ncoords
;
1923 atomic
->cat6
.type
= get_image_type(var
);
1924 atomic
->cat6
.typed
= true;
1925 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1926 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1928 /* even if nothing consume the result, we can't DCE the instruction: */
1929 array_insert(b
, b
->keeps
, atomic
);
1935 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1937 struct ir3_block
*b
= ctx
->block
;
1938 struct ir3_instruction
*barrier
;
1940 switch (intr
->intrinsic
) {
1941 case nir_intrinsic_barrier
:
1942 barrier
= ir3_BAR(b
);
1943 barrier
->cat7
.g
= true;
1944 barrier
->cat7
.l
= true;
1945 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1946 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1948 case nir_intrinsic_memory_barrier
:
1949 barrier
= ir3_FENCE(b
);
1950 barrier
->cat7
.g
= true;
1951 barrier
->cat7
.r
= true;
1952 barrier
->cat7
.w
= true;
1953 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1954 IR3_BARRIER_BUFFER_W
;
1955 barrier
->barrier_conflict
=
1956 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1957 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1959 case nir_intrinsic_memory_barrier_atomic_counter
:
1960 case nir_intrinsic_memory_barrier_buffer
:
1961 barrier
= ir3_FENCE(b
);
1962 barrier
->cat7
.g
= true;
1963 barrier
->cat7
.r
= true;
1964 barrier
->cat7
.w
= true;
1965 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1966 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1967 IR3_BARRIER_BUFFER_W
;
1969 case nir_intrinsic_memory_barrier_image
:
1970 // TODO double check if this should have .g set
1971 barrier
= ir3_FENCE(b
);
1972 barrier
->cat7
.g
= true;
1973 barrier
->cat7
.r
= true;
1974 barrier
->cat7
.w
= true;
1975 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1976 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1977 IR3_BARRIER_IMAGE_W
;
1979 case nir_intrinsic_memory_barrier_shared
:
1980 barrier
= ir3_FENCE(b
);
1981 barrier
->cat7
.g
= true;
1982 barrier
->cat7
.l
= true;
1983 barrier
->cat7
.r
= true;
1984 barrier
->cat7
.w
= true;
1985 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1986 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1987 IR3_BARRIER_SHARED_W
;
1989 case nir_intrinsic_group_memory_barrier
:
1990 barrier
= ir3_FENCE(b
);
1991 barrier
->cat7
.g
= true;
1992 barrier
->cat7
.l
= true;
1993 barrier
->cat7
.r
= true;
1994 barrier
->cat7
.w
= true;
1995 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1996 IR3_BARRIER_IMAGE_W
|
1997 IR3_BARRIER_BUFFER_W
;
1998 barrier
->barrier_conflict
=
1999 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
2000 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2001 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2007 /* make sure barrier doesn't get DCE'd */
2008 array_insert(b
, b
->keeps
, barrier
);
2011 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
2012 gl_system_value slot
, unsigned compmask
,
2013 struct ir3_instruction
*instr
)
2015 struct ir3_shader_variant
*so
= ctx
->so
;
2016 unsigned r
= regid(so
->inputs_count
, 0);
2017 unsigned n
= so
->inputs_count
++;
2019 so
->inputs
[n
].sysval
= true;
2020 so
->inputs
[n
].slot
= slot
;
2021 so
->inputs
[n
].compmask
= compmask
;
2022 so
->inputs
[n
].regid
= r
;
2023 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
2026 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
2027 ctx
->ir
->inputs
[r
] = instr
;
2030 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
2031 struct ir3_instruction
*instr
)
2033 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
2037 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2039 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
2040 struct ir3_instruction
**dst
;
2041 struct ir3_instruction
* const *src
;
2042 struct ir3_block
*b
= ctx
->block
;
2043 nir_const_value
*const_offset
;
2046 if (info
->has_dest
) {
2047 unsigned n
= nir_intrinsic_dest_components(intr
);
2048 dst
= get_dst(ctx
, &intr
->dest
, n
);
2053 switch (intr
->intrinsic
) {
2054 case nir_intrinsic_load_uniform
:
2055 idx
= nir_intrinsic_base(intr
);
2056 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2058 idx
+= const_offset
->u32
[0];
2059 for (int i
= 0; i
< intr
->num_components
; i
++) {
2060 unsigned n
= idx
* 4 + i
;
2061 dst
[i
] = create_uniform(ctx
, n
);
2064 src
= get_src(ctx
, &intr
->src
[0]);
2065 for (int i
= 0; i
< intr
->num_components
; i
++) {
2066 int n
= idx
* 4 + i
;
2067 dst
[i
] = create_uniform_indirect(ctx
, n
,
2068 get_addr(ctx
, src
[0], 4));
2070 /* NOTE: if relative addressing is used, we set
2071 * constlen in the compiler (to worst-case value)
2072 * since we don't know in the assembler what the max
2073 * addr reg value can be:
2075 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2078 case nir_intrinsic_load_ubo
:
2079 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2081 case nir_intrinsic_load_input
:
2082 idx
= nir_intrinsic_base(intr
);
2083 comp
= nir_intrinsic_component(intr
);
2084 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2086 idx
+= const_offset
->u32
[0];
2087 for (int i
= 0; i
< intr
->num_components
; i
++) {
2088 unsigned n
= idx
* 4 + i
+ comp
;
2089 dst
[i
] = ctx
->ir
->inputs
[n
];
2092 src
= get_src(ctx
, &intr
->src
[0]);
2093 struct ir3_instruction
*collect
=
2094 create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2095 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2096 for (int i
= 0; i
< intr
->num_components
; i
++) {
2097 unsigned n
= idx
* 4 + i
+ comp
;
2098 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2103 case nir_intrinsic_load_ssbo
:
2104 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2106 case nir_intrinsic_store_ssbo
:
2107 emit_intrinsic_store_ssbo(ctx
, intr
);
2109 case nir_intrinsic_get_buffer_size
:
2110 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2112 case nir_intrinsic_ssbo_atomic_add
:
2113 case nir_intrinsic_ssbo_atomic_imin
:
2114 case nir_intrinsic_ssbo_atomic_umin
:
2115 case nir_intrinsic_ssbo_atomic_imax
:
2116 case nir_intrinsic_ssbo_atomic_umax
:
2117 case nir_intrinsic_ssbo_atomic_and
:
2118 case nir_intrinsic_ssbo_atomic_or
:
2119 case nir_intrinsic_ssbo_atomic_xor
:
2120 case nir_intrinsic_ssbo_atomic_exchange
:
2121 case nir_intrinsic_ssbo_atomic_comp_swap
:
2122 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2124 case nir_intrinsic_load_shared
:
2125 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2127 case nir_intrinsic_store_shared
:
2128 emit_intrinsic_store_shared(ctx
, intr
);
2130 case nir_intrinsic_shared_atomic_add
:
2131 case nir_intrinsic_shared_atomic_imin
:
2132 case nir_intrinsic_shared_atomic_umin
:
2133 case nir_intrinsic_shared_atomic_imax
:
2134 case nir_intrinsic_shared_atomic_umax
:
2135 case nir_intrinsic_shared_atomic_and
:
2136 case nir_intrinsic_shared_atomic_or
:
2137 case nir_intrinsic_shared_atomic_xor
:
2138 case nir_intrinsic_shared_atomic_exchange
:
2139 case nir_intrinsic_shared_atomic_comp_swap
:
2140 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2142 case nir_intrinsic_image_var_load
:
2143 emit_intrinsic_load_image(ctx
, intr
, dst
);
2145 case nir_intrinsic_image_var_store
:
2146 emit_intrinsic_store_image(ctx
, intr
);
2148 case nir_intrinsic_image_var_size
:
2149 emit_intrinsic_image_size(ctx
, intr
, dst
);
2151 case nir_intrinsic_image_var_atomic_add
:
2152 case nir_intrinsic_image_var_atomic_min
:
2153 case nir_intrinsic_image_var_atomic_max
:
2154 case nir_intrinsic_image_var_atomic_and
:
2155 case nir_intrinsic_image_var_atomic_or
:
2156 case nir_intrinsic_image_var_atomic_xor
:
2157 case nir_intrinsic_image_var_atomic_exchange
:
2158 case nir_intrinsic_image_var_atomic_comp_swap
:
2159 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2161 case nir_intrinsic_barrier
:
2162 case nir_intrinsic_memory_barrier
:
2163 case nir_intrinsic_group_memory_barrier
:
2164 case nir_intrinsic_memory_barrier_atomic_counter
:
2165 case nir_intrinsic_memory_barrier_buffer
:
2166 case nir_intrinsic_memory_barrier_image
:
2167 case nir_intrinsic_memory_barrier_shared
:
2168 emit_intrinsic_barrier(ctx
, intr
);
2169 /* note that blk ptr no longer valid, make that obvious: */
2172 case nir_intrinsic_store_output
:
2173 idx
= nir_intrinsic_base(intr
);
2174 comp
= nir_intrinsic_component(intr
);
2175 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2176 compile_assert(ctx
, const_offset
!= NULL
);
2177 idx
+= const_offset
->u32
[0];
2179 src
= get_src(ctx
, &intr
->src
[0]);
2180 for (int i
= 0; i
< intr
->num_components
; i
++) {
2181 unsigned n
= idx
* 4 + i
+ comp
;
2182 ctx
->ir
->outputs
[n
] = src
[i
];
2185 case nir_intrinsic_load_first_vertex
:
2186 if (!ctx
->basevertex
) {
2187 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2188 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
2190 dst
[0] = ctx
->basevertex
;
2192 case nir_intrinsic_load_vertex_id_zero_base
:
2193 case nir_intrinsic_load_vertex_id
:
2194 if (!ctx
->vertex_id
) {
2195 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2196 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2197 ctx
->vertex_id
= create_input(b
, 0);
2198 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2200 dst
[0] = ctx
->vertex_id
;
2202 case nir_intrinsic_load_instance_id
:
2203 if (!ctx
->instance_id
) {
2204 ctx
->instance_id
= create_input(b
, 0);
2205 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2208 dst
[0] = ctx
->instance_id
;
2210 case nir_intrinsic_load_user_clip_plane
:
2211 idx
= nir_intrinsic_ucp_id(intr
);
2212 for (int i
= 0; i
< intr
->num_components
; i
++) {
2213 unsigned n
= idx
* 4 + i
;
2214 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2217 case nir_intrinsic_load_front_face
:
2218 if (!ctx
->frag_face
) {
2219 ctx
->so
->frag_face
= true;
2220 ctx
->frag_face
= create_input(b
, 0);
2221 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2223 /* for fragface, we get -1 for back and 0 for front. However this is
2224 * the inverse of what nir expects (where ~0 is true).
2226 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2227 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2229 case nir_intrinsic_load_local_invocation_id
:
2230 if (!ctx
->local_invocation_id
) {
2231 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2232 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2233 0x7, ctx
->local_invocation_id
);
2235 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2237 case nir_intrinsic_load_work_group_id
:
2238 if (!ctx
->work_group_id
) {
2239 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2240 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2241 0x7, ctx
->work_group_id
);
2242 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2244 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2246 case nir_intrinsic_load_num_work_groups
:
2247 for (int i
= 0; i
< intr
->num_components
; i
++) {
2248 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2251 case nir_intrinsic_load_local_group_size
:
2252 for (int i
= 0; i
< intr
->num_components
; i
++) {
2253 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2256 case nir_intrinsic_discard_if
:
2257 case nir_intrinsic_discard
: {
2258 struct ir3_instruction
*cond
, *kill
;
2260 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2261 /* conditional discard: */
2262 src
= get_src(ctx
, &intr
->src
[0]);
2263 cond
= ir3_b2n(b
, src
[0]);
2265 /* unconditional discard: */
2266 cond
= create_immed(b
, 1);
2269 /* NOTE: only cmps.*.* can write p0.x: */
2270 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2271 cond
->cat2
.condition
= IR3_COND_NE
;
2273 /* condition always goes in predicate register: */
2274 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2276 kill
= ir3_KILL(b
, cond
, 0);
2277 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2279 array_insert(b
, b
->keeps
, kill
);
2280 ctx
->so
->has_kill
= true;
2285 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2286 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2291 put_dst(ctx
, &intr
->dest
);
2295 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2297 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2298 instr
->def
.num_components
);
2299 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2301 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2302 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
.u32
[i
], type
);
2306 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2308 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2309 undef
->def
.num_components
);
2310 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2312 /* backend doesn't want undefined instructions, so just plug
2315 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2316 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2320 * texture fetch/sample instructions:
2324 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2326 unsigned coords
, flags
= 0;
2328 /* note: would use tex->coord_components.. except txs.. also,
2329 * since array index goes after shadow ref, we don't want to
2332 switch (tex
->sampler_dim
) {
2333 case GLSL_SAMPLER_DIM_1D
:
2334 case GLSL_SAMPLER_DIM_BUF
:
2337 case GLSL_SAMPLER_DIM_2D
:
2338 case GLSL_SAMPLER_DIM_RECT
:
2339 case GLSL_SAMPLER_DIM_EXTERNAL
:
2340 case GLSL_SAMPLER_DIM_MS
:
2343 case GLSL_SAMPLER_DIM_3D
:
2344 case GLSL_SAMPLER_DIM_CUBE
:
2346 flags
|= IR3_INSTR_3D
;
2349 unreachable("bad sampler_dim");
2352 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2353 flags
|= IR3_INSTR_S
;
2355 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2356 flags
|= IR3_INSTR_A
;
2363 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2365 struct ir3_block
*b
= ctx
->block
;
2366 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2367 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2368 struct ir3_instruction
*lod
, *compare
, *proj
;
2369 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2370 unsigned i
, coords
, flags
;
2371 unsigned nsrc0
= 0, nsrc1
= 0;
2375 coord
= off
= ddx
= ddy
= NULL
;
2376 lod
= proj
= compare
= NULL
;
2378 /* TODO: might just be one component for gathers? */
2379 dst
= get_dst(ctx
, &tex
->dest
, 4);
2381 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2382 switch (tex
->src
[i
].src_type
) {
2383 case nir_tex_src_coord
:
2384 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2386 case nir_tex_src_bias
:
2387 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2390 case nir_tex_src_lod
:
2391 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2394 case nir_tex_src_comparator
: /* shadow comparator */
2395 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2397 case nir_tex_src_projector
:
2398 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2401 case nir_tex_src_offset
:
2402 off
= get_src(ctx
, &tex
->src
[i
].src
);
2405 case nir_tex_src_ddx
:
2406 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2408 case nir_tex_src_ddy
:
2409 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2412 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2413 tex
->src
[i
].src_type
);
2419 case nir_texop_tex
: opc
= OPC_SAM
; break;
2420 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2421 case nir_texop_txl
: opc
= OPC_SAML
; break;
2422 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2423 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2424 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2426 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2427 * what blob does, seems gather is broken?), and a3xx did
2428 * not support it (but probably could also emulate).
2430 switch (tex
->component
) {
2431 case 0: opc
= OPC_GATHER4R
; break;
2432 case 1: opc
= OPC_GATHER4G
; break;
2433 case 2: opc
= OPC_GATHER4B
; break;
2434 case 3: opc
= OPC_GATHER4A
; break;
2437 case nir_texop_txf_ms
:
2439 case nir_texop_query_levels
:
2440 case nir_texop_texture_samples
:
2441 case nir_texop_samples_identical
:
2442 case nir_texop_txf_ms_mcs
:
2443 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2447 tex_info(tex
, &flags
, &coords
);
2450 * lay out the first argument in the proper order:
2451 * - actual coordinates first
2452 * - shadow reference
2455 * - starting at offset 4, dpdx.xy, dpdy.xy
2457 * bias/lod go into the second arg
2460 /* insert tex coords: */
2461 for (i
= 0; i
< coords
; i
++)
2466 /* scale up integer coords for TXF based on the LOD */
2467 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2469 for (i
= 0; i
< coords
; i
++)
2470 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2474 /* hw doesn't do 1d, so we treat it as 2d with
2475 * height of 1, and patch up the y coord.
2476 * TODO: y coord should be (int)0 in some cases..
2478 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2481 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2482 src0
[nsrc0
++] = compare
;
2484 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2485 struct ir3_instruction
*idx
= coord
[coords
];
2487 /* the array coord for cube arrays needs 0.5 added to it */
2488 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2489 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2491 src0
[nsrc0
++] = idx
;
2495 src0
[nsrc0
++] = proj
;
2496 flags
|= IR3_INSTR_P
;
2499 /* pad to 4, then ddx/ddy: */
2500 if (tex
->op
== nir_texop_txd
) {
2502 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2503 for (i
= 0; i
< coords
; i
++)
2504 src0
[nsrc0
++] = ddx
[i
];
2506 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2507 for (i
= 0; i
< coords
; i
++)
2508 src0
[nsrc0
++] = ddy
[i
];
2510 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2514 * second argument (if applicable):
2519 if (has_off
| has_lod
| has_bias
) {
2521 unsigned off_coords
= coords
;
2522 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2524 for (i
= 0; i
< off_coords
; i
++)
2525 src1
[nsrc1
++] = off
[i
];
2527 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2528 flags
|= IR3_INSTR_O
;
2531 if (has_lod
| has_bias
)
2532 src1
[nsrc1
++] = lod
;
2535 switch (tex
->dest_type
) {
2536 case nir_type_invalid
:
2537 case nir_type_float
:
2548 unreachable("bad dest_type");
2551 if (opc
== OPC_GETLOD
)
2554 unsigned tex_idx
= tex
->texture_index
;
2556 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2558 struct ir3_instruction
*col0
= create_collect(ctx
, src0
, nsrc0
);
2559 struct ir3_instruction
*col1
= create_collect(ctx
, src1
, nsrc1
);
2561 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2562 tex_idx
, tex_idx
, col0
, col1
);
2564 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2565 /* only need first 3 components: */
2566 sam
->regs
[0]->wrmask
= 0x7;
2567 split_dest(b
, dst
, sam
, 0, 3);
2569 /* we need to sample the alpha separately with a non-ASTC
2572 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2573 tex_idx
, tex_idx
, col0
, col1
);
2575 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2577 /* fixup .w component: */
2578 split_dest(b
, &dst
[3], sam
, 3, 1);
2580 /* normal (non-workaround) case: */
2581 split_dest(b
, dst
, sam
, 0, 4);
2584 /* GETLOD returns results in 4.8 fixed point */
2585 if (opc
== OPC_GETLOD
) {
2586 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2588 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2589 for (i
= 0; i
< 2; i
++) {
2590 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2595 put_dst(ctx
, &tex
->dest
);
2599 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2601 struct ir3_block
*b
= ctx
->block
;
2602 struct ir3_instruction
**dst
, *sam
;
2604 dst
= get_dst(ctx
, &tex
->dest
, 1);
2606 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2607 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2609 /* even though there is only one component, since it ends
2610 * up in .z rather than .x, we need a split_dest()
2612 split_dest(b
, dst
, sam
, 0, 3);
2614 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2615 * the value in TEX_CONST_0 is zero-based.
2617 if (ctx
->levels_add_one
)
2618 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2620 put_dst(ctx
, &tex
->dest
);
2624 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2626 struct ir3_block
*b
= ctx
->block
;
2627 struct ir3_instruction
**dst
, *sam
;
2628 struct ir3_instruction
*lod
;
2629 unsigned flags
, coords
;
2631 tex_info(tex
, &flags
, &coords
);
2633 /* Actually we want the number of dimensions, not coordinates. This
2634 * distinction only matters for cubes.
2636 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2639 dst
= get_dst(ctx
, &tex
->dest
, 4);
2641 compile_assert(ctx
, tex
->num_srcs
== 1);
2642 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2644 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2646 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2647 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2649 split_dest(b
, dst
, sam
, 0, 4);
2651 /* Array size actually ends up in .w rather than .z. This doesn't
2652 * matter for miplevel 0, but for higher mips the value in z is
2653 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2654 * returned, which means that we have to add 1 to it for arrays.
2656 if (tex
->is_array
) {
2657 if (ctx
->levels_add_one
) {
2658 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2660 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2664 put_dst(ctx
, &tex
->dest
);
2668 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2670 switch (jump
->type
) {
2671 case nir_jump_break
:
2672 case nir_jump_continue
:
2673 case nir_jump_return
:
2674 /* I *think* we can simply just ignore this, and use the
2675 * successor block link to figure out where we need to
2676 * jump to for break/continue
2680 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2686 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2688 switch (instr
->type
) {
2689 case nir_instr_type_alu
:
2690 emit_alu(ctx
, nir_instr_as_alu(instr
));
2692 case nir_instr_type_intrinsic
:
2693 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2695 case nir_instr_type_load_const
:
2696 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2698 case nir_instr_type_ssa_undef
:
2699 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2701 case nir_instr_type_tex
: {
2702 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2703 /* couple tex instructions get special-cased:
2707 emit_tex_txs(ctx
, tex
);
2709 case nir_texop_query_levels
:
2710 emit_tex_query_levels(ctx
, tex
);
2718 case nir_instr_type_jump
:
2719 emit_jump(ctx
, nir_instr_as_jump(instr
));
2721 case nir_instr_type_phi
:
2722 /* we have converted phi webs to regs in NIR by now */
2723 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2725 case nir_instr_type_call
:
2726 case nir_instr_type_parallel_copy
:
2727 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2732 static struct ir3_block
*
2733 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2735 struct ir3_block
*block
;
2736 struct hash_entry
*hentry
;
2737 struct set_entry
*sentry
;
2740 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2742 return hentry
->data
;
2744 block
= ir3_block_create(ctx
->ir
);
2745 block
->nblock
= nblock
;
2746 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2748 block
->predecessors_count
= nblock
->predecessors
->entries
;
2749 block
->predecessors
= ralloc_array_size(block
,
2750 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
2752 set_foreach(nblock
->predecessors
, sentry
) {
2753 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
2760 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2762 struct ir3_block
*block
= get_block(ctx
, nblock
);
2764 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2765 if (nblock
->successors
[i
]) {
2766 block
->successors
[i
] =
2767 get_block(ctx
, nblock
->successors
[i
]);
2772 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2774 /* re-emit addr register in each block if needed: */
2775 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2776 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2777 ctx
->addr_ht
[i
] = NULL
;
2780 nir_foreach_instr(instr
, nblock
) {
2781 emit_instr(ctx
, instr
);
2787 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2790 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2792 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2794 ctx
->block
->condition
=
2795 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2797 emit_cf_list(ctx
, &nif
->then_list
);
2798 emit_cf_list(ctx
, &nif
->else_list
);
2802 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2804 emit_cf_list(ctx
, &nloop
->body
);
2808 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2810 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2811 switch (node
->type
) {
2812 case nir_cf_node_block
:
2813 emit_block(ctx
, nir_cf_node_as_block(node
));
2815 case nir_cf_node_if
:
2816 emit_if(ctx
, nir_cf_node_as_if(node
));
2818 case nir_cf_node_loop
:
2819 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2821 case nir_cf_node_function
:
2822 compile_error(ctx
, "TODO\n");
2828 /* emit stream-out code. At this point, the current block is the original
2829 * (nir) end block, and nir ensures that all flow control paths terminate
2830 * into the end block. We re-purpose the original end block to generate
2831 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2832 * block holding stream-out write instructions, followed by the new end
2836 * p0.x = (vtxcnt < maxvtxcnt)
2837 * // succs: blockStreamOut, blockNewEnd
2840 * ... stream-out instructions ...
2841 * // succs: blockNewEnd
2847 emit_stream_out(struct ir3_context
*ctx
)
2849 struct ir3_shader_variant
*v
= ctx
->so
;
2850 struct ir3
*ir
= ctx
->ir
;
2851 struct pipe_stream_output_info
*strmout
=
2852 &ctx
->so
->shader
->stream_output
;
2853 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2854 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2855 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2857 /* create vtxcnt input in input block at top of shader,
2858 * so that it is seen as live over the entire duration
2861 vtxcnt
= create_input(ctx
->in_block
, 0);
2862 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2864 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2866 /* at this point, we are at the original 'end' block,
2867 * re-purpose this block to stream-out condition, then
2868 * append stream-out block and new-end block
2870 orig_end_block
= ctx
->block
;
2872 // TODO these blocks need to update predecessors..
2873 // maybe w/ store_global intrinsic, we could do this
2874 // stuff in nir->nir pass
2876 stream_out_block
= ir3_block_create(ir
);
2877 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2879 new_end_block
= ir3_block_create(ir
);
2880 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2882 orig_end_block
->successors
[0] = stream_out_block
;
2883 orig_end_block
->successors
[1] = new_end_block
;
2884 stream_out_block
->successors
[0] = new_end_block
;
2886 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2887 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2888 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2889 cond
->cat2
.condition
= IR3_COND_LT
;
2891 /* condition goes on previous block to the conditional,
2892 * since it is used to pick which of the two successor
2895 orig_end_block
->condition
= cond
;
2897 /* switch to stream_out_block to generate the stream-out
2900 ctx
->block
= stream_out_block
;
2902 /* Calculate base addresses based on vtxcnt. Instructions
2903 * generated for bases not used in following loop will be
2904 * stripped out in the backend.
2906 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2907 unsigned stride
= strmout
->stride
[i
];
2908 struct ir3_instruction
*base
, *off
;
2910 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2912 /* 24-bit should be enough: */
2913 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2914 create_immed(ctx
->block
, stride
* 4), 0);
2916 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2919 /* Generate the per-output store instructions: */
2920 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2921 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2922 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2923 struct ir3_instruction
*base
, *out
, *stg
;
2925 base
= bases
[strmout
->output
[i
].output_buffer
];
2926 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2928 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2929 create_immed(ctx
->block
, 1), 0);
2930 stg
->cat6
.type
= TYPE_U32
;
2931 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2933 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2937 /* and finally switch to the new_end_block: */
2938 ctx
->block
= new_end_block
;
2942 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2944 nir_metadata_require(impl
, nir_metadata_block_index
);
2946 emit_cf_list(ctx
, &impl
->body
);
2947 emit_block(ctx
, impl
->end_block
);
2949 /* at this point, we should have a single empty block,
2950 * into which we emit the 'end' instruction.
2952 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2954 /* If stream-out (aka transform-feedback) enabled, emit the
2955 * stream-out instructions, followed by a new empty block (into
2956 * which the 'end' instruction lands).
2958 * NOTE: it is done in this order, rather than inserting before
2959 * we emit end_block, because NIR guarantees that all blocks
2960 * flow into end_block, and that end_block has no successors.
2961 * So by re-purposing end_block as the first block of stream-
2962 * out, we guarantee that all exit paths flow into the stream-
2965 if ((ctx
->compiler
->gpu_id
< 500) &&
2966 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2967 !ctx
->so
->key
.binning_pass
) {
2968 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2969 emit_stream_out(ctx
);
2972 ir3_END(ctx
->block
);
2976 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2978 struct ir3_shader_variant
*so
= ctx
->so
;
2979 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2980 unsigned ncomp
= glsl_get_components(in
->type
);
2981 unsigned n
= in
->data
.driver_location
;
2982 unsigned slot
= in
->data
.location
;
2984 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2985 slot
, array_len
, ncomp
, n
);
2987 /* let's pretend things other than vec4 don't exist: */
2988 ncomp
= MAX2(ncomp
, 4);
2989 compile_assert(ctx
, ncomp
== 4);
2991 so
->inputs
[n
].slot
= slot
;
2992 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2993 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2994 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2996 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2997 for (int i
= 0; i
< ncomp
; i
++) {
2998 struct ir3_instruction
*instr
= NULL
;
2999 unsigned idx
= (n
* 4) + i
;
3001 if (slot
== VARYING_SLOT_POS
) {
3002 so
->inputs
[n
].bary
= false;
3003 so
->frag_coord
= true;
3004 instr
= create_frag_coord(ctx
, i
);
3005 } else if (slot
== VARYING_SLOT_PNTC
) {
3006 /* see for example st_get_generic_varying_index().. this is
3007 * maybe a bit mesa/st specific. But we need things to line
3008 * up for this in fdN_program:
3009 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
3010 * if (emit->sprite_coord_enable & texmask) {
3014 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
3015 so
->inputs
[n
].bary
= true;
3016 instr
= create_frag_input(ctx
, false);
3018 bool use_ldlv
= false;
3020 /* detect the special case for front/back colors where
3021 * we need to do flat vs smooth shading depending on
3024 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3026 case VARYING_SLOT_COL0
:
3027 case VARYING_SLOT_COL1
:
3028 case VARYING_SLOT_BFC0
:
3029 case VARYING_SLOT_BFC1
:
3030 so
->inputs
[n
].rasterflat
= true;
3037 if (ctx
->flat_bypass
) {
3038 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3039 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3043 so
->inputs
[n
].bary
= true;
3045 instr
= create_frag_input(ctx
, use_ldlv
);
3048 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3050 ctx
->ir
->inputs
[idx
] = instr
;
3052 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3053 for (int i
= 0; i
< ncomp
; i
++) {
3054 unsigned idx
= (n
* 4) + i
;
3055 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3056 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
3059 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3062 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3063 so
->total_in
+= ncomp
;
3068 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3070 struct ir3_shader_variant
*so
= ctx
->so
;
3071 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3072 unsigned ncomp
= glsl_get_components(out
->type
);
3073 unsigned n
= out
->data
.driver_location
;
3074 unsigned slot
= out
->data
.location
;
3077 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3078 slot
, array_len
, ncomp
, n
);
3080 /* let's pretend things other than vec4 don't exist: */
3081 ncomp
= MAX2(ncomp
, 4);
3082 compile_assert(ctx
, ncomp
== 4);
3084 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3086 case FRAG_RESULT_DEPTH
:
3087 comp
= 2; /* tgsi will write to .z component */
3088 so
->writes_pos
= true;
3090 case FRAG_RESULT_COLOR
:
3094 if (slot
>= FRAG_RESULT_DATA0
)
3096 compile_error(ctx
, "unknown FS output name: %s\n",
3097 gl_frag_result_name(slot
));
3099 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3101 case VARYING_SLOT_POS
:
3102 so
->writes_pos
= true;
3104 case VARYING_SLOT_PSIZ
:
3105 so
->writes_psize
= true;
3107 case VARYING_SLOT_COL0
:
3108 case VARYING_SLOT_COL1
:
3109 case VARYING_SLOT_BFC0
:
3110 case VARYING_SLOT_BFC1
:
3111 case VARYING_SLOT_FOGC
:
3112 case VARYING_SLOT_CLIP_DIST0
:
3113 case VARYING_SLOT_CLIP_DIST1
:
3114 case VARYING_SLOT_CLIP_VERTEX
:
3117 if (slot
>= VARYING_SLOT_VAR0
)
3119 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3121 compile_error(ctx
, "unknown VS output name: %s\n",
3122 gl_varying_slot_name(slot
));
3125 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3128 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3130 so
->outputs
[n
].slot
= slot
;
3131 so
->outputs
[n
].regid
= regid(n
, comp
);
3132 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3134 for (int i
= 0; i
< ncomp
; i
++) {
3135 unsigned idx
= (n
* 4) + i
;
3136 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3137 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3142 max_drvloc(struct exec_list
*vars
)
3145 nir_foreach_variable(var
, vars
) {
3146 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3151 static const unsigned max_sysvals
[SHADER_MAX
] = {
3152 [SHADER_VERTEX
] = 16,
3153 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3157 emit_instructions(struct ir3_context
*ctx
)
3159 unsigned ninputs
, noutputs
;
3160 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3162 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3163 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3165 /* we need to leave room for sysvals:
3167 ninputs
+= max_sysvals
[ctx
->so
->type
];
3169 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3171 /* Create inputs in first block: */
3172 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3173 ctx
->in_block
= ctx
->block
;
3174 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3176 ninputs
-= max_sysvals
[ctx
->so
->type
];
3178 /* for fragment shader, we have a single input register (usually
3179 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3181 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3182 // TODO maybe a helper for fi since we need it a few places..
3183 struct ir3_instruction
*instr
;
3184 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3185 ir3_reg_create(instr
, 0, 0);
3186 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3187 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3188 ctx
->frag_pos
= instr
;
3192 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3193 setup_input(ctx
, var
);
3196 /* Setup outputs: */
3197 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3198 setup_output(ctx
, var
);
3201 /* Setup registers (which should only be arrays): */
3202 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3203 declare_array(ctx
, reg
);
3206 /* NOTE: need to do something more clever when we support >1 fxn */
3207 nir_foreach_register(reg
, &fxn
->registers
) {
3208 declare_array(ctx
, reg
);
3210 /* And emit the body: */
3212 emit_function(ctx
, fxn
);
3215 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3216 * for a fragment shader are just bary.f instructions. The *actual* inputs
3217 * from the hw perspective are the frag_pos and optionally frag_coord and
3221 fixup_frag_inputs(struct ir3_context
*ctx
)
3223 struct ir3_shader_variant
*so
= ctx
->so
;
3224 struct ir3
*ir
= ctx
->ir
;
3225 struct ir3_instruction
**inputs
;
3226 struct ir3_instruction
*instr
;
3231 n
= 4; /* always have frag_pos */
3232 n
+= COND(so
->frag_face
, 4);
3233 n
+= COND(so
->frag_coord
, 4);
3235 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3237 if (so
->frag_face
) {
3238 /* this ultimately gets assigned to hr0.x so doesn't conflict
3239 * with frag_coord/frag_pos..
3241 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3242 ctx
->frag_face
->regs
[0]->num
= 0;
3244 /* remaining channels not used, but let's avoid confusing
3245 * other parts that expect inputs to come in groups of vec4
3247 inputs
[ir
->ninputs
++] = NULL
;
3248 inputs
[ir
->ninputs
++] = NULL
;
3249 inputs
[ir
->ninputs
++] = NULL
;
3252 /* since we don't know where to set the regid for frag_coord,
3253 * we have to use r0.x for it. But we don't want to *always*
3254 * use r1.x for frag_pos as that could increase the register
3255 * footprint on simple shaders:
3257 if (so
->frag_coord
) {
3258 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3259 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3260 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3261 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3263 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3264 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3265 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3266 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3269 /* we always have frag_pos: */
3270 so
->pos_regid
= regid
;
3273 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3274 instr
->regs
[0]->num
= regid
++;
3275 inputs
[ir
->ninputs
++] = instr
;
3276 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3279 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3280 instr
->regs
[0]->num
= regid
++;
3281 inputs
[ir
->ninputs
++] = instr
;
3282 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3284 ir
->inputs
= inputs
;
3287 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3288 * need to assign the tex state indexes for these after we know the
3292 fixup_astc_srgb(struct ir3_context
*ctx
)
3294 struct ir3_shader_variant
*so
= ctx
->so
;
3295 /* indexed by original tex idx, value is newly assigned alpha sampler
3296 * state tex idx. Zero is invalid since there is at least one sampler
3299 unsigned alt_tex_state
[16] = {0};
3300 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3303 so
->astc_srgb
.base
= tex_idx
;
3305 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3306 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3308 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3310 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3311 /* assign new alternate/alpha tex state slot: */
3312 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3313 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3314 so
->astc_srgb
.count
++;
3317 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3322 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3323 struct ir3_shader_variant
*so
)
3325 struct ir3_context
*ctx
;
3327 struct ir3_instruction
**inputs
;
3328 unsigned i
, j
, actual_in
, inloc
;
3329 int ret
= 0, max_bary
;
3333 ctx
= compile_init(compiler
, so
);
3335 DBG("INIT failed!");
3340 emit_instructions(ctx
);
3343 DBG("EMIT failed!");
3348 ir
= so
->ir
= ctx
->ir
;
3350 /* keep track of the inputs from TGSI perspective.. */
3351 inputs
= ir
->inputs
;
3353 /* but fixup actual inputs for frag shader: */
3354 if (so
->type
== SHADER_FRAGMENT
)
3355 fixup_frag_inputs(ctx
);
3357 /* at this point, for binning pass, throw away unneeded outputs: */
3358 if (so
->key
.binning_pass
) {
3359 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3360 unsigned slot
= so
->outputs
[i
].slot
;
3362 /* throw away everything but first position/psize */
3363 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3365 so
->outputs
[j
] = so
->outputs
[i
];
3366 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3367 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3368 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3369 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3374 so
->outputs_count
= j
;
3375 ir
->noutputs
= j
* 4;
3378 /* if we want half-precision outputs, mark the output registers
3381 if (so
->key
.half_precision
) {
3382 for (i
= 0; i
< ir
->noutputs
; i
++) {
3383 struct ir3_instruction
*out
= ir
->outputs
[i
];
3388 /* if frag shader writes z, that needs to be full precision: */
3389 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3392 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3393 /* output could be a fanout (ie. texture fetch output)
3394 * in which case we need to propagate the half-reg flag
3395 * up to the definer so that RA sees it:
3397 if (out
->opc
== OPC_META_FO
) {
3398 out
= out
->regs
[1]->instr
;
3399 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3402 if (out
->opc
== OPC_MOV
) {
3403 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3408 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3409 printf("BEFORE CP:\n");
3415 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3416 printf("BEFORE GROUPING:\n");
3420 ir3_sched_add_deps(ir
);
3422 /* Group left/right neighbors, inserting mov's where needed to
3427 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3428 printf("AFTER GROUPING:\n");
3434 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3435 printf("AFTER DEPTH:\n");
3439 ret
= ir3_sched(ir
);
3441 DBG("SCHED failed!");
3445 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3446 printf("AFTER SCHED:\n");
3450 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3456 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3457 printf("AFTER RA:\n");
3461 /* fixup input/outputs: */
3462 for (i
= 0; i
< so
->outputs_count
; i
++) {
3463 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3466 /* Note that some or all channels of an input may be unused: */
3469 for (i
= 0; i
< so
->inputs_count
; i
++) {
3470 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3471 so
->inputs
[i
].ncomp
= 0;
3472 so
->inputs
[i
].inloc
= inloc
;
3473 for (j
= 0; j
< 4; j
++) {
3474 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3475 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3476 compmask
|= (1 << j
);
3477 regid
= in
->regs
[0]->num
- j
;
3479 so
->inputs
[i
].ncomp
++;
3480 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3482 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3483 in
->regs
[1]->iim_val
= inloc
+ j
;
3488 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3490 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3492 } else if (!so
->inputs
[i
].sysval
){
3493 so
->inputs
[i
].compmask
= compmask
;
3495 so
->inputs
[i
].regid
= regid
;
3499 fixup_astc_srgb(ctx
);
3501 /* We need to do legalize after (for frag shader's) the "bary.f"
3502 * offsets (inloc) have been assigned.
3504 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3506 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3507 printf("AFTER LEGALIZE:\n");
3511 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3512 if (so
->type
== SHADER_VERTEX
)
3513 so
->total_in
= actual_in
;
3515 so
->total_in
= max_bary
+ 1;
3520 ir3_destroy(so
->ir
);