1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
41 #include "freedreno_util.h"
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
47 #include "instr-a3xx.h"
52 struct ir3_compiler
*compiler
;
54 const struct tgsi_token
*tokens
;
58 struct ir3_shader_variant
*so
;
60 struct ir3_block
*block
; /* the current block */
61 struct ir3_block
*in_block
; /* block created for shader inputs */
63 nir_function_impl
*impl
;
65 /* For fragment shaders, from the hw perspective the only
66 * actual input is r0.xy position register passed to bary.f.
67 * But TGSI doesn't know that, it still declares things as
68 * IN[] registers. So we do all the input tracking normally
69 * and fix things up after compile_instructions()
71 * NOTE that frag_pos is the hardware position (possibly it
72 * is actually an index or tag or some such.. it is *not*
73 * values that can be directly used for gl_FragCoord..)
75 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
77 /* For vertex shaders, keep track of the system values sources */
78 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
83 /* mapping from nir_variable to ir3_array: */
84 struct hash_table
*var_ht
;
87 /* a common pattern for indirect addressing is to request the
88 * same address register multiple times. To avoid generating
89 * duplicate instruction sequences (which our backend does not
90 * try to clean up, since that should be done as the NIR stage)
91 * we cache the address value generated for a given src value:
93 struct hash_table
*addr_ht
;
95 /* maps nir_block to ir3_block, mostly for the purposes of
96 * figuring out the blocks successors
98 struct hash_table
*block_ht
;
100 /* for calculating input/output positions/linkages: */
103 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
104 * so we need to use ldlv.u32 to load the varying directly:
108 /* on a3xx, we need to add one to # of array levels:
112 /* on a3xx, we need to scale up integer coords for isaml based
115 bool unminify_coords
;
117 /* for looking up which system value is which */
118 unsigned sysval_semantics
[8];
120 /* set if we encounter something we can't handle yet, so we
121 * can bail cleanly and fallback to TGSI compiler f/e
127 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
128 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
130 static struct nir_shader
*to_nir(struct ir3_compile
*ctx
,
131 const struct tgsi_token
*tokens
, struct ir3_shader_variant
*so
)
133 static const nir_shader_compiler_options options
= {
138 .lower_ffract
= true,
139 .native_integers
= true,
141 struct nir_lower_tex_options tex_options
= {
147 case SHADER_FRAGMENT
:
149 tex_options
.saturate_s
= so
->key
.fsaturate_s
;
150 tex_options
.saturate_t
= so
->key
.fsaturate_t
;
151 tex_options
.saturate_r
= so
->key
.fsaturate_r
;
154 tex_options
.saturate_s
= so
->key
.vsaturate_s
;
155 tex_options
.saturate_t
= so
->key
.vsaturate_t
;
156 tex_options
.saturate_r
= so
->key
.vsaturate_r
;
160 if (ctx
->compiler
->gpu_id
>= 400) {
161 /* a4xx seems to have *no* sam.p */
162 tex_options
.lower_txp
= ~0; /* lower all txp */
164 /* a3xx just needs to avoid sam.p for 3d tex */
165 tex_options
.lower_txp
= (1 << GLSL_SAMPLER_DIM_3D
);
168 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
170 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
171 debug_printf("----------------------\n");
172 nir_print_shader(s
, stdout
);
173 debug_printf("----------------------\n");
176 nir_opt_global_to_local(s
);
177 nir_convert_to_ssa(s
);
178 if (s
->stage
== MESA_SHADER_VERTEX
) {
179 nir_lower_clip_vs(s
, so
->key
.ucp_enables
);
180 } else if (s
->stage
== MESA_SHADER_FRAGMENT
) {
181 nir_lower_clip_fs(s
, so
->key
.ucp_enables
);
183 nir_lower_tex(s
, &tex_options
);
185 nir_lower_load_const_to_scalar(s
);
190 nir_lower_vars_to_ssa(s
);
191 nir_lower_alu_to_scalar(s
);
192 nir_lower_phis_to_scalar(s
);
194 progress
|= nir_copy_prop(s
);
195 progress
|= nir_opt_dce(s
);
196 progress
|= nir_opt_cse(s
);
197 progress
|= ir3_nir_lower_if_else(s
);
198 progress
|= nir_opt_algebraic(s
);
199 progress
|= nir_opt_constant_folding(s
);
203 nir_remove_dead_variables(s
);
204 nir_validate_shader(s
);
206 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
207 debug_printf("----------------------\n");
208 nir_print_shader(s
, stdout
);
209 debug_printf("----------------------\n");
215 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
216 static const struct tgsi_token
*
217 lower_tgsi(struct ir3_compile
*ctx
, const struct tgsi_token
*tokens
,
218 struct ir3_shader_variant
*so
)
220 struct tgsi_shader_info info
;
221 struct tgsi_lowering_config lconfig
= {
222 .color_two_side
= so
->key
.color_two_side
,
225 return tgsi_transform_lowering(&lconfig
, tokens
, &info
);
228 static struct ir3_compile
*
229 compile_init(struct ir3_compiler
*compiler
,
230 struct ir3_shader_variant
*so
,
231 const struct tgsi_token
*tokens
)
233 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
234 const struct tgsi_token
*lowered_tokens
;
236 if (compiler
->gpu_id
>= 400) {
237 /* need special handling for "flat" */
238 ctx
->flat_bypass
= true;
239 ctx
->levels_add_one
= false;
240 ctx
->unminify_coords
= false;
242 /* no special handling for "flat" */
243 ctx
->flat_bypass
= false;
244 ctx
->levels_add_one
= true;
245 ctx
->unminify_coords
= true;
248 ctx
->compiler
= compiler
;
252 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
253 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
254 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
255 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
256 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
257 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
258 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
259 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
261 lowered_tokens
= lower_tgsi(ctx
, tokens
, so
);
263 lowered_tokens
= tokens
;
264 ctx
->s
= to_nir(ctx
, lowered_tokens
, so
);
266 if (lowered_tokens
!= tokens
)
267 free((void *)lowered_tokens
);
269 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
271 /* Layout of constant registers:
273 * num_uniform * vec4 - user consts
274 * 4 * vec4 - UBO addresses
275 * if (vertex shader) {
276 * N * vec4 - driver params (IR3_DP_*)
277 * 1 * vec4 - stream-out addresses
280 * TODO this could be made more dynamic, to at least skip sections
281 * that we don't need..
284 /* reserve 4 (vec4) slots for ubo base addresses: */
285 so
->first_immediate
+= 4;
287 if (so
->type
== SHADER_VERTEX
) {
288 /* driver params (see ir3_driver_param): */
289 so
->first_immediate
+= IR3_DP_COUNT
/4; /* convert to vec4 */
290 /* one (vec4) slot for stream-output base addresses: */
291 so
->first_immediate
++;
298 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
301 va_start(ap
, format
);
302 _debug_vprintf(format
, ap
);
304 nir_print_shader(ctx
->s
, stdout
);
309 #define compile_assert(ctx, cond) do { \
310 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
314 compile_free(struct ir3_compile
*ctx
)
319 /* global per-array information: */
321 unsigned length
, aid
;
324 /* per-block array state: */
325 struct ir3_array_value
{
326 /* TODO drop length/aid, and just have ptr back to ir3_array */
327 unsigned length
, aid
;
328 /* initial array element values are phi's, other than for the
329 * entry block. The phi src's get added later in a resolve step
330 * after we have visited all the blocks, to account for back
333 struct ir3_instruction
**phis
;
334 /* current array element values (as block is processed). When
335 * the array phi's are resolved, it will contain the array state
336 * at exit of block, so successor blocks can use it to add their
339 struct ir3_instruction
*arr
[];
342 /* track array assignments per basic block. When an array is read
343 * outside of the same basic block, we can use NIR's dominance-frontier
344 * information to figure out where phi nodes are needed.
346 struct ir3_nir_block_data
{
348 /* indexed by array-id (aid): */
349 struct ir3_array_value
*arrs
[];
352 static struct ir3_nir_block_data
*
353 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
356 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
357 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
364 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
366 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
367 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
368 arr
->length
= length
;
369 arr
->aid
= ++ctx
->num_arrays
;
370 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
374 nir_block_pred(nir_block
*block
)
376 assert(block
->predecessors
->entries
< 2);
377 if (block
->predecessors
->entries
== 0)
379 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
382 static struct ir3_array_value
*
383 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
385 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
386 struct ir3_block
*block
= ctx
->block
;
387 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
388 struct ir3_array
*arr
= entry
->data
;
390 if (!bd
->arrs
[arr
->aid
]) {
391 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
392 (arr
->length
* sizeof(av
->arr
[0])));
393 struct ir3_array_value
*defn
= NULL
;
394 nir_block
*pred_block
;
396 av
->length
= arr
->length
;
399 /* For loops, we have to consider that we have not visited some
400 * of the blocks who should feed into the phi (ie. back-edges in
401 * the cfg).. for example:
404 * block { load_var; ... }
405 * if then block {} else block {}
406 * block { store_var; ... }
407 * if then block {} else block {}
411 * We can skip the phi if we can chase the block predecessors
412 * until finding the block previously defining the array without
413 * crossing a block that has more than one predecessor.
415 * Otherwise create phi's and resolve them as a post-pass after
416 * all the blocks have been visited (to handle back-edges).
419 for (pred_block
= block
->nblock
;
420 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
421 pred_block
= nir_block_pred(pred_block
)) {
422 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
423 struct ir3_nir_block_data
*pbd
= pblock
->bd
;
426 defn
= pbd
->arrs
[arr
->aid
];
430 /* only one possible definer: */
431 for (unsigned i
= 0; i
< arr
->length
; i
++)
432 av
->arr
[i
] = defn
->arr
[i
];
433 } else if (pred_block
) {
434 /* not the first block, and multiple potential definers: */
435 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
437 for (unsigned i
= 0; i
< arr
->length
; i
++) {
438 struct ir3_instruction
*phi
;
440 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
441 1 + ctx
->impl
->num_blocks
);
442 ir3_reg_create(phi
, 0, 0); /* dst */
444 /* phi's should go at head of block: */
445 list_delinit(&phi
->node
);
446 list_add(&phi
->node
, &block
->instr_list
);
448 av
->phis
[i
] = av
->arr
[i
] = phi
;
451 /* Some shaders end up reading array elements without
452 * first writing.. so initialize things to prevent null
455 for (unsigned i
= 0; i
< arr
->length
; i
++)
456 av
->arr
[i
] = create_immed(block
, 0);
459 bd
->arrs
[arr
->aid
] = av
;
462 return bd
->arrs
[arr
->aid
];
466 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
467 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
469 struct ir3_block
*block
;
470 struct ir3_nir_block_data
*bd
;
472 if (BITSET_TEST(visited
, nblock
->index
))
475 BITSET_SET(visited
, nblock
->index
);
477 block
= get_block(ctx
, nblock
);
480 if (bd
&& bd
->arrs
[av
->aid
]) {
481 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
482 for (unsigned i
= 0; i
< av
->length
; i
++) {
483 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
487 /* didn't find defn, recurse predecessors: */
488 struct set_entry
*entry
;
489 set_foreach(nblock
->predecessors
, entry
) {
490 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
496 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
498 struct ir3_nir_block_data
*bd
= block
->bd
;
499 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
504 /* TODO use nir dom_frontier to help us with this? */
506 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
507 struct ir3_array_value
*av
= bd
->arrs
[i
];
508 BITSET_WORD visited
[bitset_words
];
509 struct set_entry
*entry
;
511 if (!(av
&& av
->phis
))
514 memset(visited
, 0, sizeof(visited
));
515 set_foreach(block
->nblock
->predecessors
, entry
) {
516 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
521 /* allocate a n element value array (to be populated by caller) and
524 static struct ir3_instruction
**
525 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
527 struct ir3_instruction
**value
=
528 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
529 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
533 static struct ir3_instruction
**
534 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
537 return __get_dst(ctx
, &dst
->ssa
, n
);
539 return __get_dst(ctx
, dst
->reg
.reg
, n
);
543 static struct ir3_instruction
**
544 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
546 return __get_dst(ctx
, dst
, n
);
549 static struct ir3_instruction
**
550 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
552 struct hash_entry
*entry
;
554 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
556 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
558 compile_assert(ctx
, entry
);
562 static struct ir3_instruction
*
563 create_immed(struct ir3_block
*block
, uint32_t val
)
565 struct ir3_instruction
*mov
;
567 mov
= ir3_instr_create(block
, 1, 0);
568 mov
->cat1
.src_type
= TYPE_U32
;
569 mov
->cat1
.dst_type
= TYPE_U32
;
570 ir3_reg_create(mov
, 0, 0);
571 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
576 static struct ir3_instruction
*
577 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
579 struct ir3_instruction
*instr
, *immed
;
581 /* TODO in at least some cases, the backend could probably be
582 * made clever enough to propagate IR3_REG_HALF..
584 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
585 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
587 immed
= create_immed(block
, 2);
588 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
590 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
591 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
592 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
594 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
595 instr
->regs
[0]->num
= regid(REG_A0
, 0);
596 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
597 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
602 /* caches addr values to avoid generating multiple cov/shl/mova
603 * sequences for each use of a given NIR level src as address
605 static struct ir3_instruction
*
606 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
608 struct ir3_instruction
*addr
;
609 struct hash_entry
*entry
;
610 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
614 /* TODO do we need to cache per block? */
615 addr
= create_addr(ctx
->block
, src
);
616 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
621 static struct ir3_instruction
*
622 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
624 struct ir3_block
*b
= ctx
->block
;
625 struct ir3_instruction
*cond
;
627 /* NOTE: only cmps.*.* can write p0.x: */
628 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
629 cond
->cat2
.condition
= IR3_COND_NE
;
631 /* condition always goes in predicate register: */
632 cond
->regs
[0]->num
= regid(REG_P0
, 0);
637 static struct ir3_instruction
*
638 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
640 struct ir3_instruction
*mov
;
642 mov
= ir3_instr_create(ctx
->block
, 1, 0);
643 /* TODO get types right? */
644 mov
->cat1
.src_type
= TYPE_F32
;
645 mov
->cat1
.dst_type
= TYPE_F32
;
646 ir3_reg_create(mov
, 0, 0);
647 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
652 static struct ir3_instruction
*
653 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
654 struct ir3_instruction
*address
)
656 struct ir3_instruction
*mov
;
658 mov
= ir3_instr_create(ctx
->block
, 1, 0);
659 mov
->cat1
.src_type
= TYPE_U32
;
660 mov
->cat1
.dst_type
= TYPE_U32
;
661 ir3_reg_create(mov
, 0, 0);
662 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
664 ir3_instr_set_address(mov
, address
);
669 static struct ir3_instruction
*
670 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
673 struct ir3_instruction
*collect
;
678 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
679 ir3_reg_create(collect
, 0, 0); /* dst */
680 for (unsigned i
= 0; i
< arrsz
; i
++)
681 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
686 static struct ir3_instruction
*
687 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
688 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
690 struct ir3_block
*block
= ctx
->block
;
691 struct ir3_instruction
*mov
;
692 struct ir3_register
*src
;
694 mov
= ir3_instr_create(block
, 1, 0);
695 mov
->cat1
.src_type
= TYPE_U32
;
696 mov
->cat1
.dst_type
= TYPE_U32
;
697 ir3_reg_create(mov
, 0, 0);
698 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
699 src
->instr
= collect
;
703 ir3_instr_set_address(mov
, address
);
708 static struct ir3_instruction
*
709 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
710 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
711 struct ir3_instruction
*collect
)
713 struct ir3_block
*block
= ctx
->block
;
714 struct ir3_instruction
*mov
;
715 struct ir3_register
*dst
;
717 mov
= ir3_instr_create(block
, 1, 0);
718 mov
->cat1
.src_type
= TYPE_U32
;
719 mov
->cat1
.dst_type
= TYPE_U32
;
720 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
723 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
724 mov
->fanin
= collect
;
726 ir3_instr_set_address(mov
, address
);
731 static struct ir3_instruction
*
732 create_input(struct ir3_block
*block
, unsigned n
)
734 struct ir3_instruction
*in
;
736 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
737 in
->inout
.block
= block
;
738 ir3_reg_create(in
, n
, 0);
743 static struct ir3_instruction
*
744 create_frag_input(struct ir3_compile
*ctx
, unsigned n
, bool use_ldlv
)
746 struct ir3_block
*block
= ctx
->block
;
747 struct ir3_instruction
*instr
;
748 struct ir3_instruction
*inloc
= create_immed(block
, n
);
751 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
752 instr
->cat6
.type
= TYPE_U32
;
753 instr
->cat6
.iim_val
= 1;
755 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
756 instr
->regs
[2]->wrmask
= 0x3;
762 static struct ir3_instruction
*
763 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
765 struct ir3_block
*block
= ctx
->block
;
766 struct ir3_instruction
*instr
;
768 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
770 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
775 /* for frag_coord, we get unsigned values.. we need
776 * to subtract (integer) 8 and divide by 16 (right-
777 * shift by 4) then convert to float:
781 * mov.u32f32 dst, tmp
784 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
785 create_immed(block
, 8), 0);
786 instr
= ir3_SHR_B(block
, instr
, 0,
787 create_immed(block
, 4), 0);
788 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
794 /* seems that we can use these as-is: */
795 return ctx
->frag_coord
[comp
];
799 static struct ir3_instruction
*
800 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
802 struct ir3_block
*block
= ctx
->block
;
803 struct ir3_instruction
*instr
;
807 compile_assert(ctx
, !ctx
->frag_face
);
809 ctx
->frag_face
= create_input(block
, 0);
810 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
812 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
813 * positive vs negative float.. and piglit further seems to
814 * expect -1.0 or 1.0:
816 * mul.s tmp, hr0.x, 2
818 * mov.s32f32, dst, tmp
821 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
822 create_immed(block
, 2), 0);
823 instr
= ir3_ADD_S(block
, instr
, 0,
824 create_immed(block
, 1), 0);
825 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
830 return create_immed(block
, fui(0.0));
833 return create_immed(block
, fui(1.0));
837 static struct ir3_instruction
*
838 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
840 /* first four vec4 sysval's reserved for UBOs: */
841 /* NOTE: dp is in scalar, but there can be >4 dp components: */
842 unsigned n
= ctx
->so
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
843 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
844 return create_uniform(ctx
, r
);
847 /* helper for instructions that produce multiple consecutive scalar
848 * outputs which need to have a split/fanout meta instruction inserted
851 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
852 struct ir3_instruction
*src
, unsigned n
)
854 struct ir3_instruction
*prev
= NULL
;
855 for (int i
= 0, j
= 0; i
< n
; i
++) {
856 struct ir3_instruction
*split
=
857 ir3_instr_create(block
, -1, OPC_META_FO
);
858 ir3_reg_create(split
, 0, IR3_REG_SSA
);
859 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
863 split
->cp
.left
= prev
;
864 split
->cp
.left_cnt
++;
865 prev
->cp
.right
= split
;
866 prev
->cp
.right_cnt
++;
870 if (src
->regs
[0]->wrmask
& (1 << i
))
876 * Adreno uses uint rather than having dedicated bool type,
877 * which (potentially) requires some conversion, in particular
878 * when using output of an bool instr to int input, or visa
882 * -------+---------+-------+-
886 * To convert from an adreno bool (uint) to nir, use:
888 * absneg.s dst, (neg)src
890 * To convert back in the other direction:
892 * absneg.s dst, (abs)arc
894 * The CP step can clean up the absneg.s that cancel each other
895 * out, and with a slight bit of extra cleverness (to recognize
896 * the instructions which produce either a 0 or 1) can eliminate
897 * the absneg.s's completely when an instruction that wants
898 * 0/1 consumes the result. For example, when a nir 'bcsel'
899 * consumes the result of 'feq'. So we should be able to get by
900 * without a boolean resolve step, and without incuring any
901 * extra penalty in instruction count.
904 /* NIR bool -> native (adreno): */
905 static struct ir3_instruction
*
906 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
908 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
911 /* native (adreno) -> NIR bool: */
912 static struct ir3_instruction
*
913 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
915 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
919 * alu/sfu instructions:
923 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
925 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
926 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
927 struct ir3_block
*b
= ctx
->block
;
929 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
931 /* Vectors are special in that they have non-scalarized writemasks,
932 * and just take the first swizzle channel for each argument in
933 * order into each writemask channel.
935 if ((alu
->op
== nir_op_vec2
) ||
936 (alu
->op
== nir_op_vec3
) ||
937 (alu
->op
== nir_op_vec4
)) {
939 for (int i
= 0; i
< info
->num_inputs
; i
++) {
940 nir_alu_src
*asrc
= &alu
->src
[i
];
942 compile_assert(ctx
, !asrc
->abs
);
943 compile_assert(ctx
, !asrc
->negate
);
945 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
947 src
[i
] = create_immed(ctx
->block
, 0);
948 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
954 /* General case: We can just grab the one used channel per src. */
955 for (int i
= 0; i
< info
->num_inputs
; i
++) {
956 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
957 nir_alu_src
*asrc
= &alu
->src
[i
];
959 compile_assert(ctx
, !asrc
->abs
);
960 compile_assert(ctx
, !asrc
->negate
);
962 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
964 compile_assert(ctx
, src
[i
]);
969 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
972 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
975 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
978 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
981 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
984 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
987 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
988 dst
[0]->cat2
.condition
= IR3_COND_NE
;
989 dst
[0] = ir3_n2b(b
, dst
[0]);
992 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
995 dst
[0] = ir3_b2n(b
, src
[0]);
998 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
999 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1000 dst
[0] = ir3_n2b(b
, dst
[0]);
1004 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1007 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1010 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1013 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1016 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1019 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1022 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1025 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1028 dst
[0] = ir3_DSX(b
, src
[0], 0);
1029 dst
[0]->cat5
.type
= TYPE_F32
;
1032 dst
[0] = ir3_DSY(b
, src
[0], 0);
1033 dst
[0]->cat5
.type
= TYPE_F32
;
1037 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1038 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1039 dst
[0] = ir3_n2b(b
, dst
[0]);
1042 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1043 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1044 dst
[0] = ir3_n2b(b
, dst
[0]);
1047 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1048 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1049 dst
[0] = ir3_n2b(b
, dst
[0]);
1052 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1053 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1054 dst
[0] = ir3_n2b(b
, dst
[0]);
1057 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1060 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1063 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1065 case nir_op_fround_even
:
1066 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1069 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1073 dst
[0] = ir3_SIN(b
, src
[0], 0);
1076 dst
[0] = ir3_COS(b
, src
[0], 0);
1079 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1082 dst
[0] = ir3_RCP(b
, src
[0], 0);
1085 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1088 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1091 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1095 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1098 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1101 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1104 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1107 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1110 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1113 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1117 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1118 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1119 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1120 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1122 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1123 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1124 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1127 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1130 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1133 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1136 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1139 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1141 case nir_op_isign
: {
1142 /* maybe this would be sane to lower in nir.. */
1143 struct ir3_instruction
*neg
, *pos
;
1145 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1146 neg
->cat2
.condition
= IR3_COND_LT
;
1148 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1149 pos
->cat2
.condition
= IR3_COND_GT
;
1151 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1156 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1159 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1162 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1165 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1166 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1167 dst
[0] = ir3_n2b(b
, dst
[0]);
1170 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1171 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1172 dst
[0] = ir3_n2b(b
, dst
[0]);
1175 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1176 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1177 dst
[0] = ir3_n2b(b
, dst
[0]);
1180 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1181 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1182 dst
[0] = ir3_n2b(b
, dst
[0]);
1185 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1186 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1187 dst
[0] = ir3_n2b(b
, dst
[0]);
1190 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1191 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1192 dst
[0] = ir3_n2b(b
, dst
[0]);
1196 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1200 compile_error(ctx
, "Unhandled ALU op: %s\n",
1201 nir_op_infos
[alu
->op
].name
);
1206 /* handles direct/indirect UBO reads: */
1208 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1209 struct ir3_instruction
**dst
)
1211 struct ir3_block
*b
= ctx
->block
;
1212 struct ir3_instruction
*addr
, *src0
, *src1
;
1213 /* UBO addresses are the first driver params: */
1214 unsigned ubo
= regid(ctx
->so
->first_driver_param
+ IR3_UBOS_OFF
, 0);
1215 unsigned off
= intr
->const_index
[0];
1217 /* First src is ubo index, which could either be an immed or not: */
1218 src0
= get_src(ctx
, &intr
->src
[0])[0];
1219 if (is_same_type_mov(src0
) &&
1220 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1221 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1223 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1226 if (intr
->intrinsic
== nir_intrinsic_load_ubo_indirect
) {
1227 /* For load_ubo_indirect, second src is indirect offset: */
1228 src1
= get_src(ctx
, &intr
->src
[1])[0];
1230 /* and add offset to addr: */
1231 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1234 /* if offset is to large to encode in the ldg, split it out: */
1235 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1236 /* split out the minimal amount to improve the odds that
1237 * cp can fit the immediate in the add.s instruction:
1239 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1240 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1244 for (int i
= 0; i
< intr
->num_components
; i
++) {
1245 struct ir3_instruction
*load
=
1246 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1247 load
->cat6
.type
= TYPE_U32
;
1248 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1253 /* handles array reads: */
1255 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1256 struct ir3_instruction
**dst
)
1258 nir_deref_var
*dvar
= intr
->variables
[0];
1259 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1260 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1262 compile_assert(ctx
, dvar
->deref
.child
&&
1263 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1265 switch (darr
->deref_array_type
) {
1266 case nir_deref_array_type_direct
:
1267 /* direct access does not require anything special: */
1268 for (int i
= 0; i
< intr
->num_components
; i
++) {
1269 unsigned n
= darr
->base_offset
* 4 + i
;
1270 compile_assert(ctx
, n
< arr
->length
);
1271 dst
[i
] = arr
->arr
[n
];
1274 case nir_deref_array_type_indirect
: {
1275 /* for indirect, we need to collect all the array elements: */
1276 struct ir3_instruction
*collect
=
1277 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1278 struct ir3_instruction
*addr
=
1279 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1280 for (int i
= 0; i
< intr
->num_components
; i
++) {
1281 unsigned n
= darr
->base_offset
* 4 + i
;
1282 compile_assert(ctx
, n
< arr
->length
);
1283 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1288 compile_error(ctx
, "Unhandled load deref type: %u\n",
1289 darr
->deref_array_type
);
1294 /* handles array writes: */
1296 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1298 nir_deref_var
*dvar
= intr
->variables
[0];
1299 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1300 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1301 struct ir3_instruction
**src
;
1303 compile_assert(ctx
, dvar
->deref
.child
&&
1304 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1306 src
= get_src(ctx
, &intr
->src
[0]);
1308 switch (darr
->deref_array_type
) {
1309 case nir_deref_array_type_direct
:
1310 /* direct access does not require anything special: */
1311 for (int i
= 0; i
< intr
->num_components
; i
++) {
1312 unsigned n
= darr
->base_offset
* 4 + i
;
1313 compile_assert(ctx
, n
< arr
->length
);
1314 arr
->arr
[n
] = src
[i
];
1317 case nir_deref_array_type_indirect
: {
1318 /* for indirect, create indirect-store and fan that out: */
1319 struct ir3_instruction
*collect
=
1320 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1321 struct ir3_instruction
*addr
=
1322 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1323 for (int i
= 0; i
< intr
->num_components
; i
++) {
1324 struct ir3_instruction
*store
;
1325 unsigned n
= darr
->base_offset
* 4 + i
;
1326 compile_assert(ctx
, n
< arr
->length
);
1328 store
= create_indirect_store(ctx
, arr
->length
,
1329 n
, src
[i
], addr
, collect
);
1331 store
->fanin
->fi
.aid
= arr
->aid
;
1333 /* TODO: probably split this out to be used for
1334 * store_output_indirect? or move this into
1335 * create_indirect_store()?
1337 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1338 struct ir3_instruction
*split
;
1340 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1342 ir3_reg_create(split
, 0, 0);
1343 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1345 arr
->arr
[j
] = split
;
1348 /* fixup fanout/split neighbors: */
1349 for (int i
= 0; i
< arr
->length
; i
++) {
1350 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1351 arr
->arr
[i
+1] : NULL
;
1352 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1353 arr
->arr
[i
-1] : NULL
;
1358 compile_error(ctx
, "Unhandled store deref type: %u\n",
1359 darr
->deref_array_type
);
1364 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1365 struct ir3_instruction
*instr
)
1367 struct ir3_shader_variant
*so
= ctx
->so
;
1368 unsigned r
= regid(so
->inputs_count
, 0);
1369 unsigned n
= so
->inputs_count
++;
1371 so
->inputs
[n
].sysval
= true;
1372 so
->inputs
[n
].slot
= slot
;
1373 so
->inputs
[n
].compmask
= 1;
1374 so
->inputs
[n
].regid
= r
;
1375 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_FLAT
;
1378 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1379 ctx
->ir
->inputs
[r
] = instr
;
1383 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1385 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1386 struct ir3_instruction
**dst
, **src
;
1387 struct ir3_block
*b
= ctx
->block
;
1388 unsigned idx
= intr
->const_index
[0];
1390 if (info
->has_dest
) {
1391 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1396 switch (intr
->intrinsic
) {
1397 case nir_intrinsic_load_uniform
:
1398 for (int i
= 0; i
< intr
->num_components
; i
++) {
1399 unsigned n
= idx
* 4 + i
;
1400 dst
[i
] = create_uniform(ctx
, n
);
1403 case nir_intrinsic_load_uniform_indirect
:
1404 src
= get_src(ctx
, &intr
->src
[0]);
1405 for (int i
= 0; i
< intr
->num_components
; i
++) {
1406 unsigned n
= idx
* 4 + i
;
1407 dst
[i
] = create_uniform_indirect(ctx
, n
,
1408 get_addr(ctx
, src
[0]));
1410 /* NOTE: if relative addressing is used, we set constlen in
1411 * the compiler (to worst-case value) since we don't know in
1412 * the assembler what the max addr reg value can be:
1414 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1416 case nir_intrinsic_load_ubo
:
1417 case nir_intrinsic_load_ubo_indirect
:
1418 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1420 case nir_intrinsic_load_input
:
1421 for (int i
= 0; i
< intr
->num_components
; i
++) {
1422 unsigned n
= idx
* 4 + i
;
1423 dst
[i
] = ctx
->ir
->inputs
[n
];
1426 case nir_intrinsic_load_input_indirect
:
1427 src
= get_src(ctx
, &intr
->src
[0]);
1428 struct ir3_instruction
*collect
=
1429 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1430 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1431 for (int i
= 0; i
< intr
->num_components
; i
++) {
1432 unsigned n
= idx
* 4 + i
;
1433 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1437 case nir_intrinsic_load_var
:
1438 emit_intrinisic_load_var(ctx
, intr
, dst
);
1440 case nir_intrinsic_store_var
:
1441 emit_intrinisic_store_var(ctx
, intr
);
1443 case nir_intrinsic_store_output
:
1444 src
= get_src(ctx
, &intr
->src
[0]);
1445 for (int i
= 0; i
< intr
->num_components
; i
++) {
1446 unsigned n
= idx
* 4 + i
;
1447 ctx
->ir
->outputs
[n
] = src
[i
];
1450 case nir_intrinsic_load_base_vertex
:
1451 if (!ctx
->basevertex
) {
1452 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1453 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1456 dst
[0] = ctx
->basevertex
;
1458 case nir_intrinsic_load_vertex_id_zero_base
:
1459 if (!ctx
->vertex_id
) {
1460 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1461 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
1464 dst
[0] = ctx
->vertex_id
;
1466 case nir_intrinsic_load_instance_id
:
1467 if (!ctx
->instance_id
) {
1468 ctx
->instance_id
= create_input(ctx
->block
, 0);
1469 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1472 dst
[0] = ctx
->instance_id
;
1474 case nir_intrinsic_load_user_clip_plane
:
1475 for (int i
= 0; i
< intr
->num_components
; i
++) {
1476 unsigned n
= idx
* 4 + i
;
1477 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1480 case nir_intrinsic_discard_if
:
1481 case nir_intrinsic_discard
: {
1482 struct ir3_instruction
*cond
, *kill
;
1484 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1485 /* conditional discard: */
1486 src
= get_src(ctx
, &intr
->src
[0]);
1487 cond
= ir3_b2n(b
, src
[0]);
1489 /* unconditional discard: */
1490 cond
= create_immed(b
, 1);
1493 /* NOTE: only cmps.*.* can write p0.x: */
1494 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1495 cond
->cat2
.condition
= IR3_COND_NE
;
1497 /* condition always goes in predicate register: */
1498 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1500 kill
= ir3_KILL(b
, cond
, 0);
1501 array_insert(ctx
->ir
->predicates
, kill
);
1503 array_insert(ctx
->ir
->keeps
, kill
);
1504 ctx
->so
->has_kill
= true;
1509 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1510 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1516 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1518 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1519 instr
->def
.num_components
);
1520 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1521 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1525 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1527 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1528 undef
->def
.num_components
);
1529 /* backend doesn't want undefined instructions, so just plug
1532 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1533 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1537 * texture fetch/sample instructions:
1541 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1543 unsigned coords
, flags
= 0;
1545 /* note: would use tex->coord_components.. except txs.. also,
1546 * since array index goes after shadow ref, we don't want to
1549 switch (tex
->sampler_dim
) {
1550 case GLSL_SAMPLER_DIM_1D
:
1551 case GLSL_SAMPLER_DIM_BUF
:
1554 case GLSL_SAMPLER_DIM_2D
:
1555 case GLSL_SAMPLER_DIM_RECT
:
1556 case GLSL_SAMPLER_DIM_EXTERNAL
:
1557 case GLSL_SAMPLER_DIM_MS
:
1560 case GLSL_SAMPLER_DIM_3D
:
1561 case GLSL_SAMPLER_DIM_CUBE
:
1563 flags
|= IR3_INSTR_3D
;
1566 unreachable("bad sampler_dim");
1570 flags
|= IR3_INSTR_S
;
1573 flags
|= IR3_INSTR_A
;
1580 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1582 struct ir3_block
*b
= ctx
->block
;
1583 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1584 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1585 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1586 unsigned i
, coords
, flags
;
1587 unsigned nsrc0
= 0, nsrc1
= 0;
1591 coord
= off
= ddx
= ddy
= NULL
;
1592 lod
= proj
= compare
= NULL
;
1594 /* TODO: might just be one component for gathers? */
1595 dst
= get_dst(ctx
, &tex
->dest
, 4);
1597 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1598 switch (tex
->src
[i
].src_type
) {
1599 case nir_tex_src_coord
:
1600 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1602 case nir_tex_src_bias
:
1603 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1606 case nir_tex_src_lod
:
1607 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1610 case nir_tex_src_comparitor
: /* shadow comparator */
1611 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1613 case nir_tex_src_projector
:
1614 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1617 case nir_tex_src_offset
:
1618 off
= get_src(ctx
, &tex
->src
[i
].src
);
1621 case nir_tex_src_ddx
:
1622 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1624 case nir_tex_src_ddy
:
1625 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1628 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1629 tex
->src
[i
].src_type
);
1635 case nir_texop_tex
: opc
= OPC_SAM
; break;
1636 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1637 case nir_texop_txl
: opc
= OPC_SAML
; break;
1638 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1639 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1640 case nir_texop_txf_ms
:
1644 case nir_texop_query_levels
:
1645 case nir_texop_texture_samples
:
1646 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1650 tex_info(tex
, &flags
, &coords
);
1652 /* scale up integer coords for TXF based on the LOD */
1653 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1655 for (i
= 0; i
< coords
; i
++)
1656 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1659 /* the array coord for cube arrays needs 0.5 added to it */
1660 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& tex
->is_array
&&
1662 coord
[3] = ir3_ADD_F(b
, coord
[3], 0, create_immed(b
, fui(0.5)), 0);
1665 * lay out the first argument in the proper order:
1666 * - actual coordinates first
1667 * - shadow reference
1670 * - starting at offset 4, dpdx.xy, dpdy.xy
1672 * bias/lod go into the second arg
1675 /* insert tex coords: */
1676 for (i
= 0; i
< coords
; i
++)
1677 src0
[nsrc0
++] = coord
[i
];
1680 /* hw doesn't do 1d, so we treat it as 2d with
1681 * height of 1, and patch up the y coord.
1682 * TODO: y coord should be (int)0 in some cases..
1684 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1688 src0
[nsrc0
++] = compare
;
1691 src0
[nsrc0
++] = coord
[coords
];
1694 src0
[nsrc0
++] = proj
;
1695 flags
|= IR3_INSTR_P
;
1698 /* pad to 4, then ddx/ddy: */
1699 if (tex
->op
== nir_texop_txd
) {
1701 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1702 for (i
= 0; i
< coords
; i
++)
1703 src0
[nsrc0
++] = ddx
[i
];
1705 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1706 for (i
= 0; i
< coords
; i
++)
1707 src0
[nsrc0
++] = ddy
[i
];
1709 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1713 * second argument (if applicable):
1718 if (has_off
| has_lod
| has_bias
) {
1720 for (i
= 0; i
< coords
; i
++)
1721 src1
[nsrc1
++] = off
[i
];
1723 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1724 flags
|= IR3_INSTR_O
;
1727 if (has_lod
| has_bias
)
1728 src1
[nsrc1
++] = lod
;
1731 switch (tex
->dest_type
) {
1732 case nir_type_invalid
:
1733 case nir_type_float
:
1739 case nir_type_unsigned
:
1744 unreachable("bad dest_type");
1747 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1748 flags
, tex
->sampler_index
, tex
->sampler_index
,
1749 create_collect(b
, src0
, nsrc0
),
1750 create_collect(b
, src1
, nsrc1
));
1752 split_dest(b
, dst
, sam
, 4);
1756 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1758 struct ir3_block
*b
= ctx
->block
;
1759 struct ir3_instruction
**dst
, *sam
;
1761 dst
= get_dst(ctx
, &tex
->dest
, 1);
1763 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1764 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1766 /* even though there is only one component, since it ends
1767 * up in .z rather than .x, we need a split_dest()
1769 split_dest(b
, dst
, sam
, 3);
1771 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1772 * the value in TEX_CONST_0 is zero-based.
1774 if (ctx
->levels_add_one
)
1775 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1779 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1781 struct ir3_block
*b
= ctx
->block
;
1782 struct ir3_instruction
**dst
, *sam
, *lod
;
1783 unsigned flags
, coords
;
1785 tex_info(tex
, &flags
, &coords
);
1787 /* Actually we want the number of dimensions, not coordinates. This
1788 * distinction only matters for cubes.
1790 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1793 dst
= get_dst(ctx
, &tex
->dest
, 4);
1795 compile_assert(ctx
, tex
->num_srcs
== 1);
1796 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1798 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1800 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1801 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1803 split_dest(b
, dst
, sam
, 4);
1805 /* Array size actually ends up in .w rather than .z. This doesn't
1806 * matter for miplevel 0, but for higher mips the value in z is
1807 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1808 * returned, which means that we have to add 1 to it for arrays.
1810 if (tex
->is_array
) {
1811 if (ctx
->levels_add_one
) {
1812 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1814 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1820 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1822 struct ir3_instruction
*phi
, **dst
;
1824 /* NOTE: phi's should be lowered to scalar at this point */
1825 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1827 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1829 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1830 1 + exec_list_length(&nphi
->srcs
));
1831 ir3_reg_create(phi
, 0, 0); /* dst */
1832 phi
->phi
.nphi
= nphi
;
1837 /* phi instructions are left partially constructed. We don't resolve
1838 * their srcs until the end of the block, since (eg. loops) one of
1839 * the phi's srcs might be defined after the phi due to back edges in
1843 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1845 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1846 nir_phi_instr
*nphi
;
1848 /* phi's only come at start of block: */
1849 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1852 if (!instr
->phi
.nphi
)
1855 nphi
= instr
->phi
.nphi
;
1856 instr
->phi
.nphi
= NULL
;
1858 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1859 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1860 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1864 resolve_array_phis(ctx
, block
);
1868 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1870 switch (jump
->type
) {
1871 case nir_jump_break
:
1872 case nir_jump_continue
:
1873 /* I *think* we can simply just ignore this, and use the
1874 * successor block link to figure out where we need to
1875 * jump to for break/continue
1879 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1885 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1887 switch (instr
->type
) {
1888 case nir_instr_type_alu
:
1889 emit_alu(ctx
, nir_instr_as_alu(instr
));
1891 case nir_instr_type_intrinsic
:
1892 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1894 case nir_instr_type_load_const
:
1895 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1897 case nir_instr_type_ssa_undef
:
1898 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1900 case nir_instr_type_tex
: {
1901 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1902 /* couple tex instructions get special-cased:
1906 emit_tex_txs(ctx
, tex
);
1908 case nir_texop_query_levels
:
1909 emit_tex_query_levels(ctx
, tex
);
1917 case nir_instr_type_phi
:
1918 emit_phi(ctx
, nir_instr_as_phi(instr
));
1920 case nir_instr_type_jump
:
1921 emit_jump(ctx
, nir_instr_as_jump(instr
));
1923 case nir_instr_type_call
:
1924 case nir_instr_type_parallel_copy
:
1925 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1930 static struct ir3_block
*
1931 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1933 struct ir3_block
*block
;
1934 struct hash_entry
*entry
;
1935 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1939 block
= ir3_block_create(ctx
->ir
);
1940 block
->nblock
= nblock
;
1941 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1947 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1949 struct ir3_block
*block
= get_block(ctx
, nblock
);
1951 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1952 if (nblock
->successors
[i
]) {
1953 block
->successors
[i
] =
1954 get_block(ctx
, nblock
->successors
[i
]);
1959 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1961 nir_foreach_instr(nblock
, instr
) {
1962 emit_instr(ctx
, instr
);
1968 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1971 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1973 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1975 ctx
->block
->condition
=
1976 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1978 emit_cf_list(ctx
, &nif
->then_list
);
1979 emit_cf_list(ctx
, &nif
->else_list
);
1983 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1985 emit_cf_list(ctx
, &nloop
->body
);
1989 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1991 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1992 switch (node
->type
) {
1993 case nir_cf_node_block
:
1994 emit_block(ctx
, nir_cf_node_as_block(node
));
1996 case nir_cf_node_if
:
1997 emit_if(ctx
, nir_cf_node_as_if(node
));
1999 case nir_cf_node_loop
:
2000 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2002 case nir_cf_node_function
:
2003 compile_error(ctx
, "TODO\n");
2009 /* emit stream-out code. At this point, the current block is the original
2010 * (nir) end block, and nir ensures that all flow control paths terminate
2011 * into the end block. We re-purpose the original end block to generate
2012 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2013 * block holding stream-out write instructions, followed by the new end
2017 * p0.x = (vtxcnt < maxvtxcnt)
2018 * // succs: blockStreamOut, blockNewEnd
2021 * ... stream-out instructions ...
2022 * // succs: blockNewEnd
2028 emit_stream_out(struct ir3_compile
*ctx
)
2030 struct ir3_shader_variant
*v
= ctx
->so
;
2031 struct ir3
*ir
= ctx
->ir
;
2032 struct pipe_stream_output_info
*strmout
=
2033 &ctx
->so
->shader
->stream_output
;
2034 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2035 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2036 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2038 /* create vtxcnt input in input block at top of shader,
2039 * so that it is seen as live over the entire duration
2042 vtxcnt
= create_input(ctx
->in_block
, 0);
2043 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2045 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2047 /* at this point, we are at the original 'end' block,
2048 * re-purpose this block to stream-out condition, then
2049 * append stream-out block and new-end block
2051 orig_end_block
= ctx
->block
;
2053 stream_out_block
= ir3_block_create(ir
);
2054 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2056 new_end_block
= ir3_block_create(ir
);
2057 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2059 orig_end_block
->successors
[0] = stream_out_block
;
2060 orig_end_block
->successors
[1] = new_end_block
;
2061 stream_out_block
->successors
[0] = new_end_block
;
2063 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2064 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2065 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2066 cond
->cat2
.condition
= IR3_COND_LT
;
2068 /* condition goes on previous block to the conditional,
2069 * since it is used to pick which of the two successor
2072 orig_end_block
->condition
= cond
;
2074 /* switch to stream_out_block to generate the stream-out
2077 ctx
->block
= stream_out_block
;
2079 /* Calculate base addresses based on vtxcnt. Instructions
2080 * generated for bases not used in following loop will be
2081 * stripped out in the backend.
2083 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2084 unsigned stride
= strmout
->stride
[i
];
2085 struct ir3_instruction
*base
, *off
;
2087 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ IR3_TFBOS_OFF
, i
));
2089 /* 24-bit should be enough: */
2090 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2091 create_immed(ctx
->block
, stride
* 4), 0);
2093 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2096 /* Generate the per-output store instructions: */
2097 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2098 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2099 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2100 struct ir3_instruction
*base
, *out
, *stg
;
2102 base
= bases
[strmout
->output
[i
].output_buffer
];
2103 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2105 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2106 create_immed(ctx
->block
, 1), 0);
2107 stg
->cat6
.type
= TYPE_U32
;
2108 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2110 array_insert(ctx
->ir
->keeps
, stg
);
2114 /* and finally switch to the new_end_block: */
2115 ctx
->block
= new_end_block
;
2119 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2121 emit_cf_list(ctx
, &impl
->body
);
2122 emit_block(ctx
, impl
->end_block
);
2124 /* at this point, we should have a single empty block,
2125 * into which we emit the 'end' instruction.
2127 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2129 /* If stream-out (aka transform-feedback) enabled, emit the
2130 * stream-out instructions, followed by a new empty block (into
2131 * which the 'end' instruction lands).
2133 * NOTE: it is done in this order, rather than inserting before
2134 * we emit end_block, because NIR guarantees that all blocks
2135 * flow into end_block, and that end_block has no successors.
2136 * So by re-purposing end_block as the first block of stream-
2137 * out, we guarantee that all exit paths flow into the stream-
2140 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2141 !ctx
->so
->key
.binning_pass
) {
2142 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2143 emit_stream_out(ctx
);
2146 ir3_END(ctx
->block
);
2150 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2152 struct ir3_shader_variant
*so
= ctx
->so
;
2153 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2154 unsigned ncomp
= glsl_get_components(in
->type
);
2155 unsigned n
= in
->data
.driver_location
;
2156 unsigned slot
= in
->data
.location
;
2158 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2159 slot
, array_len
, ncomp
, n
);
2161 so
->inputs
[n
].slot
= slot
;
2162 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2163 so
->inputs
[n
].inloc
= ctx
->next_inloc
;
2164 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_NONE
;
2165 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2166 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2168 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2169 for (int i
= 0; i
< ncomp
; i
++) {
2170 struct ir3_instruction
*instr
= NULL
;
2171 unsigned idx
= (n
* 4) + i
;
2173 if (slot
== VARYING_SLOT_POS
) {
2174 so
->inputs
[n
].bary
= false;
2175 so
->frag_coord
= true;
2176 instr
= create_frag_coord(ctx
, i
);
2177 } else if (slot
== VARYING_SLOT_FACE
) {
2178 so
->inputs
[n
].bary
= false;
2179 so
->frag_face
= true;
2180 instr
= create_frag_face(ctx
, i
);
2182 bool use_ldlv
= false;
2184 /* detect the special case for front/back colors where
2185 * we need to do flat vs smooth shading depending on
2188 if (in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) {
2190 case VARYING_SLOT_COL0
:
2191 case VARYING_SLOT_COL1
:
2192 case VARYING_SLOT_BFC0
:
2193 case VARYING_SLOT_BFC1
:
2194 so
->inputs
[n
].rasterflat
= true;
2201 if (ctx
->flat_bypass
) {
2202 if ((so
->inputs
[n
].interpolate
== INTERP_QUALIFIER_FLAT
) ||
2203 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2207 so
->inputs
[n
].bary
= true;
2209 instr
= create_frag_input(ctx
,
2210 so
->inputs
[n
].inloc
+ i
- 8, use_ldlv
);
2213 ctx
->ir
->inputs
[idx
] = instr
;
2215 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2216 for (int i
= 0; i
< ncomp
; i
++) {
2217 unsigned idx
= (n
* 4) + i
;
2218 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2221 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2224 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2225 ctx
->next_inloc
+= ncomp
;
2226 so
->total_in
+= ncomp
;
2231 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2233 struct ir3_shader_variant
*so
= ctx
->so
;
2234 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2235 unsigned ncomp
= glsl_get_components(out
->type
);
2236 unsigned n
= out
->data
.driver_location
;
2237 unsigned slot
= out
->data
.location
;
2240 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2241 slot
, array_len
, ncomp
, n
);
2243 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2245 case FRAG_RESULT_DEPTH
:
2246 comp
= 2; /* tgsi will write to .z component */
2247 so
->writes_pos
= true;
2249 case FRAG_RESULT_COLOR
:
2253 if (slot
>= FRAG_RESULT_DATA0
)
2255 compile_error(ctx
, "unknown FS output name: %s\n",
2256 gl_frag_result_name(slot
));
2258 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2260 case VARYING_SLOT_POS
:
2261 so
->writes_pos
= true;
2263 case VARYING_SLOT_PSIZ
:
2264 so
->writes_psize
= true;
2266 case VARYING_SLOT_COL0
:
2267 case VARYING_SLOT_COL1
:
2268 case VARYING_SLOT_BFC0
:
2269 case VARYING_SLOT_BFC1
:
2270 case VARYING_SLOT_FOGC
:
2271 case VARYING_SLOT_CLIP_DIST0
:
2272 case VARYING_SLOT_CLIP_DIST1
:
2275 if (slot
>= VARYING_SLOT_VAR0
)
2277 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2279 compile_error(ctx
, "unknown VS output name: %s\n",
2280 gl_varying_slot_name(slot
));
2283 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2286 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2288 so
->outputs
[n
].slot
= slot
;
2289 so
->outputs
[n
].regid
= regid(n
, comp
);
2290 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2292 for (int i
= 0; i
< ncomp
; i
++) {
2293 unsigned idx
= (n
* 4) + i
;
2295 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2300 emit_instructions(struct ir3_compile
*ctx
)
2302 unsigned ninputs
, noutputs
;
2303 nir_function_impl
*fxn
= NULL
;
2305 /* Find the main function: */
2306 nir_foreach_overload(ctx
->s
, overload
) {
2307 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
2308 compile_assert(ctx
, overload
->impl
);
2309 fxn
= overload
->impl
;
2313 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2314 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2316 /* or vtx shaders, we need to leave room for sysvals:
2318 if (ctx
->so
->type
== SHADER_VERTEX
) {
2322 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2324 /* Create inputs in first block: */
2325 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2326 ctx
->in_block
= ctx
->block
;
2327 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2329 if (ctx
->so
->type
== SHADER_VERTEX
) {
2330 ctx
->ir
->ninputs
-= 8;
2333 /* for fragment shader, we have a single input register (usually
2334 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2336 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2337 // TODO maybe a helper for fi since we need it a few places..
2338 struct ir3_instruction
*instr
;
2339 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2340 ir3_reg_create(instr
, 0, 0);
2341 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2342 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2343 ctx
->frag_pos
= instr
;
2347 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->inputs
) {
2348 setup_input(ctx
, var
);
2351 /* Setup outputs: */
2352 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->outputs
) {
2353 setup_output(ctx
, var
);
2356 /* Setup variables (which should only be arrays): */
2357 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->globals
) {
2358 declare_var(ctx
, var
);
2361 /* And emit the body: */
2363 emit_function(ctx
, fxn
);
2365 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2366 resolve_phis(ctx
, block
);
2370 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2371 * for a fragment shader are just bary.f instructions. The *actual* inputs
2372 * from the hw perspective are the frag_pos and optionally frag_coord and
2376 fixup_frag_inputs(struct ir3_compile
*ctx
)
2378 struct ir3_shader_variant
*so
= ctx
->so
;
2379 struct ir3
*ir
= ctx
->ir
;
2380 struct ir3_instruction
**inputs
;
2381 struct ir3_instruction
*instr
;
2386 n
= 4; /* always have frag_pos */
2387 n
+= COND(so
->frag_face
, 4);
2388 n
+= COND(so
->frag_coord
, 4);
2390 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2392 if (so
->frag_face
) {
2393 /* this ultimately gets assigned to hr0.x so doesn't conflict
2394 * with frag_coord/frag_pos..
2396 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2397 ctx
->frag_face
->regs
[0]->num
= 0;
2399 /* remaining channels not used, but let's avoid confusing
2400 * other parts that expect inputs to come in groups of vec4
2402 inputs
[ir
->ninputs
++] = NULL
;
2403 inputs
[ir
->ninputs
++] = NULL
;
2404 inputs
[ir
->ninputs
++] = NULL
;
2407 /* since we don't know where to set the regid for frag_coord,
2408 * we have to use r0.x for it. But we don't want to *always*
2409 * use r1.x for frag_pos as that could increase the register
2410 * footprint on simple shaders:
2412 if (so
->frag_coord
) {
2413 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2414 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2415 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2416 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2418 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2419 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2420 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2421 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2424 /* we always have frag_pos: */
2425 so
->pos_regid
= regid
;
2428 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2429 instr
->regs
[0]->num
= regid
++;
2430 inputs
[ir
->ninputs
++] = instr
;
2431 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2434 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2435 instr
->regs
[0]->num
= regid
++;
2436 inputs
[ir
->ninputs
++] = instr
;
2437 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2439 ir
->inputs
= inputs
;
2443 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2444 struct ir3_shader_variant
*so
)
2446 struct ir3_compile
*ctx
;
2448 struct ir3_instruction
**inputs
;
2449 unsigned i
, j
, actual_in
;
2450 int ret
= 0, max_bary
;
2454 ctx
= compile_init(compiler
, so
, so
->shader
->tokens
);
2456 DBG("INIT failed!");
2461 emit_instructions(ctx
);
2464 DBG("EMIT failed!");
2469 ir
= so
->ir
= ctx
->ir
;
2471 /* keep track of the inputs from TGSI perspective.. */
2472 inputs
= ir
->inputs
;
2474 /* but fixup actual inputs for frag shader: */
2475 if (so
->type
== SHADER_FRAGMENT
)
2476 fixup_frag_inputs(ctx
);
2478 /* at this point, for binning pass, throw away unneeded outputs: */
2479 if (so
->key
.binning_pass
) {
2480 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2481 unsigned slot
= so
->outputs
[i
].slot
;
2483 /* throw away everything but first position/psize */
2484 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2486 so
->outputs
[j
] = so
->outputs
[i
];
2487 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2488 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2489 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2490 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2495 so
->outputs_count
= j
;
2496 ir
->noutputs
= j
* 4;
2499 /* if we want half-precision outputs, mark the output registers
2502 if (so
->key
.half_precision
) {
2503 for (i
= 0; i
< ir
->noutputs
; i
++) {
2504 struct ir3_instruction
*out
= ir
->outputs
[i
];
2507 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2508 /* output could be a fanout (ie. texture fetch output)
2509 * in which case we need to propagate the half-reg flag
2510 * up to the definer so that RA sees it:
2512 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2513 out
= out
->regs
[1]->instr
;
2514 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2517 if (out
->category
== 1) {
2518 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2523 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2524 printf("BEFORE CP:\n");
2530 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2531 printf("BEFORE GROUPING:\n");
2535 /* Group left/right neighbors, inserting mov's where needed to
2542 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2543 printf("AFTER DEPTH:\n");
2547 ret
= ir3_sched(ir
);
2549 DBG("SCHED failed!");
2553 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2554 printf("AFTER SCHED:\n");
2558 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2564 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2565 printf("AFTER RA:\n");
2569 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2571 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2572 printf("AFTER LEGALIZE:\n");
2576 /* fixup input/outputs: */
2577 for (i
= 0; i
< so
->outputs_count
; i
++) {
2578 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2579 /* preserve hack for depth output.. tgsi writes depth to .z,
2580 * but what we give the hw is the scalar register:
2582 if ((so
->type
== SHADER_FRAGMENT
) &&
2583 (so
->outputs
[i
].slot
== FRAG_RESULT_DEPTH
))
2584 so
->outputs
[i
].regid
+= 2;
2587 /* Note that some or all channels of an input may be unused: */
2589 for (i
= 0; i
< so
->inputs_count
; i
++) {
2590 unsigned j
, regid
= ~0, compmask
= 0;
2591 so
->inputs
[i
].ncomp
= 0;
2592 for (j
= 0; j
< 4; j
++) {
2593 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2595 compmask
|= (1 << j
);
2596 regid
= in
->regs
[0]->num
- j
;
2598 so
->inputs
[i
].ncomp
++;
2601 so
->inputs
[i
].regid
= regid
;
2602 so
->inputs
[i
].compmask
= compmask
;
2605 /* fragment shader always gets full vec4's even if it doesn't
2606 * fetch all components, but vertex shader we need to update
2607 * with the actual number of components fetch, otherwise thing
2608 * will hang due to mismaptch between VFD_DECODE's and
2611 if (so
->type
== SHADER_VERTEX
)
2612 so
->total_in
= actual_in
;
2614 so
->total_in
= align(max_bary
+ 1, 4);
2619 ir3_destroy(so
->ir
);