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freedreno/ir3: move inputs/outputs to shader
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_compiler_nir.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include <stdarg.h>
30
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
37
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
40
41 #include "freedreno_util.h"
42
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
45 #include "ir3_nir.h"
46
47 #include "instr-a3xx.h"
48 #include "ir3.h"
49
50
51 static struct ir3_instruction * create_immed(struct ir3_block *block, uint32_t val);
52
53 struct ir3_compile {
54 struct ir3_compiler *compiler;
55
56 const struct tgsi_token *tokens;
57 struct nir_shader *s;
58
59 struct ir3 *ir;
60 struct ir3_shader_variant *so;
61
62 /* bitmask of which samplers are integer: */
63 uint16_t integer_s;
64
65 struct ir3_block *block;
66
67 /* For fragment shaders, from the hw perspective the only
68 * actual input is r0.xy position register passed to bary.f.
69 * But TGSI doesn't know that, it still declares things as
70 * IN[] registers. So we do all the input tracking normally
71 * and fix things up after compile_instructions()
72 *
73 * NOTE that frag_pos is the hardware position (possibly it
74 * is actually an index or tag or some such.. it is *not*
75 * values that can be directly used for gl_FragCoord..)
76 */
77 struct ir3_instruction *frag_pos, *frag_face, *frag_coord[4];
78
79 /* For vertex shaders, keep track of the system values sources */
80 struct ir3_instruction *vertex_id, *basevertex, *instance_id;
81
82 /* mapping from nir_register to defining instruction: */
83 struct hash_table *def_ht;
84
85 /* mapping from nir_variable to ir3_array: */
86 struct hash_table *var_ht;
87 unsigned num_arrays;
88
89 /* a common pattern for indirect addressing is to request the
90 * same address register multiple times. To avoid generating
91 * duplicate instruction sequences (which our backend does not
92 * try to clean up, since that should be done as the NIR stage)
93 * we cache the address value generated for a given src value:
94 */
95 struct hash_table *addr_ht;
96
97 /* for calculating input/output positions/linkages: */
98 unsigned next_inloc;
99
100 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
101 * so we need to use ldlv.u32 to load the varying directly:
102 */
103 bool flat_bypass;
104
105 /* on a3xx, we need to add one to # of array levels:
106 */
107 bool levels_add_one;
108
109 /* for looking up which system value is which */
110 unsigned sysval_semantics[8];
111
112 /* list of kill instructions: */
113 struct ir3_instruction *kill[16];
114 unsigned int kill_count;
115
116 /* set if we encounter something we can't handle yet, so we
117 * can bail cleanly and fallback to TGSI compiler f/e
118 */
119 bool error;
120 };
121
122
123 static struct nir_shader *to_nir(const struct tgsi_token *tokens)
124 {
125 struct nir_shader_compiler_options options = {
126 .lower_fpow = true,
127 .lower_fsat = true,
128 .lower_scmp = true,
129 .lower_flrp = true,
130 .native_integers = true,
131 };
132 bool progress;
133
134 struct nir_shader *s = tgsi_to_nir(tokens, &options);
135
136 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
137 debug_printf("----------------------\n");
138 nir_print_shader(s, stdout);
139 debug_printf("----------------------\n");
140 }
141
142 nir_opt_global_to_local(s);
143 nir_convert_to_ssa(s);
144 nir_lower_idiv(s);
145
146 do {
147 progress = false;
148
149 nir_lower_vars_to_ssa(s);
150 nir_lower_alu_to_scalar(s);
151
152 progress |= nir_copy_prop(s);
153 progress |= nir_opt_dce(s);
154 progress |= nir_opt_cse(s);
155 progress |= ir3_nir_lower_if_else(s);
156 progress |= nir_opt_algebraic(s);
157 progress |= nir_opt_constant_folding(s);
158
159 } while (progress);
160
161 nir_remove_dead_variables(s);
162 nir_validate_shader(s);
163
164 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
165 debug_printf("----------------------\n");
166 nir_print_shader(s, stdout);
167 debug_printf("----------------------\n");
168 }
169
170 return s;
171 }
172
173 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
174 static const struct tgsi_token *
175 lower_tgsi(struct ir3_compile *ctx, const struct tgsi_token *tokens,
176 struct ir3_shader_variant *so)
177 {
178 struct tgsi_shader_info info;
179 struct tgsi_lowering_config lconfig = {
180 .color_two_side = so->key.color_two_side,
181 .lower_FRC = true,
182 };
183
184 switch (so->type) {
185 case SHADER_FRAGMENT:
186 case SHADER_COMPUTE:
187 lconfig.saturate_s = so->key.fsaturate_s;
188 lconfig.saturate_t = so->key.fsaturate_t;
189 lconfig.saturate_r = so->key.fsaturate_r;
190 break;
191 case SHADER_VERTEX:
192 lconfig.saturate_s = so->key.vsaturate_s;
193 lconfig.saturate_t = so->key.vsaturate_t;
194 lconfig.saturate_r = so->key.vsaturate_r;
195 break;
196 }
197
198 if (ctx->compiler->gpu_id >= 400) {
199 /* a4xx seems to have *no* sam.p */
200 lconfig.lower_TXP = ~0; /* lower all txp */
201 } else {
202 /* a3xx just needs to avoid sam.p for 3d tex */
203 lconfig.lower_TXP = (1 << TGSI_TEXTURE_3D);
204 }
205
206 return tgsi_transform_lowering(&lconfig, tokens, &info);
207 }
208
209 static struct ir3_compile *
210 compile_init(struct ir3_compiler *compiler,
211 struct ir3_shader_variant *so,
212 const struct tgsi_token *tokens)
213 {
214 struct ir3_compile *ctx = rzalloc(NULL, struct ir3_compile);
215 const struct tgsi_token *lowered_tokens;
216
217 if (compiler->gpu_id >= 400) {
218 /* need special handling for "flat" */
219 ctx->flat_bypass = true;
220 ctx->levels_add_one = false;
221 } else {
222 /* no special handling for "flat" */
223 ctx->flat_bypass = false;
224 ctx->levels_add_one = true;
225 }
226
227 switch (so->type) {
228 case SHADER_FRAGMENT:
229 case SHADER_COMPUTE:
230 ctx->integer_s = so->key.finteger_s;
231 break;
232 case SHADER_VERTEX:
233 ctx->integer_s = so->key.vinteger_s;
234 break;
235 }
236
237 ctx->compiler = compiler;
238 ctx->ir = so->ir;
239 ctx->so = so;
240 ctx->next_inloc = 8;
241 ctx->def_ht = _mesa_hash_table_create(ctx,
242 _mesa_hash_pointer, _mesa_key_pointer_equal);
243 ctx->var_ht = _mesa_hash_table_create(ctx,
244 _mesa_hash_pointer, _mesa_key_pointer_equal);
245 ctx->addr_ht = _mesa_hash_table_create(ctx,
246 _mesa_hash_pointer, _mesa_key_pointer_equal);
247
248 lowered_tokens = lower_tgsi(ctx, tokens, so);
249 if (!lowered_tokens)
250 lowered_tokens = tokens;
251 ctx->s = to_nir(lowered_tokens);
252
253 if (lowered_tokens != tokens)
254 free((void *)lowered_tokens);
255
256 so->first_driver_param = so->first_immediate = ctx->s->num_uniforms;
257
258 /* one (vec4) slot for vertex id base: */
259 if (so->type == SHADER_VERTEX)
260 so->first_immediate++;
261
262 /* reserve 4 (vec4) slots for ubo base addresses: */
263 so->first_immediate += 4;
264
265 return ctx;
266 }
267
268 static void
269 compile_error(struct ir3_compile *ctx, const char *format, ...)
270 {
271 va_list ap;
272 va_start(ap, format);
273 _debug_vprintf(format, ap);
274 va_end(ap);
275 nir_print_shader(ctx->s, stdout);
276 ctx->error = true;
277 debug_assert(0);
278 }
279
280 #define compile_assert(ctx, cond) do { \
281 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
282 } while (0)
283
284 static void
285 compile_free(struct ir3_compile *ctx)
286 {
287 ralloc_free(ctx);
288 }
289
290
291 struct ir3_array {
292 unsigned length, aid;
293 struct ir3_instruction *arr[];
294 };
295
296 static void
297 declare_var(struct ir3_compile *ctx, nir_variable *var)
298 {
299 unsigned length = glsl_get_length(var->type) * 4; /* always vec4, at least with ttn */
300 struct ir3_array *arr = ralloc_size(ctx, sizeof(*arr) +
301 (length * sizeof(arr->arr[0])));
302 arr->length = length;
303 arr->aid = ++ctx->num_arrays;
304 /* Some shaders end up reading array elements without first writing..
305 * so initialize things to prevent null instr ptrs later:
306 */
307 for (unsigned i = 0; i < length; i++)
308 arr->arr[i] = create_immed(ctx->block, 0);
309 _mesa_hash_table_insert(ctx->var_ht, var, arr);
310 }
311
312 static struct ir3_array *
313 get_var(struct ir3_compile *ctx, nir_variable *var)
314 {
315 struct hash_entry *entry = _mesa_hash_table_search(ctx->var_ht, var);
316 return entry->data;
317 }
318
319 /* allocate a n element value array (to be populated by caller) and
320 * insert in def_ht
321 */
322 static struct ir3_instruction **
323 __get_dst(struct ir3_compile *ctx, void *key, unsigned n)
324 {
325 struct ir3_instruction **value =
326 ralloc_array(ctx->def_ht, struct ir3_instruction *, n);
327 _mesa_hash_table_insert(ctx->def_ht, key, value);
328 return value;
329 }
330
331 static struct ir3_instruction **
332 get_dst(struct ir3_compile *ctx, nir_dest *dst, unsigned n)
333 {
334 if (dst->is_ssa) {
335 return __get_dst(ctx, &dst->ssa, n);
336 } else {
337 return __get_dst(ctx, dst->reg.reg, n);
338 }
339 }
340
341 static struct ir3_instruction **
342 get_dst_ssa(struct ir3_compile *ctx, nir_ssa_def *dst, unsigned n)
343 {
344 return __get_dst(ctx, dst, n);
345 }
346
347 static struct ir3_instruction **
348 get_src(struct ir3_compile *ctx, nir_src *src)
349 {
350 struct hash_entry *entry;
351 if (src->is_ssa) {
352 entry = _mesa_hash_table_search(ctx->def_ht, src->ssa);
353 } else {
354 entry = _mesa_hash_table_search(ctx->def_ht, src->reg.reg);
355 }
356 compile_assert(ctx, entry);
357 return entry->data;
358 }
359
360 static struct ir3_instruction *
361 create_immed(struct ir3_block *block, uint32_t val)
362 {
363 struct ir3_instruction *mov;
364
365 mov = ir3_instr_create(block, 1, 0);
366 mov->cat1.src_type = TYPE_U32;
367 mov->cat1.dst_type = TYPE_U32;
368 ir3_reg_create(mov, 0, 0);
369 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
370
371 return mov;
372 }
373
374 static struct ir3_instruction *
375 create_addr(struct ir3_block *block, struct ir3_instruction *src)
376 {
377 struct ir3_instruction *instr, *immed;
378
379 /* TODO in at least some cases, the backend could probably be
380 * made clever enough to propagate IR3_REG_HALF..
381 */
382 instr = ir3_COV(block, src, TYPE_U32, TYPE_S16);
383 instr->regs[0]->flags |= IR3_REG_HALF;
384
385 immed = create_immed(block, 2);
386 immed->regs[0]->flags |= IR3_REG_HALF;
387
388 instr = ir3_SHL_B(block, instr, 0, immed, 0);
389 instr->regs[0]->flags |= IR3_REG_HALF;
390 instr->regs[1]->flags |= IR3_REG_HALF;
391
392 instr = ir3_MOV(block, instr, TYPE_S16);
393 instr->regs[0]->num = regid(REG_A0, 0);
394 instr->regs[0]->flags |= IR3_REG_HALF;
395 instr->regs[1]->flags |= IR3_REG_HALF;
396
397 return instr;
398 }
399
400 /* caches addr values to avoid generating multiple cov/shl/mova
401 * sequences for each use of a given NIR level src as address
402 */
403 static struct ir3_instruction *
404 get_addr(struct ir3_compile *ctx, struct ir3_instruction *src)
405 {
406 struct ir3_instruction *addr;
407 struct hash_entry *entry;
408 entry = _mesa_hash_table_search(ctx->addr_ht, src);
409 if (entry)
410 return entry->data;
411
412 /* TODO do we need to cache per block? */
413 addr = create_addr(ctx->block, src);
414 _mesa_hash_table_insert(ctx->addr_ht, src, addr);
415
416 return addr;
417 }
418
419 static struct ir3_instruction *
420 create_uniform(struct ir3_compile *ctx, unsigned n)
421 {
422 struct ir3_instruction *mov;
423
424 mov = ir3_instr_create(ctx->block, 1, 0);
425 /* TODO get types right? */
426 mov->cat1.src_type = TYPE_F32;
427 mov->cat1.dst_type = TYPE_F32;
428 ir3_reg_create(mov, 0, 0);
429 ir3_reg_create(mov, n, IR3_REG_CONST);
430
431 return mov;
432 }
433
434 static struct ir3_instruction *
435 create_uniform_indirect(struct ir3_compile *ctx, unsigned n,
436 struct ir3_instruction *address)
437 {
438 struct ir3_instruction *mov;
439
440 mov = ir3_instr_create(ctx->block, 1, 0);
441 mov->cat1.src_type = TYPE_U32;
442 mov->cat1.dst_type = TYPE_U32;
443 ir3_reg_create(mov, 0, 0);
444 ir3_reg_create(mov, n, IR3_REG_CONST | IR3_REG_RELATIV);
445 mov->address = address;
446
447 array_insert(ctx->ir->indirects, mov);
448
449 return mov;
450 }
451
452 static struct ir3_instruction *
453 create_collect(struct ir3_block *block, struct ir3_instruction **arr,
454 unsigned arrsz)
455 {
456 struct ir3_instruction *collect;
457
458 if (arrsz == 0)
459 return NULL;
460
461 collect = ir3_instr_create2(block, -1, OPC_META_FI, 1 + arrsz);
462 ir3_reg_create(collect, 0, 0); /* dst */
463 for (unsigned i = 0; i < arrsz; i++)
464 ir3_reg_create(collect, 0, IR3_REG_SSA)->instr = arr[i];
465
466 return collect;
467 }
468
469 static struct ir3_instruction *
470 create_indirect_load(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
471 struct ir3_instruction *address, struct ir3_instruction *collect)
472 {
473 struct ir3_block *block = ctx->block;
474 struct ir3_instruction *mov;
475 struct ir3_register *src;
476
477 mov = ir3_instr_create(block, 1, 0);
478 mov->cat1.src_type = TYPE_U32;
479 mov->cat1.dst_type = TYPE_U32;
480 ir3_reg_create(mov, 0, 0);
481 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
482 src->instr = collect;
483 src->size = arrsz;
484 src->offset = n;
485 mov->address = address;
486
487 array_insert(ctx->ir->indirects, mov);
488
489 return mov;
490 }
491
492 static struct ir3_instruction *
493 create_indirect_store(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
494 struct ir3_instruction *src, struct ir3_instruction *address,
495 struct ir3_instruction *collect)
496 {
497 struct ir3_block *block = ctx->block;
498 struct ir3_instruction *mov;
499 struct ir3_register *dst;
500
501 mov = ir3_instr_create(block, 1, 0);
502 mov->cat1.src_type = TYPE_U32;
503 mov->cat1.dst_type = TYPE_U32;
504 dst = ir3_reg_create(mov, 0, IR3_REG_RELATIV);
505 dst->size = arrsz;
506 dst->offset = n;
507 ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src;
508 mov->address = address;
509 mov->fanin = collect;
510
511 array_insert(ctx->ir->indirects, mov);
512
513 return mov;
514 }
515
516 static struct ir3_instruction *
517 create_input(struct ir3_block *block, struct ir3_instruction *instr,
518 unsigned n)
519 {
520 struct ir3_instruction *in;
521
522 in = ir3_instr_create(block, -1, OPC_META_INPUT);
523 in->inout.block = block;
524 ir3_reg_create(in, n, 0);
525 if (instr)
526 ir3_reg_create(in, 0, IR3_REG_SSA)->instr = instr;
527
528 return in;
529 }
530
531 static struct ir3_instruction *
532 create_frag_input(struct ir3_compile *ctx, unsigned n, bool use_ldlv)
533 {
534 struct ir3_block *block = ctx->block;
535 struct ir3_instruction *instr;
536 struct ir3_instruction *inloc = create_immed(block, n);
537
538 if (use_ldlv) {
539 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
540 instr->cat6.type = TYPE_U32;
541 instr->cat6.iim_val = 1;
542 } else {
543 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_pos, 0);
544 instr->regs[2]->wrmask = 0x3;
545 }
546
547 return instr;
548 }
549
550 static struct ir3_instruction *
551 create_frag_coord(struct ir3_compile *ctx, unsigned comp)
552 {
553 struct ir3_block *block = ctx->block;
554 struct ir3_instruction *instr;
555
556 compile_assert(ctx, !ctx->frag_coord[comp]);
557
558 ctx->frag_coord[comp] = create_input(ctx->block, NULL, 0);
559
560 switch (comp) {
561 case 0: /* .x */
562 case 1: /* .y */
563 /* for frag_coord, we get unsigned values.. we need
564 * to subtract (integer) 8 and divide by 16 (right-
565 * shift by 4) then convert to float:
566 *
567 * sub.s tmp, src, 8
568 * shr.b tmp, tmp, 4
569 * mov.u32f32 dst, tmp
570 *
571 */
572 instr = ir3_SUB_S(block, ctx->frag_coord[comp], 0,
573 create_immed(block, 8), 0);
574 instr = ir3_SHR_B(block, instr, 0,
575 create_immed(block, 4), 0);
576 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
577
578 return instr;
579 case 2: /* .z */
580 case 3: /* .w */
581 default:
582 /* seems that we can use these as-is: */
583 return ctx->frag_coord[comp];
584 }
585 }
586
587 static struct ir3_instruction *
588 create_frag_face(struct ir3_compile *ctx, unsigned comp)
589 {
590 struct ir3_block *block = ctx->block;
591 struct ir3_instruction *instr;
592
593 switch (comp) {
594 case 0: /* .x */
595 compile_assert(ctx, !ctx->frag_face);
596
597 ctx->frag_face = create_input(block, NULL, 0);
598 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
599
600 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
601 * positive vs negative float.. and piglit further seems to
602 * expect -1.0 or 1.0:
603 *
604 * mul.s tmp, hr0.x, 2
605 * add.s tmp, tmp, 1
606 * mov.s32f32, dst, tmp
607 *
608 */
609 instr = ir3_MUL_S(block, ctx->frag_face, 0,
610 create_immed(block, 2), 0);
611 instr = ir3_ADD_S(block, instr, 0,
612 create_immed(block, 1), 0);
613 instr = ir3_COV(block, instr, TYPE_S32, TYPE_F32);
614
615 return instr;
616 case 1: /* .y */
617 case 2: /* .z */
618 return create_immed(block, fui(0.0));
619 default:
620 case 3: /* .w */
621 return create_immed(block, fui(1.0));
622 }
623 }
624
625 /* helper for instructions that produce multiple consecutive scalar
626 * outputs which need to have a split/fanout meta instruction inserted
627 */
628 static void
629 split_dest(struct ir3_block *block, struct ir3_instruction **dst,
630 struct ir3_instruction *src)
631 {
632 struct ir3_instruction *prev = NULL;
633 for (int i = 0, j = 0; i < 4; i++) {
634 struct ir3_instruction *split =
635 ir3_instr_create(block, -1, OPC_META_FO);
636 ir3_reg_create(split, 0, IR3_REG_SSA);
637 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = src;
638 split->fo.off = i;
639
640 if (prev) {
641 split->cp.left = prev;
642 split->cp.left_cnt++;
643 prev->cp.right = split;
644 prev->cp.right_cnt++;
645 }
646 prev = split;
647
648 if (src->regs[0]->wrmask & (1 << i))
649 dst[j++] = split;
650 }
651 }
652
653 /*
654 * Adreno uses uint rather than having dedicated bool type,
655 * which (potentially) requires some conversion, in particular
656 * when using output of an bool instr to int input, or visa
657 * versa.
658 *
659 * | Adreno | NIR |
660 * -------+---------+-------+-
661 * true | 1 | ~0 |
662 * false | 0 | 0 |
663 *
664 * To convert from an adreno bool (uint) to nir, use:
665 *
666 * absneg.s dst, (neg)src
667 *
668 * To convert back in the other direction:
669 *
670 * absneg.s dst, (abs)arc
671 *
672 * The CP step can clean up the absneg.s that cancel each other
673 * out, and with a slight bit of extra cleverness (to recognize
674 * the instructions which produce either a 0 or 1) can eliminate
675 * the absneg.s's completely when an instruction that wants
676 * 0/1 consumes the result. For example, when a nir 'bcsel'
677 * consumes the result of 'feq'. So we should be able to get by
678 * without a boolean resolve step, and without incuring any
679 * extra penalty in instruction count.
680 */
681
682 /* NIR bool -> native (adreno): */
683 static struct ir3_instruction *
684 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
685 {
686 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
687 }
688
689 /* native (adreno) -> NIR bool: */
690 static struct ir3_instruction *
691 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
692 {
693 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
694 }
695
696 /*
697 * alu/sfu instructions:
698 */
699
700 static void
701 emit_alu(struct ir3_compile *ctx, nir_alu_instr *alu)
702 {
703 const nir_op_info *info = &nir_op_infos[alu->op];
704 struct ir3_instruction **dst, *src[info->num_inputs];
705 struct ir3_block *b = ctx->block;
706
707 dst = get_dst(ctx, &alu->dest.dest, MAX2(info->output_size, 1));
708
709 /* Vectors are special in that they have non-scalarized writemasks,
710 * and just take the first swizzle channel for each argument in
711 * order into each writemask channel.
712 */
713 if ((alu->op == nir_op_vec2) ||
714 (alu->op == nir_op_vec3) ||
715 (alu->op == nir_op_vec4)) {
716
717 for (int i = 0; i < info->num_inputs; i++) {
718 nir_alu_src *asrc = &alu->src[i];
719
720 compile_assert(ctx, !asrc->abs);
721 compile_assert(ctx, !asrc->negate);
722
723 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[0]];
724 if (!src[i])
725 src[i] = create_immed(ctx->block, 0);
726 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
727 }
728
729 return;
730 }
731
732 /* General case: We can just grab the one used channel per src. */
733 for (int i = 0; i < info->num_inputs; i++) {
734 unsigned chan = ffs(alu->dest.write_mask) - 1;
735 nir_alu_src *asrc = &alu->src[i];
736
737 compile_assert(ctx, !asrc->abs);
738 compile_assert(ctx, !asrc->negate);
739
740 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
741
742 compile_assert(ctx, src[i]);
743 }
744
745 switch (alu->op) {
746 case nir_op_f2i:
747 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_S32);
748 break;
749 case nir_op_f2u:
750 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_U32);
751 break;
752 case nir_op_i2f:
753 dst[0] = ir3_COV(b, src[0], TYPE_S32, TYPE_F32);
754 break;
755 case nir_op_u2f:
756 dst[0] = ir3_COV(b, src[0], TYPE_U32, TYPE_F32);
757 break;
758 case nir_op_imov:
759 dst[0] = ir3_MOV(b, src[0], TYPE_S32);
760 break;
761 case nir_op_fmov:
762 dst[0] = ir3_MOV(b, src[0], TYPE_F32);
763 break;
764 case nir_op_f2b:
765 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
766 dst[0]->cat2.condition = IR3_COND_NE;
767 dst[0] = ir3_n2b(b, dst[0]);
768 break;
769 case nir_op_b2f:
770 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
771 break;
772 case nir_op_b2i:
773 dst[0] = ir3_b2n(b, src[0]);
774 break;
775 case nir_op_i2b:
776 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
777 dst[0]->cat2.condition = IR3_COND_NE;
778 dst[0] = ir3_n2b(b, dst[0]);
779 break;
780
781 case nir_op_fneg:
782 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
783 break;
784 case nir_op_fabs:
785 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
786 break;
787 case nir_op_fmax:
788 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
789 break;
790 case nir_op_fmin:
791 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
792 break;
793 case nir_op_fmul:
794 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
795 break;
796 case nir_op_fadd:
797 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
798 break;
799 case nir_op_fsub:
800 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
801 break;
802 case nir_op_ffma:
803 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
804 break;
805 case nir_op_fddx:
806 dst[0] = ir3_DSX(b, src[0], 0);
807 dst[0]->cat5.type = TYPE_F32;
808 break;
809 case nir_op_fddy:
810 dst[0] = ir3_DSY(b, src[0], 0);
811 dst[0]->cat5.type = TYPE_F32;
812 break;
813 break;
814 case nir_op_flt:
815 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
816 dst[0]->cat2.condition = IR3_COND_LT;
817 dst[0] = ir3_n2b(b, dst[0]);
818 break;
819 case nir_op_fge:
820 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
821 dst[0]->cat2.condition = IR3_COND_GE;
822 dst[0] = ir3_n2b(b, dst[0]);
823 break;
824 case nir_op_feq:
825 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
826 dst[0]->cat2.condition = IR3_COND_EQ;
827 dst[0] = ir3_n2b(b, dst[0]);
828 break;
829 case nir_op_fne:
830 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
831 dst[0]->cat2.condition = IR3_COND_NE;
832 dst[0] = ir3_n2b(b, dst[0]);
833 break;
834 case nir_op_fceil:
835 dst[0] = ir3_CEIL_F(b, src[0], 0);
836 break;
837 case nir_op_ffloor:
838 dst[0] = ir3_FLOOR_F(b, src[0], 0);
839 break;
840 case nir_op_ftrunc:
841 dst[0] = ir3_TRUNC_F(b, src[0], 0);
842 break;
843 case nir_op_fround_even:
844 dst[0] = ir3_RNDNE_F(b, src[0], 0);
845 break;
846 case nir_op_fsign:
847 dst[0] = ir3_SIGN_F(b, src[0], 0);
848 break;
849
850 case nir_op_fsin:
851 dst[0] = ir3_SIN(b, src[0], 0);
852 break;
853 case nir_op_fcos:
854 dst[0] = ir3_COS(b, src[0], 0);
855 break;
856 case nir_op_frsq:
857 dst[0] = ir3_RSQ(b, src[0], 0);
858 break;
859 case nir_op_frcp:
860 dst[0] = ir3_RCP(b, src[0], 0);
861 break;
862 case nir_op_flog2:
863 dst[0] = ir3_LOG2(b, src[0], 0);
864 break;
865 case nir_op_fexp2:
866 dst[0] = ir3_EXP2(b, src[0], 0);
867 break;
868 case nir_op_fsqrt:
869 dst[0] = ir3_SQRT(b, src[0], 0);
870 break;
871
872 case nir_op_iabs:
873 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
874 break;
875 case nir_op_iadd:
876 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
877 break;
878 case nir_op_iand:
879 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
880 break;
881 case nir_op_imax:
882 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
883 break;
884 case nir_op_imin:
885 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
886 break;
887 case nir_op_imul:
888 /*
889 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
890 * mull.u tmp0, a, b ; mul low, i.e. al * bl
891 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
892 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
893 */
894 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
895 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
896 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
897 break;
898 case nir_op_ineg:
899 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
900 break;
901 case nir_op_inot:
902 dst[0] = ir3_NOT_B(b, src[0], 0);
903 break;
904 case nir_op_ior:
905 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
906 break;
907 case nir_op_ishl:
908 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
909 break;
910 case nir_op_ishr:
911 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
912 break;
913 case nir_op_isign: {
914 /* maybe this would be sane to lower in nir.. */
915 struct ir3_instruction *neg, *pos;
916
917 neg = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
918 neg->cat2.condition = IR3_COND_LT;
919
920 pos = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
921 pos->cat2.condition = IR3_COND_GT;
922
923 dst[0] = ir3_SUB_U(b, pos, 0, neg, 0);
924
925 break;
926 }
927 case nir_op_isub:
928 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
929 break;
930 case nir_op_ixor:
931 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
932 break;
933 case nir_op_ushr:
934 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
935 break;
936 case nir_op_ilt:
937 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
938 dst[0]->cat2.condition = IR3_COND_LT;
939 dst[0] = ir3_n2b(b, dst[0]);
940 break;
941 case nir_op_ige:
942 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
943 dst[0]->cat2.condition = IR3_COND_GE;
944 dst[0] = ir3_n2b(b, dst[0]);
945 break;
946 case nir_op_ieq:
947 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
948 dst[0]->cat2.condition = IR3_COND_EQ;
949 dst[0] = ir3_n2b(b, dst[0]);
950 break;
951 case nir_op_ine:
952 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
953 dst[0]->cat2.condition = IR3_COND_NE;
954 dst[0] = ir3_n2b(b, dst[0]);
955 break;
956 case nir_op_ult:
957 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
958 dst[0]->cat2.condition = IR3_COND_LT;
959 dst[0] = ir3_n2b(b, dst[0]);
960 break;
961 case nir_op_uge:
962 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
963 dst[0]->cat2.condition = IR3_COND_GE;
964 dst[0] = ir3_n2b(b, dst[0]);
965 break;
966
967 case nir_op_bcsel:
968 dst[0] = ir3_SEL_B32(b, src[1], 0, ir3_b2n(b, src[0]), 0, src[2], 0);
969 break;
970
971 default:
972 compile_error(ctx, "Unhandled ALU op: %s\n",
973 nir_op_infos[alu->op].name);
974 break;
975 }
976 }
977
978 /* handles direct/indirect UBO reads: */
979 static void
980 emit_intrinsic_load_ubo(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
981 struct ir3_instruction **dst)
982 {
983 struct ir3_block *b = ctx->block;
984 struct ir3_instruction *addr, *src0, *src1;
985 /* UBO addresses are the first driver params: */
986 unsigned ubo = regid(ctx->so->first_driver_param, 0);
987 unsigned off = intr->const_index[0];
988
989 /* First src is ubo index, which could either be an immed or not: */
990 src0 = get_src(ctx, &intr->src[0])[0];
991 if (is_same_type_mov(src0) &&
992 (src0->regs[1]->flags & IR3_REG_IMMED)) {
993 addr = create_uniform(ctx, ubo + src0->regs[1]->iim_val);
994 } else {
995 addr = create_uniform_indirect(ctx, ubo, get_addr(ctx, src0));
996 }
997
998 if (intr->intrinsic == nir_intrinsic_load_ubo_indirect) {
999 /* For load_ubo_indirect, second src is indirect offset: */
1000 src1 = get_src(ctx, &intr->src[1])[0];
1001
1002 /* and add offset to addr: */
1003 addr = ir3_ADD_S(b, addr, 0, src1, 0);
1004 }
1005
1006 /* if offset is to large to encode in the ldg, split it out: */
1007 if ((off + (intr->num_components * 4)) > 1024) {
1008 /* split out the minimal amount to improve the odds that
1009 * cp can fit the immediate in the add.s instruction:
1010 */
1011 unsigned off2 = off + (intr->num_components * 4) - 1024;
1012 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
1013 off -= off2;
1014 }
1015
1016 for (int i = 0; i < intr->num_components; i++) {
1017 struct ir3_instruction *load =
1018 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
1019 load->cat6.type = TYPE_U32;
1020 load->cat6.offset = off + i * 4; /* byte offset */
1021 dst[i] = load;
1022 }
1023 }
1024
1025 /* handles array reads: */
1026 static void
1027 emit_intrinisic_load_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
1028 struct ir3_instruction **dst)
1029 {
1030 nir_deref_var *dvar = intr->variables[0];
1031 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
1032 struct ir3_array *arr = get_var(ctx, dvar->var);
1033
1034 compile_assert(ctx, dvar->deref.child &&
1035 (dvar->deref.child->deref_type == nir_deref_type_array));
1036
1037 switch (darr->deref_array_type) {
1038 case nir_deref_array_type_direct:
1039 /* direct access does not require anything special: */
1040 for (int i = 0; i < intr->num_components; i++) {
1041 unsigned n = darr->base_offset * 4 + i;
1042 compile_assert(ctx, n < arr->length);
1043 dst[i] = arr->arr[n];
1044 }
1045 break;
1046 case nir_deref_array_type_indirect: {
1047 /* for indirect, we need to collect all the array elements: */
1048 struct ir3_instruction *collect =
1049 create_collect(ctx->block, arr->arr, arr->length);
1050 struct ir3_instruction *addr =
1051 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1052 for (int i = 0; i < intr->num_components; i++) {
1053 unsigned n = darr->base_offset * 4 + i;
1054 compile_assert(ctx, n < arr->length);
1055 dst[i] = create_indirect_load(ctx, arr->length, n, addr, collect);
1056 }
1057 break;
1058 }
1059 default:
1060 compile_error(ctx, "Unhandled load deref type: %u\n",
1061 darr->deref_array_type);
1062 break;
1063 }
1064 }
1065
1066 /* handles array writes: */
1067 static void
1068 emit_intrinisic_store_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1069 {
1070 nir_deref_var *dvar = intr->variables[0];
1071 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
1072 struct ir3_array *arr = get_var(ctx, dvar->var);
1073 struct ir3_instruction **src;
1074
1075 compile_assert(ctx, dvar->deref.child &&
1076 (dvar->deref.child->deref_type == nir_deref_type_array));
1077
1078 src = get_src(ctx, &intr->src[0]);
1079
1080 switch (darr->deref_array_type) {
1081 case nir_deref_array_type_direct:
1082 /* direct access does not require anything special: */
1083 for (int i = 0; i < intr->num_components; i++) {
1084 unsigned n = darr->base_offset * 4 + i;
1085 compile_assert(ctx, n < arr->length);
1086 arr->arr[n] = src[i];
1087 }
1088 break;
1089 case nir_deref_array_type_indirect: {
1090 /* for indirect, create indirect-store and fan that out: */
1091 struct ir3_instruction *collect =
1092 create_collect(ctx->block, arr->arr, arr->length);
1093 struct ir3_instruction *addr =
1094 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1095 for (int i = 0; i < intr->num_components; i++) {
1096 struct ir3_instruction *store;
1097 unsigned n = darr->base_offset * 4 + i;
1098 compile_assert(ctx, n < arr->length);
1099
1100 store = create_indirect_store(ctx, arr->length,
1101 n, src[i], addr, collect);
1102
1103 store->fanin->fi.aid = arr->aid;
1104
1105 /* TODO: probably split this out to be used for
1106 * store_output_indirect? or move this into
1107 * create_indirect_store()?
1108 */
1109 for (int j = i; j < arr->length; j += 4) {
1110 struct ir3_instruction *split;
1111
1112 split = ir3_instr_create(ctx->block, -1, OPC_META_FO);
1113 split->fo.off = j;
1114 ir3_reg_create(split, 0, 0);
1115 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = store;
1116
1117 arr->arr[j] = split;
1118 }
1119 }
1120 break;
1121 }
1122 default:
1123 compile_error(ctx, "Unhandled store deref type: %u\n",
1124 darr->deref_array_type);
1125 break;
1126 }
1127 }
1128
1129 static void add_sysval_input(struct ir3_compile *ctx, unsigned name,
1130 struct ir3_instruction *instr)
1131 {
1132 struct ir3_shader_variant *so = ctx->so;
1133 unsigned r = regid(so->inputs_count, 0);
1134 unsigned n = so->inputs_count++;
1135
1136 so->inputs[n].semantic = ir3_semantic_name(name, 0);
1137 so->inputs[n].compmask = 1;
1138 so->inputs[n].regid = r;
1139 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1140 so->total_in++;
1141
1142 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1143 ctx->ir->inputs[r] = instr;
1144 }
1145
1146 static void
1147 emit_intrinisic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1148 {
1149 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1150 struct ir3_instruction **dst, **src;
1151 struct ir3_block *b = ctx->block;
1152 unsigned idx = intr->const_index[0];
1153
1154 if (info->has_dest) {
1155 dst = get_dst(ctx, &intr->dest, intr->num_components);
1156 } else {
1157 dst = NULL;
1158 }
1159
1160 switch (intr->intrinsic) {
1161 case nir_intrinsic_load_uniform:
1162 for (int i = 0; i < intr->num_components; i++) {
1163 unsigned n = idx * 4 + i;
1164 dst[i] = create_uniform(ctx, n);
1165 }
1166 break;
1167 case nir_intrinsic_load_uniform_indirect:
1168 src = get_src(ctx, &intr->src[0]);
1169 for (int i = 0; i < intr->num_components; i++) {
1170 unsigned n = idx * 4 + i;
1171 dst[i] = create_uniform_indirect(ctx, n,
1172 get_addr(ctx, src[0]));
1173 }
1174 break;
1175 case nir_intrinsic_load_ubo:
1176 case nir_intrinsic_load_ubo_indirect:
1177 emit_intrinsic_load_ubo(ctx, intr, dst);
1178 break;
1179 case nir_intrinsic_load_input:
1180 for (int i = 0; i < intr->num_components; i++) {
1181 unsigned n = idx * 4 + i;
1182 dst[i] = ctx->ir->inputs[n];
1183 }
1184 break;
1185 case nir_intrinsic_load_input_indirect:
1186 src = get_src(ctx, &intr->src[0]);
1187 struct ir3_instruction *collect =
1188 create_collect(b, ctx->ir->inputs, ctx->ir->ninputs);
1189 struct ir3_instruction *addr = get_addr(ctx, src[0]);
1190 for (int i = 0; i < intr->num_components; i++) {
1191 unsigned n = idx * 4 + i;
1192 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1193 n, addr, collect);
1194 }
1195 break;
1196 case nir_intrinsic_load_var:
1197 emit_intrinisic_load_var(ctx, intr, dst);
1198 break;
1199 case nir_intrinsic_store_var:
1200 emit_intrinisic_store_var(ctx, intr);
1201 break;
1202 case nir_intrinsic_store_output:
1203 src = get_src(ctx, &intr->src[0]);
1204 for (int i = 0; i < intr->num_components; i++) {
1205 unsigned n = idx * 4 + i;
1206 ctx->ir->outputs[n] = src[i];
1207 }
1208 break;
1209 case nir_intrinsic_load_base_vertex:
1210 if (!ctx->basevertex) {
1211 /* first four vec4 sysval's reserved for UBOs: */
1212 unsigned r = regid(ctx->so->first_driver_param + 4, 0);
1213 ctx->basevertex = create_uniform(ctx, r);
1214 add_sysval_input(ctx, TGSI_SEMANTIC_BASEVERTEX,
1215 ctx->basevertex);
1216 }
1217 dst[0] = ctx->basevertex;
1218 break;
1219 case nir_intrinsic_load_vertex_id_zero_base:
1220 if (!ctx->vertex_id) {
1221 ctx->vertex_id = create_input(ctx->block, NULL, 0);
1222 add_sysval_input(ctx, TGSI_SEMANTIC_VERTEXID_NOBASE,
1223 ctx->vertex_id);
1224 }
1225 dst[0] = ctx->vertex_id;
1226 break;
1227 case nir_intrinsic_load_instance_id:
1228 if (!ctx->instance_id) {
1229 ctx->instance_id = create_input(ctx->block, NULL, 0);
1230 add_sysval_input(ctx, TGSI_SEMANTIC_INSTANCEID,
1231 ctx->instance_id);
1232 }
1233 dst[0] = ctx->instance_id;
1234 break;
1235 case nir_intrinsic_discard_if:
1236 case nir_intrinsic_discard: {
1237 struct ir3_instruction *cond, *kill;
1238
1239 if (intr->intrinsic == nir_intrinsic_discard_if) {
1240 /* conditional discard: */
1241 src = get_src(ctx, &intr->src[0]);
1242 cond = ir3_b2n(b, src[0]);
1243 } else {
1244 /* unconditional discard: */
1245 cond = create_immed(b, 1);
1246 }
1247
1248 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1249 cond->cat2.condition = IR3_COND_NE;
1250
1251 /* condition always goes in predicate register: */
1252 cond->regs[0]->num = regid(REG_P0, 0);
1253
1254 kill = ir3_KILL(b, cond, 0);
1255 array_insert(ctx->ir->predicates, kill);
1256
1257 ctx->kill[ctx->kill_count++] = kill;
1258 ctx->so->has_kill = true;
1259
1260 break;
1261 }
1262 default:
1263 compile_error(ctx, "Unhandled intrinsic type: %s\n",
1264 nir_intrinsic_infos[intr->intrinsic].name);
1265 break;
1266 }
1267 }
1268
1269 static void
1270 emit_load_const(struct ir3_compile *ctx, nir_load_const_instr *instr)
1271 {
1272 struct ir3_instruction **dst = get_dst_ssa(ctx, &instr->def,
1273 instr->def.num_components);
1274 for (int i = 0; i < instr->def.num_components; i++)
1275 dst[i] = create_immed(ctx->block, instr->value.u[i]);
1276 }
1277
1278 static void
1279 emit_undef(struct ir3_compile *ctx, nir_ssa_undef_instr *undef)
1280 {
1281 struct ir3_instruction **dst = get_dst_ssa(ctx, &undef->def,
1282 undef->def.num_components);
1283 /* backend doesn't want undefined instructions, so just plug
1284 * in 0.0..
1285 */
1286 for (int i = 0; i < undef->def.num_components; i++)
1287 dst[i] = create_immed(ctx->block, fui(0.0));
1288 }
1289
1290 /*
1291 * texture fetch/sample instructions:
1292 */
1293
1294 static void
1295 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1296 {
1297 unsigned coords, flags = 0;
1298
1299 /* note: would use tex->coord_components.. except txs.. also,
1300 * since array index goes after shadow ref, we don't want to
1301 * count it:
1302 */
1303 switch (tex->sampler_dim) {
1304 case GLSL_SAMPLER_DIM_1D:
1305 case GLSL_SAMPLER_DIM_BUF:
1306 coords = 1;
1307 break;
1308 case GLSL_SAMPLER_DIM_2D:
1309 case GLSL_SAMPLER_DIM_RECT:
1310 case GLSL_SAMPLER_DIM_EXTERNAL:
1311 case GLSL_SAMPLER_DIM_MS:
1312 coords = 2;
1313 break;
1314 case GLSL_SAMPLER_DIM_3D:
1315 case GLSL_SAMPLER_DIM_CUBE:
1316 coords = 3;
1317 flags |= IR3_INSTR_3D;
1318 break;
1319 default:
1320 unreachable("bad sampler_dim");
1321 }
1322
1323 if (tex->is_shadow)
1324 flags |= IR3_INSTR_S;
1325
1326 if (tex->is_array)
1327 flags |= IR3_INSTR_A;
1328
1329 *flagsp = flags;
1330 *coordsp = coords;
1331 }
1332
1333 static void
1334 emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex)
1335 {
1336 struct ir3_block *b = ctx->block;
1337 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1338 struct ir3_instruction **coord, *lod, *compare, *proj, **off, **ddx, **ddy;
1339 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1340 unsigned i, coords, flags;
1341 unsigned nsrc0 = 0, nsrc1 = 0;
1342 type_t type;
1343 opc_t opc = 0;
1344
1345 coord = off = ddx = ddy = NULL;
1346 lod = proj = compare = NULL;
1347
1348 /* TODO: might just be one component for gathers? */
1349 dst = get_dst(ctx, &tex->dest, 4);
1350
1351 for (unsigned i = 0; i < tex->num_srcs; i++) {
1352 switch (tex->src[i].src_type) {
1353 case nir_tex_src_coord:
1354 coord = get_src(ctx, &tex->src[i].src);
1355 break;
1356 case nir_tex_src_bias:
1357 lod = get_src(ctx, &tex->src[i].src)[0];
1358 has_bias = true;
1359 break;
1360 case nir_tex_src_lod:
1361 lod = get_src(ctx, &tex->src[i].src)[0];
1362 has_lod = true;
1363 break;
1364 case nir_tex_src_comparitor: /* shadow comparator */
1365 compare = get_src(ctx, &tex->src[i].src)[0];
1366 break;
1367 case nir_tex_src_projector:
1368 proj = get_src(ctx, &tex->src[i].src)[0];
1369 has_proj = true;
1370 break;
1371 case nir_tex_src_offset:
1372 off = get_src(ctx, &tex->src[i].src);
1373 has_off = true;
1374 break;
1375 case nir_tex_src_ddx:
1376 ddx = get_src(ctx, &tex->src[i].src);
1377 break;
1378 case nir_tex_src_ddy:
1379 ddy = get_src(ctx, &tex->src[i].src);
1380 break;
1381 default:
1382 compile_error(ctx, "Unhandled NIR tex serc type: %d\n",
1383 tex->src[i].src_type);
1384 return;
1385 }
1386 }
1387
1388 switch (tex->op) {
1389 case nir_texop_tex: opc = OPC_SAM; break;
1390 case nir_texop_txb: opc = OPC_SAMB; break;
1391 case nir_texop_txl: opc = OPC_SAML; break;
1392 case nir_texop_txd: opc = OPC_SAMGQ; break;
1393 case nir_texop_txf: opc = OPC_ISAML; break;
1394 case nir_texop_txf_ms:
1395 case nir_texop_txs:
1396 case nir_texop_lod:
1397 case nir_texop_tg4:
1398 case nir_texop_query_levels:
1399 compile_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1400 return;
1401 }
1402
1403 tex_info(tex, &flags, &coords);
1404
1405 /* scale up integer coords for TXF based on the LOD */
1406 if (opc == OPC_ISAML) {
1407 assert(has_lod);
1408 for (i = 0; i < coords; i++)
1409 coord[i] = ir3_SHL_B(b, coord[i], 0, lod, 0);
1410 }
1411 /*
1412 * lay out the first argument in the proper order:
1413 * - actual coordinates first
1414 * - shadow reference
1415 * - array index
1416 * - projection w
1417 * - starting at offset 4, dpdx.xy, dpdy.xy
1418 *
1419 * bias/lod go into the second arg
1420 */
1421
1422 /* insert tex coords: */
1423 for (i = 0; i < coords; i++)
1424 src0[nsrc0++] = coord[i];
1425
1426 if (coords == 1) {
1427 /* hw doesn't do 1d, so we treat it as 2d with
1428 * height of 1, and patch up the y coord.
1429 * TODO: y coord should be (int)0 in some cases..
1430 */
1431 src0[nsrc0++] = create_immed(b, fui(0.5));
1432 }
1433
1434 if (tex->is_shadow)
1435 src0[nsrc0++] = compare;
1436
1437 if (tex->is_array)
1438 src0[nsrc0++] = coord[coords];
1439
1440 if (has_proj) {
1441 src0[nsrc0++] = proj;
1442 flags |= IR3_INSTR_P;
1443 }
1444
1445 /* pad to 4, then ddx/ddy: */
1446 if (tex->op == nir_texop_txd) {
1447 while (nsrc0 < 4)
1448 src0[nsrc0++] = create_immed(b, fui(0.0));
1449 for (i = 0; i < coords; i++)
1450 src0[nsrc0++] = ddx[i];
1451 if (coords < 2)
1452 src0[nsrc0++] = create_immed(b, fui(0.0));
1453 for (i = 0; i < coords; i++)
1454 src0[nsrc0++] = ddy[i];
1455 if (coords < 2)
1456 src0[nsrc0++] = create_immed(b, fui(0.0));
1457 }
1458
1459 /*
1460 * second argument (if applicable):
1461 * - offsets
1462 * - lod
1463 * - bias
1464 */
1465 if (has_off | has_lod | has_bias) {
1466 if (has_off) {
1467 for (i = 0; i < coords; i++)
1468 src1[nsrc1++] = off[i];
1469 if (coords < 2)
1470 src1[nsrc1++] = create_immed(b, fui(0.0));
1471 flags |= IR3_INSTR_O;
1472 }
1473
1474 if (has_lod | has_bias)
1475 src1[nsrc1++] = lod;
1476 }
1477
1478 switch (tex->dest_type) {
1479 case nir_type_invalid:
1480 case nir_type_float:
1481 type = TYPE_F32;
1482 break;
1483 case nir_type_int:
1484 type = TYPE_S32;
1485 break;
1486 case nir_type_unsigned:
1487 case nir_type_bool:
1488 type = TYPE_U32;
1489 break;
1490 default:
1491 unreachable("bad dest_type");
1492 }
1493
1494 sam = ir3_SAM(b, opc, type, TGSI_WRITEMASK_XYZW,
1495 flags, tex->sampler_index, tex->sampler_index,
1496 create_collect(b, src0, nsrc0),
1497 create_collect(b, src1, nsrc1));
1498
1499 split_dest(b, dst, sam);
1500 }
1501
1502 static void
1503 emit_tex_query_levels(struct ir3_compile *ctx, nir_tex_instr *tex)
1504 {
1505 struct ir3_block *b = ctx->block;
1506 struct ir3_instruction **dst, *sam;
1507
1508 dst = get_dst(ctx, &tex->dest, 1);
1509
1510 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, TGSI_WRITEMASK_Z, 0,
1511 tex->sampler_index, tex->sampler_index, NULL, NULL);
1512
1513 /* even though there is only one component, since it ends
1514 * up in .z rather than .x, we need a split_dest()
1515 */
1516 split_dest(b, dst, sam);
1517
1518 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1519 * the value in TEX_CONST_0 is zero-based.
1520 */
1521 if (ctx->levels_add_one)
1522 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1523 }
1524
1525 static void
1526 emit_tex_txs(struct ir3_compile *ctx, nir_tex_instr *tex)
1527 {
1528 struct ir3_block *b = ctx->block;
1529 struct ir3_instruction **dst, *sam, *lod;
1530 unsigned flags, coords;
1531
1532 tex_info(tex, &flags, &coords);
1533
1534 dst = get_dst(ctx, &tex->dest, 4);
1535
1536 compile_assert(ctx, tex->num_srcs == 1);
1537 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
1538
1539 lod = get_src(ctx, &tex->src[0].src)[0];
1540
1541 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, TGSI_WRITEMASK_XYZW, flags,
1542 tex->sampler_index, tex->sampler_index, lod, NULL);
1543
1544 split_dest(b, dst, sam);
1545
1546 /* Array size actually ends up in .w rather than .z. This doesn't
1547 * matter for miplevel 0, but for higher mips the value in z is
1548 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1549 * returned, which means that we have to add 1 to it for arrays.
1550 */
1551 if (tex->is_array) {
1552 if (ctx->levels_add_one) {
1553 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
1554 } else {
1555 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
1556 }
1557 }
1558 }
1559
1560 static void
1561 emit_instr(struct ir3_compile *ctx, nir_instr *instr)
1562 {
1563 switch (instr->type) {
1564 case nir_instr_type_alu:
1565 emit_alu(ctx, nir_instr_as_alu(instr));
1566 break;
1567 case nir_instr_type_intrinsic:
1568 emit_intrinisic(ctx, nir_instr_as_intrinsic(instr));
1569 break;
1570 case nir_instr_type_load_const:
1571 emit_load_const(ctx, nir_instr_as_load_const(instr));
1572 break;
1573 case nir_instr_type_ssa_undef:
1574 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1575 break;
1576 case nir_instr_type_tex: {
1577 nir_tex_instr *tex = nir_instr_as_tex(instr);
1578 /* couple tex instructions get special-cased:
1579 */
1580 switch (tex->op) {
1581 case nir_texop_txs:
1582 emit_tex_txs(ctx, tex);
1583 break;
1584 case nir_texop_query_levels:
1585 emit_tex_query_levels(ctx, tex);
1586 break;
1587 default:
1588 emit_tex(ctx, tex);
1589 break;
1590 }
1591 break;
1592 }
1593 case nir_instr_type_call:
1594 case nir_instr_type_jump:
1595 case nir_instr_type_phi:
1596 case nir_instr_type_parallel_copy:
1597 compile_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1598 break;
1599 }
1600 }
1601
1602 static void
1603 emit_block(struct ir3_compile *ctx, nir_block *block)
1604 {
1605 nir_foreach_instr(block, instr) {
1606 emit_instr(ctx, instr);
1607 if (ctx->error)
1608 return;
1609 }
1610 }
1611
1612 static void
1613 emit_function(struct ir3_compile *ctx, nir_function_impl *impl)
1614 {
1615 foreach_list_typed(nir_cf_node, node, node, &impl->body) {
1616 switch (node->type) {
1617 case nir_cf_node_block:
1618 emit_block(ctx, nir_cf_node_as_block(node));
1619 break;
1620 case nir_cf_node_if:
1621 case nir_cf_node_loop:
1622 case nir_cf_node_function:
1623 compile_error(ctx, "TODO\n");
1624 break;
1625 }
1626 if (ctx->error)
1627 return;
1628 }
1629 }
1630
1631 static void
1632 setup_input(struct ir3_compile *ctx, nir_variable *in)
1633 {
1634 struct ir3_shader_variant *so = ctx->so;
1635 unsigned array_len = MAX2(glsl_get_length(in->type), 1);
1636 unsigned ncomp = glsl_get_components(in->type);
1637 /* XXX: map loc slots to semantics */
1638 unsigned semantic_name = in->data.location;
1639 unsigned semantic_index = in->data.index;
1640 unsigned n = in->data.driver_location;
1641
1642 DBG("; in: %u:%u, len=%ux%u, loc=%u\n",
1643 semantic_name, semantic_index, array_len,
1644 ncomp, n);
1645
1646 so->inputs[n].semantic =
1647 ir3_semantic_name(semantic_name, semantic_index);
1648 so->inputs[n].compmask = (1 << ncomp) - 1;
1649 so->inputs[n].inloc = ctx->next_inloc;
1650 so->inputs[n].interpolate = 0;
1651 so->inputs_count = MAX2(so->inputs_count, n + 1);
1652
1653 /* the fdN_program_emit() code expects tgsi consts here, so map
1654 * things back to tgsi for now:
1655 */
1656 switch (in->data.interpolation) {
1657 case INTERP_QUALIFIER_FLAT:
1658 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1659 break;
1660 case INTERP_QUALIFIER_NOPERSPECTIVE:
1661 so->inputs[n].interpolate = TGSI_INTERPOLATE_LINEAR;
1662 break;
1663 case INTERP_QUALIFIER_SMOOTH:
1664 so->inputs[n].interpolate = TGSI_INTERPOLATE_PERSPECTIVE;
1665 break;
1666 }
1667
1668 for (int i = 0; i < ncomp; i++) {
1669 struct ir3_instruction *instr = NULL;
1670 unsigned idx = (n * 4) + i;
1671
1672 if (ctx->so->type == SHADER_FRAGMENT) {
1673 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1674 so->inputs[n].bary = false;
1675 so->frag_coord = true;
1676 instr = create_frag_coord(ctx, i);
1677 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1678 so->inputs[n].bary = false;
1679 so->frag_face = true;
1680 instr = create_frag_face(ctx, i);
1681 } else {
1682 bool use_ldlv = false;
1683
1684 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1685 * from the semantic name:
1686 */
1687 if ((in->data.interpolation == INTERP_QUALIFIER_NONE) &&
1688 ((semantic_name == TGSI_SEMANTIC_COLOR) ||
1689 (semantic_name == TGSI_SEMANTIC_BCOLOR)))
1690 so->inputs[n].interpolate = TGSI_INTERPOLATE_COLOR;
1691
1692 if (ctx->flat_bypass) {
1693 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1694 * from the semantic name:
1695 */
1696 switch (so->inputs[n].interpolate) {
1697 case TGSI_INTERPOLATE_COLOR:
1698 if (!ctx->so->key.rasterflat)
1699 break;
1700 /* fallthrough */
1701 case TGSI_INTERPOLATE_CONSTANT:
1702 use_ldlv = true;
1703 break;
1704 }
1705 }
1706
1707 so->inputs[n].bary = true;
1708
1709 instr = create_frag_input(ctx,
1710 so->inputs[n].inloc + i - 8, use_ldlv);
1711 }
1712 } else {
1713 instr = create_input(ctx->block, NULL, idx);
1714 }
1715
1716 ctx->ir->inputs[idx] = instr;
1717 }
1718
1719 if (so->inputs[n].bary || (ctx->so->type == SHADER_VERTEX)) {
1720 ctx->next_inloc += ncomp;
1721 so->total_in += ncomp;
1722 }
1723 }
1724
1725 static void
1726 setup_output(struct ir3_compile *ctx, nir_variable *out)
1727 {
1728 struct ir3_shader_variant *so = ctx->so;
1729 unsigned array_len = MAX2(glsl_get_length(out->type), 1);
1730 unsigned ncomp = glsl_get_components(out->type);
1731 /* XXX: map loc slots to semantics */
1732 unsigned semantic_name = out->data.location;
1733 unsigned semantic_index = out->data.index;
1734 unsigned n = out->data.driver_location;
1735 unsigned comp = 0;
1736
1737 DBG("; out: %u:%u, len=%ux%u, loc=%u\n",
1738 semantic_name, semantic_index, array_len,
1739 ncomp, n);
1740
1741 if (ctx->so->type == SHADER_VERTEX) {
1742 switch (semantic_name) {
1743 case TGSI_SEMANTIC_POSITION:
1744 so->writes_pos = true;
1745 break;
1746 case TGSI_SEMANTIC_PSIZE:
1747 so->writes_psize = true;
1748 break;
1749 case TGSI_SEMANTIC_COLOR:
1750 case TGSI_SEMANTIC_BCOLOR:
1751 case TGSI_SEMANTIC_GENERIC:
1752 case TGSI_SEMANTIC_FOG:
1753 case TGSI_SEMANTIC_TEXCOORD:
1754 break;
1755 default:
1756 compile_error(ctx, "unknown VS semantic name: %s\n",
1757 tgsi_semantic_names[semantic_name]);
1758 }
1759 } else {
1760 switch (semantic_name) {
1761 case TGSI_SEMANTIC_POSITION:
1762 comp = 2; /* tgsi will write to .z component */
1763 so->writes_pos = true;
1764 break;
1765 case TGSI_SEMANTIC_COLOR:
1766 break;
1767 default:
1768 compile_error(ctx, "unknown FS semantic name: %s\n",
1769 tgsi_semantic_names[semantic_name]);
1770 }
1771 }
1772
1773 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
1774
1775 so->outputs[n].semantic =
1776 ir3_semantic_name(semantic_name, semantic_index);
1777 so->outputs[n].regid = regid(n, comp);
1778 so->outputs_count = MAX2(so->outputs_count, n + 1);
1779
1780 for (int i = 0; i < ncomp; i++) {
1781 unsigned idx = (n * 4) + i;
1782
1783 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
1784 }
1785 }
1786
1787 static void
1788 emit_instructions(struct ir3_compile *ctx)
1789 {
1790 unsigned ninputs = exec_list_length(&ctx->s->inputs) * 4;
1791 unsigned noutputs = exec_list_length(&ctx->s->outputs) * 4;
1792
1793 /* we need to allocate big enough outputs array so that
1794 * we can stuff the kill's at the end. Likewise for vtx
1795 * shaders, we need to leave room for sysvals:
1796 */
1797 if (ctx->so->type == SHADER_FRAGMENT) {
1798 noutputs += ARRAY_SIZE(ctx->kill);
1799 } else if (ctx->so->type == SHADER_VERTEX) {
1800 ninputs += 8;
1801 }
1802
1803 ctx->ir = ir3_create(ctx->compiler, ninputs, noutputs);
1804 ctx->block = ir3_block_create(ctx->ir);
1805 ctx->ir->block = ctx->block;
1806
1807 if (ctx->so->type == SHADER_FRAGMENT) {
1808 ctx->ir->noutputs -= ARRAY_SIZE(ctx->kill);
1809 } else if (ctx->so->type == SHADER_VERTEX) {
1810 ctx->ir->ninputs -= 8;
1811 }
1812
1813 /* for fragment shader, we have a single input register (usually
1814 * r0.xy) which is used as the base for bary.f varying fetch instrs:
1815 */
1816 if (ctx->so->type == SHADER_FRAGMENT) {
1817 // TODO maybe a helper for fi since we need it a few places..
1818 struct ir3_instruction *instr;
1819 instr = ir3_instr_create(ctx->block, -1, OPC_META_FI);
1820 ir3_reg_create(instr, 0, 0);
1821 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.x */
1822 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.y */
1823 ctx->frag_pos = instr;
1824 }
1825
1826 /* Setup inputs: */
1827 foreach_list_typed(nir_variable, var, node, &ctx->s->inputs) {
1828 setup_input(ctx, var);
1829 }
1830
1831 /* Setup outputs: */
1832 foreach_list_typed(nir_variable, var, node, &ctx->s->outputs) {
1833 setup_output(ctx, var);
1834 }
1835
1836 /* Setup variables (which should only be arrays): */
1837 foreach_list_typed(nir_variable, var, node, &ctx->s->globals) {
1838 declare_var(ctx, var);
1839 }
1840
1841 /* Find the main function and emit the body: */
1842 nir_foreach_overload(ctx->s, overload) {
1843 compile_assert(ctx, strcmp(overload->function->name, "main") == 0);
1844 compile_assert(ctx, overload->impl);
1845 emit_function(ctx, overload->impl);
1846 if (ctx->error)
1847 return;
1848 }
1849 }
1850
1851 /* from NIR perspective, we actually have inputs. But most of the "inputs"
1852 * for a fragment shader are just bary.f instructions. The *actual* inputs
1853 * from the hw perspective are the frag_pos and optionally frag_coord and
1854 * frag_face.
1855 */
1856 static void
1857 fixup_frag_inputs(struct ir3_compile *ctx)
1858 {
1859 struct ir3_shader_variant *so = ctx->so;
1860 struct ir3 *ir = ctx->ir;
1861 struct ir3_instruction **inputs;
1862 struct ir3_instruction *instr;
1863 int n, regid = 0;
1864
1865 ir->ninputs = 0;
1866
1867 n = 4; /* always have frag_pos */
1868 n += COND(so->frag_face, 4);
1869 n += COND(so->frag_coord, 4);
1870
1871 inputs = ir3_alloc(ctx->ir, n * (sizeof(struct ir3_instruction *)));
1872
1873 if (so->frag_face) {
1874 /* this ultimately gets assigned to hr0.x so doesn't conflict
1875 * with frag_coord/frag_pos..
1876 */
1877 inputs[ir->ninputs++] = ctx->frag_face;
1878 ctx->frag_face->regs[0]->num = 0;
1879
1880 /* remaining channels not used, but let's avoid confusing
1881 * other parts that expect inputs to come in groups of vec4
1882 */
1883 inputs[ir->ninputs++] = NULL;
1884 inputs[ir->ninputs++] = NULL;
1885 inputs[ir->ninputs++] = NULL;
1886 }
1887
1888 /* since we don't know where to set the regid for frag_coord,
1889 * we have to use r0.x for it. But we don't want to *always*
1890 * use r1.x for frag_pos as that could increase the register
1891 * footprint on simple shaders:
1892 */
1893 if (so->frag_coord) {
1894 ctx->frag_coord[0]->regs[0]->num = regid++;
1895 ctx->frag_coord[1]->regs[0]->num = regid++;
1896 ctx->frag_coord[2]->regs[0]->num = regid++;
1897 ctx->frag_coord[3]->regs[0]->num = regid++;
1898
1899 inputs[ir->ninputs++] = ctx->frag_coord[0];
1900 inputs[ir->ninputs++] = ctx->frag_coord[1];
1901 inputs[ir->ninputs++] = ctx->frag_coord[2];
1902 inputs[ir->ninputs++] = ctx->frag_coord[3];
1903 }
1904
1905 /* we always have frag_pos: */
1906 so->pos_regid = regid;
1907
1908 /* r0.x */
1909 instr = create_input(ctx->block, NULL, ir->ninputs);
1910 instr->regs[0]->num = regid++;
1911 inputs[ir->ninputs++] = instr;
1912 ctx->frag_pos->regs[1]->instr = instr;
1913
1914 /* r0.y */
1915 instr = create_input(ctx->block, NULL, ir->ninputs);
1916 instr->regs[0]->num = regid++;
1917 inputs[ir->ninputs++] = instr;
1918 ctx->frag_pos->regs[2]->instr = instr;
1919
1920 ir->inputs = inputs;
1921 }
1922
1923 int
1924 ir3_compile_shader_nir(struct ir3_compiler *compiler,
1925 struct ir3_shader_variant *so,
1926 const struct tgsi_token *tokens,
1927 struct ir3_shader_key key)
1928 {
1929 struct ir3_compile *ctx;
1930 struct ir3 *ir;
1931 struct ir3_instruction **inputs;
1932 unsigned i, j, actual_in;
1933 int ret = 0, max_bary;
1934
1935 assert(!so->ir);
1936
1937 ctx = compile_init(compiler, so, tokens);
1938 if (!ctx) {
1939 DBG("INIT failed!");
1940 ret = -1;
1941 goto out;
1942 }
1943
1944 emit_instructions(ctx);
1945
1946 if (ctx->error) {
1947 DBG("EMIT failed!");
1948 ret = -1;
1949 goto out;
1950 }
1951
1952 ir = so->ir = ctx->ir;
1953
1954 /* keep track of the inputs from TGSI perspective.. */
1955 inputs = ir->inputs;
1956
1957 /* but fixup actual inputs for frag shader: */
1958 if (so->type == SHADER_FRAGMENT)
1959 fixup_frag_inputs(ctx);
1960
1961 /* at this point, for binning pass, throw away unneeded outputs: */
1962 if (key.binning_pass) {
1963 for (i = 0, j = 0; i < so->outputs_count; i++) {
1964 unsigned name = sem2name(so->outputs[i].semantic);
1965 unsigned idx = sem2idx(so->outputs[i].semantic);
1966
1967 /* throw away everything but first position/psize */
1968 if ((idx == 0) && ((name == TGSI_SEMANTIC_POSITION) ||
1969 (name == TGSI_SEMANTIC_PSIZE))) {
1970 if (i != j) {
1971 so->outputs[j] = so->outputs[i];
1972 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
1973 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
1974 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
1975 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
1976 }
1977 j++;
1978 }
1979 }
1980 so->outputs_count = j;
1981 ir->noutputs = j * 4;
1982 }
1983
1984 /* if we want half-precision outputs, mark the output registers
1985 * as half:
1986 */
1987 if (key.half_precision) {
1988 for (i = 0; i < ir->noutputs; i++) {
1989 struct ir3_instruction *out = ir->outputs[i];
1990 if (!out)
1991 continue;
1992 out->regs[0]->flags |= IR3_REG_HALF;
1993 /* output could be a fanout (ie. texture fetch output)
1994 * in which case we need to propagate the half-reg flag
1995 * up to the definer so that RA sees it:
1996 */
1997 if (is_meta(out) && (out->opc == OPC_META_FO)) {
1998 out = out->regs[1]->instr;
1999 out->regs[0]->flags |= IR3_REG_HALF;
2000 }
2001 }
2002 }
2003
2004 /* at this point, we want the kill's in the outputs array too,
2005 * so that they get scheduled (since they have no dst).. we've
2006 * already ensured that the array is big enough in push_block():
2007 */
2008 if (so->type == SHADER_FRAGMENT) {
2009 for (i = 0; i < ctx->kill_count; i++)
2010 ir->outputs[ir->noutputs++] = ctx->kill[i];
2011 }
2012
2013 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2014 printf("BEFORE CP:\n");
2015 ir3_print(ir);
2016 }
2017
2018 ir3_cp(ir);
2019
2020 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2021 printf("BEFORE GROUPING:\n");
2022 ir3_print(ir);
2023 }
2024
2025 /* Group left/right neighbors, inserting mov's where needed to
2026 * solve conflicts:
2027 */
2028 ir3_group(ir);
2029
2030 ir3_depth(ir);
2031
2032 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2033 printf("AFTER DEPTH:\n");
2034 ir3_print(ir);
2035 }
2036
2037 ret = ir3_sched(ir);
2038 if (ret) {
2039 DBG("SCHED failed!");
2040 goto out;
2041 }
2042
2043 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2044 printf("AFTER SCHED:\n");
2045 ir3_print(ir);
2046 }
2047
2048 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
2049 if (ret) {
2050 DBG("RA failed!");
2051 goto out;
2052 }
2053
2054 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2055 printf("AFTER RA:\n");
2056 ir3_print(ir);
2057 }
2058
2059 ir3_legalize(ir, &so->has_samp, &max_bary);
2060
2061 /* fixup input/outputs: */
2062 for (i = 0; i < so->outputs_count; i++) {
2063 so->outputs[i].regid = ir->outputs[i*4]->regs[0]->num;
2064 /* preserve hack for depth output.. tgsi writes depth to .z,
2065 * but what we give the hw is the scalar register:
2066 */
2067 if ((so->type == SHADER_FRAGMENT) &&
2068 (sem2name(so->outputs[i].semantic) == TGSI_SEMANTIC_POSITION))
2069 so->outputs[i].regid += 2;
2070 }
2071
2072 /* Note that some or all channels of an input may be unused: */
2073 actual_in = 0;
2074 for (i = 0; i < so->inputs_count; i++) {
2075 unsigned j, regid = ~0, compmask = 0;
2076 so->inputs[i].ncomp = 0;
2077 for (j = 0; j < 4; j++) {
2078 struct ir3_instruction *in = inputs[(i*4) + j];
2079 if (in) {
2080 compmask |= (1 << j);
2081 regid = in->regs[0]->num - j;
2082 actual_in++;
2083 so->inputs[i].ncomp++;
2084 }
2085 }
2086 so->inputs[i].regid = regid;
2087 so->inputs[i].compmask = compmask;
2088 }
2089
2090 /* fragment shader always gets full vec4's even if it doesn't
2091 * fetch all components, but vertex shader we need to update
2092 * with the actual number of components fetch, otherwise thing
2093 * will hang due to mismaptch between VFD_DECODE's and
2094 * TOTALATTRTOVS
2095 */
2096 if (so->type == SHADER_VERTEX)
2097 so->total_in = actual_in;
2098 else
2099 so->total_in = align(max_bary + 1, 4);
2100
2101 out:
2102 if (ret) {
2103 ir3_destroy(so->ir);
2104 so->ir = NULL;
2105 }
2106 compile_free(ctx);
2107
2108 return ret;
2109 }