1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* For fragment shaders: */
75 struct ir3_instruction
*samp_id
, *samp_mask_in
;
77 /* Compute shader inputs: */
78 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
85 /* a common pattern for indirect addressing is to request the
86 * same address register multiple times. To avoid generating
87 * duplicate instruction sequences (which our backend does not
88 * try to clean up, since that should be done as the NIR stage)
89 * we cache the address value generated for a given src value:
91 * Note that we have to cache these per alignment, since same
92 * src used for an array of vec1 cannot be also used for an
95 struct hash_table
*addr_ht
[4];
97 /* last dst array, for indirect we need to insert a var-store.
99 struct ir3_instruction
**last_dst
;
102 /* maps nir_block to ir3_block, mostly for the purposes of
103 * figuring out the blocks successors
105 struct hash_table
*block_ht
;
107 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
108 * so we need to use ldlv.u32 to load the varying directly:
112 /* on a3xx, we need to add one to # of array levels:
116 /* on a3xx, we need to scale up integer coords for isaml based
119 bool unminify_coords
;
121 /* on a4xx, for array textures we need to add 0.5 to the array
124 bool array_index_add_half
;
126 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
129 unsigned max_texture_index
;
131 /* set if we encounter something we can't handle yet, so we
132 * can bail cleanly and fallback to TGSI compiler f/e
137 /* gpu pointer size in units of 32bit registers/slots */
138 static unsigned pointer_size(struct ir3_context
*ctx
)
140 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
143 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
144 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
147 static struct ir3_context
*
148 compile_init(struct ir3_compiler
*compiler
,
149 struct ir3_shader_variant
*so
)
151 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
153 if (compiler
->gpu_id
>= 400) {
154 /* need special handling for "flat" */
155 ctx
->flat_bypass
= true;
156 ctx
->levels_add_one
= false;
157 ctx
->unminify_coords
= false;
158 ctx
->array_index_add_half
= true;
160 if (so
->type
== SHADER_VERTEX
)
161 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
162 else if (so
->type
== SHADER_FRAGMENT
)
163 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
166 /* no special handling for "flat" */
167 ctx
->flat_bypass
= false;
168 ctx
->levels_add_one
= true;
169 ctx
->unminify_coords
= true;
170 ctx
->array_index_add_half
= false;
173 ctx
->compiler
= compiler
;
176 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
177 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
178 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
179 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
181 /* TODO: maybe generate some sort of bitmask of what key
182 * lowers vs what shader has (ie. no need to lower
183 * texture clamp lowering if no texture sample instrs)..
184 * although should be done further up the stack to avoid
185 * creating duplicate variants..
188 if (ir3_key_lowers_nir(&so
->key
)) {
189 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
190 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
192 /* fast-path for shader key that lowers nothing in NIR: */
193 ctx
->s
= so
->shader
->nir
;
196 /* this needs to be the last pass run, so do this here instead of
197 * in ir3_optimize_nir():
199 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
200 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
202 if (fd_mesa_debug
& FD_DBG_DISASM
) {
203 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
204 so
->shader
->id
, so
->id
, so
->type
,
205 so
->key
.binning_pass
, so
->key
.color_two_side
,
206 so
->key
.half_precision
);
207 nir_print_shader(ctx
->s
, stdout
);
210 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
212 so
->num_uniforms
= ctx
->s
->num_uniforms
;
213 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
215 /* Layout of constant registers, each section aligned to vec4. Note
216 * that pointer size (ubo, etc) changes depending on generation.
221 * if (vertex shader) {
222 * driver params (IR3_DP_*)
223 * if (stream_output.num_outputs > 0)
224 * stream-out addresses
228 * Immediates go last mostly because they are inserted in the CP pass
229 * after the nir -> ir3 frontend.
231 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
232 unsigned ptrsz
= pointer_size(ctx
);
234 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
236 if (so
->num_ubos
> 0) {
237 so
->constbase
.ubo
= constoff
;
238 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
241 if (so
->const_layout
.ssbo_size
.count
> 0) {
242 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
243 so
->constbase
.ssbo_sizes
= constoff
;
244 constoff
+= align(cnt
, 4) / 4;
247 if (so
->const_layout
.image_dims
.count
> 0) {
248 unsigned cnt
= so
->const_layout
.image_dims
.count
;
249 so
->constbase
.image_dims
= constoff
;
250 constoff
+= align(cnt
, 4) / 4;
253 unsigned num_driver_params
= 0;
254 if (so
->type
== SHADER_VERTEX
) {
255 num_driver_params
= IR3_DP_VS_COUNT
;
256 } else if (so
->type
== SHADER_COMPUTE
) {
257 num_driver_params
= IR3_DP_CS_COUNT
;
260 so
->constbase
.driver_param
= constoff
;
261 constoff
+= align(num_driver_params
, 4) / 4;
263 if ((so
->type
== SHADER_VERTEX
) &&
264 (compiler
->gpu_id
< 500) &&
265 so
->shader
->stream_output
.num_outputs
> 0) {
266 so
->constbase
.tfbo
= constoff
;
267 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
270 so
->constbase
.immediate
= constoff
;
276 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
279 va_start(ap
, format
);
280 _debug_vprintf(format
, ap
);
282 nir_print_shader(ctx
->s
, stdout
);
287 #define compile_assert(ctx, cond) do { \
288 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
292 compile_free(struct ir3_context
*ctx
)
298 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
300 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
301 arr
->id
= ++ctx
->num_arrays
;
302 /* NOTE: sometimes we get non array regs, for example for arrays of
303 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
304 * treat a non-array as if it was an array of length 1.
306 * It would be nice if there was a nir pass to convert arrays of
309 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
310 compile_assert(ctx
, arr
->length
> 0);
312 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
315 static struct ir3_array
*
316 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
318 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
322 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
326 /* relative (indirect) if address!=NULL */
327 static struct ir3_instruction
*
328 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
329 struct ir3_instruction
*address
)
331 struct ir3_block
*block
= ctx
->block
;
332 struct ir3_instruction
*mov
;
333 struct ir3_register
*src
;
335 mov
= ir3_instr_create(block
, OPC_MOV
);
336 mov
->cat1
.src_type
= TYPE_U32
;
337 mov
->cat1
.dst_type
= TYPE_U32
;
338 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
339 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
340 ir3_reg_create(mov
, 0, 0);
341 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
342 COND(address
, IR3_REG_RELATIV
));
343 src
->instr
= arr
->last_write
;
344 src
->size
= arr
->length
;
345 src
->array
.id
= arr
->id
;
346 src
->array
.offset
= n
;
349 ir3_instr_set_address(mov
, address
);
354 /* relative (indirect) if address!=NULL */
356 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
357 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
359 struct ir3_block
*block
= ctx
->block
;
360 struct ir3_instruction
*mov
;
361 struct ir3_register
*dst
;
363 /* if not relative store, don't create an extra mov, since that
364 * ends up being difficult for cp to remove.
369 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
370 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
372 dst
->flags
|= IR3_REG_ARRAY
;
373 dst
->instr
= arr
->last_write
;
374 dst
->size
= arr
->length
;
375 dst
->array
.id
= arr
->id
;
376 dst
->array
.offset
= n
;
378 arr
->last_write
= src
;
380 array_insert(block
, block
->keeps
, src
);
385 mov
= ir3_instr_create(block
, OPC_MOV
);
386 mov
->cat1
.src_type
= TYPE_U32
;
387 mov
->cat1
.dst_type
= TYPE_U32
;
388 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
389 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
390 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
391 COND(address
, IR3_REG_RELATIV
));
392 dst
->instr
= arr
->last_write
;
393 dst
->size
= arr
->length
;
394 dst
->array
.id
= arr
->id
;
395 dst
->array
.offset
= n
;
396 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
399 ir3_instr_set_address(mov
, address
);
401 arr
->last_write
= mov
;
403 /* the array store may only matter to something in an earlier
404 * block (ie. loops), but since arrays are not in SSA, depth
405 * pass won't know this.. so keep all array stores:
407 array_insert(block
, block
->keeps
, mov
);
410 static inline type_t
utype_for_size(unsigned bit_size
)
413 case 32: return TYPE_U32
;
414 case 16: return TYPE_U16
;
415 case 8: return TYPE_U8
;
416 default: unreachable("bad bitsize"); return ~0;
420 static inline type_t
utype_src(nir_src src
)
421 { return utype_for_size(nir_src_bit_size(src
)); }
423 static inline type_t
utype_dst(nir_dest dst
)
424 { return utype_for_size(nir_dest_bit_size(dst
)); }
426 /* allocate a n element value array (to be populated by caller) and
429 static struct ir3_instruction
**
430 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
432 struct ir3_instruction
**value
=
433 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
434 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
438 static struct ir3_instruction
**
439 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
441 struct ir3_instruction
**value
;
444 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
446 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
449 /* NOTE: in non-ssa case, we don't really need to store last_dst
450 * but this helps us catch cases where put_dst() call is forgotten
452 compile_assert(ctx
, !ctx
->last_dst
);
453 ctx
->last_dst
= value
;
459 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
461 static struct ir3_instruction
* const *
462 get_src(struct ir3_context
*ctx
, nir_src
*src
)
465 struct hash_entry
*entry
;
466 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
467 compile_assert(ctx
, entry
);
470 nir_register
*reg
= src
->reg
.reg
;
471 struct ir3_array
*arr
= get_array(ctx
, reg
);
472 unsigned num_components
= arr
->r
->num_components
;
473 struct ir3_instruction
*addr
= NULL
;
474 struct ir3_instruction
**value
=
475 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
477 if (src
->reg
.indirect
)
478 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
479 reg
->num_components
);
481 for (unsigned i
= 0; i
< num_components
; i
++) {
482 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
483 compile_assert(ctx
, n
< arr
->length
);
484 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
492 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
494 unsigned bit_size
= nir_dest_bit_size(*dst
);
497 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
498 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
499 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
500 if (ctx
->last_dst
[i
]->opc
== OPC_META_FO
)
501 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
506 nir_register
*reg
= dst
->reg
.reg
;
507 struct ir3_array
*arr
= get_array(ctx
, reg
);
508 unsigned num_components
= ctx
->last_dst_n
;
509 struct ir3_instruction
*addr
= NULL
;
511 if (dst
->reg
.indirect
)
512 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
513 reg
->num_components
);
515 for (unsigned i
= 0; i
< num_components
; i
++) {
516 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
517 compile_assert(ctx
, n
< arr
->length
);
518 if (!ctx
->last_dst
[i
])
520 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
523 ralloc_free(ctx
->last_dst
);
525 ctx
->last_dst
= NULL
;
529 static struct ir3_instruction
*
530 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
532 struct ir3_instruction
*mov
;
533 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
535 mov
= ir3_instr_create(block
, OPC_MOV
);
536 mov
->cat1
.src_type
= type
;
537 mov
->cat1
.dst_type
= type
;
538 ir3_reg_create(mov
, 0, flags
);
539 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
544 static struct ir3_instruction
*
545 create_immed(struct ir3_block
*block
, uint32_t val
)
547 return create_immed_typed(block
, val
, TYPE_U32
);
550 static struct ir3_instruction
*
551 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
553 struct ir3_instruction
*instr
, *immed
;
555 /* TODO in at least some cases, the backend could probably be
556 * made clever enough to propagate IR3_REG_HALF..
558 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
559 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
566 /* src *= 2 => src <<= 1: */
567 immed
= create_immed(block
, 1);
568 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
570 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
571 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
572 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
576 immed
= create_immed(block
, 3);
577 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
579 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
580 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
581 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
584 /* src *= 4 => src <<= 2: */
585 immed
= create_immed(block
, 2);
586 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
588 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
589 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
590 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
593 unreachable("bad align");
597 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
598 instr
->regs
[0]->num
= regid(REG_A0
, 0);
599 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
600 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
605 /* caches addr values to avoid generating multiple cov/shl/mova
606 * sequences for each use of a given NIR level src as address
608 static struct ir3_instruction
*
609 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
611 struct ir3_instruction
*addr
;
612 unsigned idx
= align
- 1;
614 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
616 if (!ctx
->addr_ht
[idx
]) {
617 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
618 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
620 struct hash_entry
*entry
;
621 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
626 addr
= create_addr(ctx
->block
, src
, align
);
627 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
632 static struct ir3_instruction
*
633 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
635 struct ir3_block
*b
= ctx
->block
;
636 struct ir3_instruction
*cond
;
638 /* NOTE: only cmps.*.* can write p0.x: */
639 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
640 cond
->cat2
.condition
= IR3_COND_NE
;
642 /* condition always goes in predicate register: */
643 cond
->regs
[0]->num
= regid(REG_P0
, 0);
648 static struct ir3_instruction
*
649 create_uniform(struct ir3_context
*ctx
, unsigned n
)
651 struct ir3_instruction
*mov
;
653 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
654 /* TODO get types right? */
655 mov
->cat1
.src_type
= TYPE_F32
;
656 mov
->cat1
.dst_type
= TYPE_F32
;
657 ir3_reg_create(mov
, 0, 0);
658 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
663 static struct ir3_instruction
*
664 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
665 struct ir3_instruction
*address
)
667 struct ir3_instruction
*mov
;
669 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
670 mov
->cat1
.src_type
= TYPE_U32
;
671 mov
->cat1
.dst_type
= TYPE_U32
;
672 ir3_reg_create(mov
, 0, 0);
673 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
675 ir3_instr_set_address(mov
, address
);
680 static struct ir3_instruction
*
681 create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
684 struct ir3_block
*block
= ctx
->block
;
685 struct ir3_instruction
*collect
;
690 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
692 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
693 ir3_reg_create(collect
, 0, flags
); /* dst */
694 for (unsigned i
= 0; i
< arrsz
; i
++) {
695 struct ir3_instruction
*elem
= arr
[i
];
697 /* Since arrays are pre-colored in RA, we can't assume that
698 * things will end up in the right place. (Ie. if a collect
699 * joins elements from two different arrays.) So insert an
702 * We could possibly skip this if all the collected elements
703 * are contiguous elements in a single array.. not sure how
704 * likely that is to happen.
706 * Fixes a problem with glamor shaders, that in effect do
713 * color = texture2D(tex, texcoord);
715 * In this case, texcoord will end up as nir registers (which
716 * translate to ir3 array's of length 1. And we can't assume
717 * the two (or more) arrays will get allocated in consecutive
721 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
722 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
723 elem
= ir3_MOV(block
, elem
, type
);
726 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
727 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
733 static struct ir3_instruction
*
734 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
735 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
737 struct ir3_block
*block
= ctx
->block
;
738 struct ir3_instruction
*mov
;
739 struct ir3_register
*src
;
741 mov
= ir3_instr_create(block
, OPC_MOV
);
742 mov
->cat1
.src_type
= TYPE_U32
;
743 mov
->cat1
.dst_type
= TYPE_U32
;
744 ir3_reg_create(mov
, 0, 0);
745 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
746 src
->instr
= collect
;
748 src
->array
.offset
= n
;
750 ir3_instr_set_address(mov
, address
);
755 static struct ir3_instruction
*
756 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
758 struct ir3_instruction
*in
;
760 in
= ir3_instr_create(block
, OPC_META_INPUT
);
761 in
->inout
.block
= block
;
762 ir3_reg_create(in
, n
, 0);
764 in
->regs
[0]->wrmask
= compmask
;
769 static struct ir3_instruction
*
770 create_input(struct ir3_block
*block
, unsigned n
)
772 return create_input_compmask(block
, n
, 0x1);
775 static struct ir3_instruction
*
776 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
778 struct ir3_block
*block
= ctx
->block
;
779 struct ir3_instruction
*instr
;
780 /* actual inloc is assigned and fixed up later: */
781 struct ir3_instruction
*inloc
= create_immed(block
, 0);
784 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
785 instr
->cat6
.type
= TYPE_U32
;
786 instr
->cat6
.iim_val
= 1;
788 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
789 instr
->regs
[2]->wrmask
= 0x3;
795 static struct ir3_instruction
*
796 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
798 struct ir3_block
*block
= ctx
->block
;
799 struct ir3_instruction
*instr
;
801 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
803 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
808 /* for frag_coord, we get unsigned values.. we need
809 * to subtract (integer) 8 and divide by 16 (right-
810 * shift by 4) then convert to float:
814 * mov.u32f32 dst, tmp
817 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
818 create_immed(block
, 8), 0);
819 instr
= ir3_SHR_B(block
, instr
, 0,
820 create_immed(block
, 4), 0);
821 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
827 /* seems that we can use these as-is: */
828 return ctx
->frag_coord
[comp
];
832 static struct ir3_instruction
*
833 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
835 /* first four vec4 sysval's reserved for UBOs: */
836 /* NOTE: dp is in scalar, but there can be >4 dp components: */
837 unsigned n
= ctx
->so
->constbase
.driver_param
;
838 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
839 return create_uniform(ctx
, r
);
842 /* helper for instructions that produce multiple consecutive scalar
843 * outputs which need to have a split/fanout meta instruction inserted
846 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
847 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
849 struct ir3_instruction
*prev
= NULL
;
851 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
856 for (int i
= 0, j
= 0; i
< n
; i
++) {
857 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
858 ir3_reg_create(split
, 0, IR3_REG_SSA
);
859 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
860 split
->fo
.off
= i
+ base
;
863 split
->cp
.left
= prev
;
864 split
->cp
.left_cnt
++;
865 prev
->cp
.right
= split
;
866 prev
->cp
.right_cnt
++;
870 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
876 * Adreno uses uint rather than having dedicated bool type,
877 * which (potentially) requires some conversion, in particular
878 * when using output of an bool instr to int input, or visa
882 * -------+---------+-------+-
886 * To convert from an adreno bool (uint) to nir, use:
888 * absneg.s dst, (neg)src
890 * To convert back in the other direction:
892 * absneg.s dst, (abs)arc
894 * The CP step can clean up the absneg.s that cancel each other
895 * out, and with a slight bit of extra cleverness (to recognize
896 * the instructions which produce either a 0 or 1) can eliminate
897 * the absneg.s's completely when an instruction that wants
898 * 0/1 consumes the result. For example, when a nir 'bcsel'
899 * consumes the result of 'feq'. So we should be able to get by
900 * without a boolean resolve step, and without incuring any
901 * extra penalty in instruction count.
904 /* NIR bool -> native (adreno): */
905 static struct ir3_instruction
*
906 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
908 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
911 /* native (adreno) -> NIR bool: */
912 static struct ir3_instruction
*
913 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
915 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
919 * alu/sfu instructions:
922 static struct ir3_instruction
*
923 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
924 unsigned src_bitsize
, nir_op op
)
926 type_t src_type
, dst_type
;
930 case nir_op_f2f16_rtne
:
931 case nir_op_f2f16_rtz
:
932 case nir_op_f2f16_undef
:
939 switch (src_bitsize
) {
947 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
956 switch (src_bitsize
) {
967 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
976 switch (src_bitsize
) {
987 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
992 compile_error(ctx
, "invalid conversion op: %u", op
);
1002 case nir_op_f2f16_rtne
:
1003 case nir_op_f2f16_rtz
:
1004 case nir_op_f2f16_undef
:
1005 /* TODO how to handle rounding mode? */
1008 dst_type
= TYPE_F16
;
1013 dst_type
= TYPE_S32
;
1018 dst_type
= TYPE_S16
;
1028 dst_type
= TYPE_U32
;
1033 dst_type
= TYPE_U16
;
1042 compile_error(ctx
, "invalid conversion op: %u", op
);
1045 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
1049 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
1051 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1052 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
1053 unsigned bs
[info
->num_inputs
]; /* bit size */
1054 struct ir3_block
*b
= ctx
->block
;
1055 unsigned dst_sz
, wrmask
;
1057 if (alu
->dest
.dest
.is_ssa
) {
1058 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
1059 wrmask
= (1 << dst_sz
) - 1;
1061 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
1062 wrmask
= alu
->dest
.write_mask
;
1065 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
1067 /* Vectors are special in that they have non-scalarized writemasks,
1068 * and just take the first swizzle channel for each argument in
1069 * order into each writemask channel.
1071 if ((alu
->op
== nir_op_vec2
) ||
1072 (alu
->op
== nir_op_vec3
) ||
1073 (alu
->op
== nir_op_vec4
)) {
1075 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1076 nir_alu_src
*asrc
= &alu
->src
[i
];
1078 compile_assert(ctx
, !asrc
->abs
);
1079 compile_assert(ctx
, !asrc
->negate
);
1081 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
1083 src
[i
] = create_immed(ctx
->block
, 0);
1084 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
1087 put_dst(ctx
, &alu
->dest
.dest
);
1091 /* We also get mov's with more than one component for mov's so
1092 * handle those specially:
1094 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
1095 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
1096 nir_alu_src
*asrc
= &alu
->src
[0];
1097 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
1099 for (unsigned i
= 0; i
< dst_sz
; i
++) {
1100 if (wrmask
& (1 << i
)) {
1101 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
1107 put_dst(ctx
, &alu
->dest
.dest
);
1111 /* General case: We can just grab the one used channel per src. */
1112 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1113 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
1114 nir_alu_src
*asrc
= &alu
->src
[i
];
1116 compile_assert(ctx
, !asrc
->abs
);
1117 compile_assert(ctx
, !asrc
->negate
);
1119 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
1120 bs
[i
] = nir_src_bit_size(asrc
->src
);
1122 compile_assert(ctx
, src
[i
]);
1127 case nir_op_f2f16_rtne
:
1128 case nir_op_f2f16_rtz
:
1129 case nir_op_f2f16_undef
:
1146 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
1149 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
1150 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1151 dst
[0] = ir3_n2b(b
, dst
[0]);
1154 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
1157 dst
[0] = ir3_b2n(b
, src
[0]);
1160 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1161 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1162 dst
[0] = ir3_n2b(b
, dst
[0]);
1166 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1169 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1172 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1175 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1178 /* if there is just a single use of the src, and it supports
1179 * (sat) bit, we can just fold the (sat) flag back to the
1180 * src instruction and create a mov. This is easier for cp
1183 * TODO probably opc_cat==4 is ok too
1185 if (alu
->src
[0].src
.is_ssa
&&
1186 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
1187 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
1188 src
[0]->flags
|= IR3_INSTR_SAT
;
1189 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
1191 /* otherwise generate a max.f that saturates.. blob does
1192 * similar (generating a cat2 mov using max.f)
1194 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
1195 dst
[0]->flags
|= IR3_INSTR_SAT
;
1199 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1202 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1205 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1208 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1211 dst
[0] = ir3_DSX(b
, src
[0], 0);
1212 dst
[0]->cat5
.type
= TYPE_F32
;
1215 dst
[0] = ir3_DSY(b
, src
[0], 0);
1216 dst
[0]->cat5
.type
= TYPE_F32
;
1220 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1221 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1222 dst
[0] = ir3_n2b(b
, dst
[0]);
1225 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1226 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1227 dst
[0] = ir3_n2b(b
, dst
[0]);
1230 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1231 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1232 dst
[0] = ir3_n2b(b
, dst
[0]);
1235 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1236 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1237 dst
[0] = ir3_n2b(b
, dst
[0]);
1240 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1243 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1246 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1248 case nir_op_fround_even
:
1249 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1252 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1256 dst
[0] = ir3_SIN(b
, src
[0], 0);
1259 dst
[0] = ir3_COS(b
, src
[0], 0);
1262 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1265 dst
[0] = ir3_RCP(b
, src
[0], 0);
1268 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1271 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1274 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1278 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1281 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1284 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1287 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1290 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1293 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1296 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1300 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1301 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1302 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1303 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1305 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1306 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1307 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1310 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1313 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1316 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1319 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1322 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1324 case nir_op_isign
: {
1325 /* maybe this would be sane to lower in nir.. */
1326 struct ir3_instruction
*neg
, *pos
;
1328 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1329 neg
->cat2
.condition
= IR3_COND_LT
;
1331 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1332 pos
->cat2
.condition
= IR3_COND_GT
;
1334 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1339 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1342 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1345 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1348 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1349 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1350 dst
[0] = ir3_n2b(b
, dst
[0]);
1353 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1354 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1355 dst
[0] = ir3_n2b(b
, dst
[0]);
1358 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1359 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1360 dst
[0] = ir3_n2b(b
, dst
[0]);
1363 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1364 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1365 dst
[0] = ir3_n2b(b
, dst
[0]);
1368 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1369 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1370 dst
[0] = ir3_n2b(b
, dst
[0]);
1373 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1374 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1375 dst
[0] = ir3_n2b(b
, dst
[0]);
1378 case nir_op_bcsel
: {
1379 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
1380 compile_assert(ctx
, bs
[1] == bs
[2]);
1381 /* the boolean condition is 32b even if src[1] and src[2] are
1382 * half-precision, but sel.b16 wants all three src's to be the
1386 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
1387 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
1390 case nir_op_bit_count
:
1391 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1393 case nir_op_ifind_msb
: {
1394 struct ir3_instruction
*cmp
;
1395 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1396 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1397 cmp
->cat2
.condition
= IR3_COND_GE
;
1398 dst
[0] = ir3_SEL_B32(b
,
1399 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1403 case nir_op_ufind_msb
:
1404 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1405 dst
[0] = ir3_SEL_B32(b
,
1406 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1407 src
[0], 0, dst
[0], 0);
1409 case nir_op_find_lsb
:
1410 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1411 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1413 case nir_op_bitfield_reverse
:
1414 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1418 compile_error(ctx
, "Unhandled ALU op: %s\n",
1419 nir_op_infos
[alu
->op
].name
);
1423 put_dst(ctx
, &alu
->dest
.dest
);
1426 /* handles direct/indirect UBO reads: */
1428 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1429 struct ir3_instruction
**dst
)
1431 struct ir3_block
*b
= ctx
->block
;
1432 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1433 nir_const_value
*const_offset
;
1434 /* UBO addresses are the first driver params: */
1435 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1436 const unsigned ptrsz
= pointer_size(ctx
);
1440 /* First src is ubo index, which could either be an immed or not: */
1441 src0
= get_src(ctx
, &intr
->src
[0])[0];
1442 if (is_same_type_mov(src0
) &&
1443 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1444 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1445 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1447 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1448 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1451 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1454 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1456 off
+= const_offset
->u32
[0];
1458 /* For load_ubo_indirect, second src is indirect offset: */
1459 src1
= get_src(ctx
, &intr
->src
[1])[0];
1461 /* and add offset to addr: */
1462 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1465 /* if offset is to large to encode in the ldg, split it out: */
1466 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1467 /* split out the minimal amount to improve the odds that
1468 * cp can fit the immediate in the add.s instruction:
1470 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1471 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1476 struct ir3_instruction
*carry
;
1478 /* handle 32b rollover, ie:
1479 * if (addr < base_lo)
1482 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1483 carry
->cat2
.condition
= IR3_COND_LT
;
1484 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1486 addr
= create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1489 for (int i
= 0; i
< intr
->num_components
; i
++) {
1490 struct ir3_instruction
*load
=
1491 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1492 load
->cat6
.type
= TYPE_U32
;
1493 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1498 /* src[] = { buffer_index, offset }. No const_index */
1500 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1501 struct ir3_instruction
**dst
)
1503 struct ir3_block
*b
= ctx
->block
;
1504 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1505 nir_const_value
*const_offset
;
1507 /* can this be non-const buffer_index? how do we handle that? */
1508 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1509 compile_assert(ctx
, const_offset
);
1511 offset
= get_src(ctx
, &intr
->src
[1])[0];
1513 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1514 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1518 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1520 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1522 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1523 ldgb
->cat6
.iim_val
= intr
->num_components
;
1525 ldgb
->cat6
.type
= TYPE_U32
;
1526 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1527 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1529 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1532 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1534 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1536 struct ir3_block
*b
= ctx
->block
;
1537 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1538 nir_const_value
*const_offset
;
1539 /* TODO handle wrmask properly, see _store_shared().. but I think
1540 * it is more a PITA than that, since blob ends up loading the
1541 * masked components and writing them back out.
1543 unsigned wrmask
= intr
->const_index
[0];
1544 unsigned ncomp
= ffs(~wrmask
) - 1;
1546 /* can this be non-const buffer_index? how do we handle that? */
1547 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1548 compile_assert(ctx
, const_offset
);
1550 offset
= get_src(ctx
, &intr
->src
[2])[0];
1552 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1555 src0
= create_collect(ctx
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1556 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1557 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1562 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1563 src0
, 0, src1
, 0, src2
, 0);
1564 stgb
->cat6
.iim_val
= ncomp
;
1566 stgb
->cat6
.type
= TYPE_U32
;
1567 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1568 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1570 array_insert(b
, b
->keeps
, stgb
);
1573 /* src[] = { block_index } */
1575 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1576 struct ir3_instruction
**dst
)
1578 /* SSBO size stored as a const starting at ssbo_sizes: */
1579 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1580 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1581 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1583 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1585 dst
[0] = create_uniform(ctx
, idx
);
1589 * SSBO atomic intrinsics
1591 * All of the SSBO atomic memory operations read a value from memory,
1592 * compute a new value using one of the operations below, write the new
1593 * value to memory, and return the original value read.
1595 * All operations take 3 sources except CompSwap that takes 4. These
1596 * sources represent:
1598 * 0: The SSBO buffer index.
1599 * 1: The offset into the SSBO buffer of the variable that the atomic
1600 * operation will operate on.
1601 * 2: The data parameter to the atomic function (i.e. the value to add
1602 * in ssbo_atomic_add, etc).
1603 * 3: For CompSwap only: the second data parameter.
1605 static struct ir3_instruction
*
1606 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1608 struct ir3_block
*b
= ctx
->block
;
1609 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1610 nir_const_value
*const_offset
;
1611 type_t type
= TYPE_U32
;
1613 /* can this be non-const buffer_index? how do we handle that? */
1614 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1615 compile_assert(ctx
, const_offset
);
1616 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1618 offset
= get_src(ctx
, &intr
->src
[1])[0];
1620 /* src0 is data (or uvec2(data, compare))
1622 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1624 * Note that nir already multiplies the offset by four
1626 src0
= get_src(ctx
, &intr
->src
[2])[0];
1627 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1628 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1633 switch (intr
->intrinsic
) {
1634 case nir_intrinsic_ssbo_atomic_add
:
1635 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1637 case nir_intrinsic_ssbo_atomic_imin
:
1638 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1641 case nir_intrinsic_ssbo_atomic_umin
:
1642 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1644 case nir_intrinsic_ssbo_atomic_imax
:
1645 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1648 case nir_intrinsic_ssbo_atomic_umax
:
1649 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1651 case nir_intrinsic_ssbo_atomic_and
:
1652 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1654 case nir_intrinsic_ssbo_atomic_or
:
1655 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1657 case nir_intrinsic_ssbo_atomic_xor
:
1658 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1660 case nir_intrinsic_ssbo_atomic_exchange
:
1661 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1663 case nir_intrinsic_ssbo_atomic_comp_swap
:
1664 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1665 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1667 get_src(ctx
, &intr
->src
[3])[0],
1669 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1675 atomic
->cat6
.iim_val
= 1;
1677 atomic
->cat6
.type
= type
;
1678 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1679 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1681 /* even if nothing consume the result, we can't DCE the instruction: */
1682 array_insert(b
, b
->keeps
, atomic
);
1687 /* src[] = { offset }. const_index[] = { base } */
1689 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1690 struct ir3_instruction
**dst
)
1692 struct ir3_block
*b
= ctx
->block
;
1693 struct ir3_instruction
*ldl
, *offset
;
1696 offset
= get_src(ctx
, &intr
->src
[0])[0];
1697 base
= nir_intrinsic_base(intr
);
1699 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1700 ldl
->cat6
.src_offset
= base
;
1701 ldl
->cat6
.type
= utype_dst(intr
->dest
);
1702 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1704 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1705 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1707 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1710 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1712 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1714 struct ir3_block
*b
= ctx
->block
;
1715 struct ir3_instruction
*stl
, *offset
;
1716 struct ir3_instruction
* const *value
;
1717 unsigned base
, wrmask
;
1719 value
= get_src(ctx
, &intr
->src
[0]);
1720 offset
= get_src(ctx
, &intr
->src
[1])[0];
1722 base
= nir_intrinsic_base(intr
);
1723 wrmask
= nir_intrinsic_write_mask(intr
);
1725 /* Combine groups of consecutive enabled channels in one write
1726 * message. We use ffs to find the first enabled channel and then ffs on
1727 * the bit-inverse, down-shifted writemask to determine the length of
1728 * the block of enabled bits.
1730 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1733 unsigned first_component
= ffs(wrmask
) - 1;
1734 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1736 stl
= ir3_STL(b
, offset
, 0,
1737 create_collect(ctx
, &value
[first_component
], length
), 0,
1738 create_immed(b
, length
), 0);
1739 stl
->cat6
.dst_offset
= first_component
+ base
;
1740 stl
->cat6
.type
= utype_src(intr
->src
[0]);
1741 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1742 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1744 array_insert(b
, b
->keeps
, stl
);
1746 /* Clear the bits in the writemask that we just wrote, then try
1747 * again to see if more channels are left.
1749 wrmask
&= (15 << (first_component
+ length
));
1754 * CS shared variable atomic intrinsics
1756 * All of the shared variable atomic memory operations read a value from
1757 * memory, compute a new value using one of the operations below, write the
1758 * new value to memory, and return the original value read.
1760 * All operations take 2 sources except CompSwap that takes 3. These
1761 * sources represent:
1763 * 0: The offset into the shared variable storage region that the atomic
1764 * operation will operate on.
1765 * 1: The data parameter to the atomic function (i.e. the value to add
1766 * in shared_atomic_add, etc).
1767 * 2: For CompSwap only: the second data parameter.
1769 static struct ir3_instruction
*
1770 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1772 struct ir3_block
*b
= ctx
->block
;
1773 struct ir3_instruction
*atomic
, *src0
, *src1
;
1774 type_t type
= TYPE_U32
;
1776 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1777 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1779 switch (intr
->intrinsic
) {
1780 case nir_intrinsic_shared_atomic_add
:
1781 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1783 case nir_intrinsic_shared_atomic_imin
:
1784 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1787 case nir_intrinsic_shared_atomic_umin
:
1788 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1790 case nir_intrinsic_shared_atomic_imax
:
1791 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1794 case nir_intrinsic_shared_atomic_umax
:
1795 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1797 case nir_intrinsic_shared_atomic_and
:
1798 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1800 case nir_intrinsic_shared_atomic_or
:
1801 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1803 case nir_intrinsic_shared_atomic_xor
:
1804 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1806 case nir_intrinsic_shared_atomic_exchange
:
1807 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1809 case nir_intrinsic_shared_atomic_comp_swap
:
1810 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1811 src1
= create_collect(ctx
, (struct ir3_instruction
*[]){
1812 get_src(ctx
, &intr
->src
[2])[0],
1815 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1821 atomic
->cat6
.iim_val
= 1;
1823 atomic
->cat6
.type
= type
;
1824 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1825 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1827 /* even if nothing consume the result, we can't DCE the instruction: */
1828 array_insert(b
, b
->keeps
, atomic
);
1833 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1834 * state block (for load). To simplify things, invert the image id and
1835 * map it from end of state block, ie. image 0 becomes num-1, image 1
1836 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1837 * state when switching shaders.
1839 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1840 * coded. Also, since all the gl shader stages (ie. everything but CS)
1841 * share the same SSBO/image state block, this might require some more
1842 * logic if we supported images in anything other than FS..
1845 get_image_slot(struct ir3_context
*ctx
, const nir_deref_var
*deref
)
1847 const nir_variable
*var
= deref
->var
;
1848 unsigned int loc
= var
->data
.driver_location
;
1850 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
; tail
= tail
->child
) {
1851 compile_assert(ctx
, tail
->child
->deref_type
== nir_deref_type_array
);
1853 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1854 compile_assert(ctx
, deref_array
->deref_array_type
== nir_deref_array_type_direct
);
1856 const unsigned elem_sz
= glsl_count_attribute_slots(deref_array
->deref
.type
, false);
1857 const unsigned size
= glsl_get_length(tail
->type
);
1858 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1860 loc
+= base
* elem_sz
;
1863 /* TODO figure out real limit per generation, and don't hardcode: */
1864 const unsigned max_samplers
= 16;
1865 return max_samplers
- loc
- 1;
1868 /* see tex_info() for equiv logic for texture instructions.. it would be
1869 * nice if this could be better unified..
1872 get_image_coords(const nir_variable
*var
, unsigned *flagsp
)
1874 const struct glsl_type
*type
= glsl_without_array(var
->type
);
1875 unsigned coords
, flags
= 0;
1877 switch (glsl_get_sampler_dim(type
)) {
1878 case GLSL_SAMPLER_DIM_1D
:
1879 case GLSL_SAMPLER_DIM_BUF
:
1882 case GLSL_SAMPLER_DIM_2D
:
1883 case GLSL_SAMPLER_DIM_RECT
:
1884 case GLSL_SAMPLER_DIM_EXTERNAL
:
1885 case GLSL_SAMPLER_DIM_MS
:
1888 case GLSL_SAMPLER_DIM_3D
:
1889 case GLSL_SAMPLER_DIM_CUBE
:
1890 flags
|= IR3_INSTR_3D
;
1894 unreachable("bad sampler dim");
1898 if (glsl_sampler_type_is_array(type
)) {
1899 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1901 flags
|= IR3_INSTR_A
;
1911 get_image_type(const nir_variable
*var
)
1913 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1914 case GLSL_TYPE_UINT
:
1918 case GLSL_TYPE_FLOAT
:
1921 unreachable("bad sampler type.");
1926 static struct ir3_instruction
*
1927 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1928 struct ir3_instruction
* const *coords
, bool byteoff
)
1930 struct ir3_block
*b
= ctx
->block
;
1931 struct ir3_instruction
*offset
;
1932 unsigned ncoords
= get_image_coords(var
, NULL
);
1934 /* to calculate the byte offset (yes, uggg) we need (up to) three
1935 * const values to know the bytes per pixel, and y and z stride:
1937 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1938 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1940 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1941 (1 << var
->data
.driver_location
));
1943 /* offset = coords.x * bytes_per_pixel: */
1944 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1946 /* offset += coords.y * y_pitch: */
1947 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1948 coords
[1], 0, offset
, 0);
1951 /* offset += coords.z * z_pitch: */
1952 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1953 coords
[2], 0, offset
, 0);
1957 /* Some cases, like atomics, seem to use dword offset instead
1958 * of byte offsets.. blob just puts an extra shr.b in there
1961 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1964 return create_collect(ctx
, (struct ir3_instruction
*[]){
1970 /* src[] = { coord, sample_index }. const_index[] = {} */
1972 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1973 struct ir3_instruction
**dst
)
1975 struct ir3_block
*b
= ctx
->block
;
1976 const nir_variable
*var
= intr
->variables
[0]->var
;
1977 struct ir3_instruction
*sam
;
1978 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1979 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
1980 unsigned tex_idx
= get_image_slot(ctx
, intr
->variables
[0]);
1981 type_t type
= get_image_type(var
);
1983 /* hmm, this seems a bit odd, but it is what blob does and (at least
1984 * a5xx) just faults on bogus addresses otherwise:
1986 if (flags
& IR3_INSTR_3D
) {
1987 flags
&= ~IR3_INSTR_3D
;
1988 flags
|= IR3_INSTR_A
;
1991 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1992 tex_idx
, tex_idx
, create_collect(ctx
, coords
, ncoords
), NULL
);
1994 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1995 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1997 split_dest(b
, dst
, sam
, 0, 4);
2000 /* src[] = { coord, sample_index, value }. const_index[] = {} */
2002 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2004 struct ir3_block
*b
= ctx
->block
;
2005 const nir_variable
*var
= intr
->variables
[0]->var
;
2006 struct ir3_instruction
*stib
, *offset
;
2007 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
2008 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
2009 unsigned ncoords
= get_image_coords(var
, NULL
);
2010 unsigned tex_idx
= get_image_slot(ctx
, intr
->variables
[0]);
2014 * src2 is 64b byte offset
2017 offset
= get_image_offset(ctx
, var
, coords
, true);
2019 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
2020 * too and takes a dword offset.. not quite sure yet why blob uses
2021 * one over the other in various cases.
2024 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
2025 create_collect(ctx
, value
, 4), 0,
2026 create_collect(ctx
, coords
, ncoords
), 0,
2028 stib
->cat6
.iim_val
= 4;
2029 stib
->cat6
.d
= ncoords
;
2030 stib
->cat6
.type
= get_image_type(var
);
2031 stib
->cat6
.typed
= true;
2032 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2033 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2035 array_insert(b
, b
->keeps
, stib
);
2039 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
2040 struct ir3_instruction
**dst
)
2042 struct ir3_block
*b
= ctx
->block
;
2043 const nir_variable
*var
= intr
->variables
[0]->var
;
2044 unsigned tex_idx
= get_image_slot(ctx
, intr
->variables
[0]);
2045 struct ir3_instruction
*sam
, *lod
;
2046 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
2048 lod
= create_immed(b
, 0);
2049 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2050 tex_idx
, tex_idx
, lod
, NULL
);
2052 /* Array size actually ends up in .w rather than .z. This doesn't
2053 * matter for miplevel 0, but for higher mips the value in z is
2054 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2055 * returned, which means that we have to add 1 to it for arrays for
2058 * Note use a temporary dst and then copy, since the size of the dst
2059 * array that is passed in is based on nir's understanding of the
2060 * result size, not the hardware's
2062 struct ir3_instruction
*tmp
[4];
2064 split_dest(b
, tmp
, sam
, 0, 4);
2066 for (unsigned i
= 0; i
< ncoords
; i
++)
2069 if (flags
& IR3_INSTR_A
) {
2070 if (ctx
->levels_add_one
) {
2071 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
2073 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
2078 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
2079 static struct ir3_instruction
*
2080 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2082 struct ir3_block
*b
= ctx
->block
;
2083 const nir_variable
*var
= intr
->variables
[0]->var
;
2084 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
2085 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
2086 unsigned ncoords
= get_image_coords(var
, NULL
);
2088 image
= create_immed(b
, get_image_slot(ctx
, intr
->variables
[0]));
2090 /* src0 is value (or uvec2(value, compare))
2092 * src2 is 64b byte offset
2094 src0
= get_src(ctx
, &intr
->src
[2])[0];
2095 src1
= create_collect(ctx
, coords
, ncoords
);
2096 src2
= get_image_offset(ctx
, var
, coords
, false);
2098 switch (intr
->intrinsic
) {
2099 case nir_intrinsic_image_var_atomic_add
:
2100 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2102 case nir_intrinsic_image_var_atomic_min
:
2103 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2105 case nir_intrinsic_image_var_atomic_max
:
2106 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2108 case nir_intrinsic_image_var_atomic_and
:
2109 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2111 case nir_intrinsic_image_var_atomic_or
:
2112 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2114 case nir_intrinsic_image_var_atomic_xor
:
2115 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2117 case nir_intrinsic_image_var_atomic_exchange
:
2118 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2120 case nir_intrinsic_image_var_atomic_comp_swap
:
2121 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
2122 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
2124 get_src(ctx
, &intr
->src
[3])[0],
2126 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2132 atomic
->cat6
.iim_val
= 1;
2133 atomic
->cat6
.d
= ncoords
;
2134 atomic
->cat6
.type
= get_image_type(var
);
2135 atomic
->cat6
.typed
= true;
2136 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2137 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2139 /* even if nothing consume the result, we can't DCE the instruction: */
2140 array_insert(b
, b
->keeps
, atomic
);
2146 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2148 struct ir3_block
*b
= ctx
->block
;
2149 struct ir3_instruction
*barrier
;
2151 switch (intr
->intrinsic
) {
2152 case nir_intrinsic_barrier
:
2153 barrier
= ir3_BAR(b
);
2154 barrier
->cat7
.g
= true;
2155 barrier
->cat7
.l
= true;
2156 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
2157 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2159 case nir_intrinsic_memory_barrier
:
2160 barrier
= ir3_FENCE(b
);
2161 barrier
->cat7
.g
= true;
2162 barrier
->cat7
.r
= true;
2163 barrier
->cat7
.w
= true;
2164 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
2165 IR3_BARRIER_BUFFER_W
;
2166 barrier
->barrier_conflict
=
2167 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2168 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2170 case nir_intrinsic_memory_barrier_atomic_counter
:
2171 case nir_intrinsic_memory_barrier_buffer
:
2172 barrier
= ir3_FENCE(b
);
2173 barrier
->cat7
.g
= true;
2174 barrier
->cat7
.r
= true;
2175 barrier
->cat7
.w
= true;
2176 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
2177 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
2178 IR3_BARRIER_BUFFER_W
;
2180 case nir_intrinsic_memory_barrier_image
:
2181 // TODO double check if this should have .g set
2182 barrier
= ir3_FENCE(b
);
2183 barrier
->cat7
.g
= true;
2184 barrier
->cat7
.r
= true;
2185 barrier
->cat7
.w
= true;
2186 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2187 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
2188 IR3_BARRIER_IMAGE_W
;
2190 case nir_intrinsic_memory_barrier_shared
:
2191 barrier
= ir3_FENCE(b
);
2192 barrier
->cat7
.g
= true;
2193 barrier
->cat7
.l
= true;
2194 barrier
->cat7
.r
= true;
2195 barrier
->cat7
.w
= true;
2196 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
2197 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
2198 IR3_BARRIER_SHARED_W
;
2200 case nir_intrinsic_group_memory_barrier
:
2201 barrier
= ir3_FENCE(b
);
2202 barrier
->cat7
.g
= true;
2203 barrier
->cat7
.l
= true;
2204 barrier
->cat7
.r
= true;
2205 barrier
->cat7
.w
= true;
2206 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
2207 IR3_BARRIER_IMAGE_W
|
2208 IR3_BARRIER_BUFFER_W
;
2209 barrier
->barrier_conflict
=
2210 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
2211 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2212 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2218 /* make sure barrier doesn't get DCE'd */
2219 array_insert(b
, b
->keeps
, barrier
);
2222 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
2223 gl_system_value slot
, unsigned compmask
,
2224 struct ir3_instruction
*instr
)
2226 struct ir3_shader_variant
*so
= ctx
->so
;
2227 unsigned r
= regid(so
->inputs_count
, 0);
2228 unsigned n
= so
->inputs_count
++;
2230 so
->inputs
[n
].sysval
= true;
2231 so
->inputs
[n
].slot
= slot
;
2232 so
->inputs
[n
].compmask
= compmask
;
2233 so
->inputs
[n
].regid
= r
;
2234 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
2237 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
2238 ctx
->ir
->inputs
[r
] = instr
;
2241 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
2242 struct ir3_instruction
*instr
)
2244 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
2248 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2250 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
2251 struct ir3_instruction
**dst
;
2252 struct ir3_instruction
* const *src
;
2253 struct ir3_block
*b
= ctx
->block
;
2254 nir_const_value
*const_offset
;
2257 if (info
->has_dest
) {
2258 unsigned n
= nir_intrinsic_dest_components(intr
);
2259 dst
= get_dst(ctx
, &intr
->dest
, n
);
2264 switch (intr
->intrinsic
) {
2265 case nir_intrinsic_load_uniform
:
2266 idx
= nir_intrinsic_base(intr
);
2267 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2269 idx
+= const_offset
->u32
[0];
2270 for (int i
= 0; i
< intr
->num_components
; i
++) {
2271 unsigned n
= idx
* 4 + i
;
2272 dst
[i
] = create_uniform(ctx
, n
);
2275 src
= get_src(ctx
, &intr
->src
[0]);
2276 for (int i
= 0; i
< intr
->num_components
; i
++) {
2277 int n
= idx
* 4 + i
;
2278 dst
[i
] = create_uniform_indirect(ctx
, n
,
2279 get_addr(ctx
, src
[0], 4));
2281 /* NOTE: if relative addressing is used, we set
2282 * constlen in the compiler (to worst-case value)
2283 * since we don't know in the assembler what the max
2284 * addr reg value can be:
2286 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2289 case nir_intrinsic_load_ubo
:
2290 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2292 case nir_intrinsic_load_input
:
2293 idx
= nir_intrinsic_base(intr
);
2294 comp
= nir_intrinsic_component(intr
);
2295 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2297 idx
+= const_offset
->u32
[0];
2298 for (int i
= 0; i
< intr
->num_components
; i
++) {
2299 unsigned n
= idx
* 4 + i
+ comp
;
2300 dst
[i
] = ctx
->ir
->inputs
[n
];
2303 src
= get_src(ctx
, &intr
->src
[0]);
2304 struct ir3_instruction
*collect
=
2305 create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2306 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2307 for (int i
= 0; i
< intr
->num_components
; i
++) {
2308 unsigned n
= idx
* 4 + i
+ comp
;
2309 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2314 case nir_intrinsic_load_ssbo
:
2315 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2317 case nir_intrinsic_store_ssbo
:
2318 emit_intrinsic_store_ssbo(ctx
, intr
);
2320 case nir_intrinsic_get_buffer_size
:
2321 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2323 case nir_intrinsic_ssbo_atomic_add
:
2324 case nir_intrinsic_ssbo_atomic_imin
:
2325 case nir_intrinsic_ssbo_atomic_umin
:
2326 case nir_intrinsic_ssbo_atomic_imax
:
2327 case nir_intrinsic_ssbo_atomic_umax
:
2328 case nir_intrinsic_ssbo_atomic_and
:
2329 case nir_intrinsic_ssbo_atomic_or
:
2330 case nir_intrinsic_ssbo_atomic_xor
:
2331 case nir_intrinsic_ssbo_atomic_exchange
:
2332 case nir_intrinsic_ssbo_atomic_comp_swap
:
2333 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2335 case nir_intrinsic_load_shared
:
2336 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2338 case nir_intrinsic_store_shared
:
2339 emit_intrinsic_store_shared(ctx
, intr
);
2341 case nir_intrinsic_shared_atomic_add
:
2342 case nir_intrinsic_shared_atomic_imin
:
2343 case nir_intrinsic_shared_atomic_umin
:
2344 case nir_intrinsic_shared_atomic_imax
:
2345 case nir_intrinsic_shared_atomic_umax
:
2346 case nir_intrinsic_shared_atomic_and
:
2347 case nir_intrinsic_shared_atomic_or
:
2348 case nir_intrinsic_shared_atomic_xor
:
2349 case nir_intrinsic_shared_atomic_exchange
:
2350 case nir_intrinsic_shared_atomic_comp_swap
:
2351 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2353 case nir_intrinsic_image_var_load
:
2354 emit_intrinsic_load_image(ctx
, intr
, dst
);
2356 case nir_intrinsic_image_var_store
:
2357 emit_intrinsic_store_image(ctx
, intr
);
2359 case nir_intrinsic_image_var_size
:
2360 emit_intrinsic_image_size(ctx
, intr
, dst
);
2362 case nir_intrinsic_image_var_atomic_add
:
2363 case nir_intrinsic_image_var_atomic_min
:
2364 case nir_intrinsic_image_var_atomic_max
:
2365 case nir_intrinsic_image_var_atomic_and
:
2366 case nir_intrinsic_image_var_atomic_or
:
2367 case nir_intrinsic_image_var_atomic_xor
:
2368 case nir_intrinsic_image_var_atomic_exchange
:
2369 case nir_intrinsic_image_var_atomic_comp_swap
:
2370 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2372 case nir_intrinsic_barrier
:
2373 case nir_intrinsic_memory_barrier
:
2374 case nir_intrinsic_group_memory_barrier
:
2375 case nir_intrinsic_memory_barrier_atomic_counter
:
2376 case nir_intrinsic_memory_barrier_buffer
:
2377 case nir_intrinsic_memory_barrier_image
:
2378 case nir_intrinsic_memory_barrier_shared
:
2379 emit_intrinsic_barrier(ctx
, intr
);
2380 /* note that blk ptr no longer valid, make that obvious: */
2383 case nir_intrinsic_store_output
:
2384 idx
= nir_intrinsic_base(intr
);
2385 comp
= nir_intrinsic_component(intr
);
2386 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2387 compile_assert(ctx
, const_offset
!= NULL
);
2388 idx
+= const_offset
->u32
[0];
2390 src
= get_src(ctx
, &intr
->src
[0]);
2391 for (int i
= 0; i
< intr
->num_components
; i
++) {
2392 unsigned n
= idx
* 4 + i
+ comp
;
2393 ctx
->ir
->outputs
[n
] = src
[i
];
2396 case nir_intrinsic_load_first_vertex
:
2397 if (!ctx
->basevertex
) {
2398 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2399 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
2401 dst
[0] = ctx
->basevertex
;
2403 case nir_intrinsic_load_vertex_id_zero_base
:
2404 case nir_intrinsic_load_vertex_id
:
2405 if (!ctx
->vertex_id
) {
2406 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2407 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2408 ctx
->vertex_id
= create_input(b
, 0);
2409 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2411 dst
[0] = ctx
->vertex_id
;
2413 case nir_intrinsic_load_instance_id
:
2414 if (!ctx
->instance_id
) {
2415 ctx
->instance_id
= create_input(b
, 0);
2416 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2419 dst
[0] = ctx
->instance_id
;
2421 case nir_intrinsic_load_sample_id
:
2422 if (!ctx
->samp_id
) {
2423 ctx
->samp_id
= create_input(b
, 0);
2424 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
2425 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
2428 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
2430 case nir_intrinsic_load_sample_mask_in
:
2431 if (!ctx
->samp_mask_in
) {
2432 ctx
->samp_mask_in
= create_input(b
, 0);
2433 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
2436 dst
[0] = ctx
->samp_mask_in
;
2438 case nir_intrinsic_load_user_clip_plane
:
2439 idx
= nir_intrinsic_ucp_id(intr
);
2440 for (int i
= 0; i
< intr
->num_components
; i
++) {
2441 unsigned n
= idx
* 4 + i
;
2442 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2445 case nir_intrinsic_load_front_face
:
2446 if (!ctx
->frag_face
) {
2447 ctx
->so
->frag_face
= true;
2448 ctx
->frag_face
= create_input(b
, 0);
2449 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2451 /* for fragface, we get -1 for back and 0 for front. However this is
2452 * the inverse of what nir expects (where ~0 is true).
2454 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2455 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2457 case nir_intrinsic_load_local_invocation_id
:
2458 if (!ctx
->local_invocation_id
) {
2459 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2460 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2461 0x7, ctx
->local_invocation_id
);
2463 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2465 case nir_intrinsic_load_work_group_id
:
2466 if (!ctx
->work_group_id
) {
2467 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2468 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2469 0x7, ctx
->work_group_id
);
2470 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2472 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2474 case nir_intrinsic_load_num_work_groups
:
2475 for (int i
= 0; i
< intr
->num_components
; i
++) {
2476 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2479 case nir_intrinsic_load_local_group_size
:
2480 for (int i
= 0; i
< intr
->num_components
; i
++) {
2481 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2484 case nir_intrinsic_discard_if
:
2485 case nir_intrinsic_discard
: {
2486 struct ir3_instruction
*cond
, *kill
;
2488 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2489 /* conditional discard: */
2490 src
= get_src(ctx
, &intr
->src
[0]);
2491 cond
= ir3_b2n(b
, src
[0]);
2493 /* unconditional discard: */
2494 cond
= create_immed(b
, 1);
2497 /* NOTE: only cmps.*.* can write p0.x: */
2498 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2499 cond
->cat2
.condition
= IR3_COND_NE
;
2501 /* condition always goes in predicate register: */
2502 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2504 kill
= ir3_KILL(b
, cond
, 0);
2505 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2507 array_insert(b
, b
->keeps
, kill
);
2508 ctx
->so
->has_kill
= true;
2513 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2514 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2519 put_dst(ctx
, &intr
->dest
);
2523 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2525 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2526 instr
->def
.num_components
);
2527 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2529 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2530 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
.u32
[i
], type
);
2534 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2536 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2537 undef
->def
.num_components
);
2538 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2540 /* backend doesn't want undefined instructions, so just plug
2543 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2544 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2548 * texture fetch/sample instructions:
2552 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2554 unsigned coords
, flags
= 0;
2556 /* note: would use tex->coord_components.. except txs.. also,
2557 * since array index goes after shadow ref, we don't want to
2560 switch (tex
->sampler_dim
) {
2561 case GLSL_SAMPLER_DIM_1D
:
2562 case GLSL_SAMPLER_DIM_BUF
:
2565 case GLSL_SAMPLER_DIM_2D
:
2566 case GLSL_SAMPLER_DIM_RECT
:
2567 case GLSL_SAMPLER_DIM_EXTERNAL
:
2568 case GLSL_SAMPLER_DIM_MS
:
2571 case GLSL_SAMPLER_DIM_3D
:
2572 case GLSL_SAMPLER_DIM_CUBE
:
2574 flags
|= IR3_INSTR_3D
;
2577 unreachable("bad sampler_dim");
2580 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2581 flags
|= IR3_INSTR_S
;
2583 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2584 flags
|= IR3_INSTR_A
;
2591 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2593 struct ir3_block
*b
= ctx
->block
;
2594 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2595 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2596 struct ir3_instruction
*lod
, *compare
, *proj
;
2597 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2598 unsigned i
, coords
, flags
;
2599 unsigned nsrc0
= 0, nsrc1
= 0;
2603 coord
= off
= ddx
= ddy
= NULL
;
2604 lod
= proj
= compare
= NULL
;
2606 /* TODO: might just be one component for gathers? */
2607 dst
= get_dst(ctx
, &tex
->dest
, 4);
2609 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2610 switch (tex
->src
[i
].src_type
) {
2611 case nir_tex_src_coord
:
2612 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2614 case nir_tex_src_bias
:
2615 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2618 case nir_tex_src_lod
:
2619 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2622 case nir_tex_src_comparator
: /* shadow comparator */
2623 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2625 case nir_tex_src_projector
:
2626 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2629 case nir_tex_src_offset
:
2630 off
= get_src(ctx
, &tex
->src
[i
].src
);
2633 case nir_tex_src_ddx
:
2634 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2636 case nir_tex_src_ddy
:
2637 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2640 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2641 tex
->src
[i
].src_type
);
2647 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2648 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2649 case nir_texop_txl
: opc
= OPC_SAML
; break;
2650 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2651 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2652 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2654 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2655 * what blob does, seems gather is broken?), and a3xx did
2656 * not support it (but probably could also emulate).
2658 switch (tex
->component
) {
2659 case 0: opc
= OPC_GATHER4R
; break;
2660 case 1: opc
= OPC_GATHER4G
; break;
2661 case 2: opc
= OPC_GATHER4B
; break;
2662 case 3: opc
= OPC_GATHER4A
; break;
2665 case nir_texop_txf_ms
:
2667 case nir_texop_query_levels
:
2668 case nir_texop_texture_samples
:
2669 case nir_texop_samples_identical
:
2670 case nir_texop_txf_ms_mcs
:
2671 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2675 tex_info(tex
, &flags
, &coords
);
2678 * lay out the first argument in the proper order:
2679 * - actual coordinates first
2680 * - shadow reference
2683 * - starting at offset 4, dpdx.xy, dpdy.xy
2685 * bias/lod go into the second arg
2688 /* insert tex coords: */
2689 for (i
= 0; i
< coords
; i
++)
2694 /* scale up integer coords for TXF based on the LOD */
2695 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2697 for (i
= 0; i
< coords
; i
++)
2698 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2702 /* hw doesn't do 1d, so we treat it as 2d with
2703 * height of 1, and patch up the y coord.
2704 * TODO: y coord should be (int)0 in some cases..
2706 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2709 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2710 src0
[nsrc0
++] = compare
;
2712 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2713 struct ir3_instruction
*idx
= coord
[coords
];
2715 /* the array coord for cube arrays needs 0.5 added to it */
2716 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2717 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2719 src0
[nsrc0
++] = idx
;
2723 src0
[nsrc0
++] = proj
;
2724 flags
|= IR3_INSTR_P
;
2727 /* pad to 4, then ddx/ddy: */
2728 if (tex
->op
== nir_texop_txd
) {
2730 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2731 for (i
= 0; i
< coords
; i
++)
2732 src0
[nsrc0
++] = ddx
[i
];
2734 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2735 for (i
= 0; i
< coords
; i
++)
2736 src0
[nsrc0
++] = ddy
[i
];
2738 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2742 * second argument (if applicable):
2747 if (has_off
| has_lod
| has_bias
) {
2749 unsigned off_coords
= coords
;
2750 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2752 for (i
= 0; i
< off_coords
; i
++)
2753 src1
[nsrc1
++] = off
[i
];
2755 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2756 flags
|= IR3_INSTR_O
;
2759 if (has_lod
| has_bias
)
2760 src1
[nsrc1
++] = lod
;
2763 switch (tex
->dest_type
) {
2764 case nir_type_invalid
:
2765 case nir_type_float
:
2776 unreachable("bad dest_type");
2779 if (opc
== OPC_GETLOD
)
2782 unsigned tex_idx
= tex
->texture_index
;
2784 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2786 struct ir3_instruction
*col0
= create_collect(ctx
, src0
, nsrc0
);
2787 struct ir3_instruction
*col1
= create_collect(ctx
, src1
, nsrc1
);
2789 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2790 tex_idx
, tex_idx
, col0
, col1
);
2792 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2793 /* only need first 3 components: */
2794 sam
->regs
[0]->wrmask
= 0x7;
2795 split_dest(b
, dst
, sam
, 0, 3);
2797 /* we need to sample the alpha separately with a non-ASTC
2800 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2801 tex_idx
, tex_idx
, col0
, col1
);
2803 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2805 /* fixup .w component: */
2806 split_dest(b
, &dst
[3], sam
, 3, 1);
2808 /* normal (non-workaround) case: */
2809 split_dest(b
, dst
, sam
, 0, 4);
2812 /* GETLOD returns results in 4.8 fixed point */
2813 if (opc
== OPC_GETLOD
) {
2814 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2816 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2817 for (i
= 0; i
< 2; i
++) {
2818 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2823 put_dst(ctx
, &tex
->dest
);
2827 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2829 struct ir3_block
*b
= ctx
->block
;
2830 struct ir3_instruction
**dst
, *sam
;
2832 dst
= get_dst(ctx
, &tex
->dest
, 1);
2834 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2835 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2837 /* even though there is only one component, since it ends
2838 * up in .z rather than .x, we need a split_dest()
2840 split_dest(b
, dst
, sam
, 0, 3);
2842 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2843 * the value in TEX_CONST_0 is zero-based.
2845 if (ctx
->levels_add_one
)
2846 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2848 put_dst(ctx
, &tex
->dest
);
2852 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2854 struct ir3_block
*b
= ctx
->block
;
2855 struct ir3_instruction
**dst
, *sam
;
2856 struct ir3_instruction
*lod
;
2857 unsigned flags
, coords
;
2859 tex_info(tex
, &flags
, &coords
);
2861 /* Actually we want the number of dimensions, not coordinates. This
2862 * distinction only matters for cubes.
2864 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2867 dst
= get_dst(ctx
, &tex
->dest
, 4);
2869 compile_assert(ctx
, tex
->num_srcs
== 1);
2870 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2872 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2874 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2875 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2877 split_dest(b
, dst
, sam
, 0, 4);
2879 /* Array size actually ends up in .w rather than .z. This doesn't
2880 * matter for miplevel 0, but for higher mips the value in z is
2881 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2882 * returned, which means that we have to add 1 to it for arrays.
2884 if (tex
->is_array
) {
2885 if (ctx
->levels_add_one
) {
2886 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2888 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2892 put_dst(ctx
, &tex
->dest
);
2896 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2898 switch (jump
->type
) {
2899 case nir_jump_break
:
2900 case nir_jump_continue
:
2901 case nir_jump_return
:
2902 /* I *think* we can simply just ignore this, and use the
2903 * successor block link to figure out where we need to
2904 * jump to for break/continue
2908 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2914 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2916 switch (instr
->type
) {
2917 case nir_instr_type_alu
:
2918 emit_alu(ctx
, nir_instr_as_alu(instr
));
2920 case nir_instr_type_intrinsic
:
2921 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2923 case nir_instr_type_load_const
:
2924 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2926 case nir_instr_type_ssa_undef
:
2927 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2929 case nir_instr_type_tex
: {
2930 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2931 /* couple tex instructions get special-cased:
2935 emit_tex_txs(ctx
, tex
);
2937 case nir_texop_query_levels
:
2938 emit_tex_query_levels(ctx
, tex
);
2946 case nir_instr_type_jump
:
2947 emit_jump(ctx
, nir_instr_as_jump(instr
));
2949 case nir_instr_type_phi
:
2950 /* we have converted phi webs to regs in NIR by now */
2951 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2953 case nir_instr_type_call
:
2954 case nir_instr_type_parallel_copy
:
2955 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2960 static struct ir3_block
*
2961 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2963 struct ir3_block
*block
;
2964 struct hash_entry
*hentry
;
2965 struct set_entry
*sentry
;
2968 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2970 return hentry
->data
;
2972 block
= ir3_block_create(ctx
->ir
);
2973 block
->nblock
= nblock
;
2974 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2976 block
->predecessors_count
= nblock
->predecessors
->entries
;
2977 block
->predecessors
= ralloc_array_size(block
,
2978 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
2980 set_foreach(nblock
->predecessors
, sentry
) {
2981 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
2988 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2990 struct ir3_block
*block
= get_block(ctx
, nblock
);
2992 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2993 if (nblock
->successors
[i
]) {
2994 block
->successors
[i
] =
2995 get_block(ctx
, nblock
->successors
[i
]);
3000 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
3002 /* re-emit addr register in each block if needed: */
3003 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
3004 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
3005 ctx
->addr_ht
[i
] = NULL
;
3008 nir_foreach_instr(instr
, nblock
) {
3009 emit_instr(ctx
, instr
);
3015 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
3018 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
3020 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
3022 ctx
->block
->condition
=
3023 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
3025 emit_cf_list(ctx
, &nif
->then_list
);
3026 emit_cf_list(ctx
, &nif
->else_list
);
3030 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
3032 emit_cf_list(ctx
, &nloop
->body
);
3036 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
3038 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3039 switch (node
->type
) {
3040 case nir_cf_node_block
:
3041 emit_block(ctx
, nir_cf_node_as_block(node
));
3043 case nir_cf_node_if
:
3044 emit_if(ctx
, nir_cf_node_as_if(node
));
3046 case nir_cf_node_loop
:
3047 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3049 case nir_cf_node_function
:
3050 compile_error(ctx
, "TODO\n");
3056 /* emit stream-out code. At this point, the current block is the original
3057 * (nir) end block, and nir ensures that all flow control paths terminate
3058 * into the end block. We re-purpose the original end block to generate
3059 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
3060 * block holding stream-out write instructions, followed by the new end
3064 * p0.x = (vtxcnt < maxvtxcnt)
3065 * // succs: blockStreamOut, blockNewEnd
3068 * ... stream-out instructions ...
3069 * // succs: blockNewEnd
3075 emit_stream_out(struct ir3_context
*ctx
)
3077 struct ir3_shader_variant
*v
= ctx
->so
;
3078 struct ir3
*ir
= ctx
->ir
;
3079 struct pipe_stream_output_info
*strmout
=
3080 &ctx
->so
->shader
->stream_output
;
3081 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
3082 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
3083 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
3085 /* create vtxcnt input in input block at top of shader,
3086 * so that it is seen as live over the entire duration
3089 vtxcnt
= create_input(ctx
->in_block
, 0);
3090 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
3092 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
3094 /* at this point, we are at the original 'end' block,
3095 * re-purpose this block to stream-out condition, then
3096 * append stream-out block and new-end block
3098 orig_end_block
= ctx
->block
;
3100 // TODO these blocks need to update predecessors..
3101 // maybe w/ store_global intrinsic, we could do this
3102 // stuff in nir->nir pass
3104 stream_out_block
= ir3_block_create(ir
);
3105 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
3107 new_end_block
= ir3_block_create(ir
);
3108 list_addtail(&new_end_block
->node
, &ir
->block_list
);
3110 orig_end_block
->successors
[0] = stream_out_block
;
3111 orig_end_block
->successors
[1] = new_end_block
;
3112 stream_out_block
->successors
[0] = new_end_block
;
3114 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
3115 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
3116 cond
->regs
[0]->num
= regid(REG_P0
, 0);
3117 cond
->cat2
.condition
= IR3_COND_LT
;
3119 /* condition goes on previous block to the conditional,
3120 * since it is used to pick which of the two successor
3123 orig_end_block
->condition
= cond
;
3125 /* switch to stream_out_block to generate the stream-out
3128 ctx
->block
= stream_out_block
;
3130 /* Calculate base addresses based on vtxcnt. Instructions
3131 * generated for bases not used in following loop will be
3132 * stripped out in the backend.
3134 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3135 unsigned stride
= strmout
->stride
[i
];
3136 struct ir3_instruction
*base
, *off
;
3138 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
3140 /* 24-bit should be enough: */
3141 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
3142 create_immed(ctx
->block
, stride
* 4), 0);
3144 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
3147 /* Generate the per-output store instructions: */
3148 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
3149 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
3150 unsigned c
= j
+ strmout
->output
[i
].start_component
;
3151 struct ir3_instruction
*base
, *out
, *stg
;
3153 base
= bases
[strmout
->output
[i
].output_buffer
];
3154 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
3156 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
3157 create_immed(ctx
->block
, 1), 0);
3158 stg
->cat6
.type
= TYPE_U32
;
3159 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
3161 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
3165 /* and finally switch to the new_end_block: */
3166 ctx
->block
= new_end_block
;
3170 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
3172 nir_metadata_require(impl
, nir_metadata_block_index
);
3174 emit_cf_list(ctx
, &impl
->body
);
3175 emit_block(ctx
, impl
->end_block
);
3177 /* at this point, we should have a single empty block,
3178 * into which we emit the 'end' instruction.
3180 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
3182 /* If stream-out (aka transform-feedback) enabled, emit the
3183 * stream-out instructions, followed by a new empty block (into
3184 * which the 'end' instruction lands).
3186 * NOTE: it is done in this order, rather than inserting before
3187 * we emit end_block, because NIR guarantees that all blocks
3188 * flow into end_block, and that end_block has no successors.
3189 * So by re-purposing end_block as the first block of stream-
3190 * out, we guarantee that all exit paths flow into the stream-
3193 if ((ctx
->compiler
->gpu_id
< 500) &&
3194 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
3195 !ctx
->so
->key
.binning_pass
) {
3196 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
3197 emit_stream_out(ctx
);
3200 ir3_END(ctx
->block
);
3204 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
3206 struct ir3_shader_variant
*so
= ctx
->so
;
3207 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
3208 unsigned ncomp
= glsl_get_components(in
->type
);
3209 unsigned n
= in
->data
.driver_location
;
3210 unsigned slot
= in
->data
.location
;
3212 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
3213 slot
, array_len
, ncomp
, n
);
3215 /* let's pretend things other than vec4 don't exist: */
3216 ncomp
= MAX2(ncomp
, 4);
3217 compile_assert(ctx
, ncomp
== 4);
3219 so
->inputs
[n
].slot
= slot
;
3220 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
3221 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
3222 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
3224 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3225 for (int i
= 0; i
< ncomp
; i
++) {
3226 struct ir3_instruction
*instr
= NULL
;
3227 unsigned idx
= (n
* 4) + i
;
3229 if (slot
== VARYING_SLOT_POS
) {
3230 so
->inputs
[n
].bary
= false;
3231 so
->frag_coord
= true;
3232 instr
= create_frag_coord(ctx
, i
);
3233 } else if (slot
== VARYING_SLOT_PNTC
) {
3234 /* see for example st_get_generic_varying_index().. this is
3235 * maybe a bit mesa/st specific. But we need things to line
3236 * up for this in fdN_program:
3237 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
3238 * if (emit->sprite_coord_enable & texmask) {
3242 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
3243 so
->inputs
[n
].bary
= true;
3244 instr
= create_frag_input(ctx
, false);
3246 bool use_ldlv
= false;
3248 /* detect the special case for front/back colors where
3249 * we need to do flat vs smooth shading depending on
3252 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3254 case VARYING_SLOT_COL0
:
3255 case VARYING_SLOT_COL1
:
3256 case VARYING_SLOT_BFC0
:
3257 case VARYING_SLOT_BFC1
:
3258 so
->inputs
[n
].rasterflat
= true;
3265 if (ctx
->flat_bypass
) {
3266 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3267 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3271 so
->inputs
[n
].bary
= true;
3273 instr
= create_frag_input(ctx
, use_ldlv
);
3276 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3278 ctx
->ir
->inputs
[idx
] = instr
;
3280 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3281 for (int i
= 0; i
< ncomp
; i
++) {
3282 unsigned idx
= (n
* 4) + i
;
3283 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3284 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
3287 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3290 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3291 so
->total_in
+= ncomp
;
3296 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3298 struct ir3_shader_variant
*so
= ctx
->so
;
3299 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3300 unsigned ncomp
= glsl_get_components(out
->type
);
3301 unsigned n
= out
->data
.driver_location
;
3302 unsigned slot
= out
->data
.location
;
3305 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3306 slot
, array_len
, ncomp
, n
);
3308 /* let's pretend things other than vec4 don't exist: */
3309 ncomp
= MAX2(ncomp
, 4);
3310 compile_assert(ctx
, ncomp
== 4);
3312 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3314 case FRAG_RESULT_DEPTH
:
3315 comp
= 2; /* tgsi will write to .z component */
3316 so
->writes_pos
= true;
3318 case FRAG_RESULT_COLOR
:
3322 if (slot
>= FRAG_RESULT_DATA0
)
3324 compile_error(ctx
, "unknown FS output name: %s\n",
3325 gl_frag_result_name(slot
));
3327 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3329 case VARYING_SLOT_POS
:
3330 so
->writes_pos
= true;
3332 case VARYING_SLOT_PSIZ
:
3333 so
->writes_psize
= true;
3335 case VARYING_SLOT_COL0
:
3336 case VARYING_SLOT_COL1
:
3337 case VARYING_SLOT_BFC0
:
3338 case VARYING_SLOT_BFC1
:
3339 case VARYING_SLOT_FOGC
:
3340 case VARYING_SLOT_CLIP_DIST0
:
3341 case VARYING_SLOT_CLIP_DIST1
:
3342 case VARYING_SLOT_CLIP_VERTEX
:
3345 if (slot
>= VARYING_SLOT_VAR0
)
3347 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3349 compile_error(ctx
, "unknown VS output name: %s\n",
3350 gl_varying_slot_name(slot
));
3353 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3356 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3358 so
->outputs
[n
].slot
= slot
;
3359 so
->outputs
[n
].regid
= regid(n
, comp
);
3360 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3362 for (int i
= 0; i
< ncomp
; i
++) {
3363 unsigned idx
= (n
* 4) + i
;
3364 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3365 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3370 max_drvloc(struct exec_list
*vars
)
3373 nir_foreach_variable(var
, vars
) {
3374 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3379 static const unsigned max_sysvals
[SHADER_MAX
] = {
3380 [SHADER_FRAGMENT
] = 8,
3381 [SHADER_VERTEX
] = 16,
3382 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3386 emit_instructions(struct ir3_context
*ctx
)
3388 unsigned ninputs
, noutputs
;
3389 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3391 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3392 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3394 /* we need to leave room for sysvals:
3396 ninputs
+= max_sysvals
[ctx
->so
->type
];
3398 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3400 /* Create inputs in first block: */
3401 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3402 ctx
->in_block
= ctx
->block
;
3403 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3405 ninputs
-= max_sysvals
[ctx
->so
->type
];
3407 /* for fragment shader, we have a single input register (usually
3408 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3410 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3411 // TODO maybe a helper for fi since we need it a few places..
3412 struct ir3_instruction
*instr
;
3413 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3414 ir3_reg_create(instr
, 0, 0);
3415 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3416 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3417 ctx
->frag_pos
= instr
;
3421 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3422 setup_input(ctx
, var
);
3425 /* Setup outputs: */
3426 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3427 setup_output(ctx
, var
);
3430 /* Setup registers (which should only be arrays): */
3431 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3432 declare_array(ctx
, reg
);
3435 /* NOTE: need to do something more clever when we support >1 fxn */
3436 nir_foreach_register(reg
, &fxn
->registers
) {
3437 declare_array(ctx
, reg
);
3439 /* And emit the body: */
3441 emit_function(ctx
, fxn
);
3444 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3445 * for a fragment shader are just bary.f instructions. The *actual* inputs
3446 * from the hw perspective are the frag_pos and optionally frag_coord and
3450 fixup_frag_inputs(struct ir3_context
*ctx
)
3452 struct ir3_shader_variant
*so
= ctx
->so
;
3453 struct ir3
*ir
= ctx
->ir
;
3454 struct ir3_instruction
**inputs
;
3455 struct ir3_instruction
*instr
;
3460 n
= 4; /* always have frag_pos */
3461 n
+= COND(so
->frag_face
, 4);
3462 n
+= COND(so
->frag_coord
, 4);
3464 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3466 if (so
->frag_face
) {
3467 /* this ultimately gets assigned to hr0.x so doesn't conflict
3468 * with frag_coord/frag_pos..
3470 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3471 ctx
->frag_face
->regs
[0]->num
= 0;
3473 /* remaining channels not used, but let's avoid confusing
3474 * other parts that expect inputs to come in groups of vec4
3476 inputs
[ir
->ninputs
++] = NULL
;
3477 inputs
[ir
->ninputs
++] = NULL
;
3478 inputs
[ir
->ninputs
++] = NULL
;
3481 /* since we don't know where to set the regid for frag_coord,
3482 * we have to use r0.x for it. But we don't want to *always*
3483 * use r1.x for frag_pos as that could increase the register
3484 * footprint on simple shaders:
3486 if (so
->frag_coord
) {
3487 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3488 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3489 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3490 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3492 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3493 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3494 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3495 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3498 /* we always have frag_pos: */
3499 so
->pos_regid
= regid
;
3502 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3503 instr
->regs
[0]->num
= regid
++;
3504 inputs
[ir
->ninputs
++] = instr
;
3505 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3508 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3509 instr
->regs
[0]->num
= regid
++;
3510 inputs
[ir
->ninputs
++] = instr
;
3511 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3513 ir
->inputs
= inputs
;
3516 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3517 * need to assign the tex state indexes for these after we know the
3521 fixup_astc_srgb(struct ir3_context
*ctx
)
3523 struct ir3_shader_variant
*so
= ctx
->so
;
3524 /* indexed by original tex idx, value is newly assigned alpha sampler
3525 * state tex idx. Zero is invalid since there is at least one sampler
3528 unsigned alt_tex_state
[16] = {0};
3529 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3532 so
->astc_srgb
.base
= tex_idx
;
3534 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3535 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3537 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3539 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3540 /* assign new alternate/alpha tex state slot: */
3541 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3542 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3543 so
->astc_srgb
.count
++;
3546 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3551 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3552 struct ir3_shader_variant
*so
)
3554 struct ir3_context
*ctx
;
3556 struct ir3_instruction
**inputs
;
3557 unsigned i
, j
, actual_in
, inloc
;
3558 int ret
= 0, max_bary
;
3562 ctx
= compile_init(compiler
, so
);
3564 DBG("INIT failed!");
3569 emit_instructions(ctx
);
3572 DBG("EMIT failed!");
3577 ir
= so
->ir
= ctx
->ir
;
3579 /* keep track of the inputs from TGSI perspective.. */
3580 inputs
= ir
->inputs
;
3582 /* but fixup actual inputs for frag shader: */
3583 if (so
->type
== SHADER_FRAGMENT
)
3584 fixup_frag_inputs(ctx
);
3586 /* at this point, for binning pass, throw away unneeded outputs: */
3587 if (so
->key
.binning_pass
) {
3588 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3589 unsigned slot
= so
->outputs
[i
].slot
;
3591 /* throw away everything but first position/psize */
3592 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3594 so
->outputs
[j
] = so
->outputs
[i
];
3595 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3596 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3597 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3598 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3603 so
->outputs_count
= j
;
3604 ir
->noutputs
= j
* 4;
3607 /* if we want half-precision outputs, mark the output registers
3610 if (so
->key
.half_precision
) {
3611 for (i
= 0; i
< ir
->noutputs
; i
++) {
3612 struct ir3_instruction
*out
= ir
->outputs
[i
];
3617 /* if frag shader writes z, that needs to be full precision: */
3618 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3621 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3622 /* output could be a fanout (ie. texture fetch output)
3623 * in which case we need to propagate the half-reg flag
3624 * up to the definer so that RA sees it:
3626 if (out
->opc
== OPC_META_FO
) {
3627 out
= out
->regs
[1]->instr
;
3628 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3631 if (out
->opc
== OPC_MOV
) {
3632 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3637 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3638 printf("BEFORE CP:\n");
3644 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3645 printf("BEFORE GROUPING:\n");
3649 ir3_sched_add_deps(ir
);
3651 /* Group left/right neighbors, inserting mov's where needed to
3656 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3657 printf("AFTER GROUPING:\n");
3663 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3664 printf("AFTER DEPTH:\n");
3668 ret
= ir3_sched(ir
);
3670 DBG("SCHED failed!");
3674 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3675 printf("AFTER SCHED:\n");
3679 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3685 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3686 printf("AFTER RA:\n");
3690 /* fixup input/outputs: */
3691 for (i
= 0; i
< so
->outputs_count
; i
++) {
3692 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3695 /* Note that some or all channels of an input may be unused: */
3698 for (i
= 0; i
< so
->inputs_count
; i
++) {
3699 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3700 so
->inputs
[i
].ncomp
= 0;
3701 so
->inputs
[i
].inloc
= inloc
;
3702 for (j
= 0; j
< 4; j
++) {
3703 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3704 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3705 compmask
|= (1 << j
);
3706 regid
= in
->regs
[0]->num
- j
;
3708 so
->inputs
[i
].ncomp
++;
3709 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3711 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3712 in
->regs
[1]->iim_val
= inloc
+ j
;
3717 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3719 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3721 } else if (!so
->inputs
[i
].sysval
){
3722 so
->inputs
[i
].compmask
= compmask
;
3724 so
->inputs
[i
].regid
= regid
;
3728 fixup_astc_srgb(ctx
);
3730 /* We need to do legalize after (for frag shader's) the "bary.f"
3731 * offsets (inloc) have been assigned.
3733 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3735 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3736 printf("AFTER LEGALIZE:\n");
3740 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3741 if (so
->type
== SHADER_VERTEX
)
3742 so
->total_in
= actual_in
;
3744 so
->total_in
= max_bary
+ 1;
3749 ir3_destroy(so
->ir
);