1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
40 #include "freedreno_util.h"
42 #include "ir3_compiler.h"
43 #include "ir3_shader.h"
46 #include "instr-a3xx.h"
51 struct ir3_compiler
*compiler
;
53 const struct tgsi_token
*tokens
;
57 struct ir3_shader_variant
*so
;
59 struct ir3_block
*block
; /* the current block */
60 struct ir3_block
*in_block
; /* block created for shader inputs */
62 nir_function_impl
*impl
;
64 /* For fragment shaders, from the hw perspective the only
65 * actual input is r0.xy position register passed to bary.f.
66 * But TGSI doesn't know that, it still declares things as
67 * IN[] registers. So we do all the input tracking normally
68 * and fix things up after compile_instructions()
70 * NOTE that frag_pos is the hardware position (possibly it
71 * is actually an index or tag or some such.. it is *not*
72 * values that can be directly used for gl_FragCoord..)
74 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
76 /* For vertex shaders, keep track of the system values sources */
77 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
79 /* mapping from nir_register to defining instruction: */
80 struct hash_table
*def_ht
;
82 /* mapping from nir_variable to ir3_array: */
83 struct hash_table
*var_ht
;
86 /* a common pattern for indirect addressing is to request the
87 * same address register multiple times. To avoid generating
88 * duplicate instruction sequences (which our backend does not
89 * try to clean up, since that should be done as the NIR stage)
90 * we cache the address value generated for a given src value:
92 struct hash_table
*addr_ht
;
94 /* maps nir_block to ir3_block, mostly for the purposes of
95 * figuring out the blocks successors
97 struct hash_table
*block_ht
;
99 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
100 * so we need to use ldlv.u32 to load the varying directly:
104 /* on a3xx, we need to add one to # of array levels:
108 /* on a3xx, we need to scale up integer coords for isaml based
111 bool unminify_coords
;
113 /* for looking up which system value is which */
114 unsigned sysval_semantics
[8];
116 /* set if we encounter something we can't handle yet, so we
117 * can bail cleanly and fallback to TGSI compiler f/e
123 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
124 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
126 static struct nir_shader
*to_nir(struct ir3_compile
*ctx
,
127 const struct tgsi_token
*tokens
, struct ir3_shader_variant
*so
)
129 static const nir_shader_compiler_options options
= {
134 .lower_ffract
= true,
135 .native_integers
= true,
137 struct nir_lower_tex_options tex_options
= {
143 case SHADER_FRAGMENT
:
145 tex_options
.saturate_s
= so
->key
.fsaturate_s
;
146 tex_options
.saturate_t
= so
->key
.fsaturate_t
;
147 tex_options
.saturate_r
= so
->key
.fsaturate_r
;
150 tex_options
.saturate_s
= so
->key
.vsaturate_s
;
151 tex_options
.saturate_t
= so
->key
.vsaturate_t
;
152 tex_options
.saturate_r
= so
->key
.vsaturate_r
;
156 if (ctx
->compiler
->gpu_id
>= 400) {
157 /* a4xx seems to have *no* sam.p */
158 tex_options
.lower_txp
= ~0; /* lower all txp */
160 /* a3xx just needs to avoid sam.p for 3d tex */
161 tex_options
.lower_txp
= (1 << GLSL_SAMPLER_DIM_3D
);
164 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
166 if (fd_mesa_debug
& FD_DBG_DISASM
) {
167 debug_printf("----------------------\n");
168 nir_print_shader(s
, stdout
);
169 debug_printf("----------------------\n");
172 nir_opt_global_to_local(s
);
173 nir_convert_to_ssa(s
);
174 if (s
->stage
== MESA_SHADER_VERTEX
) {
175 nir_lower_clip_vs(s
, so
->key
.ucp_enables
);
176 } else if (s
->stage
== MESA_SHADER_FRAGMENT
) {
177 nir_lower_clip_fs(s
, so
->key
.ucp_enables
);
179 nir_lower_tex(s
, &tex_options
);
180 if (so
->key
.color_two_side
)
181 nir_lower_two_sided_color(s
);
183 nir_lower_load_const_to_scalar(s
);
188 nir_lower_vars_to_ssa(s
);
189 nir_lower_alu_to_scalar(s
);
190 nir_lower_phis_to_scalar(s
);
192 progress
|= nir_copy_prop(s
);
193 progress
|= nir_opt_dce(s
);
194 progress
|= nir_opt_cse(s
);
195 progress
|= ir3_nir_lower_if_else(s
);
196 progress
|= nir_opt_algebraic(s
);
197 progress
|= nir_opt_constant_folding(s
);
201 nir_remove_dead_variables(s
);
202 nir_validate_shader(s
);
204 if (fd_mesa_debug
& FD_DBG_DISASM
) {
205 debug_printf("----------------------\n");
206 nir_print_shader(s
, stdout
);
207 debug_printf("----------------------\n");
213 static struct ir3_compile
*
214 compile_init(struct ir3_compiler
*compiler
,
215 struct ir3_shader_variant
*so
,
216 const struct tgsi_token
*tokens
)
218 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
220 if (compiler
->gpu_id
>= 400) {
221 /* need special handling for "flat" */
222 ctx
->flat_bypass
= true;
223 ctx
->levels_add_one
= false;
224 ctx
->unminify_coords
= false;
226 /* no special handling for "flat" */
227 ctx
->flat_bypass
= false;
228 ctx
->levels_add_one
= true;
229 ctx
->unminify_coords
= true;
232 ctx
->compiler
= compiler
;
235 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
236 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
237 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
238 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
239 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
240 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
242 ctx
->s
= to_nir(ctx
, tokens
, so
);
244 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
246 /* Layout of constant registers:
248 * num_uniform * vec4 - user consts
249 * 4 * vec4 - UBO addresses
250 * if (vertex shader) {
251 * N * vec4 - driver params (IR3_DP_*)
252 * 1 * vec4 - stream-out addresses
255 * TODO this could be made more dynamic, to at least skip sections
256 * that we don't need..
259 /* reserve 4 (vec4) slots for ubo base addresses: */
260 so
->first_immediate
+= 4;
262 if (so
->type
== SHADER_VERTEX
) {
263 /* driver params (see ir3_driver_param): */
264 so
->first_immediate
+= IR3_DP_COUNT
/4; /* convert to vec4 */
265 /* one (vec4) slot for stream-output base addresses: */
266 so
->first_immediate
++;
273 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
276 va_start(ap
, format
);
277 _debug_vprintf(format
, ap
);
279 nir_print_shader(ctx
->s
, stdout
);
284 #define compile_assert(ctx, cond) do { \
285 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
289 compile_free(struct ir3_compile
*ctx
)
294 /* global per-array information: */
296 unsigned length
, aid
;
299 /* per-block array state: */
300 struct ir3_array_value
{
301 /* TODO drop length/aid, and just have ptr back to ir3_array */
302 unsigned length
, aid
;
303 /* initial array element values are phi's, other than for the
304 * entry block. The phi src's get added later in a resolve step
305 * after we have visited all the blocks, to account for back
308 struct ir3_instruction
**phis
;
309 /* current array element values (as block is processed). When
310 * the array phi's are resolved, it will contain the array state
311 * at exit of block, so successor blocks can use it to add their
314 struct ir3_instruction
*arr
[];
317 /* track array assignments per basic block. When an array is read
318 * outside of the same basic block, we can use NIR's dominance-frontier
319 * information to figure out where phi nodes are needed.
321 struct ir3_nir_block_data
{
323 /* indexed by array-id (aid): */
324 struct ir3_array_value
*arrs
[];
327 static struct ir3_nir_block_data
*
328 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
331 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
332 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
339 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
341 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
342 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
343 arr
->length
= length
;
344 arr
->aid
= ++ctx
->num_arrays
;
345 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
349 nir_block_pred(nir_block
*block
)
351 assert(block
->predecessors
->entries
< 2);
352 if (block
->predecessors
->entries
== 0)
354 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
357 static struct ir3_array_value
*
358 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
360 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
361 struct ir3_block
*block
= ctx
->block
;
362 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
363 struct ir3_array
*arr
= entry
->data
;
365 if (!bd
->arrs
[arr
->aid
]) {
366 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
367 (arr
->length
* sizeof(av
->arr
[0])));
368 struct ir3_array_value
*defn
= NULL
;
369 nir_block
*pred_block
;
371 av
->length
= arr
->length
;
374 /* For loops, we have to consider that we have not visited some
375 * of the blocks who should feed into the phi (ie. back-edges in
376 * the cfg).. for example:
379 * block { load_var; ... }
380 * if then block {} else block {}
381 * block { store_var; ... }
382 * if then block {} else block {}
386 * We can skip the phi if we can chase the block predecessors
387 * until finding the block previously defining the array without
388 * crossing a block that has more than one predecessor.
390 * Otherwise create phi's and resolve them as a post-pass after
391 * all the blocks have been visited (to handle back-edges).
394 for (pred_block
= block
->nblock
;
395 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
396 pred_block
= nir_block_pred(pred_block
)) {
397 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
398 struct ir3_nir_block_data
*pbd
= pblock
->data
;
401 defn
= pbd
->arrs
[arr
->aid
];
405 /* only one possible definer: */
406 for (unsigned i
= 0; i
< arr
->length
; i
++)
407 av
->arr
[i
] = defn
->arr
[i
];
408 } else if (pred_block
) {
409 /* not the first block, and multiple potential definers: */
410 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
412 for (unsigned i
= 0; i
< arr
->length
; i
++) {
413 struct ir3_instruction
*phi
;
415 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
416 1 + ctx
->impl
->num_blocks
);
417 ir3_reg_create(phi
, 0, 0); /* dst */
419 /* phi's should go at head of block: */
420 list_delinit(&phi
->node
);
421 list_add(&phi
->node
, &block
->instr_list
);
423 av
->phis
[i
] = av
->arr
[i
] = phi
;
426 /* Some shaders end up reading array elements without
427 * first writing.. so initialize things to prevent null
430 for (unsigned i
= 0; i
< arr
->length
; i
++)
431 av
->arr
[i
] = create_immed(block
, 0);
434 bd
->arrs
[arr
->aid
] = av
;
437 return bd
->arrs
[arr
->aid
];
441 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
442 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
444 struct ir3_block
*block
;
445 struct ir3_nir_block_data
*bd
;
447 if (BITSET_TEST(visited
, nblock
->index
))
450 BITSET_SET(visited
, nblock
->index
);
452 block
= get_block(ctx
, nblock
);
455 if (bd
&& bd
->arrs
[av
->aid
]) {
456 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
457 for (unsigned i
= 0; i
< av
->length
; i
++) {
458 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
462 /* didn't find defn, recurse predecessors: */
463 struct set_entry
*entry
;
464 set_foreach(nblock
->predecessors
, entry
) {
465 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
471 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
473 struct ir3_nir_block_data
*bd
= block
->data
;
474 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
479 /* TODO use nir dom_frontier to help us with this? */
481 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
482 struct ir3_array_value
*av
= bd
->arrs
[i
];
483 BITSET_WORD visited
[bitset_words
];
484 struct set_entry
*entry
;
486 if (!(av
&& av
->phis
))
489 memset(visited
, 0, sizeof(visited
));
490 set_foreach(block
->nblock
->predecessors
, entry
) {
491 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
496 /* allocate a n element value array (to be populated by caller) and
499 static struct ir3_instruction
**
500 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
502 struct ir3_instruction
**value
=
503 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
504 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
508 static struct ir3_instruction
**
509 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
512 return __get_dst(ctx
, &dst
->ssa
, n
);
514 return __get_dst(ctx
, dst
->reg
.reg
, n
);
518 static struct ir3_instruction
**
519 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
521 return __get_dst(ctx
, dst
, n
);
524 static struct ir3_instruction
**
525 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
527 struct hash_entry
*entry
;
529 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
531 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
533 compile_assert(ctx
, entry
);
537 static struct ir3_instruction
*
538 create_immed(struct ir3_block
*block
, uint32_t val
)
540 struct ir3_instruction
*mov
;
542 mov
= ir3_instr_create(block
, 1, 0);
543 mov
->cat1
.src_type
= TYPE_U32
;
544 mov
->cat1
.dst_type
= TYPE_U32
;
545 ir3_reg_create(mov
, 0, 0);
546 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
551 static struct ir3_instruction
*
552 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
554 struct ir3_instruction
*instr
, *immed
;
556 /* TODO in at least some cases, the backend could probably be
557 * made clever enough to propagate IR3_REG_HALF..
559 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
560 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
562 immed
= create_immed(block
, 2);
563 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
565 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
566 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
567 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
569 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
570 instr
->regs
[0]->num
= regid(REG_A0
, 0);
571 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
572 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
577 /* caches addr values to avoid generating multiple cov/shl/mova
578 * sequences for each use of a given NIR level src as address
580 static struct ir3_instruction
*
581 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
583 struct ir3_instruction
*addr
;
586 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
587 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
589 struct hash_entry
*entry
;
590 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
595 addr
= create_addr(ctx
->block
, src
);
596 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
601 static struct ir3_instruction
*
602 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
604 struct ir3_block
*b
= ctx
->block
;
605 struct ir3_instruction
*cond
;
607 /* NOTE: only cmps.*.* can write p0.x: */
608 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
609 cond
->cat2
.condition
= IR3_COND_NE
;
611 /* condition always goes in predicate register: */
612 cond
->regs
[0]->num
= regid(REG_P0
, 0);
617 static struct ir3_instruction
*
618 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
620 struct ir3_instruction
*mov
;
622 mov
= ir3_instr_create(ctx
->block
, 1, 0);
623 /* TODO get types right? */
624 mov
->cat1
.src_type
= TYPE_F32
;
625 mov
->cat1
.dst_type
= TYPE_F32
;
626 ir3_reg_create(mov
, 0, 0);
627 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
632 static struct ir3_instruction
*
633 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
634 struct ir3_instruction
*address
)
636 struct ir3_instruction
*mov
;
638 mov
= ir3_instr_create(ctx
->block
, 1, 0);
639 mov
->cat1
.src_type
= TYPE_U32
;
640 mov
->cat1
.dst_type
= TYPE_U32
;
641 ir3_reg_create(mov
, 0, 0);
642 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
644 ir3_instr_set_address(mov
, address
);
649 static struct ir3_instruction
*
650 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
653 struct ir3_instruction
*collect
;
658 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
659 ir3_reg_create(collect
, 0, 0); /* dst */
660 for (unsigned i
= 0; i
< arrsz
; i
++)
661 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
666 static struct ir3_instruction
*
667 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
668 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
670 struct ir3_block
*block
= ctx
->block
;
671 struct ir3_instruction
*mov
;
672 struct ir3_register
*src
;
674 mov
= ir3_instr_create(block
, 1, 0);
675 mov
->cat1
.src_type
= TYPE_U32
;
676 mov
->cat1
.dst_type
= TYPE_U32
;
677 ir3_reg_create(mov
, 0, 0);
678 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
679 src
->instr
= collect
;
683 ir3_instr_set_address(mov
, address
);
688 static struct ir3_instruction
*
689 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
690 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
691 struct ir3_instruction
*collect
)
693 struct ir3_block
*block
= ctx
->block
;
694 struct ir3_instruction
*mov
;
695 struct ir3_register
*dst
;
697 mov
= ir3_instr_create(block
, 1, 0);
698 mov
->cat1
.src_type
= TYPE_U32
;
699 mov
->cat1
.dst_type
= TYPE_U32
;
700 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
703 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
704 mov
->fanin
= collect
;
706 ir3_instr_set_address(mov
, address
);
711 static struct ir3_instruction
*
712 create_input(struct ir3_block
*block
, unsigned n
)
714 struct ir3_instruction
*in
;
716 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
717 in
->inout
.block
= block
;
718 ir3_reg_create(in
, n
, 0);
723 static struct ir3_instruction
*
724 create_frag_input(struct ir3_compile
*ctx
, bool use_ldlv
)
726 struct ir3_block
*block
= ctx
->block
;
727 struct ir3_instruction
*instr
;
728 /* actual inloc is assigned and fixed up later: */
729 struct ir3_instruction
*inloc
= create_immed(block
, 0);
732 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
733 instr
->cat6
.type
= TYPE_U32
;
734 instr
->cat6
.iim_val
= 1;
736 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
737 instr
->regs
[2]->wrmask
= 0x3;
743 static struct ir3_instruction
*
744 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
746 struct ir3_block
*block
= ctx
->block
;
747 struct ir3_instruction
*instr
;
749 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
751 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
756 /* for frag_coord, we get unsigned values.. we need
757 * to subtract (integer) 8 and divide by 16 (right-
758 * shift by 4) then convert to float:
762 * mov.u32f32 dst, tmp
765 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
766 create_immed(block
, 8), 0);
767 instr
= ir3_SHR_B(block
, instr
, 0,
768 create_immed(block
, 4), 0);
769 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
775 /* seems that we can use these as-is: */
776 return ctx
->frag_coord
[comp
];
780 static struct ir3_instruction
*
781 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
783 struct ir3_block
*block
= ctx
->block
;
784 struct ir3_instruction
*instr
;
788 compile_assert(ctx
, !ctx
->frag_face
);
790 ctx
->frag_face
= create_input(block
, 0);
791 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
793 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
794 * positive vs negative float.. and piglit further seems to
795 * expect -1.0 or 1.0:
797 * mul.s tmp, hr0.x, 2
799 * mov.s32f32, dst, tmp
802 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
803 create_immed(block
, 2), 0);
804 instr
= ir3_ADD_S(block
, instr
, 0,
805 create_immed(block
, 1), 0);
806 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
811 return create_immed(block
, fui(0.0));
814 return create_immed(block
, fui(1.0));
818 static struct ir3_instruction
*
819 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
821 /* first four vec4 sysval's reserved for UBOs: */
822 /* NOTE: dp is in scalar, but there can be >4 dp components: */
823 unsigned n
= ctx
->so
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
824 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
825 return create_uniform(ctx
, r
);
828 /* helper for instructions that produce multiple consecutive scalar
829 * outputs which need to have a split/fanout meta instruction inserted
832 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
833 struct ir3_instruction
*src
, unsigned n
)
835 struct ir3_instruction
*prev
= NULL
;
836 for (int i
= 0, j
= 0; i
< n
; i
++) {
837 struct ir3_instruction
*split
=
838 ir3_instr_create(block
, -1, OPC_META_FO
);
839 ir3_reg_create(split
, 0, IR3_REG_SSA
);
840 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
844 split
->cp
.left
= prev
;
845 split
->cp
.left_cnt
++;
846 prev
->cp
.right
= split
;
847 prev
->cp
.right_cnt
++;
851 if (src
->regs
[0]->wrmask
& (1 << i
))
857 * Adreno uses uint rather than having dedicated bool type,
858 * which (potentially) requires some conversion, in particular
859 * when using output of an bool instr to int input, or visa
863 * -------+---------+-------+-
867 * To convert from an adreno bool (uint) to nir, use:
869 * absneg.s dst, (neg)src
871 * To convert back in the other direction:
873 * absneg.s dst, (abs)arc
875 * The CP step can clean up the absneg.s that cancel each other
876 * out, and with a slight bit of extra cleverness (to recognize
877 * the instructions which produce either a 0 or 1) can eliminate
878 * the absneg.s's completely when an instruction that wants
879 * 0/1 consumes the result. For example, when a nir 'bcsel'
880 * consumes the result of 'feq'. So we should be able to get by
881 * without a boolean resolve step, and without incuring any
882 * extra penalty in instruction count.
885 /* NIR bool -> native (adreno): */
886 static struct ir3_instruction
*
887 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
889 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
892 /* native (adreno) -> NIR bool: */
893 static struct ir3_instruction
*
894 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
896 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
900 * alu/sfu instructions:
904 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
906 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
907 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
908 struct ir3_block
*b
= ctx
->block
;
910 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
912 /* Vectors are special in that they have non-scalarized writemasks,
913 * and just take the first swizzle channel for each argument in
914 * order into each writemask channel.
916 if ((alu
->op
== nir_op_vec2
) ||
917 (alu
->op
== nir_op_vec3
) ||
918 (alu
->op
== nir_op_vec4
)) {
920 for (int i
= 0; i
< info
->num_inputs
; i
++) {
921 nir_alu_src
*asrc
= &alu
->src
[i
];
923 compile_assert(ctx
, !asrc
->abs
);
924 compile_assert(ctx
, !asrc
->negate
);
926 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
928 src
[i
] = create_immed(ctx
->block
, 0);
929 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
935 /* General case: We can just grab the one used channel per src. */
936 for (int i
= 0; i
< info
->num_inputs
; i
++) {
937 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
938 nir_alu_src
*asrc
= &alu
->src
[i
];
940 compile_assert(ctx
, !asrc
->abs
);
941 compile_assert(ctx
, !asrc
->negate
);
943 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
945 compile_assert(ctx
, src
[i
]);
950 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
953 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
956 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
959 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
962 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
965 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
968 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
969 dst
[0]->cat2
.condition
= IR3_COND_NE
;
970 dst
[0] = ir3_n2b(b
, dst
[0]);
973 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
976 dst
[0] = ir3_b2n(b
, src
[0]);
979 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
980 dst
[0]->cat2
.condition
= IR3_COND_NE
;
981 dst
[0] = ir3_n2b(b
, dst
[0]);
985 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
988 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
991 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
994 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
997 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1000 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1003 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1006 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1009 dst
[0] = ir3_DSX(b
, src
[0], 0);
1010 dst
[0]->cat5
.type
= TYPE_F32
;
1013 dst
[0] = ir3_DSY(b
, src
[0], 0);
1014 dst
[0]->cat5
.type
= TYPE_F32
;
1018 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1019 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1020 dst
[0] = ir3_n2b(b
, dst
[0]);
1023 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1024 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1025 dst
[0] = ir3_n2b(b
, dst
[0]);
1028 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1029 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1030 dst
[0] = ir3_n2b(b
, dst
[0]);
1033 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1034 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1035 dst
[0] = ir3_n2b(b
, dst
[0]);
1038 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1041 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1044 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1046 case nir_op_fround_even
:
1047 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1050 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1054 dst
[0] = ir3_SIN(b
, src
[0], 0);
1057 dst
[0] = ir3_COS(b
, src
[0], 0);
1060 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1063 dst
[0] = ir3_RCP(b
, src
[0], 0);
1066 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1069 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1072 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1076 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1079 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1082 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1085 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1088 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1094 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1098 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1099 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1100 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1101 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1103 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1104 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1105 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1108 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1111 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1114 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1117 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1120 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1122 case nir_op_isign
: {
1123 /* maybe this would be sane to lower in nir.. */
1124 struct ir3_instruction
*neg
, *pos
;
1126 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1127 neg
->cat2
.condition
= IR3_COND_LT
;
1129 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1130 pos
->cat2
.condition
= IR3_COND_GT
;
1132 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1137 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1140 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1143 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1146 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1147 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1148 dst
[0] = ir3_n2b(b
, dst
[0]);
1151 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1152 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1153 dst
[0] = ir3_n2b(b
, dst
[0]);
1156 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1157 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1158 dst
[0] = ir3_n2b(b
, dst
[0]);
1161 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1162 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1163 dst
[0] = ir3_n2b(b
, dst
[0]);
1166 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1167 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1168 dst
[0] = ir3_n2b(b
, dst
[0]);
1171 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1172 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1173 dst
[0] = ir3_n2b(b
, dst
[0]);
1177 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1180 case nir_op_bit_count
:
1181 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1183 case nir_op_ifind_msb
: {
1184 struct ir3_instruction
*cmp
;
1185 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1186 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1187 cmp
->cat2
.condition
= IR3_COND_GE
;
1188 dst
[0] = ir3_SEL_B32(b
,
1189 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1193 case nir_op_ufind_msb
:
1194 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1195 dst
[0] = ir3_SEL_B32(b
,
1196 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1197 src
[0], 0, dst
[0], 0);
1199 case nir_op_find_lsb
:
1200 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1201 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1203 case nir_op_bitfield_reverse
:
1204 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1208 compile_error(ctx
, "Unhandled ALU op: %s\n",
1209 nir_op_infos
[alu
->op
].name
);
1214 /* handles direct/indirect UBO reads: */
1216 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1217 struct ir3_instruction
**dst
)
1219 struct ir3_block
*b
= ctx
->block
;
1220 struct ir3_instruction
*addr
, *src0
, *src1
;
1221 nir_const_value
*const_offset
;
1222 /* UBO addresses are the first driver params: */
1223 unsigned ubo
= regid(ctx
->so
->first_driver_param
+ IR3_UBOS_OFF
, 0);
1224 unsigned off
= intr
->const_index
[0];
1226 /* First src is ubo index, which could either be an immed or not: */
1227 src0
= get_src(ctx
, &intr
->src
[0])[0];
1228 if (is_same_type_mov(src0
) &&
1229 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1230 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1232 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1235 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1237 off
+= const_offset
->u
[0];
1239 /* For load_ubo_indirect, second src is indirect offset: */
1240 src1
= get_src(ctx
, &intr
->src
[1])[0];
1242 /* and add offset to addr: */
1243 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1246 /* if offset is to large to encode in the ldg, split it out: */
1247 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1248 /* split out the minimal amount to improve the odds that
1249 * cp can fit the immediate in the add.s instruction:
1251 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1252 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1256 for (int i
= 0; i
< intr
->num_components
; i
++) {
1257 struct ir3_instruction
*load
=
1258 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1259 load
->cat6
.type
= TYPE_U32
;
1260 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1265 /* handles array reads: */
1267 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1268 struct ir3_instruction
**dst
)
1270 nir_deref_var
*dvar
= intr
->variables
[0];
1271 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1272 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1274 compile_assert(ctx
, dvar
->deref
.child
&&
1275 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1277 switch (darr
->deref_array_type
) {
1278 case nir_deref_array_type_direct
:
1279 /* direct access does not require anything special: */
1280 for (int i
= 0; i
< intr
->num_components
; i
++) {
1281 unsigned n
= darr
->base_offset
* 4 + i
;
1282 compile_assert(ctx
, n
< arr
->length
);
1283 dst
[i
] = arr
->arr
[n
];
1286 case nir_deref_array_type_indirect
: {
1287 /* for indirect, we need to collect all the array elements: */
1288 struct ir3_instruction
*collect
=
1289 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1290 struct ir3_instruction
*addr
=
1291 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1292 for (int i
= 0; i
< intr
->num_components
; i
++) {
1293 unsigned n
= darr
->base_offset
* 4 + i
;
1294 compile_assert(ctx
, n
< arr
->length
);
1295 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1300 compile_error(ctx
, "Unhandled load deref type: %u\n",
1301 darr
->deref_array_type
);
1306 /* handles array writes: */
1308 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1310 nir_deref_var
*dvar
= intr
->variables
[0];
1311 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1312 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1313 struct ir3_instruction
**src
;
1315 compile_assert(ctx
, dvar
->deref
.child
&&
1316 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1318 src
= get_src(ctx
, &intr
->src
[0]);
1320 switch (darr
->deref_array_type
) {
1321 case nir_deref_array_type_direct
:
1322 /* direct access does not require anything special: */
1323 for (int i
= 0; i
< intr
->num_components
; i
++) {
1324 unsigned n
= darr
->base_offset
* 4 + i
;
1325 compile_assert(ctx
, n
< arr
->length
);
1326 arr
->arr
[n
] = src
[i
];
1329 case nir_deref_array_type_indirect
: {
1330 /* for indirect, create indirect-store and fan that out: */
1331 struct ir3_instruction
*collect
=
1332 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1333 struct ir3_instruction
*addr
=
1334 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1335 for (int i
= 0; i
< intr
->num_components
; i
++) {
1336 struct ir3_instruction
*store
;
1337 unsigned n
= darr
->base_offset
* 4 + i
;
1338 compile_assert(ctx
, n
< arr
->length
);
1340 store
= create_indirect_store(ctx
, arr
->length
,
1341 n
, src
[i
], addr
, collect
);
1343 store
->fanin
->fi
.aid
= arr
->aid
;
1345 /* TODO: probably split this out to be used for
1346 * store_output_indirect? or move this into
1347 * create_indirect_store()?
1349 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1350 struct ir3_instruction
*split
;
1352 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1354 ir3_reg_create(split
, 0, 0);
1355 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1357 arr
->arr
[j
] = split
;
1360 /* fixup fanout/split neighbors: */
1361 for (int i
= 0; i
< arr
->length
; i
++) {
1362 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1363 arr
->arr
[i
+1] : NULL
;
1364 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1365 arr
->arr
[i
-1] : NULL
;
1370 compile_error(ctx
, "Unhandled store deref type: %u\n",
1371 darr
->deref_array_type
);
1376 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1377 struct ir3_instruction
*instr
)
1379 struct ir3_shader_variant
*so
= ctx
->so
;
1380 unsigned r
= regid(so
->inputs_count
, 0);
1381 unsigned n
= so
->inputs_count
++;
1383 so
->inputs
[n
].sysval
= true;
1384 so
->inputs
[n
].slot
= slot
;
1385 so
->inputs
[n
].compmask
= 1;
1386 so
->inputs
[n
].regid
= r
;
1387 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_FLAT
;
1390 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1391 ctx
->ir
->inputs
[r
] = instr
;
1395 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1397 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1398 struct ir3_instruction
**dst
, **src
;
1399 struct ir3_block
*b
= ctx
->block
;
1400 unsigned idx
= intr
->const_index
[0];
1401 nir_const_value
*const_offset
;
1403 if (info
->has_dest
) {
1404 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1409 switch (intr
->intrinsic
) {
1410 case nir_intrinsic_load_uniform
:
1411 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1413 idx
+= const_offset
->u
[0];
1414 for (int i
= 0; i
< intr
->num_components
; i
++) {
1415 unsigned n
= idx
* 4 + i
;
1416 dst
[i
] = create_uniform(ctx
, n
);
1419 src
= get_src(ctx
, &intr
->src
[0]);
1420 for (int i
= 0; i
< intr
->num_components
; i
++) {
1421 unsigned n
= idx
* 4 + i
;
1422 dst
[i
] = create_uniform_indirect(ctx
, n
,
1423 get_addr(ctx
, src
[0]));
1425 /* NOTE: if relative addressing is used, we set
1426 * constlen in the compiler (to worst-case value)
1427 * since we don't know in the assembler what the max
1428 * addr reg value can be:
1430 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1433 case nir_intrinsic_load_ubo
:
1434 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1436 case nir_intrinsic_load_input
:
1437 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1439 idx
+= const_offset
->u
[0];
1440 for (int i
= 0; i
< intr
->num_components
; i
++) {
1441 unsigned n
= idx
* 4 + i
;
1442 dst
[i
] = ctx
->ir
->inputs
[n
];
1445 src
= get_src(ctx
, &intr
->src
[0]);
1446 struct ir3_instruction
*collect
=
1447 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1448 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1449 for (int i
= 0; i
< intr
->num_components
; i
++) {
1450 unsigned n
= idx
* 4 + i
;
1451 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1456 case nir_intrinsic_load_var
:
1457 emit_intrinisic_load_var(ctx
, intr
, dst
);
1459 case nir_intrinsic_store_var
:
1460 emit_intrinisic_store_var(ctx
, intr
);
1462 case nir_intrinsic_store_output
:
1463 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1464 compile_assert(ctx
, const_offset
!= NULL
);
1465 idx
+= const_offset
->u
[0];
1467 src
= get_src(ctx
, &intr
->src
[0]);
1468 for (int i
= 0; i
< intr
->num_components
; i
++) {
1469 unsigned n
= idx
* 4 + i
;
1470 ctx
->ir
->outputs
[n
] = src
[i
];
1473 case nir_intrinsic_load_base_vertex
:
1474 if (!ctx
->basevertex
) {
1475 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1476 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1479 dst
[0] = ctx
->basevertex
;
1481 case nir_intrinsic_load_vertex_id_zero_base
:
1482 if (!ctx
->vertex_id
) {
1483 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1484 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
1487 dst
[0] = ctx
->vertex_id
;
1489 case nir_intrinsic_load_instance_id
:
1490 if (!ctx
->instance_id
) {
1491 ctx
->instance_id
= create_input(ctx
->block
, 0);
1492 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1495 dst
[0] = ctx
->instance_id
;
1497 case nir_intrinsic_load_user_clip_plane
:
1498 for (int i
= 0; i
< intr
->num_components
; i
++) {
1499 unsigned n
= idx
* 4 + i
;
1500 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1503 case nir_intrinsic_discard_if
:
1504 case nir_intrinsic_discard
: {
1505 struct ir3_instruction
*cond
, *kill
;
1507 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1508 /* conditional discard: */
1509 src
= get_src(ctx
, &intr
->src
[0]);
1510 cond
= ir3_b2n(b
, src
[0]);
1512 /* unconditional discard: */
1513 cond
= create_immed(b
, 1);
1516 /* NOTE: only cmps.*.* can write p0.x: */
1517 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1518 cond
->cat2
.condition
= IR3_COND_NE
;
1520 /* condition always goes in predicate register: */
1521 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1523 kill
= ir3_KILL(b
, cond
, 0);
1524 array_insert(ctx
->ir
->predicates
, kill
);
1526 array_insert(ctx
->ir
->keeps
, kill
);
1527 ctx
->so
->has_kill
= true;
1532 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1533 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1539 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1541 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1542 instr
->def
.num_components
);
1543 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1544 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1548 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1550 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1551 undef
->def
.num_components
);
1552 /* backend doesn't want undefined instructions, so just plug
1555 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1556 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1560 * texture fetch/sample instructions:
1564 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1566 unsigned coords
, flags
= 0;
1568 /* note: would use tex->coord_components.. except txs.. also,
1569 * since array index goes after shadow ref, we don't want to
1572 switch (tex
->sampler_dim
) {
1573 case GLSL_SAMPLER_DIM_1D
:
1574 case GLSL_SAMPLER_DIM_BUF
:
1577 case GLSL_SAMPLER_DIM_2D
:
1578 case GLSL_SAMPLER_DIM_RECT
:
1579 case GLSL_SAMPLER_DIM_EXTERNAL
:
1580 case GLSL_SAMPLER_DIM_MS
:
1583 case GLSL_SAMPLER_DIM_3D
:
1584 case GLSL_SAMPLER_DIM_CUBE
:
1586 flags
|= IR3_INSTR_3D
;
1589 unreachable("bad sampler_dim");
1592 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1593 flags
|= IR3_INSTR_S
;
1595 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1596 flags
|= IR3_INSTR_A
;
1603 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1605 struct ir3_block
*b
= ctx
->block
;
1606 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1607 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1608 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1609 unsigned i
, coords
, flags
;
1610 unsigned nsrc0
= 0, nsrc1
= 0;
1614 coord
= off
= ddx
= ddy
= NULL
;
1615 lod
= proj
= compare
= NULL
;
1617 /* TODO: might just be one component for gathers? */
1618 dst
= get_dst(ctx
, &tex
->dest
, 4);
1620 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1621 switch (tex
->src
[i
].src_type
) {
1622 case nir_tex_src_coord
:
1623 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1625 case nir_tex_src_bias
:
1626 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1629 case nir_tex_src_lod
:
1630 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1633 case nir_tex_src_comparitor
: /* shadow comparator */
1634 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1636 case nir_tex_src_projector
:
1637 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1640 case nir_tex_src_offset
:
1641 off
= get_src(ctx
, &tex
->src
[i
].src
);
1644 case nir_tex_src_ddx
:
1645 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1647 case nir_tex_src_ddy
:
1648 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1651 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1652 tex
->src
[i
].src_type
);
1658 case nir_texop_tex
: opc
= OPC_SAM
; break;
1659 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1660 case nir_texop_txl
: opc
= OPC_SAML
; break;
1661 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1662 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1663 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1664 case nir_texop_txf_ms
:
1667 case nir_texop_query_levels
:
1668 case nir_texop_texture_samples
:
1669 case nir_texop_samples_identical
:
1670 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1674 tex_info(tex
, &flags
, &coords
);
1676 /* scale up integer coords for TXF based on the LOD */
1677 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1679 for (i
= 0; i
< coords
; i
++)
1680 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1683 /* the array coord for cube arrays needs 0.5 added to it */
1684 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& tex
->is_array
&&
1686 coord
[3] = ir3_ADD_F(b
, coord
[3], 0, create_immed(b
, fui(0.5)), 0);
1689 * lay out the first argument in the proper order:
1690 * - actual coordinates first
1691 * - shadow reference
1694 * - starting at offset 4, dpdx.xy, dpdy.xy
1696 * bias/lod go into the second arg
1699 /* insert tex coords: */
1700 for (i
= 0; i
< coords
; i
++)
1701 src0
[nsrc0
++] = coord
[i
];
1704 /* hw doesn't do 1d, so we treat it as 2d with
1705 * height of 1, and patch up the y coord.
1706 * TODO: y coord should be (int)0 in some cases..
1708 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1711 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1712 src0
[nsrc0
++] = compare
;
1714 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1715 src0
[nsrc0
++] = coord
[coords
];
1718 src0
[nsrc0
++] = proj
;
1719 flags
|= IR3_INSTR_P
;
1722 /* pad to 4, then ddx/ddy: */
1723 if (tex
->op
== nir_texop_txd
) {
1725 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1726 for (i
= 0; i
< coords
; i
++)
1727 src0
[nsrc0
++] = ddx
[i
];
1729 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1730 for (i
= 0; i
< coords
; i
++)
1731 src0
[nsrc0
++] = ddy
[i
];
1733 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1737 * second argument (if applicable):
1742 if (has_off
| has_lod
| has_bias
) {
1744 for (i
= 0; i
< coords
; i
++)
1745 src1
[nsrc1
++] = off
[i
];
1747 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1748 flags
|= IR3_INSTR_O
;
1751 if (has_lod
| has_bias
)
1752 src1
[nsrc1
++] = lod
;
1755 switch (tex
->dest_type
) {
1756 case nir_type_invalid
:
1757 case nir_type_float
:
1768 unreachable("bad dest_type");
1771 if (opc
== OPC_GETLOD
)
1774 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1775 flags
, tex
->sampler_index
, tex
->sampler_index
,
1776 create_collect(b
, src0
, nsrc0
),
1777 create_collect(b
, src1
, nsrc1
));
1779 split_dest(b
, dst
, sam
, 4);
1781 /* GETLOD returns results in 4.8 fixed point */
1782 if (opc
== OPC_GETLOD
) {
1783 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1785 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1786 for (i
= 0; i
< 2; i
++) {
1787 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1794 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1796 struct ir3_block
*b
= ctx
->block
;
1797 struct ir3_instruction
**dst
, *sam
;
1799 dst
= get_dst(ctx
, &tex
->dest
, 1);
1801 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1802 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1804 /* even though there is only one component, since it ends
1805 * up in .z rather than .x, we need a split_dest()
1807 split_dest(b
, dst
, sam
, 3);
1809 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1810 * the value in TEX_CONST_0 is zero-based.
1812 if (ctx
->levels_add_one
)
1813 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1817 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1819 struct ir3_block
*b
= ctx
->block
;
1820 struct ir3_instruction
**dst
, *sam
, *lod
;
1821 unsigned flags
, coords
;
1823 tex_info(tex
, &flags
, &coords
);
1825 /* Actually we want the number of dimensions, not coordinates. This
1826 * distinction only matters for cubes.
1828 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1831 dst
= get_dst(ctx
, &tex
->dest
, 4);
1833 compile_assert(ctx
, tex
->num_srcs
== 1);
1834 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1836 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1838 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1839 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1841 split_dest(b
, dst
, sam
, 4);
1843 /* Array size actually ends up in .w rather than .z. This doesn't
1844 * matter for miplevel 0, but for higher mips the value in z is
1845 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1846 * returned, which means that we have to add 1 to it for arrays.
1848 if (tex
->is_array
) {
1849 if (ctx
->levels_add_one
) {
1850 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1852 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1858 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1860 struct ir3_instruction
*phi
, **dst
;
1862 /* NOTE: phi's should be lowered to scalar at this point */
1863 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1865 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1867 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1868 1 + exec_list_length(&nphi
->srcs
));
1869 ir3_reg_create(phi
, 0, 0); /* dst */
1870 phi
->phi
.nphi
= nphi
;
1875 /* phi instructions are left partially constructed. We don't resolve
1876 * their srcs until the end of the block, since (eg. loops) one of
1877 * the phi's srcs might be defined after the phi due to back edges in
1881 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1883 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1884 nir_phi_instr
*nphi
;
1886 /* phi's only come at start of block: */
1887 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1890 if (!instr
->phi
.nphi
)
1893 nphi
= instr
->phi
.nphi
;
1894 instr
->phi
.nphi
= NULL
;
1896 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1897 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1898 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1902 resolve_array_phis(ctx
, block
);
1906 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1908 switch (jump
->type
) {
1909 case nir_jump_break
:
1910 case nir_jump_continue
:
1911 /* I *think* we can simply just ignore this, and use the
1912 * successor block link to figure out where we need to
1913 * jump to for break/continue
1917 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1923 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1925 switch (instr
->type
) {
1926 case nir_instr_type_alu
:
1927 emit_alu(ctx
, nir_instr_as_alu(instr
));
1929 case nir_instr_type_intrinsic
:
1930 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1932 case nir_instr_type_load_const
:
1933 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1935 case nir_instr_type_ssa_undef
:
1936 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1938 case nir_instr_type_tex
: {
1939 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1940 /* couple tex instructions get special-cased:
1944 emit_tex_txs(ctx
, tex
);
1946 case nir_texop_query_levels
:
1947 emit_tex_query_levels(ctx
, tex
);
1949 case nir_texop_samples_identical
:
1950 unreachable("nir_texop_samples_identical");
1957 case nir_instr_type_phi
:
1958 emit_phi(ctx
, nir_instr_as_phi(instr
));
1960 case nir_instr_type_jump
:
1961 emit_jump(ctx
, nir_instr_as_jump(instr
));
1963 case nir_instr_type_call
:
1964 case nir_instr_type_parallel_copy
:
1965 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1970 static struct ir3_block
*
1971 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1973 struct ir3_block
*block
;
1974 struct hash_entry
*entry
;
1975 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1979 block
= ir3_block_create(ctx
->ir
);
1980 block
->nblock
= nblock
;
1981 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1987 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1989 struct ir3_block
*block
= get_block(ctx
, nblock
);
1991 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1992 if (nblock
->successors
[i
]) {
1993 block
->successors
[i
] =
1994 get_block(ctx
, nblock
->successors
[i
]);
1999 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2001 /* re-emit addr register in each block if needed: */
2002 _mesa_hash_table_destroy(ctx
->addr_ht
, NULL
);
2003 ctx
->addr_ht
= NULL
;
2005 nir_foreach_instr(nblock
, instr
) {
2006 emit_instr(ctx
, instr
);
2012 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
2015 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
2017 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2019 ctx
->block
->condition
=
2020 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2022 emit_cf_list(ctx
, &nif
->then_list
);
2023 emit_cf_list(ctx
, &nif
->else_list
);
2027 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
2029 emit_cf_list(ctx
, &nloop
->body
);
2033 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
2035 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2036 switch (node
->type
) {
2037 case nir_cf_node_block
:
2038 emit_block(ctx
, nir_cf_node_as_block(node
));
2040 case nir_cf_node_if
:
2041 emit_if(ctx
, nir_cf_node_as_if(node
));
2043 case nir_cf_node_loop
:
2044 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2046 case nir_cf_node_function
:
2047 compile_error(ctx
, "TODO\n");
2053 /* emit stream-out code. At this point, the current block is the original
2054 * (nir) end block, and nir ensures that all flow control paths terminate
2055 * into the end block. We re-purpose the original end block to generate
2056 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2057 * block holding stream-out write instructions, followed by the new end
2061 * p0.x = (vtxcnt < maxvtxcnt)
2062 * // succs: blockStreamOut, blockNewEnd
2065 * ... stream-out instructions ...
2066 * // succs: blockNewEnd
2072 emit_stream_out(struct ir3_compile
*ctx
)
2074 struct ir3_shader_variant
*v
= ctx
->so
;
2075 struct ir3
*ir
= ctx
->ir
;
2076 struct pipe_stream_output_info
*strmout
=
2077 &ctx
->so
->shader
->stream_output
;
2078 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2079 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2080 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2082 /* create vtxcnt input in input block at top of shader,
2083 * so that it is seen as live over the entire duration
2086 vtxcnt
= create_input(ctx
->in_block
, 0);
2087 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2089 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2091 /* at this point, we are at the original 'end' block,
2092 * re-purpose this block to stream-out condition, then
2093 * append stream-out block and new-end block
2095 orig_end_block
= ctx
->block
;
2097 stream_out_block
= ir3_block_create(ir
);
2098 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2100 new_end_block
= ir3_block_create(ir
);
2101 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2103 orig_end_block
->successors
[0] = stream_out_block
;
2104 orig_end_block
->successors
[1] = new_end_block
;
2105 stream_out_block
->successors
[0] = new_end_block
;
2107 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2108 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2109 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2110 cond
->cat2
.condition
= IR3_COND_LT
;
2112 /* condition goes on previous block to the conditional,
2113 * since it is used to pick which of the two successor
2116 orig_end_block
->condition
= cond
;
2118 /* switch to stream_out_block to generate the stream-out
2121 ctx
->block
= stream_out_block
;
2123 /* Calculate base addresses based on vtxcnt. Instructions
2124 * generated for bases not used in following loop will be
2125 * stripped out in the backend.
2127 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2128 unsigned stride
= strmout
->stride
[i
];
2129 struct ir3_instruction
*base
, *off
;
2131 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ IR3_TFBOS_OFF
, i
));
2133 /* 24-bit should be enough: */
2134 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2135 create_immed(ctx
->block
, stride
* 4), 0);
2137 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2140 /* Generate the per-output store instructions: */
2141 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2142 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2143 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2144 struct ir3_instruction
*base
, *out
, *stg
;
2146 base
= bases
[strmout
->output
[i
].output_buffer
];
2147 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2149 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2150 create_immed(ctx
->block
, 1), 0);
2151 stg
->cat6
.type
= TYPE_U32
;
2152 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2154 array_insert(ctx
->ir
->keeps
, stg
);
2158 /* and finally switch to the new_end_block: */
2159 ctx
->block
= new_end_block
;
2163 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2165 emit_cf_list(ctx
, &impl
->body
);
2166 emit_block(ctx
, impl
->end_block
);
2168 /* at this point, we should have a single empty block,
2169 * into which we emit the 'end' instruction.
2171 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2173 /* If stream-out (aka transform-feedback) enabled, emit the
2174 * stream-out instructions, followed by a new empty block (into
2175 * which the 'end' instruction lands).
2177 * NOTE: it is done in this order, rather than inserting before
2178 * we emit end_block, because NIR guarantees that all blocks
2179 * flow into end_block, and that end_block has no successors.
2180 * So by re-purposing end_block as the first block of stream-
2181 * out, we guarantee that all exit paths flow into the stream-
2184 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2185 !ctx
->so
->key
.binning_pass
) {
2186 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2187 emit_stream_out(ctx
);
2190 ir3_END(ctx
->block
);
2194 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2196 struct ir3_shader_variant
*so
= ctx
->so
;
2197 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2198 unsigned ncomp
= glsl_get_components(in
->type
);
2199 unsigned n
= in
->data
.driver_location
;
2200 unsigned slot
= in
->data
.location
;
2202 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2203 slot
, array_len
, ncomp
, n
);
2205 so
->inputs
[n
].slot
= slot
;
2206 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2207 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2208 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2210 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2211 for (int i
= 0; i
< ncomp
; i
++) {
2212 struct ir3_instruction
*instr
= NULL
;
2213 unsigned idx
= (n
* 4) + i
;
2215 if (slot
== VARYING_SLOT_POS
) {
2216 so
->inputs
[n
].bary
= false;
2217 so
->frag_coord
= true;
2218 instr
= create_frag_coord(ctx
, i
);
2219 } else if (slot
== VARYING_SLOT_FACE
) {
2220 so
->inputs
[n
].bary
= false;
2221 so
->frag_face
= true;
2222 instr
= create_frag_face(ctx
, i
);
2224 bool use_ldlv
= false;
2226 /* detect the special case for front/back colors where
2227 * we need to do flat vs smooth shading depending on
2230 if (in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) {
2232 case VARYING_SLOT_COL0
:
2233 case VARYING_SLOT_COL1
:
2234 case VARYING_SLOT_BFC0
:
2235 case VARYING_SLOT_BFC1
:
2236 so
->inputs
[n
].rasterflat
= true;
2243 if (ctx
->flat_bypass
) {
2244 if ((so
->inputs
[n
].interpolate
== INTERP_QUALIFIER_FLAT
) ||
2245 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2249 so
->inputs
[n
].bary
= true;
2251 instr
= create_frag_input(ctx
, use_ldlv
);
2254 ctx
->ir
->inputs
[idx
] = instr
;
2256 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2257 for (int i
= 0; i
< ncomp
; i
++) {
2258 unsigned idx
= (n
* 4) + i
;
2259 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2262 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2265 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2266 so
->total_in
+= ncomp
;
2271 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2273 struct ir3_shader_variant
*so
= ctx
->so
;
2274 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2275 unsigned ncomp
= glsl_get_components(out
->type
);
2276 unsigned n
= out
->data
.driver_location
;
2277 unsigned slot
= out
->data
.location
;
2280 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2281 slot
, array_len
, ncomp
, n
);
2283 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2285 case FRAG_RESULT_DEPTH
:
2286 comp
= 2; /* tgsi will write to .z component */
2287 so
->writes_pos
= true;
2289 case FRAG_RESULT_COLOR
:
2293 if (slot
>= FRAG_RESULT_DATA0
)
2295 compile_error(ctx
, "unknown FS output name: %s\n",
2296 gl_frag_result_name(slot
));
2298 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2300 case VARYING_SLOT_POS
:
2301 so
->writes_pos
= true;
2303 case VARYING_SLOT_PSIZ
:
2304 so
->writes_psize
= true;
2306 case VARYING_SLOT_COL0
:
2307 case VARYING_SLOT_COL1
:
2308 case VARYING_SLOT_BFC0
:
2309 case VARYING_SLOT_BFC1
:
2310 case VARYING_SLOT_FOGC
:
2311 case VARYING_SLOT_CLIP_DIST0
:
2312 case VARYING_SLOT_CLIP_DIST1
:
2315 if (slot
>= VARYING_SLOT_VAR0
)
2317 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2319 compile_error(ctx
, "unknown VS output name: %s\n",
2320 gl_varying_slot_name(slot
));
2323 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2326 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2328 so
->outputs
[n
].slot
= slot
;
2329 so
->outputs
[n
].regid
= regid(n
, comp
);
2330 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2332 for (int i
= 0; i
< ncomp
; i
++) {
2333 unsigned idx
= (n
* 4) + i
;
2335 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2340 emit_instructions(struct ir3_compile
*ctx
)
2342 unsigned ninputs
, noutputs
;
2343 nir_function_impl
*fxn
= NULL
;
2345 /* Find the main function: */
2346 nir_foreach_overload(ctx
->s
, overload
) {
2347 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
2348 compile_assert(ctx
, overload
->impl
);
2349 fxn
= overload
->impl
;
2353 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2354 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2356 /* or vtx shaders, we need to leave room for sysvals:
2358 if (ctx
->so
->type
== SHADER_VERTEX
) {
2362 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2364 /* Create inputs in first block: */
2365 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2366 ctx
->in_block
= ctx
->block
;
2367 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2369 if (ctx
->so
->type
== SHADER_VERTEX
) {
2370 ctx
->ir
->ninputs
-= 8;
2373 /* for fragment shader, we have a single input register (usually
2374 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2376 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2377 // TODO maybe a helper for fi since we need it a few places..
2378 struct ir3_instruction
*instr
;
2379 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2380 ir3_reg_create(instr
, 0, 0);
2381 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2382 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2383 ctx
->frag_pos
= instr
;
2387 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2388 setup_input(ctx
, var
);
2391 /* Setup outputs: */
2392 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2393 setup_output(ctx
, var
);
2396 /* Setup variables (which should only be arrays): */
2397 nir_foreach_variable(var
, &ctx
->s
->globals
) {
2398 declare_var(ctx
, var
);
2401 /* And emit the body: */
2403 emit_function(ctx
, fxn
);
2405 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2406 resolve_phis(ctx
, block
);
2410 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2411 * for a fragment shader are just bary.f instructions. The *actual* inputs
2412 * from the hw perspective are the frag_pos and optionally frag_coord and
2416 fixup_frag_inputs(struct ir3_compile
*ctx
)
2418 struct ir3_shader_variant
*so
= ctx
->so
;
2419 struct ir3
*ir
= ctx
->ir
;
2420 struct ir3_instruction
**inputs
;
2421 struct ir3_instruction
*instr
;
2426 n
= 4; /* always have frag_pos */
2427 n
+= COND(so
->frag_face
, 4);
2428 n
+= COND(so
->frag_coord
, 4);
2430 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2432 if (so
->frag_face
) {
2433 /* this ultimately gets assigned to hr0.x so doesn't conflict
2434 * with frag_coord/frag_pos..
2436 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2437 ctx
->frag_face
->regs
[0]->num
= 0;
2439 /* remaining channels not used, but let's avoid confusing
2440 * other parts that expect inputs to come in groups of vec4
2442 inputs
[ir
->ninputs
++] = NULL
;
2443 inputs
[ir
->ninputs
++] = NULL
;
2444 inputs
[ir
->ninputs
++] = NULL
;
2447 /* since we don't know where to set the regid for frag_coord,
2448 * we have to use r0.x for it. But we don't want to *always*
2449 * use r1.x for frag_pos as that could increase the register
2450 * footprint on simple shaders:
2452 if (so
->frag_coord
) {
2453 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2454 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2455 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2456 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2458 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2459 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2460 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2461 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2464 /* we always have frag_pos: */
2465 so
->pos_regid
= regid
;
2468 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2469 instr
->regs
[0]->num
= regid
++;
2470 inputs
[ir
->ninputs
++] = instr
;
2471 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2474 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2475 instr
->regs
[0]->num
= regid
++;
2476 inputs
[ir
->ninputs
++] = instr
;
2477 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2479 ir
->inputs
= inputs
;
2483 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2484 struct ir3_shader_variant
*so
)
2486 struct ir3_compile
*ctx
;
2488 struct ir3_instruction
**inputs
;
2489 unsigned i
, j
, actual_in
, inloc
;
2490 int ret
= 0, max_bary
;
2494 ctx
= compile_init(compiler
, so
, so
->shader
->tokens
);
2496 DBG("INIT failed!");
2501 emit_instructions(ctx
);
2504 DBG("EMIT failed!");
2509 ir
= so
->ir
= ctx
->ir
;
2511 /* keep track of the inputs from TGSI perspective.. */
2512 inputs
= ir
->inputs
;
2514 /* but fixup actual inputs for frag shader: */
2515 if (so
->type
== SHADER_FRAGMENT
)
2516 fixup_frag_inputs(ctx
);
2518 /* at this point, for binning pass, throw away unneeded outputs: */
2519 if (so
->key
.binning_pass
) {
2520 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2521 unsigned slot
= so
->outputs
[i
].slot
;
2523 /* throw away everything but first position/psize */
2524 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2526 so
->outputs
[j
] = so
->outputs
[i
];
2527 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2528 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2529 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2530 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2535 so
->outputs_count
= j
;
2536 ir
->noutputs
= j
* 4;
2539 /* if we want half-precision outputs, mark the output registers
2542 if (so
->key
.half_precision
) {
2543 for (i
= 0; i
< ir
->noutputs
; i
++) {
2544 struct ir3_instruction
*out
= ir
->outputs
[i
];
2547 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2548 /* output could be a fanout (ie. texture fetch output)
2549 * in which case we need to propagate the half-reg flag
2550 * up to the definer so that RA sees it:
2552 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2553 out
= out
->regs
[1]->instr
;
2554 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2557 if (out
->category
== 1) {
2558 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2563 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2564 printf("BEFORE CP:\n");
2570 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2571 printf("BEFORE GROUPING:\n");
2575 /* Group left/right neighbors, inserting mov's where needed to
2582 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2583 printf("AFTER DEPTH:\n");
2587 ret
= ir3_sched(ir
);
2589 DBG("SCHED failed!");
2593 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2594 printf("AFTER SCHED:\n");
2598 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2604 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2605 printf("AFTER RA:\n");
2609 /* fixup input/outputs: */
2610 for (i
= 0; i
< so
->outputs_count
; i
++) {
2611 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2612 /* preserve hack for depth output.. tgsi writes depth to .z,
2613 * but what we give the hw is the scalar register:
2615 if ((so
->type
== SHADER_FRAGMENT
) &&
2616 (so
->outputs
[i
].slot
== FRAG_RESULT_DEPTH
))
2617 so
->outputs
[i
].regid
+= 2;
2620 /* Note that some or all channels of an input may be unused: */
2623 for (i
= 0; i
< so
->inputs_count
; i
++) {
2624 unsigned j
, regid
= ~0, compmask
= 0;
2625 so
->inputs
[i
].ncomp
= 0;
2626 so
->inputs
[i
].inloc
= inloc
+ 8;
2627 for (j
= 0; j
< 4; j
++) {
2628 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2629 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2630 compmask
|= (1 << j
);
2631 regid
= in
->regs
[0]->num
- j
;
2633 so
->inputs
[i
].ncomp
++;
2634 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2636 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2637 in
->regs
[1]->iim_val
= inloc
++;
2641 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
)
2643 so
->inputs
[i
].regid
= regid
;
2644 so
->inputs
[i
].compmask
= compmask
;
2647 /* We need to do legalize after (for frag shader's) the "bary.f"
2648 * offsets (inloc) have been assigned.
2650 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2652 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2653 printf("AFTER LEGALIZE:\n");
2657 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2658 if (so
->type
== SHADER_VERTEX
)
2659 so
->total_in
= actual_in
;
2661 so
->total_in
= max_bary
+ 1;
2666 ir3_destroy(so
->ir
);