1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
41 #include "freedreno_util.h"
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
47 #include "instr-a3xx.h"
51 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
54 const struct tgsi_token
*tokens
;
58 struct ir3_shader_variant
*so
;
60 /* bitmask of which samplers are integer: */
63 struct ir3_block
*block
;
65 /* For fragment shaders, from the hw perspective the only
66 * actual input is r0.xy position register passed to bary.f.
67 * But TGSI doesn't know that, it still declares things as
68 * IN[] registers. So we do all the input tracking normally
69 * and fix things up after compile_instructions()
71 * NOTE that frag_pos is the hardware position (possibly it
72 * is actually an index or tag or some such.. it is *not*
73 * values that can be directly used for gl_FragCoord..)
75 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
77 /* For vertex shaders, keep track of the system values sources */
78 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
83 /* mapping from nir_variable to ir3_array: */
84 struct hash_table
*var_ht
;
87 /* a common pattern for indirect addressing is to request the
88 * same address register multiple times. To avoid generating
89 * duplicate instruction sequences (which our backend does not
90 * try to clean up, since that should be done as the NIR stage)
91 * we cache the address value generated for a given src value:
93 struct hash_table
*addr_ht
;
95 /* for calculating input/output positions/linkages: */
98 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
99 * so we need to use ldlv.u32 to load the varying directly:
103 /* on a3xx, we need to add one to # of array levels:
107 /* for looking up which system value is which */
108 unsigned sysval_semantics
[8];
110 /* list of kill instructions: */
111 struct ir3_instruction
*kill
[16];
112 unsigned int kill_count
;
114 /* set if we encounter something we can't handle yet, so we
115 * can bail cleanly and fallback to TGSI compiler f/e
121 static struct nir_shader
*to_nir(const struct tgsi_token
*tokens
)
123 struct nir_shader_compiler_options options
= {
128 .native_integers
= true,
132 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
134 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
135 debug_printf("----------------------\n");
136 nir_print_shader(s
, stdout
);
137 debug_printf("----------------------\n");
140 nir_opt_global_to_local(s
);
141 nir_convert_to_ssa(s
);
147 nir_lower_vars_to_ssa(s
);
148 nir_lower_alu_to_scalar(s
);
150 progress
|= nir_copy_prop(s
);
151 progress
|= nir_opt_dce(s
);
152 progress
|= nir_opt_cse(s
);
153 progress
|= ir3_nir_lower_if_else(s
);
154 progress
|= nir_opt_algebraic(s
);
155 progress
|= nir_opt_constant_folding(s
);
159 nir_remove_dead_variables(s
);
160 nir_validate_shader(s
);
162 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
163 debug_printf("----------------------\n");
164 nir_print_shader(s
, stdout
);
165 debug_printf("----------------------\n");
171 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
172 static const struct tgsi_token
*
173 lower_tgsi(const struct tgsi_token
*tokens
, struct ir3_shader_variant
*so
)
175 struct tgsi_shader_info info
;
176 struct tgsi_lowering_config lconfig
= {
177 .color_two_side
= so
->key
.color_two_side
,
182 case SHADER_FRAGMENT
:
184 lconfig
.saturate_s
= so
->key
.fsaturate_s
;
185 lconfig
.saturate_t
= so
->key
.fsaturate_t
;
186 lconfig
.saturate_r
= so
->key
.fsaturate_r
;
189 lconfig
.saturate_s
= so
->key
.vsaturate_s
;
190 lconfig
.saturate_t
= so
->key
.vsaturate_t
;
191 lconfig
.saturate_r
= so
->key
.vsaturate_r
;
196 /* hack for standalone compiler which does not have
199 } else if (ir3_shader_gpuid(so
->shader
) >= 400) {
200 /* a4xx seems to have *no* sam.p */
201 lconfig
.lower_TXP
= ~0; /* lower all txp */
203 /* a3xx just needs to avoid sam.p for 3d tex */
204 lconfig
.lower_TXP
= (1 << TGSI_TEXTURE_3D
);
207 return tgsi_transform_lowering(&lconfig
, tokens
, &info
);
210 static struct ir3_compile
*
211 compile_init(struct ir3_shader_variant
*so
,
212 const struct tgsi_token
*tokens
)
214 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
215 const struct tgsi_token
*lowered_tokens
;
218 /* hack for standalone compiler which does not have
221 } else if (ir3_shader_gpuid(so
->shader
) >= 400) {
222 /* need special handling for "flat" */
223 ctx
->flat_bypass
= true;
224 ctx
->levels_add_one
= false;
226 /* no special handling for "flat" */
227 ctx
->flat_bypass
= false;
228 ctx
->levels_add_one
= true;
232 case SHADER_FRAGMENT
:
234 ctx
->integer_s
= so
->key
.finteger_s
;
237 ctx
->integer_s
= so
->key
.vinteger_s
;
244 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
245 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
246 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
247 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
248 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
249 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
251 lowered_tokens
= lower_tgsi(tokens
, so
);
253 lowered_tokens
= tokens
;
254 ctx
->s
= to_nir(lowered_tokens
);
256 if (lowered_tokens
!= tokens
)
257 free((void *)lowered_tokens
);
259 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
261 /* one (vec4) slot for vertex id base: */
262 if (so
->type
== SHADER_VERTEX
)
263 so
->first_immediate
++;
265 /* reserve 4 (vec4) slots for ubo base addresses: */
266 so
->first_immediate
+= 4;
272 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
275 va_start(ap
, format
);
276 _debug_vprintf(format
, ap
);
278 nir_print_shader(ctx
->s
, stdout
);
283 #define compile_assert(ctx, cond) do { \
284 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
288 compile_free(struct ir3_compile
*ctx
)
295 unsigned length
, aid
;
296 struct ir3_instruction
*arr
[];
300 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
302 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
303 struct ir3_array
*arr
= ralloc_size(ctx
, sizeof(*arr
) +
304 (length
* sizeof(arr
->arr
[0])));
305 arr
->length
= length
;
306 arr
->aid
= ++ctx
->num_arrays
;
307 /* Some shaders end up reading array elements without first writing..
308 * so initialize things to prevent null instr ptrs later:
310 for (unsigned i
= 0; i
< length
; i
++)
311 arr
->arr
[i
] = create_immed(ctx
->block
, 0);
312 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
315 static struct ir3_array
*
316 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
318 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
322 /* allocate a n element value array (to be populated by caller) and
325 static struct ir3_instruction
**
326 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
328 struct ir3_instruction
**value
=
329 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
330 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
334 static struct ir3_instruction
**
335 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
338 return __get_dst(ctx
, &dst
->ssa
, n
);
340 return __get_dst(ctx
, dst
->reg
.reg
, n
);
344 static struct ir3_instruction
**
345 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
347 return __get_dst(ctx
, dst
, n
);
350 static struct ir3_instruction
**
351 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
353 struct hash_entry
*entry
;
355 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
357 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
359 compile_assert(ctx
, entry
);
363 static struct ir3_instruction
*
364 create_immed(struct ir3_block
*block
, uint32_t val
)
366 struct ir3_instruction
*mov
;
368 mov
= ir3_instr_create(block
, 1, 0);
369 mov
->cat1
.src_type
= TYPE_U32
;
370 mov
->cat1
.dst_type
= TYPE_U32
;
371 ir3_reg_create(mov
, 0, 0);
372 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
377 static struct ir3_instruction
*
378 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
380 struct ir3_instruction
*instr
, *immed
;
382 /* TODO in at least some cases, the backend could probably be
383 * made clever enough to propagate IR3_REG_HALF..
385 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
386 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
388 immed
= create_immed(block
, 2);
389 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
391 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
392 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
393 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
395 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
396 instr
->regs
[0]->flags
|= IR3_REG_ADDR
| IR3_REG_HALF
;
397 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
402 /* caches addr values to avoid generating multiple cov/shl/mova
403 * sequences for each use of a given NIR level src as address
405 static struct ir3_instruction
*
406 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
408 struct ir3_instruction
*addr
;
409 struct hash_entry
*entry
;
410 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
414 /* TODO do we need to cache per block? */
415 addr
= create_addr(ctx
->block
, src
);
416 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
421 static struct ir3_instruction
*
422 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
424 struct ir3_instruction
*mov
;
426 mov
= ir3_instr_create(ctx
->block
, 1, 0);
427 /* TODO get types right? */
428 mov
->cat1
.src_type
= TYPE_F32
;
429 mov
->cat1
.dst_type
= TYPE_F32
;
430 ir3_reg_create(mov
, 0, 0);
431 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
436 static struct ir3_instruction
*
437 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
438 struct ir3_instruction
*address
)
440 struct ir3_instruction
*mov
;
442 mov
= ir3_instr_create(ctx
->block
, 1, 0);
443 mov
->cat1
.src_type
= TYPE_U32
;
444 mov
->cat1
.dst_type
= TYPE_U32
;
445 ir3_reg_create(mov
, 0, 0);
446 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
447 mov
->address
= address
;
449 array_insert(ctx
->ir
->indirects
, mov
);
454 static struct ir3_instruction
*
455 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
458 struct ir3_instruction
*collect
;
463 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
464 ir3_reg_create(collect
, 0, 0);
465 for (unsigned i
= 0; i
< arrsz
; i
++)
466 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
471 static struct ir3_instruction
*
472 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
473 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
475 struct ir3_block
*block
= ctx
->block
;
476 struct ir3_instruction
*mov
;
477 struct ir3_register
*src
;
479 mov
= ir3_instr_create(block
, 1, 0);
480 mov
->cat1
.src_type
= TYPE_U32
;
481 mov
->cat1
.dst_type
= TYPE_U32
;
482 ir3_reg_create(mov
, 0, 0);
483 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
484 src
->instr
= collect
;
487 mov
->address
= address
;
489 array_insert(ctx
->ir
->indirects
, mov
);
494 static struct ir3_instruction
*
495 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
496 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
497 struct ir3_instruction
*collect
)
499 struct ir3_block
*block
= ctx
->block
;
500 struct ir3_instruction
*mov
;
501 struct ir3_register
*dst
;
503 mov
= ir3_instr_create(block
, 1, 0);
504 mov
->cat1
.src_type
= TYPE_U32
;
505 mov
->cat1
.dst_type
= TYPE_U32
;
506 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
509 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
510 mov
->address
= address
;
511 mov
->fanin
= collect
;
513 array_insert(ctx
->ir
->indirects
, mov
);
518 static struct ir3_instruction
*
519 create_input(struct ir3_block
*block
, struct ir3_instruction
*instr
,
522 struct ir3_instruction
*in
;
524 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
525 in
->inout
.block
= block
;
526 ir3_reg_create(in
, n
, 0);
528 ir3_reg_create(in
, 0, IR3_REG_SSA
)->instr
= instr
;
533 static struct ir3_instruction
*
534 create_frag_input(struct ir3_compile
*ctx
, unsigned n
, bool use_ldlv
)
536 struct ir3_block
*block
= ctx
->block
;
537 struct ir3_instruction
*instr
;
538 struct ir3_instruction
*inloc
= create_immed(block
, n
);
541 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
542 instr
->cat6
.type
= TYPE_U32
;
543 instr
->cat6
.iim_val
= 1;
545 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
546 instr
->regs
[2]->wrmask
= 0x3;
552 static struct ir3_instruction
*
553 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
555 struct ir3_block
*block
= ctx
->block
;
556 struct ir3_instruction
*instr
;
558 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
560 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, NULL
, 0);
565 /* for frag_coord, we get unsigned values.. we need
566 * to subtract (integer) 8 and divide by 16 (right-
567 * shift by 4) then convert to float:
571 * mov.u32f32 dst, tmp
574 instr
= ir3_ADD_S(block
, ctx
->frag_coord
[comp
], 0,
575 create_immed(block
, -8), 0);
576 instr
= ir3_SHR_B(block
, instr
, 0,
577 create_immed(block
, 4), 0);
578 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
584 /* seems that we can use these as-is: */
585 return ctx
->frag_coord
[comp
];
589 static struct ir3_instruction
*
590 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
592 struct ir3_block
*block
= ctx
->block
;
593 struct ir3_instruction
*instr
;
597 compile_assert(ctx
, !ctx
->frag_face
);
599 ctx
->frag_face
= create_input(block
, NULL
, 0);
601 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
602 * positive vs negative float.. and piglit further seems to
603 * expect -1.0 or 1.0:
605 * mul.s tmp, hr0.x, 2
607 * mov.s32f32, dst, tmp
610 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
611 create_immed(block
, 2), 0);
612 instr
= ir3_ADD_S(block
, instr
, 0,
613 create_immed(block
, 1), 0);
614 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
619 return create_immed(block
, fui(0.0));
622 return create_immed(block
, fui(1.0));
626 /* helper for instructions that produce multiple consecutive scalar
627 * outputs which need to have a split/fanout meta instruction inserted
630 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
631 struct ir3_instruction
*src
)
633 struct ir3_instruction
*prev
= NULL
;
634 for (int i
= 0, j
= 0; i
< 4; i
++) {
635 struct ir3_instruction
*split
=
636 ir3_instr_create(block
, -1, OPC_META_FO
);
637 ir3_reg_create(split
, 0, IR3_REG_SSA
);
638 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
642 split
->cp
.left
= prev
;
643 split
->cp
.left_cnt
++;
644 prev
->cp
.right
= split
;
645 prev
->cp
.right_cnt
++;
649 if (src
->regs
[0]->wrmask
& (1 << i
))
655 * Adreno uses uint rather than having dedicated bool type,
656 * which (potentially) requires some conversion, in particular
657 * when using output of an bool instr to int input, or visa
661 * -------+---------+-------+-
665 * To convert from an adreno bool (uint) to nir, use:
667 * absneg.s dst, (neg)src
669 * To convert back in the other direction:
671 * absneg.s dst, (abs)arc
673 * The CP step can clean up the absneg.s that cancel each other
674 * out, and with a slight bit of extra cleverness (to recognize
675 * the instructions which produce either a 0 or 1) can eliminate
676 * the absneg.s's completely when an instruction that wants
677 * 0/1 consumes the result. For example, when a nir 'bcsel'
678 * consumes the result of 'feq'. So we should be able to get by
679 * without a boolean resolve step, and without incuring any
680 * extra penalty in instruction count.
683 /* NIR bool -> native (adreno): */
684 static struct ir3_instruction
*
685 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
687 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
690 /* native (adreno) -> NIR bool: */
691 static struct ir3_instruction
*
692 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
694 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
698 * alu/sfu instructions:
702 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
704 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
705 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
706 struct ir3_block
*b
= ctx
->block
;
708 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
710 /* Vectors are special in that they have non-scalarized writemasks,
711 * and just take the first swizzle channel for each argument in
712 * order into each writemask channel.
714 if ((alu
->op
== nir_op_vec2
) ||
715 (alu
->op
== nir_op_vec3
) ||
716 (alu
->op
== nir_op_vec4
)) {
718 for (int i
= 0; i
< info
->num_inputs
; i
++) {
719 nir_alu_src
*asrc
= &alu
->src
[i
];
721 compile_assert(ctx
, !asrc
->abs
);
722 compile_assert(ctx
, !asrc
->negate
);
724 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
726 src
[i
] = create_immed(ctx
->block
, 0);
727 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
733 /* General case: We can just grab the one used channel per src. */
734 for (int i
= 0; i
< info
->num_inputs
; i
++) {
735 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
736 nir_alu_src
*asrc
= &alu
->src
[i
];
738 compile_assert(ctx
, !asrc
->abs
);
739 compile_assert(ctx
, !asrc
->negate
);
741 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
743 compile_assert(ctx
, src
[i
]);
748 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
751 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
754 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
757 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
760 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
763 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
766 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
767 dst
[0]->cat2
.condition
= IR3_COND_NE
;
768 dst
[0] = ir3_n2b(b
, dst
[0]);
771 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
774 dst
[0] = ir3_b2n(b
, src
[0]);
777 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
778 dst
[0]->cat2
.condition
= IR3_COND_NE
;
779 dst
[0] = ir3_n2b(b
, dst
[0]);
783 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
786 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
789 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
792 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
795 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
798 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
801 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
804 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
807 dst
[0] = ir3_DSX(b
, src
[0], 0);
808 dst
[0]->cat5
.type
= TYPE_F32
;
811 dst
[0] = ir3_DSY(b
, src
[0], 0);
812 dst
[0]->cat5
.type
= TYPE_F32
;
816 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
817 dst
[0]->cat2
.condition
= IR3_COND_LT
;
818 dst
[0] = ir3_n2b(b
, dst
[0]);
821 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
822 dst
[0]->cat2
.condition
= IR3_COND_GE
;
823 dst
[0] = ir3_n2b(b
, dst
[0]);
826 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
827 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
828 dst
[0] = ir3_n2b(b
, dst
[0]);
831 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
832 dst
[0]->cat2
.condition
= IR3_COND_NE
;
833 dst
[0] = ir3_n2b(b
, dst
[0]);
836 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
839 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
842 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
844 case nir_op_fround_even
:
845 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
848 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
852 dst
[0] = ir3_SIN(b
, src
[0], 0);
855 dst
[0] = ir3_COS(b
, src
[0], 0);
858 dst
[0] = ir3_RSQ(b
, src
[0], 0);
861 dst
[0] = ir3_RCP(b
, src
[0], 0);
864 dst
[0] = ir3_LOG2(b
, src
[0], 0);
867 dst
[0] = ir3_EXP2(b
, src
[0], 0);
870 dst
[0] = ir3_SQRT(b
, src
[0], 0);
874 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
877 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
880 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
883 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
886 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
890 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
891 * mull.u tmp0, a, b ; mul low, i.e. al * bl
892 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
893 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
895 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
896 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
897 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
900 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
903 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
906 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
909 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
912 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
915 /* maybe this would be sane to lower in nir.. */
916 struct ir3_instruction
*neg
, *pos
;
918 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
919 neg
->cat2
.condition
= IR3_COND_LT
;
921 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
922 pos
->cat2
.condition
= IR3_COND_GT
;
924 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
929 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
932 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
935 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
938 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
939 dst
[0]->cat2
.condition
= IR3_COND_LT
;
940 dst
[0] = ir3_n2b(b
, dst
[0]);
943 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
944 dst
[0]->cat2
.condition
= IR3_COND_GE
;
945 dst
[0] = ir3_n2b(b
, dst
[0]);
948 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
949 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
950 dst
[0] = ir3_n2b(b
, dst
[0]);
953 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
954 dst
[0]->cat2
.condition
= IR3_COND_NE
;
955 dst
[0] = ir3_n2b(b
, dst
[0]);
958 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
959 dst
[0]->cat2
.condition
= IR3_COND_LT
;
960 dst
[0] = ir3_n2b(b
, dst
[0]);
963 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
964 dst
[0]->cat2
.condition
= IR3_COND_GE
;
965 dst
[0] = ir3_n2b(b
, dst
[0]);
969 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
973 compile_error(ctx
, "Unhandled ALU op: %s\n",
974 nir_op_infos
[alu
->op
].name
);
979 /* handles direct/indirect UBO reads: */
981 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
982 struct ir3_instruction
**dst
)
984 struct ir3_block
*b
= ctx
->block
;
985 struct ir3_instruction
*addr
, *src0
, *src1
;
986 /* UBO addresses are the first driver params: */
987 unsigned ubo
= regid(ctx
->so
->first_driver_param
, 0);
988 unsigned off
= intr
->const_index
[0];
990 /* First src is ubo index, which could either be an immed or not: */
991 src0
= get_src(ctx
, &intr
->src
[0])[0];
992 if (is_same_type_mov(src0
) &&
993 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
994 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
996 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
999 if (intr
->intrinsic
== nir_intrinsic_load_ubo_indirect
) {
1000 /* For load_ubo_indirect, second src is indirect offset: */
1001 src1
= get_src(ctx
, &intr
->src
[1])[0];
1003 /* and add offset to addr: */
1004 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1007 /* if offset is to large to encode in the ldg, split it out: */
1008 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1009 /* split out the minimal amount to improve the odds that
1010 * cp can fit the immediate in the add.s instruction:
1012 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1013 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1017 for (int i
= 0; i
< intr
->num_components
; i
++) {
1018 struct ir3_instruction
*load
=
1019 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1020 load
->cat6
.type
= TYPE_U32
;
1021 load
->cat6
.offset
= off
+ i
* 4; /* byte offset */
1026 /* handles array reads: */
1028 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1029 struct ir3_instruction
**dst
)
1031 nir_deref_var
*dvar
= intr
->variables
[0];
1032 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1033 struct ir3_array
*arr
= get_var(ctx
, dvar
->var
);
1035 compile_assert(ctx
, dvar
->deref
.child
&&
1036 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1038 switch (darr
->deref_array_type
) {
1039 case nir_deref_array_type_direct
:
1040 /* direct access does not require anything special: */
1041 for (int i
= 0; i
< intr
->num_components
; i
++) {
1042 unsigned n
= darr
->base_offset
* 4 + i
;
1043 compile_assert(ctx
, n
< arr
->length
);
1044 dst
[i
] = arr
->arr
[n
];
1047 case nir_deref_array_type_indirect
: {
1048 /* for indirect, we need to collect all the array elements: */
1049 struct ir3_instruction
*collect
=
1050 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1051 struct ir3_instruction
*addr
=
1052 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1053 for (int i
= 0; i
< intr
->num_components
; i
++) {
1054 unsigned n
= darr
->base_offset
* 4 + i
;
1055 compile_assert(ctx
, n
< arr
->length
);
1056 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1061 compile_error(ctx
, "Unhandled load deref type: %u\n",
1062 darr
->deref_array_type
);
1067 /* handles array writes: */
1069 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1071 nir_deref_var
*dvar
= intr
->variables
[0];
1072 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1073 struct ir3_array
*arr
= get_var(ctx
, dvar
->var
);
1074 struct ir3_instruction
**src
;
1076 compile_assert(ctx
, dvar
->deref
.child
&&
1077 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1079 src
= get_src(ctx
, &intr
->src
[0]);
1081 switch (darr
->deref_array_type
) {
1082 case nir_deref_array_type_direct
:
1083 /* direct access does not require anything special: */
1084 for (int i
= 0; i
< intr
->num_components
; i
++) {
1085 unsigned n
= darr
->base_offset
* 4 + i
;
1086 compile_assert(ctx
, n
< arr
->length
);
1087 arr
->arr
[n
] = src
[i
];
1090 case nir_deref_array_type_indirect
: {
1091 /* for indirect, create indirect-store and fan that out: */
1092 struct ir3_instruction
*collect
=
1093 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1094 struct ir3_instruction
*addr
=
1095 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1096 for (int i
= 0; i
< intr
->num_components
; i
++) {
1097 struct ir3_instruction
*store
;
1098 unsigned n
= darr
->base_offset
* 4 + i
;
1099 compile_assert(ctx
, n
< arr
->length
);
1101 store
= create_indirect_store(ctx
, arr
->length
,
1102 n
, src
[i
], addr
, collect
);
1104 store
->fanin
->fi
.aid
= arr
->aid
;
1106 /* TODO: probably split this out to be used for
1107 * store_output_indirect? or move this into
1108 * create_indirect_store()?
1110 for (int j
= i
; j
< arr
->length
; j
+= 4) {
1111 struct ir3_instruction
*split
;
1113 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1115 ir3_reg_create(split
, 0, 0);
1116 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1118 arr
->arr
[j
] = split
;
1124 compile_error(ctx
, "Unhandled store deref type: %u\n",
1125 darr
->deref_array_type
);
1130 static void add_sysval_input(struct ir3_compile
*ctx
, unsigned name
,
1131 struct ir3_instruction
*instr
)
1133 struct ir3_shader_variant
*so
= ctx
->so
;
1134 unsigned r
= regid(so
->inputs_count
, 0);
1135 unsigned n
= so
->inputs_count
++;
1137 so
->inputs
[n
].semantic
= ir3_semantic_name(name
, 0);
1138 so
->inputs
[n
].compmask
= 1;
1139 so
->inputs
[n
].regid
= r
;
1140 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1143 ctx
->block
->inputs
[r
] = instr
;
1147 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1149 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1150 struct ir3_instruction
**dst
, **src
;
1151 struct ir3_block
*b
= ctx
->block
;
1152 unsigned idx
= intr
->const_index
[0];
1154 if (info
->has_dest
) {
1155 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1158 switch (intr
->intrinsic
) {
1159 case nir_intrinsic_load_uniform
:
1160 compile_assert(ctx
, intr
->const_index
[1] == 1);
1161 for (int i
= 0; i
< intr
->num_components
; i
++) {
1162 unsigned n
= idx
* 4 + i
;
1163 dst
[i
] = create_uniform(ctx
, n
);
1166 case nir_intrinsic_load_uniform_indirect
:
1167 compile_assert(ctx
, intr
->const_index
[1] == 1);
1168 src
= get_src(ctx
, &intr
->src
[0]);
1169 for (int i
= 0; i
< intr
->num_components
; i
++) {
1170 unsigned n
= idx
* 4 + i
;
1171 dst
[i
] = create_uniform_indirect(ctx
, n
,
1172 get_addr(ctx
, src
[0]));
1175 case nir_intrinsic_load_ubo
:
1176 case nir_intrinsic_load_ubo_indirect
:
1177 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1179 case nir_intrinsic_load_input
:
1180 compile_assert(ctx
, intr
->const_index
[1] == 1);
1181 for (int i
= 0; i
< intr
->num_components
; i
++) {
1182 unsigned n
= idx
* 4 + i
;
1183 dst
[i
] = b
->inputs
[n
];
1186 case nir_intrinsic_load_input_indirect
:
1187 compile_assert(ctx
, intr
->const_index
[1] == 1);
1188 src
= get_src(ctx
, &intr
->src
[0]);
1189 struct ir3_instruction
*collect
=
1190 create_collect(b
, b
->inputs
, b
->ninputs
);
1191 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1192 for (int i
= 0; i
< intr
->num_components
; i
++) {
1193 unsigned n
= idx
* 4 + i
;
1194 dst
[i
] = create_indirect_load(ctx
, b
->ninputs
, n
, addr
, collect
);
1197 case nir_intrinsic_load_var
:
1198 emit_intrinisic_load_var(ctx
, intr
, dst
);
1200 case nir_intrinsic_store_var
:
1201 emit_intrinisic_store_var(ctx
, intr
);
1203 case nir_intrinsic_store_output
:
1204 compile_assert(ctx
, intr
->const_index
[1] == 1);
1205 src
= get_src(ctx
, &intr
->src
[0]);
1206 for (int i
= 0; i
< intr
->num_components
; i
++) {
1207 unsigned n
= idx
* 4 + i
;
1208 b
->outputs
[n
] = src
[i
];
1211 case nir_intrinsic_load_base_vertex
:
1212 if (!ctx
->basevertex
) {
1213 /* first four vec4 sysval's reserved for UBOs: */
1214 unsigned r
= regid(ctx
->so
->first_driver_param
+ 4, 0);
1215 ctx
->basevertex
= create_uniform(ctx
, r
);
1216 add_sysval_input(ctx
, TGSI_SEMANTIC_BASEVERTEX
,
1219 dst
[0] = ctx
->basevertex
;
1221 case nir_intrinsic_load_vertex_id_zero_base
:
1222 if (!ctx
->vertex_id
) {
1223 ctx
->vertex_id
= create_input(ctx
->block
, NULL
, 0);
1224 add_sysval_input(ctx
, TGSI_SEMANTIC_VERTEXID_NOBASE
,
1227 dst
[0] = ctx
->vertex_id
;
1229 case nir_intrinsic_load_instance_id
:
1230 if (!ctx
->instance_id
) {
1231 ctx
->instance_id
= create_input(ctx
->block
, NULL
, 0);
1232 add_sysval_input(ctx
, TGSI_SEMANTIC_INSTANCEID
,
1235 dst
[0] = ctx
->instance_id
;
1237 case nir_intrinsic_discard_if
:
1238 case nir_intrinsic_discard
: {
1239 struct ir3_instruction
*cond
, *kill
;
1241 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1242 /* conditional discard: */
1243 src
= get_src(ctx
, &intr
->src
[0]);
1244 cond
= ir3_b2n(b
, src
[0]);
1246 /* unconditional discard: */
1247 cond
= create_immed(b
, 1);
1250 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1251 cond
->cat2
.condition
= IR3_COND_NE
;
1253 /* condition always goes in predicate register: */
1254 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1256 kill
= ir3_KILL(b
, cond
, 0);
1258 ctx
->kill
[ctx
->kill_count
++] = kill
;
1259 ctx
->so
->has_kill
= true;
1264 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1265 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1271 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1273 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1274 instr
->def
.num_components
);
1275 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1276 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1280 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1282 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1283 undef
->def
.num_components
);
1284 /* backend doesn't want undefined instructions, so just plug
1287 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1288 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1292 * texture fetch/sample instructions:
1296 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1298 unsigned coords
, flags
= 0;
1300 /* note: would use tex->coord_components.. except txs.. also,
1301 * since array index goes after shadow ref, we don't want to
1304 switch (tex
->sampler_dim
) {
1305 case GLSL_SAMPLER_DIM_1D
:
1306 case GLSL_SAMPLER_DIM_BUF
:
1309 case GLSL_SAMPLER_DIM_2D
:
1310 case GLSL_SAMPLER_DIM_RECT
:
1311 case GLSL_SAMPLER_DIM_EXTERNAL
:
1312 case GLSL_SAMPLER_DIM_MS
:
1315 case GLSL_SAMPLER_DIM_3D
:
1316 case GLSL_SAMPLER_DIM_CUBE
:
1318 flags
|= IR3_INSTR_3D
;
1323 flags
|= IR3_INSTR_S
;
1326 flags
|= IR3_INSTR_A
;
1333 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1335 struct ir3_block
*b
= ctx
->block
;
1336 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1337 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1338 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1339 unsigned i
, coords
, flags
;
1340 unsigned nsrc0
= 0, nsrc1
= 0;
1344 /* TODO: might just be one component for gathers? */
1345 dst
= get_dst(ctx
, &tex
->dest
, 4);
1347 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1348 switch (tex
->src
[i
].src_type
) {
1349 case nir_tex_src_coord
:
1350 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1352 case nir_tex_src_bias
:
1353 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1356 case nir_tex_src_lod
:
1357 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1360 case nir_tex_src_comparitor
: /* shadow comparator */
1361 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1363 case nir_tex_src_projector
:
1364 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1367 case nir_tex_src_offset
:
1368 off
= get_src(ctx
, &tex
->src
[i
].src
);
1371 case nir_tex_src_ddx
:
1372 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1374 case nir_tex_src_ddy
:
1375 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1378 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1379 tex
->src
[i
].src_type
);
1385 * lay out the first argument in the proper order:
1386 * - actual coordinates first
1387 * - shadow reference
1390 * - starting at offset 4, dpdx.xy, dpdy.xy
1392 * bias/lod go into the second arg
1395 tex_info(tex
, &flags
, &coords
);
1397 /* insert tex coords: */
1398 for (i
= 0; i
< coords
; i
++)
1399 src0
[nsrc0
++] = coord
[i
];
1402 /* hw doesn't do 1d, so we treat it as 2d with
1403 * height of 1, and patch up the y coord.
1404 * TODO: y coord should be (int)0 in some cases..
1406 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1410 src0
[nsrc0
++] = compare
;
1413 src0
[nsrc0
++] = coord
[coords
];
1416 src0
[nsrc0
++] = proj
;
1417 flags
|= IR3_INSTR_P
;
1420 /* pad to 4, then ddx/ddy: */
1421 if (tex
->op
== nir_texop_txd
) {
1423 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1424 for (i
= 0; i
< coords
; i
++)
1425 src0
[nsrc0
++] = ddx
[i
];
1427 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1428 for (i
= 0; i
< coords
; i
++)
1429 src0
[nsrc0
++] = ddy
[i
];
1431 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1435 * second argument (if applicable):
1440 if (has_off
| has_lod
| has_bias
) {
1442 for (i
= 0; i
< coords
; i
++)
1443 src1
[nsrc1
++] = off
[i
];
1445 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1446 flags
|= IR3_INSTR_O
;
1449 if (has_lod
| has_bias
)
1450 src1
[nsrc1
++] = lod
;
1454 case nir_texop_tex
: opc
= OPC_SAM
; break;
1455 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1456 case nir_texop_txl
: opc
= OPC_SAML
; break;
1457 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1458 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1459 case nir_texop_txf_ms
:
1463 case nir_texop_query_levels
:
1464 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1468 switch (tex
->dest_type
) {
1469 case nir_type_invalid
:
1470 case nir_type_float
:
1476 case nir_type_unsigned
:
1482 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1483 flags
, tex
->sampler_index
, tex
->sampler_index
,
1484 create_collect(b
, src0
, nsrc0
),
1485 create_collect(b
, src1
, nsrc1
));
1487 split_dest(b
, dst
, sam
);
1491 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1493 struct ir3_block
*b
= ctx
->block
;
1494 struct ir3_instruction
**dst
, *sam
;
1496 dst
= get_dst(ctx
, &tex
->dest
, 1);
1498 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1499 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1501 /* even though there is only one component, since it ends
1502 * up in .z rather than .x, we need a split_dest()
1504 split_dest(b
, dst
, sam
);
1506 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1507 * the value in TEX_CONST_0 is zero-based.
1509 if (ctx
->levels_add_one
)
1510 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1514 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1516 struct ir3_block
*b
= ctx
->block
;
1517 struct ir3_instruction
**dst
, *sam
, *lod
;
1518 unsigned flags
, coords
;
1520 tex_info(tex
, &flags
, &coords
);
1522 dst
= get_dst(ctx
, &tex
->dest
, 4);
1524 compile_assert(ctx
, tex
->num_srcs
== 1);
1525 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1527 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1529 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1530 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1532 split_dest(b
, dst
, sam
);
1534 /* Array size actually ends up in .w rather than .z. This doesn't
1535 * matter for miplevel 0, but for higher mips the value in z is
1536 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1537 * returned, which means that we have to add 1 to it for arrays.
1539 if (tex
->is_array
) {
1540 if (ctx
->levels_add_one
) {
1541 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1543 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1549 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1551 switch (instr
->type
) {
1552 case nir_instr_type_alu
:
1553 emit_alu(ctx
, nir_instr_as_alu(instr
));
1555 case nir_instr_type_intrinsic
:
1556 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1558 case nir_instr_type_load_const
:
1559 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1561 case nir_instr_type_ssa_undef
:
1562 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1564 case nir_instr_type_tex
: {
1565 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1566 /* couple tex instructions get special-cased:
1570 emit_tex_txs(ctx
, tex
);
1572 case nir_texop_query_levels
:
1573 emit_tex_query_levels(ctx
, tex
);
1581 case nir_instr_type_call
:
1582 case nir_instr_type_jump
:
1583 case nir_instr_type_phi
:
1584 case nir_instr_type_parallel_copy
:
1585 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1591 emit_block(struct ir3_compile
*ctx
, nir_block
*block
)
1593 nir_foreach_instr(block
, instr
) {
1594 emit_instr(ctx
, instr
);
1601 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
1603 foreach_list_typed(nir_cf_node
, node
, node
, &impl
->body
) {
1604 switch (node
->type
) {
1605 case nir_cf_node_block
:
1606 emit_block(ctx
, nir_cf_node_as_block(node
));
1608 case nir_cf_node_if
:
1609 case nir_cf_node_loop
:
1610 case nir_cf_node_function
:
1611 compile_error(ctx
, "TODO\n");
1620 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
1622 struct ir3_shader_variant
*so
= ctx
->so
;
1623 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
1624 unsigned ncomp
= glsl_get_components(in
->type
);
1625 /* XXX: map loc slots to semantics */
1626 unsigned semantic_name
= in
->data
.location
;
1627 unsigned semantic_index
= in
->data
.index
;
1628 unsigned n
= in
->data
.driver_location
;
1630 DBG("; in: %u:%u, len=%ux%u, loc=%u\n",
1631 semantic_name
, semantic_index
, array_len
,
1634 so
->inputs
[n
].semantic
=
1635 ir3_semantic_name(semantic_name
, semantic_index
);
1636 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
1637 so
->inputs
[n
].inloc
= ctx
->next_inloc
;
1638 so
->inputs
[n
].interpolate
= 0;
1639 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
1641 /* the fdN_program_emit() code expects tgsi consts here, so map
1642 * things back to tgsi for now:
1644 switch (in
->data
.interpolation
) {
1645 case INTERP_QUALIFIER_FLAT
:
1646 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1648 case INTERP_QUALIFIER_NOPERSPECTIVE
:
1649 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_LINEAR
;
1651 case INTERP_QUALIFIER_SMOOTH
:
1652 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_PERSPECTIVE
;
1656 for (int i
= 0; i
< ncomp
; i
++) {
1657 struct ir3_instruction
*instr
= NULL
;
1658 unsigned idx
= (n
* 4) + i
;
1660 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
1661 if (semantic_name
== TGSI_SEMANTIC_POSITION
) {
1662 so
->inputs
[n
].bary
= false;
1663 so
->frag_coord
= true;
1664 instr
= create_frag_coord(ctx
, i
);
1665 } else if (semantic_name
== TGSI_SEMANTIC_FACE
) {
1666 so
->inputs
[n
].bary
= false;
1667 so
->frag_face
= true;
1668 instr
= create_frag_face(ctx
, i
);
1670 bool use_ldlv
= false;
1672 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1673 * from the semantic name:
1675 if ((in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) &&
1676 ((semantic_name
== TGSI_SEMANTIC_COLOR
) ||
1677 (semantic_name
== TGSI_SEMANTIC_BCOLOR
)))
1678 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_COLOR
;
1680 if (ctx
->flat_bypass
) {
1681 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1682 * from the semantic name:
1684 switch (so
->inputs
[n
].interpolate
) {
1685 case TGSI_INTERPOLATE_COLOR
:
1686 if (!ctx
->so
->key
.rasterflat
)
1689 case TGSI_INTERPOLATE_CONSTANT
:
1695 so
->inputs
[n
].bary
= true;
1697 instr
= create_frag_input(ctx
, idx
, use_ldlv
);
1700 instr
= create_input(ctx
->block
, NULL
, idx
);
1703 ctx
->block
->inputs
[idx
] = instr
;
1706 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
1707 ctx
->next_inloc
+= ncomp
;
1708 so
->total_in
+= ncomp
;
1713 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
1715 struct ir3_shader_variant
*so
= ctx
->so
;
1716 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
1717 unsigned ncomp
= glsl_get_components(out
->type
);
1718 /* XXX: map loc slots to semantics */
1719 unsigned semantic_name
= out
->data
.location
;
1720 unsigned semantic_index
= out
->data
.index
;
1721 unsigned n
= out
->data
.driver_location
;
1724 DBG("; out: %u:%u, len=%ux%u, loc=%u\n",
1725 semantic_name
, semantic_index
, array_len
,
1728 if (ctx
->so
->type
== SHADER_VERTEX
) {
1729 switch (semantic_name
) {
1730 case TGSI_SEMANTIC_POSITION
:
1731 so
->writes_pos
= true;
1733 case TGSI_SEMANTIC_PSIZE
:
1734 so
->writes_psize
= true;
1736 case TGSI_SEMANTIC_COLOR
:
1737 case TGSI_SEMANTIC_BCOLOR
:
1738 case TGSI_SEMANTIC_GENERIC
:
1739 case TGSI_SEMANTIC_FOG
:
1740 case TGSI_SEMANTIC_TEXCOORD
:
1743 compile_error(ctx
, "unknown VS semantic name: %s\n",
1744 tgsi_semantic_names
[semantic_name
]);
1747 switch (semantic_name
) {
1748 case TGSI_SEMANTIC_POSITION
:
1749 comp
= 2; /* tgsi will write to .z component */
1750 so
->writes_pos
= true;
1752 case TGSI_SEMANTIC_COLOR
:
1755 compile_error(ctx
, "unknown FS semantic name: %s\n",
1756 tgsi_semantic_names
[semantic_name
]);
1760 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
1762 so
->outputs
[n
].semantic
=
1763 ir3_semantic_name(semantic_name
, semantic_index
);
1764 so
->outputs
[n
].regid
= regid(n
, comp
);
1765 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
1767 for (int i
= 0; i
< ncomp
; i
++) {
1768 unsigned idx
= (n
* 4) + i
;
1770 ctx
->block
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
1775 emit_instructions(struct ir3_compile
*ctx
)
1777 unsigned ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
1778 unsigned noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
1780 /* we need to allocate big enough outputs array so that
1781 * we can stuff the kill's at the end:
1783 if (ctx
->so
->type
== SHADER_FRAGMENT
)
1784 noutputs
+= ARRAY_SIZE(ctx
->kill
);
1786 ctx
->block
= ir3_block_create(ctx
->ir
, 0, ninputs
, noutputs
);
1788 if (ctx
->so
->type
== SHADER_FRAGMENT
)
1789 ctx
->block
->noutputs
-= ARRAY_SIZE(ctx
->kill
);
1792 /* for fragment shader, we have a single input register (usually
1793 * r0.xy) which is used as the base for bary.f varying fetch instrs:
1795 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
1796 // TODO maybe a helper for fi since we need it a few places..
1797 struct ir3_instruction
*instr
;
1798 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
1799 ir3_reg_create(instr
, 0, 0);
1800 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
1801 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
1802 ctx
->frag_pos
= instr
;
1806 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->inputs
) {
1807 setup_input(ctx
, var
);
1810 /* Setup outputs: */
1811 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->outputs
) {
1812 setup_output(ctx
, var
);
1815 /* Setup variables (which should only be arrays): */
1816 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->globals
) {
1817 declare_var(ctx
, var
);
1820 /* Find the main function and emit the body: */
1821 nir_foreach_overload(ctx
->s
, overload
) {
1822 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
1823 compile_assert(ctx
, overload
->impl
);
1824 emit_function(ctx
, overload
->impl
);
1830 /* from NIR perspective, we actually have inputs. But most of the "inputs"
1831 * for a fragment shader are just bary.f instructions. The *actual* inputs
1832 * from the hw perspective are the frag_pos and optionally frag_coord and
1836 fixup_frag_inputs(struct ir3_compile
*ctx
)
1838 struct ir3_shader_variant
*so
= ctx
->so
;
1839 struct ir3_block
*block
= ctx
->block
;
1840 struct ir3_instruction
**inputs
;
1841 struct ir3_instruction
*instr
;
1846 n
= 4; /* always have frag_pos */
1847 n
+= COND(so
->frag_face
, 4);
1848 n
+= COND(so
->frag_coord
, 4);
1850 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
1852 if (so
->frag_face
) {
1853 /* this ultimately gets assigned to hr0.x so doesn't conflict
1854 * with frag_coord/frag_pos..
1856 inputs
[block
->ninputs
++] = ctx
->frag_face
;
1857 ctx
->frag_face
->regs
[0]->num
= 0;
1859 /* remaining channels not used, but let's avoid confusing
1860 * other parts that expect inputs to come in groups of vec4
1862 inputs
[block
->ninputs
++] = NULL
;
1863 inputs
[block
->ninputs
++] = NULL
;
1864 inputs
[block
->ninputs
++] = NULL
;
1867 /* since we don't know where to set the regid for frag_coord,
1868 * we have to use r0.x for it. But we don't want to *always*
1869 * use r1.x for frag_pos as that could increase the register
1870 * footprint on simple shaders:
1872 if (so
->frag_coord
) {
1873 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
1874 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
1875 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
1876 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
1878 inputs
[block
->ninputs
++] = ctx
->frag_coord
[0];
1879 inputs
[block
->ninputs
++] = ctx
->frag_coord
[1];
1880 inputs
[block
->ninputs
++] = ctx
->frag_coord
[2];
1881 inputs
[block
->ninputs
++] = ctx
->frag_coord
[3];
1884 /* we always have frag_pos: */
1885 so
->pos_regid
= regid
;
1888 instr
= create_input(block
, NULL
, block
->ninputs
);
1889 instr
->regs
[0]->num
= regid
++;
1890 inputs
[block
->ninputs
++] = instr
;
1891 ctx
->frag_pos
->regs
[1]->instr
= instr
;
1894 instr
= create_input(block
, NULL
, block
->ninputs
);
1895 instr
->regs
[0]->num
= regid
++;
1896 inputs
[block
->ninputs
++] = instr
;
1897 ctx
->frag_pos
->regs
[2]->instr
= instr
;
1899 block
->inputs
= inputs
;
1903 compile_dump(struct ir3_compile
*ctx
)
1905 const char *name
= (ctx
->so
->type
== SHADER_VERTEX
) ? "vert" : "frag";
1906 static unsigned n
= 0;
1909 snprintf(fname
, sizeof(fname
), "%s-%04u.dot", name
, n
++);
1910 f
= fopen(fname
, "w");
1913 ir3_block_depth(ctx
->block
);
1914 ir3_dump(ctx
->ir
, name
, ctx
->block
, f
);
1919 ir3_compile_shader_nir(struct ir3_shader_variant
*so
,
1920 const struct tgsi_token
*tokens
, struct ir3_shader_key key
)
1922 struct ir3_compile
*ctx
;
1923 struct ir3_block
*block
;
1924 struct ir3_instruction
**inputs
;
1925 unsigned i
, j
, actual_in
;
1926 int ret
= 0, max_bary
;
1930 so
->ir
= ir3_create();
1934 ctx
= compile_init(so
, tokens
);
1936 DBG("INIT failed!");
1941 emit_instructions(ctx
);
1944 DBG("EMIT failed!");
1950 so
->ir
->block
= block
;
1952 /* keep track of the inputs from TGSI perspective.. */
1953 inputs
= block
->inputs
;
1955 /* but fixup actual inputs for frag shader: */
1956 if (so
->type
== SHADER_FRAGMENT
)
1957 fixup_frag_inputs(ctx
);
1959 /* at this point, for binning pass, throw away unneeded outputs: */
1960 if (key
.binning_pass
) {
1961 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
1962 unsigned name
= sem2name(so
->outputs
[i
].semantic
);
1963 unsigned idx
= sem2idx(so
->outputs
[i
].semantic
);
1965 /* throw away everything but first position/psize */
1966 if ((idx
== 0) && ((name
== TGSI_SEMANTIC_POSITION
) ||
1967 (name
== TGSI_SEMANTIC_PSIZE
))) {
1969 so
->outputs
[j
] = so
->outputs
[i
];
1970 block
->outputs
[(j
*4)+0] = block
->outputs
[(i
*4)+0];
1971 block
->outputs
[(j
*4)+1] = block
->outputs
[(i
*4)+1];
1972 block
->outputs
[(j
*4)+2] = block
->outputs
[(i
*4)+2];
1973 block
->outputs
[(j
*4)+3] = block
->outputs
[(i
*4)+3];
1978 so
->outputs_count
= j
;
1979 block
->noutputs
= j
* 4;
1982 /* if we want half-precision outputs, mark the output registers
1985 if (key
.half_precision
) {
1986 for (i
= 0; i
< block
->noutputs
; i
++) {
1987 if (!block
->outputs
[i
])
1989 block
->outputs
[i
]->regs
[0]->flags
|= IR3_REG_HALF
;
1993 /* at this point, we want the kill's in the outputs array too,
1994 * so that they get scheduled (since they have no dst).. we've
1995 * already ensured that the array is big enough in push_block():
1997 if (so
->type
== SHADER_FRAGMENT
) {
1998 for (i
= 0; i
< ctx
->kill_count
; i
++)
1999 block
->outputs
[block
->noutputs
++] = ctx
->kill
[i
];
2002 if (fd_mesa_debug
& FD_DBG_OPTDUMP
)
2005 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2006 printf("BEFORE CP:\n");
2007 ir3_dump_instr_list(block
->head
);
2010 ir3_block_depth(block
);
2012 ir3_block_cp(block
);
2014 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2015 printf("BEFORE GROUPING:\n");
2016 ir3_dump_instr_list(block
->head
);
2019 /* Group left/right neighbors, inserting mov's where needed to
2022 ir3_block_group(block
);
2024 if (fd_mesa_debug
& FD_DBG_OPTDUMP
)
2027 ir3_block_depth(block
);
2029 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2030 printf("AFTER DEPTH:\n");
2031 ir3_dump_instr_list(block
->head
);
2034 ret
= ir3_block_sched(block
);
2036 DBG("SCHED failed!");
2040 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2041 printf("AFTER SCHED:\n");
2042 ir3_dump_instr_list(block
->head
);
2045 ret
= ir3_block_ra(block
, so
->type
, so
->frag_coord
, so
->frag_face
);
2051 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2052 printf("AFTER RA:\n");
2053 ir3_dump_instr_list(block
->head
);
2056 ir3_block_legalize(block
, &so
->has_samp
, &max_bary
);
2058 /* fixup input/outputs: */
2059 for (i
= 0; i
< so
->outputs_count
; i
++) {
2060 so
->outputs
[i
].regid
= block
->outputs
[i
*4]->regs
[0]->num
;
2061 /* preserve hack for depth output.. tgsi writes depth to .z,
2062 * but what we give the hw is the scalar register:
2064 if ((so
->type
== SHADER_FRAGMENT
) &&
2065 (sem2name(so
->outputs
[i
].semantic
) == TGSI_SEMANTIC_POSITION
))
2066 so
->outputs
[i
].regid
+= 2;
2069 /* Note that some or all channels of an input may be unused: */
2071 for (i
= 0; i
< so
->inputs_count
; i
++) {
2072 unsigned j
, regid
= ~0, compmask
= 0;
2073 so
->inputs
[i
].ncomp
= 0;
2074 for (j
= 0; j
< 4; j
++) {
2075 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2077 compmask
|= (1 << j
);
2078 regid
= in
->regs
[0]->num
- j
;
2080 so
->inputs
[i
].ncomp
++;
2083 so
->inputs
[i
].regid
= regid
;
2084 so
->inputs
[i
].compmask
= compmask
;
2087 /* fragment shader always gets full vec4's even if it doesn't
2088 * fetch all components, but vertex shader we need to update
2089 * with the actual number of components fetch, otherwise thing
2090 * will hang due to mismaptch between VFD_DECODE's and
2093 if (so
->type
== SHADER_VERTEX
)
2094 so
->total_in
= actual_in
;
2096 so
->total_in
= align(max_bary
+ 1, 4);
2100 ir3_destroy(so
->ir
);