1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
49 const struct tgsi_token
*tokens
;
53 struct ir3_shader_variant
*so
;
55 struct ir3_block
*block
; /* the current block */
56 struct ir3_block
*in_block
; /* block created for shader inputs */
58 nir_function_impl
*impl
;
60 /* For fragment shaders, from the hw perspective the only
61 * actual input is r0.xy position register passed to bary.f.
62 * But TGSI doesn't know that, it still declares things as
63 * IN[] registers. So we do all the input tracking normally
64 * and fix things up after compile_instructions()
66 * NOTE that frag_pos is the hardware position (possibly it
67 * is actually an index or tag or some such.. it is *not*
68 * values that can be directly used for gl_FragCoord..)
70 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
72 /* For vertex shaders, keep track of the system values sources */
73 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
75 /* mapping from nir_register to defining instruction: */
76 struct hash_table
*def_ht
;
78 /* mapping from nir_variable to ir3_array: */
79 struct hash_table
*var_ht
;
82 /* a common pattern for indirect addressing is to request the
83 * same address register multiple times. To avoid generating
84 * duplicate instruction sequences (which our backend does not
85 * try to clean up, since that should be done as the NIR stage)
86 * we cache the address value generated for a given src value:
88 struct hash_table
*addr_ht
;
90 /* maps nir_block to ir3_block, mostly for the purposes of
91 * figuring out the blocks successors
93 struct hash_table
*block_ht
;
95 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
96 * so we need to use ldlv.u32 to load the varying directly:
100 /* on a3xx, we need to add one to # of array levels:
104 /* on a3xx, we need to scale up integer coords for isaml based
107 bool unminify_coords
;
109 /* for looking up which system value is which */
110 unsigned sysval_semantics
[8];
112 /* set if we encounter something we can't handle yet, so we
113 * can bail cleanly and fallback to TGSI compiler f/e
119 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
120 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
123 static struct ir3_compile
*
124 compile_init(struct ir3_compiler
*compiler
,
125 struct ir3_shader_variant
*so
)
127 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
129 if (compiler
->gpu_id
>= 400) {
130 /* need special handling for "flat" */
131 ctx
->flat_bypass
= true;
132 ctx
->levels_add_one
= false;
133 ctx
->unminify_coords
= false;
135 /* no special handling for "flat" */
136 ctx
->flat_bypass
= false;
137 ctx
->levels_add_one
= true;
138 ctx
->unminify_coords
= true;
141 ctx
->compiler
= compiler
;
144 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
145 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
146 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
147 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
148 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
149 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
151 /* TODO: maybe generate some sort of bitmask of what key
152 * lowers vs what shader has (ie. no need to lower
153 * texture clamp lowering if no texture sample instrs)..
154 * although should be done further up the stack to avoid
155 * creating duplicate variants..
158 if (ir3_key_lowers_nir(&so
->key
)) {
159 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
160 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
162 /* fast-path for shader key that lowers nothing in NIR: */
163 ctx
->s
= so
->shader
->nir
;
166 if (fd_mesa_debug
& FD_DBG_DISASM
) {
167 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
168 so
->shader
->id
, so
->id
, so
->type
,
169 so
->key
.binning_pass
, so
->key
.color_two_side
,
170 so
->key
.half_precision
);
171 nir_print_shader(ctx
->s
, stdout
);
174 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
176 /* Layout of constant registers:
178 * num_uniform * vec4 - user consts
179 * 4 * vec4 - UBO addresses
180 * if (vertex shader) {
181 * N * vec4 - driver params (IR3_DP_*)
182 * 1 * vec4 - stream-out addresses
185 * TODO this could be made more dynamic, to at least skip sections
186 * that we don't need..
189 /* reserve 4 (vec4) slots for ubo base addresses: */
190 so
->first_immediate
+= 4;
192 if (so
->type
== SHADER_VERTEX
) {
193 /* driver params (see ir3_driver_param): */
194 so
->first_immediate
+= IR3_DP_COUNT
/4; /* convert to vec4 */
195 /* one (vec4) slot for stream-output base addresses: */
196 so
->first_immediate
++;
203 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
206 va_start(ap
, format
);
207 _debug_vprintf(format
, ap
);
209 nir_print_shader(ctx
->s
, stdout
);
214 #define compile_assert(ctx, cond) do { \
215 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
219 compile_free(struct ir3_compile
*ctx
)
224 /* global per-array information: */
226 unsigned length
, aid
;
229 /* per-block array state: */
230 struct ir3_array_value
{
231 /* TODO drop length/aid, and just have ptr back to ir3_array */
232 unsigned length
, aid
;
233 /* initial array element values are phi's, other than for the
234 * entry block. The phi src's get added later in a resolve step
235 * after we have visited all the blocks, to account for back
238 struct ir3_instruction
**phis
;
239 /* current array element values (as block is processed). When
240 * the array phi's are resolved, it will contain the array state
241 * at exit of block, so successor blocks can use it to add their
244 struct ir3_instruction
*arr
[];
247 /* track array assignments per basic block. When an array is read
248 * outside of the same basic block, we can use NIR's dominance-frontier
249 * information to figure out where phi nodes are needed.
251 struct ir3_nir_block_data
{
253 /* indexed by array-id (aid): */
254 struct ir3_array_value
*arrs
[];
257 static struct ir3_nir_block_data
*
258 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
261 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
262 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
269 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
271 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
272 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
273 arr
->length
= length
;
274 arr
->aid
= ++ctx
->num_arrays
;
275 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
279 nir_block_pred(nir_block
*block
)
281 assert(block
->predecessors
->entries
< 2);
282 if (block
->predecessors
->entries
== 0)
284 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
287 static struct ir3_array_value
*
288 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
290 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
291 struct ir3_block
*block
= ctx
->block
;
292 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
293 struct ir3_array
*arr
= entry
->data
;
295 if (!bd
->arrs
[arr
->aid
]) {
296 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
297 (arr
->length
* sizeof(av
->arr
[0])));
298 struct ir3_array_value
*defn
= NULL
;
299 nir_block
*pred_block
;
301 av
->length
= arr
->length
;
304 /* For loops, we have to consider that we have not visited some
305 * of the blocks who should feed into the phi (ie. back-edges in
306 * the cfg).. for example:
309 * block { load_var; ... }
310 * if then block {} else block {}
311 * block { store_var; ... }
312 * if then block {} else block {}
316 * We can skip the phi if we can chase the block predecessors
317 * until finding the block previously defining the array without
318 * crossing a block that has more than one predecessor.
320 * Otherwise create phi's and resolve them as a post-pass after
321 * all the blocks have been visited (to handle back-edges).
324 for (pred_block
= block
->nblock
;
325 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
326 pred_block
= nir_block_pred(pred_block
)) {
327 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
328 struct ir3_nir_block_data
*pbd
= pblock
->data
;
331 defn
= pbd
->arrs
[arr
->aid
];
335 /* only one possible definer: */
336 for (unsigned i
= 0; i
< arr
->length
; i
++)
337 av
->arr
[i
] = defn
->arr
[i
];
338 } else if (pred_block
) {
339 /* not the first block, and multiple potential definers: */
340 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
342 for (unsigned i
= 0; i
< arr
->length
; i
++) {
343 struct ir3_instruction
*phi
;
345 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
346 1 + ctx
->impl
->num_blocks
);
347 ir3_reg_create(phi
, 0, 0); /* dst */
349 /* phi's should go at head of block: */
350 list_delinit(&phi
->node
);
351 list_add(&phi
->node
, &block
->instr_list
);
353 av
->phis
[i
] = av
->arr
[i
] = phi
;
356 /* Some shaders end up reading array elements without
357 * first writing.. so initialize things to prevent null
360 for (unsigned i
= 0; i
< arr
->length
; i
++)
361 av
->arr
[i
] = create_immed(block
, 0);
364 bd
->arrs
[arr
->aid
] = av
;
367 return bd
->arrs
[arr
->aid
];
371 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
372 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
374 struct ir3_block
*block
;
375 struct ir3_nir_block_data
*bd
;
377 if (BITSET_TEST(visited
, nblock
->index
))
380 BITSET_SET(visited
, nblock
->index
);
382 block
= get_block(ctx
, nblock
);
385 if (bd
&& bd
->arrs
[av
->aid
]) {
386 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
387 for (unsigned i
= 0; i
< av
->length
; i
++) {
388 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
392 /* didn't find defn, recurse predecessors: */
393 struct set_entry
*entry
;
394 set_foreach(nblock
->predecessors
, entry
) {
395 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
401 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
403 struct ir3_nir_block_data
*bd
= block
->data
;
404 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
409 /* TODO use nir dom_frontier to help us with this? */
411 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
412 struct ir3_array_value
*av
= bd
->arrs
[i
];
413 BITSET_WORD visited
[bitset_words
];
414 struct set_entry
*entry
;
416 if (!(av
&& av
->phis
))
419 memset(visited
, 0, sizeof(visited
));
420 set_foreach(block
->nblock
->predecessors
, entry
) {
421 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
426 /* allocate a n element value array (to be populated by caller) and
429 static struct ir3_instruction
**
430 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
432 struct ir3_instruction
**value
=
433 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
434 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
438 static struct ir3_instruction
**
439 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
442 return __get_dst(ctx
, &dst
->ssa
, n
);
444 return __get_dst(ctx
, dst
->reg
.reg
, n
);
448 static struct ir3_instruction
**
449 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
451 return __get_dst(ctx
, dst
, n
);
454 static struct ir3_instruction
**
455 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
457 struct hash_entry
*entry
;
459 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
461 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
463 compile_assert(ctx
, entry
);
467 static struct ir3_instruction
*
468 create_immed(struct ir3_block
*block
, uint32_t val
)
470 struct ir3_instruction
*mov
;
472 mov
= ir3_instr_create(block
, 1, 0);
473 mov
->cat1
.src_type
= TYPE_U32
;
474 mov
->cat1
.dst_type
= TYPE_U32
;
475 ir3_reg_create(mov
, 0, 0);
476 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
481 static struct ir3_instruction
*
482 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
484 struct ir3_instruction
*instr
, *immed
;
486 /* TODO in at least some cases, the backend could probably be
487 * made clever enough to propagate IR3_REG_HALF..
489 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
490 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
492 immed
= create_immed(block
, 2);
493 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
495 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
496 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
497 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
499 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
500 instr
->regs
[0]->num
= regid(REG_A0
, 0);
501 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
502 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
507 /* caches addr values to avoid generating multiple cov/shl/mova
508 * sequences for each use of a given NIR level src as address
510 static struct ir3_instruction
*
511 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
513 struct ir3_instruction
*addr
;
516 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
517 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
519 struct hash_entry
*entry
;
520 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
525 addr
= create_addr(ctx
->block
, src
);
526 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
531 static struct ir3_instruction
*
532 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
534 struct ir3_block
*b
= ctx
->block
;
535 struct ir3_instruction
*cond
;
537 /* NOTE: only cmps.*.* can write p0.x: */
538 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
539 cond
->cat2
.condition
= IR3_COND_NE
;
541 /* condition always goes in predicate register: */
542 cond
->regs
[0]->num
= regid(REG_P0
, 0);
547 static struct ir3_instruction
*
548 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
550 struct ir3_instruction
*mov
;
552 mov
= ir3_instr_create(ctx
->block
, 1, 0);
553 /* TODO get types right? */
554 mov
->cat1
.src_type
= TYPE_F32
;
555 mov
->cat1
.dst_type
= TYPE_F32
;
556 ir3_reg_create(mov
, 0, 0);
557 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
562 static struct ir3_instruction
*
563 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
564 struct ir3_instruction
*address
)
566 struct ir3_instruction
*mov
;
568 mov
= ir3_instr_create(ctx
->block
, 1, 0);
569 mov
->cat1
.src_type
= TYPE_U32
;
570 mov
->cat1
.dst_type
= TYPE_U32
;
571 ir3_reg_create(mov
, 0, 0);
572 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
574 ir3_instr_set_address(mov
, address
);
579 static struct ir3_instruction
*
580 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
583 struct ir3_instruction
*collect
;
588 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
589 ir3_reg_create(collect
, 0, 0); /* dst */
590 for (unsigned i
= 0; i
< arrsz
; i
++)
591 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
596 static struct ir3_instruction
*
597 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
598 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
600 struct ir3_block
*block
= ctx
->block
;
601 struct ir3_instruction
*mov
;
602 struct ir3_register
*src
;
604 mov
= ir3_instr_create(block
, 1, 0);
605 mov
->cat1
.src_type
= TYPE_U32
;
606 mov
->cat1
.dst_type
= TYPE_U32
;
607 ir3_reg_create(mov
, 0, 0);
608 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
609 src
->instr
= collect
;
613 ir3_instr_set_address(mov
, address
);
618 static struct ir3_instruction
*
619 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
620 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
621 struct ir3_instruction
*collect
)
623 struct ir3_block
*block
= ctx
->block
;
624 struct ir3_instruction
*mov
;
625 struct ir3_register
*dst
;
627 mov
= ir3_instr_create(block
, 1, 0);
628 mov
->cat1
.src_type
= TYPE_U32
;
629 mov
->cat1
.dst_type
= TYPE_U32
;
630 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
633 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
634 mov
->fanin
= collect
;
636 ir3_instr_set_address(mov
, address
);
641 static struct ir3_instruction
*
642 create_input(struct ir3_block
*block
, unsigned n
)
644 struct ir3_instruction
*in
;
646 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
647 in
->inout
.block
= block
;
648 ir3_reg_create(in
, n
, 0);
653 static struct ir3_instruction
*
654 create_frag_input(struct ir3_compile
*ctx
, bool use_ldlv
)
656 struct ir3_block
*block
= ctx
->block
;
657 struct ir3_instruction
*instr
;
658 /* actual inloc is assigned and fixed up later: */
659 struct ir3_instruction
*inloc
= create_immed(block
, 0);
662 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
663 instr
->cat6
.type
= TYPE_U32
;
664 instr
->cat6
.iim_val
= 1;
666 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
667 instr
->regs
[2]->wrmask
= 0x3;
673 static struct ir3_instruction
*
674 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
676 struct ir3_block
*block
= ctx
->block
;
677 struct ir3_instruction
*instr
;
679 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
681 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
686 /* for frag_coord, we get unsigned values.. we need
687 * to subtract (integer) 8 and divide by 16 (right-
688 * shift by 4) then convert to float:
692 * mov.u32f32 dst, tmp
695 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
696 create_immed(block
, 8), 0);
697 instr
= ir3_SHR_B(block
, instr
, 0,
698 create_immed(block
, 4), 0);
699 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
705 /* seems that we can use these as-is: */
706 return ctx
->frag_coord
[comp
];
710 static struct ir3_instruction
*
711 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
713 struct ir3_block
*block
= ctx
->block
;
714 struct ir3_instruction
*instr
;
718 compile_assert(ctx
, !ctx
->frag_face
);
720 ctx
->frag_face
= create_input(block
, 0);
721 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
723 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
724 * positive vs negative float.. and piglit further seems to
725 * expect -1.0 or 1.0:
727 * mul.s tmp, hr0.x, 2
729 * mov.s32f32, dst, tmp
732 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
733 create_immed(block
, 2), 0);
734 instr
= ir3_ADD_S(block
, instr
, 0,
735 create_immed(block
, 1), 0);
736 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
741 return create_immed(block
, fui(0.0));
744 return create_immed(block
, fui(1.0));
748 static struct ir3_instruction
*
749 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
751 /* first four vec4 sysval's reserved for UBOs: */
752 /* NOTE: dp is in scalar, but there can be >4 dp components: */
753 unsigned n
= ctx
->so
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
754 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
755 return create_uniform(ctx
, r
);
758 /* helper for instructions that produce multiple consecutive scalar
759 * outputs which need to have a split/fanout meta instruction inserted
762 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
763 struct ir3_instruction
*src
, unsigned n
)
765 struct ir3_instruction
*prev
= NULL
;
766 for (int i
= 0, j
= 0; i
< n
; i
++) {
767 struct ir3_instruction
*split
=
768 ir3_instr_create(block
, -1, OPC_META_FO
);
769 ir3_reg_create(split
, 0, IR3_REG_SSA
);
770 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
774 split
->cp
.left
= prev
;
775 split
->cp
.left_cnt
++;
776 prev
->cp
.right
= split
;
777 prev
->cp
.right_cnt
++;
781 if (src
->regs
[0]->wrmask
& (1 << i
))
787 * Adreno uses uint rather than having dedicated bool type,
788 * which (potentially) requires some conversion, in particular
789 * when using output of an bool instr to int input, or visa
793 * -------+---------+-------+-
797 * To convert from an adreno bool (uint) to nir, use:
799 * absneg.s dst, (neg)src
801 * To convert back in the other direction:
803 * absneg.s dst, (abs)arc
805 * The CP step can clean up the absneg.s that cancel each other
806 * out, and with a slight bit of extra cleverness (to recognize
807 * the instructions which produce either a 0 or 1) can eliminate
808 * the absneg.s's completely when an instruction that wants
809 * 0/1 consumes the result. For example, when a nir 'bcsel'
810 * consumes the result of 'feq'. So we should be able to get by
811 * without a boolean resolve step, and without incuring any
812 * extra penalty in instruction count.
815 /* NIR bool -> native (adreno): */
816 static struct ir3_instruction
*
817 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
819 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
822 /* native (adreno) -> NIR bool: */
823 static struct ir3_instruction
*
824 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
826 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
830 * alu/sfu instructions:
834 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
836 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
837 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
838 struct ir3_block
*b
= ctx
->block
;
840 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
842 /* Vectors are special in that they have non-scalarized writemasks,
843 * and just take the first swizzle channel for each argument in
844 * order into each writemask channel.
846 if ((alu
->op
== nir_op_vec2
) ||
847 (alu
->op
== nir_op_vec3
) ||
848 (alu
->op
== nir_op_vec4
)) {
850 for (int i
= 0; i
< info
->num_inputs
; i
++) {
851 nir_alu_src
*asrc
= &alu
->src
[i
];
853 compile_assert(ctx
, !asrc
->abs
);
854 compile_assert(ctx
, !asrc
->negate
);
856 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
858 src
[i
] = create_immed(ctx
->block
, 0);
859 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
865 /* General case: We can just grab the one used channel per src. */
866 for (int i
= 0; i
< info
->num_inputs
; i
++) {
867 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
868 nir_alu_src
*asrc
= &alu
->src
[i
];
870 compile_assert(ctx
, !asrc
->abs
);
871 compile_assert(ctx
, !asrc
->negate
);
873 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
875 compile_assert(ctx
, src
[i
]);
880 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
883 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
886 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
889 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
892 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
895 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
898 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
899 dst
[0]->cat2
.condition
= IR3_COND_NE
;
900 dst
[0] = ir3_n2b(b
, dst
[0]);
903 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
906 dst
[0] = ir3_b2n(b
, src
[0]);
909 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
910 dst
[0]->cat2
.condition
= IR3_COND_NE
;
911 dst
[0] = ir3_n2b(b
, dst
[0]);
915 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
918 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
921 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
924 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
927 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
930 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
933 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
936 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
939 dst
[0] = ir3_DSX(b
, src
[0], 0);
940 dst
[0]->cat5
.type
= TYPE_F32
;
943 dst
[0] = ir3_DSY(b
, src
[0], 0);
944 dst
[0]->cat5
.type
= TYPE_F32
;
948 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
949 dst
[0]->cat2
.condition
= IR3_COND_LT
;
950 dst
[0] = ir3_n2b(b
, dst
[0]);
953 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
954 dst
[0]->cat2
.condition
= IR3_COND_GE
;
955 dst
[0] = ir3_n2b(b
, dst
[0]);
958 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
959 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
960 dst
[0] = ir3_n2b(b
, dst
[0]);
963 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
964 dst
[0]->cat2
.condition
= IR3_COND_NE
;
965 dst
[0] = ir3_n2b(b
, dst
[0]);
968 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
971 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
974 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
976 case nir_op_fround_even
:
977 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
980 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
984 dst
[0] = ir3_SIN(b
, src
[0], 0);
987 dst
[0] = ir3_COS(b
, src
[0], 0);
990 dst
[0] = ir3_RSQ(b
, src
[0], 0);
993 dst
[0] = ir3_RCP(b
, src
[0], 0);
996 dst
[0] = ir3_LOG2(b
, src
[0], 0);
999 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1002 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1006 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1009 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1012 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1015 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1018 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1021 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1024 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1028 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1029 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1030 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1031 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1033 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1034 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1035 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1038 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1041 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1044 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1047 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1050 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1052 case nir_op_isign
: {
1053 /* maybe this would be sane to lower in nir.. */
1054 struct ir3_instruction
*neg
, *pos
;
1056 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1057 neg
->cat2
.condition
= IR3_COND_LT
;
1059 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1060 pos
->cat2
.condition
= IR3_COND_GT
;
1062 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1067 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1070 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1073 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1076 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1077 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1078 dst
[0] = ir3_n2b(b
, dst
[0]);
1081 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1082 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1083 dst
[0] = ir3_n2b(b
, dst
[0]);
1086 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1087 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1088 dst
[0] = ir3_n2b(b
, dst
[0]);
1091 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1092 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1093 dst
[0] = ir3_n2b(b
, dst
[0]);
1096 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1097 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1098 dst
[0] = ir3_n2b(b
, dst
[0]);
1101 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1102 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1103 dst
[0] = ir3_n2b(b
, dst
[0]);
1107 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1110 case nir_op_bit_count
:
1111 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1113 case nir_op_ifind_msb
: {
1114 struct ir3_instruction
*cmp
;
1115 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1116 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1117 cmp
->cat2
.condition
= IR3_COND_GE
;
1118 dst
[0] = ir3_SEL_B32(b
,
1119 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1123 case nir_op_ufind_msb
:
1124 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1125 dst
[0] = ir3_SEL_B32(b
,
1126 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1127 src
[0], 0, dst
[0], 0);
1129 case nir_op_find_lsb
:
1130 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1131 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1133 case nir_op_bitfield_reverse
:
1134 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1138 compile_error(ctx
, "Unhandled ALU op: %s\n",
1139 nir_op_infos
[alu
->op
].name
);
1144 /* handles direct/indirect UBO reads: */
1146 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1147 struct ir3_instruction
**dst
)
1149 struct ir3_block
*b
= ctx
->block
;
1150 struct ir3_instruction
*addr
, *src0
, *src1
;
1151 nir_const_value
*const_offset
;
1152 /* UBO addresses are the first driver params: */
1153 unsigned ubo
= regid(ctx
->so
->first_driver_param
+ IR3_UBOS_OFF
, 0);
1154 unsigned off
= intr
->const_index
[0];
1156 /* First src is ubo index, which could either be an immed or not: */
1157 src0
= get_src(ctx
, &intr
->src
[0])[0];
1158 if (is_same_type_mov(src0
) &&
1159 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1160 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1162 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1165 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1167 off
+= const_offset
->u
[0];
1169 /* For load_ubo_indirect, second src is indirect offset: */
1170 src1
= get_src(ctx
, &intr
->src
[1])[0];
1172 /* and add offset to addr: */
1173 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1176 /* if offset is to large to encode in the ldg, split it out: */
1177 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1178 /* split out the minimal amount to improve the odds that
1179 * cp can fit the immediate in the add.s instruction:
1181 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1182 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1186 for (int i
= 0; i
< intr
->num_components
; i
++) {
1187 struct ir3_instruction
*load
=
1188 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1189 load
->cat6
.type
= TYPE_U32
;
1190 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1195 /* handles array reads: */
1197 emit_intrinsic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1198 struct ir3_instruction
**dst
)
1200 nir_deref_var
*dvar
= intr
->variables
[0];
1201 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1202 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1204 compile_assert(ctx
, dvar
->deref
.child
&&
1205 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1207 switch (darr
->deref_array_type
) {
1208 case nir_deref_array_type_direct
:
1209 /* direct access does not require anything special: */
1210 for (int i
= 0; i
< intr
->num_components
; i
++) {
1211 unsigned n
= darr
->base_offset
* 4 + i
;
1212 compile_assert(ctx
, n
< arr
->length
);
1213 dst
[i
] = arr
->arr
[n
];
1216 case nir_deref_array_type_indirect
: {
1217 /* for indirect, we need to collect all the array elements: */
1218 struct ir3_instruction
*collect
=
1219 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1220 struct ir3_instruction
*addr
=
1221 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1222 for (int i
= 0; i
< intr
->num_components
; i
++) {
1223 unsigned n
= darr
->base_offset
* 4 + i
;
1224 compile_assert(ctx
, n
< arr
->length
);
1225 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1230 compile_error(ctx
, "Unhandled load deref type: %u\n",
1231 darr
->deref_array_type
);
1236 /* handles array writes: */
1238 emit_intrinsic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1240 nir_deref_var
*dvar
= intr
->variables
[0];
1241 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1242 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1243 struct ir3_instruction
**src
;
1245 compile_assert(ctx
, dvar
->deref
.child
&&
1246 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1248 src
= get_src(ctx
, &intr
->src
[0]);
1250 switch (darr
->deref_array_type
) {
1251 case nir_deref_array_type_direct
:
1252 /* direct access does not require anything special: */
1253 for (int i
= 0; i
< intr
->num_components
; i
++) {
1254 /* ttn doesn't generate partial writemasks */
1255 assert(intr
->const_index
[0] ==
1256 (1 << intr
->num_components
) - 1);
1258 unsigned n
= darr
->base_offset
* 4 + i
;
1259 compile_assert(ctx
, n
< arr
->length
);
1260 arr
->arr
[n
] = src
[i
];
1263 case nir_deref_array_type_indirect
: {
1264 /* for indirect, create indirect-store and fan that out: */
1265 struct ir3_instruction
*collect
=
1266 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1267 struct ir3_instruction
*addr
=
1268 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1269 for (int i
= 0; i
< intr
->num_components
; i
++) {
1270 /* ttn doesn't generate partial writemasks */
1271 assert(intr
->const_index
[0] ==
1272 (1 << intr
->num_components
) - 1);
1274 struct ir3_instruction
*store
;
1275 unsigned n
= darr
->base_offset
* 4 + i
;
1276 compile_assert(ctx
, n
< arr
->length
);
1278 store
= create_indirect_store(ctx
, arr
->length
,
1279 n
, src
[i
], addr
, collect
);
1281 store
->fanin
->fi
.aid
= arr
->aid
;
1283 /* TODO: probably split this out to be used for
1284 * store_output_indirect? or move this into
1285 * create_indirect_store()?
1287 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1288 struct ir3_instruction
*split
;
1290 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1292 ir3_reg_create(split
, 0, 0);
1293 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1295 arr
->arr
[j
] = split
;
1298 /* fixup fanout/split neighbors: */
1299 for (int i
= 0; i
< arr
->length
; i
++) {
1300 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1301 arr
->arr
[i
+1] : NULL
;
1302 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1303 arr
->arr
[i
-1] : NULL
;
1308 compile_error(ctx
, "Unhandled store deref type: %u\n",
1309 darr
->deref_array_type
);
1314 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1315 struct ir3_instruction
*instr
)
1317 struct ir3_shader_variant
*so
= ctx
->so
;
1318 unsigned r
= regid(so
->inputs_count
, 0);
1319 unsigned n
= so
->inputs_count
++;
1321 so
->inputs
[n
].sysval
= true;
1322 so
->inputs
[n
].slot
= slot
;
1323 so
->inputs
[n
].compmask
= 1;
1324 so
->inputs
[n
].regid
= r
;
1325 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_FLAT
;
1328 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1329 ctx
->ir
->inputs
[r
] = instr
;
1333 emit_intrinsic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1335 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1336 struct ir3_instruction
**dst
, **src
;
1337 struct ir3_block
*b
= ctx
->block
;
1338 unsigned idx
= intr
->const_index
[0];
1339 nir_const_value
*const_offset
;
1341 if (info
->has_dest
) {
1342 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1347 switch (intr
->intrinsic
) {
1348 case nir_intrinsic_load_uniform
:
1349 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1351 idx
+= const_offset
->u
[0];
1352 for (int i
= 0; i
< intr
->num_components
; i
++) {
1353 unsigned n
= idx
* 4 + i
;
1354 dst
[i
] = create_uniform(ctx
, n
);
1357 src
= get_src(ctx
, &intr
->src
[0]);
1358 for (int i
= 0; i
< intr
->num_components
; i
++) {
1359 unsigned n
= idx
* 4 + i
;
1360 dst
[i
] = create_uniform_indirect(ctx
, n
,
1361 get_addr(ctx
, src
[0]));
1363 /* NOTE: if relative addressing is used, we set
1364 * constlen in the compiler (to worst-case value)
1365 * since we don't know in the assembler what the max
1366 * addr reg value can be:
1368 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1371 case nir_intrinsic_load_ubo
:
1372 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1374 case nir_intrinsic_load_input
:
1375 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1377 idx
+= const_offset
->u
[0];
1378 for (int i
= 0; i
< intr
->num_components
; i
++) {
1379 unsigned n
= idx
* 4 + i
;
1380 dst
[i
] = ctx
->ir
->inputs
[n
];
1383 src
= get_src(ctx
, &intr
->src
[0]);
1384 struct ir3_instruction
*collect
=
1385 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1386 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1387 for (int i
= 0; i
< intr
->num_components
; i
++) {
1388 unsigned n
= idx
* 4 + i
;
1389 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1394 case nir_intrinsic_load_var
:
1395 emit_intrinsic_load_var(ctx
, intr
, dst
);
1397 case nir_intrinsic_store_var
:
1398 emit_intrinsic_store_var(ctx
, intr
);
1400 case nir_intrinsic_store_output
:
1401 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1402 compile_assert(ctx
, const_offset
!= NULL
);
1403 idx
+= const_offset
->u
[0];
1405 src
= get_src(ctx
, &intr
->src
[0]);
1406 for (int i
= 0; i
< intr
->num_components
; i
++) {
1407 unsigned n
= idx
* 4 + i
;
1408 ctx
->ir
->outputs
[n
] = src
[i
];
1411 case nir_intrinsic_load_base_vertex
:
1412 if (!ctx
->basevertex
) {
1413 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1414 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1417 dst
[0] = ctx
->basevertex
;
1419 case nir_intrinsic_load_vertex_id_zero_base
:
1420 if (!ctx
->vertex_id
) {
1421 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1422 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
1425 dst
[0] = ctx
->vertex_id
;
1427 case nir_intrinsic_load_instance_id
:
1428 if (!ctx
->instance_id
) {
1429 ctx
->instance_id
= create_input(ctx
->block
, 0);
1430 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1433 dst
[0] = ctx
->instance_id
;
1435 case nir_intrinsic_load_user_clip_plane
:
1436 for (int i
= 0; i
< intr
->num_components
; i
++) {
1437 unsigned n
= idx
* 4 + i
;
1438 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1441 case nir_intrinsic_discard_if
:
1442 case nir_intrinsic_discard
: {
1443 struct ir3_instruction
*cond
, *kill
;
1445 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1446 /* conditional discard: */
1447 src
= get_src(ctx
, &intr
->src
[0]);
1448 cond
= ir3_b2n(b
, src
[0]);
1450 /* unconditional discard: */
1451 cond
= create_immed(b
, 1);
1454 /* NOTE: only cmps.*.* can write p0.x: */
1455 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1456 cond
->cat2
.condition
= IR3_COND_NE
;
1458 /* condition always goes in predicate register: */
1459 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1461 kill
= ir3_KILL(b
, cond
, 0);
1462 array_insert(ctx
->ir
->predicates
, kill
);
1464 array_insert(ctx
->ir
->keeps
, kill
);
1465 ctx
->so
->has_kill
= true;
1470 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1471 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1477 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1479 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1480 instr
->def
.num_components
);
1481 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1482 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1486 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1488 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1489 undef
->def
.num_components
);
1490 /* backend doesn't want undefined instructions, so just plug
1493 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1494 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1498 * texture fetch/sample instructions:
1502 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1504 unsigned coords
, flags
= 0;
1506 /* note: would use tex->coord_components.. except txs.. also,
1507 * since array index goes after shadow ref, we don't want to
1510 switch (tex
->sampler_dim
) {
1511 case GLSL_SAMPLER_DIM_1D
:
1512 case GLSL_SAMPLER_DIM_BUF
:
1515 case GLSL_SAMPLER_DIM_2D
:
1516 case GLSL_SAMPLER_DIM_RECT
:
1517 case GLSL_SAMPLER_DIM_EXTERNAL
:
1518 case GLSL_SAMPLER_DIM_MS
:
1521 case GLSL_SAMPLER_DIM_3D
:
1522 case GLSL_SAMPLER_DIM_CUBE
:
1524 flags
|= IR3_INSTR_3D
;
1527 unreachable("bad sampler_dim");
1530 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1531 flags
|= IR3_INSTR_S
;
1533 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1534 flags
|= IR3_INSTR_A
;
1541 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1543 struct ir3_block
*b
= ctx
->block
;
1544 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1545 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1546 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1547 unsigned i
, coords
, flags
;
1548 unsigned nsrc0
= 0, nsrc1
= 0;
1552 coord
= off
= ddx
= ddy
= NULL
;
1553 lod
= proj
= compare
= NULL
;
1555 /* TODO: might just be one component for gathers? */
1556 dst
= get_dst(ctx
, &tex
->dest
, 4);
1558 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1559 switch (tex
->src
[i
].src_type
) {
1560 case nir_tex_src_coord
:
1561 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1563 case nir_tex_src_bias
:
1564 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1567 case nir_tex_src_lod
:
1568 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1571 case nir_tex_src_comparitor
: /* shadow comparator */
1572 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1574 case nir_tex_src_projector
:
1575 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1578 case nir_tex_src_offset
:
1579 off
= get_src(ctx
, &tex
->src
[i
].src
);
1582 case nir_tex_src_ddx
:
1583 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1585 case nir_tex_src_ddy
:
1586 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1589 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1590 tex
->src
[i
].src_type
);
1596 case nir_texop_tex
: opc
= OPC_SAM
; break;
1597 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1598 case nir_texop_txl
: opc
= OPC_SAML
; break;
1599 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1600 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1601 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1602 case nir_texop_txf_ms
:
1605 case nir_texop_query_levels
:
1606 case nir_texop_texture_samples
:
1607 case nir_texop_samples_identical
:
1608 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1612 tex_info(tex
, &flags
, &coords
);
1614 /* scale up integer coords for TXF based on the LOD */
1615 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1617 for (i
= 0; i
< coords
; i
++)
1618 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1621 /* the array coord for cube arrays needs 0.5 added to it */
1622 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& tex
->is_array
&&
1624 coord
[3] = ir3_ADD_F(b
, coord
[3], 0, create_immed(b
, fui(0.5)), 0);
1627 * lay out the first argument in the proper order:
1628 * - actual coordinates first
1629 * - shadow reference
1632 * - starting at offset 4, dpdx.xy, dpdy.xy
1634 * bias/lod go into the second arg
1637 /* insert tex coords: */
1638 for (i
= 0; i
< coords
; i
++)
1639 src0
[nsrc0
++] = coord
[i
];
1642 /* hw doesn't do 1d, so we treat it as 2d with
1643 * height of 1, and patch up the y coord.
1644 * TODO: y coord should be (int)0 in some cases..
1646 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1649 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1650 src0
[nsrc0
++] = compare
;
1652 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1653 src0
[nsrc0
++] = coord
[coords
];
1656 src0
[nsrc0
++] = proj
;
1657 flags
|= IR3_INSTR_P
;
1660 /* pad to 4, then ddx/ddy: */
1661 if (tex
->op
== nir_texop_txd
) {
1663 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1664 for (i
= 0; i
< coords
; i
++)
1665 src0
[nsrc0
++] = ddx
[i
];
1667 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1668 for (i
= 0; i
< coords
; i
++)
1669 src0
[nsrc0
++] = ddy
[i
];
1671 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1675 * second argument (if applicable):
1680 if (has_off
| has_lod
| has_bias
) {
1682 for (i
= 0; i
< coords
; i
++)
1683 src1
[nsrc1
++] = off
[i
];
1685 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1686 flags
|= IR3_INSTR_O
;
1689 if (has_lod
| has_bias
)
1690 src1
[nsrc1
++] = lod
;
1693 switch (tex
->dest_type
) {
1694 case nir_type_invalid
:
1695 case nir_type_float
:
1706 unreachable("bad dest_type");
1709 if (opc
== OPC_GETLOD
)
1712 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1713 flags
, tex
->sampler_index
, tex
->sampler_index
,
1714 create_collect(b
, src0
, nsrc0
),
1715 create_collect(b
, src1
, nsrc1
));
1717 split_dest(b
, dst
, sam
, 4);
1719 /* GETLOD returns results in 4.8 fixed point */
1720 if (opc
== OPC_GETLOD
) {
1721 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1723 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1724 for (i
= 0; i
< 2; i
++) {
1725 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1732 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1734 struct ir3_block
*b
= ctx
->block
;
1735 struct ir3_instruction
**dst
, *sam
;
1737 dst
= get_dst(ctx
, &tex
->dest
, 1);
1739 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1740 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1742 /* even though there is only one component, since it ends
1743 * up in .z rather than .x, we need a split_dest()
1745 split_dest(b
, dst
, sam
, 3);
1747 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1748 * the value in TEX_CONST_0 is zero-based.
1750 if (ctx
->levels_add_one
)
1751 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1755 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1757 struct ir3_block
*b
= ctx
->block
;
1758 struct ir3_instruction
**dst
, *sam
, *lod
;
1759 unsigned flags
, coords
;
1761 tex_info(tex
, &flags
, &coords
);
1763 /* Actually we want the number of dimensions, not coordinates. This
1764 * distinction only matters for cubes.
1766 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1769 dst
= get_dst(ctx
, &tex
->dest
, 4);
1771 compile_assert(ctx
, tex
->num_srcs
== 1);
1772 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1774 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1776 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1777 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1779 split_dest(b
, dst
, sam
, 4);
1781 /* Array size actually ends up in .w rather than .z. This doesn't
1782 * matter for miplevel 0, but for higher mips the value in z is
1783 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1784 * returned, which means that we have to add 1 to it for arrays.
1786 if (tex
->is_array
) {
1787 if (ctx
->levels_add_one
) {
1788 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1790 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1796 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1798 struct ir3_instruction
*phi
, **dst
;
1800 /* NOTE: phi's should be lowered to scalar at this point */
1801 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1803 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1805 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1806 1 + exec_list_length(&nphi
->srcs
));
1807 ir3_reg_create(phi
, 0, 0); /* dst */
1808 phi
->phi
.nphi
= nphi
;
1813 /* phi instructions are left partially constructed. We don't resolve
1814 * their srcs until the end of the block, since (eg. loops) one of
1815 * the phi's srcs might be defined after the phi due to back edges in
1819 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1821 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1822 nir_phi_instr
*nphi
;
1824 /* phi's only come at start of block: */
1825 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1828 if (!instr
->phi
.nphi
)
1831 nphi
= instr
->phi
.nphi
;
1832 instr
->phi
.nphi
= NULL
;
1834 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1835 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1836 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1840 resolve_array_phis(ctx
, block
);
1844 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1846 switch (jump
->type
) {
1847 case nir_jump_break
:
1848 case nir_jump_continue
:
1849 /* I *think* we can simply just ignore this, and use the
1850 * successor block link to figure out where we need to
1851 * jump to for break/continue
1855 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1861 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1863 switch (instr
->type
) {
1864 case nir_instr_type_alu
:
1865 emit_alu(ctx
, nir_instr_as_alu(instr
));
1867 case nir_instr_type_intrinsic
:
1868 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1870 case nir_instr_type_load_const
:
1871 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1873 case nir_instr_type_ssa_undef
:
1874 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1876 case nir_instr_type_tex
: {
1877 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1878 /* couple tex instructions get special-cased:
1882 emit_tex_txs(ctx
, tex
);
1884 case nir_texop_query_levels
:
1885 emit_tex_query_levels(ctx
, tex
);
1893 case nir_instr_type_phi
:
1894 emit_phi(ctx
, nir_instr_as_phi(instr
));
1896 case nir_instr_type_jump
:
1897 emit_jump(ctx
, nir_instr_as_jump(instr
));
1899 case nir_instr_type_call
:
1900 case nir_instr_type_parallel_copy
:
1901 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1906 static struct ir3_block
*
1907 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1909 struct ir3_block
*block
;
1910 struct hash_entry
*entry
;
1911 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1915 block
= ir3_block_create(ctx
->ir
);
1916 block
->nblock
= nblock
;
1917 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1923 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1925 struct ir3_block
*block
= get_block(ctx
, nblock
);
1927 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1928 if (nblock
->successors
[i
]) {
1929 block
->successors
[i
] =
1930 get_block(ctx
, nblock
->successors
[i
]);
1935 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1937 /* re-emit addr register in each block if needed: */
1938 _mesa_hash_table_destroy(ctx
->addr_ht
, NULL
);
1939 ctx
->addr_ht
= NULL
;
1941 nir_foreach_instr(nblock
, instr
) {
1942 emit_instr(ctx
, instr
);
1948 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1951 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1953 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1955 ctx
->block
->condition
=
1956 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1958 emit_cf_list(ctx
, &nif
->then_list
);
1959 emit_cf_list(ctx
, &nif
->else_list
);
1963 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1965 emit_cf_list(ctx
, &nloop
->body
);
1969 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1971 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1972 switch (node
->type
) {
1973 case nir_cf_node_block
:
1974 emit_block(ctx
, nir_cf_node_as_block(node
));
1976 case nir_cf_node_if
:
1977 emit_if(ctx
, nir_cf_node_as_if(node
));
1979 case nir_cf_node_loop
:
1980 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1982 case nir_cf_node_function
:
1983 compile_error(ctx
, "TODO\n");
1989 /* emit stream-out code. At this point, the current block is the original
1990 * (nir) end block, and nir ensures that all flow control paths terminate
1991 * into the end block. We re-purpose the original end block to generate
1992 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
1993 * block holding stream-out write instructions, followed by the new end
1997 * p0.x = (vtxcnt < maxvtxcnt)
1998 * // succs: blockStreamOut, blockNewEnd
2001 * ... stream-out instructions ...
2002 * // succs: blockNewEnd
2008 emit_stream_out(struct ir3_compile
*ctx
)
2010 struct ir3_shader_variant
*v
= ctx
->so
;
2011 struct ir3
*ir
= ctx
->ir
;
2012 struct pipe_stream_output_info
*strmout
=
2013 &ctx
->so
->shader
->stream_output
;
2014 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2015 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2016 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2018 /* create vtxcnt input in input block at top of shader,
2019 * so that it is seen as live over the entire duration
2022 vtxcnt
= create_input(ctx
->in_block
, 0);
2023 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2025 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2027 /* at this point, we are at the original 'end' block,
2028 * re-purpose this block to stream-out condition, then
2029 * append stream-out block and new-end block
2031 orig_end_block
= ctx
->block
;
2033 stream_out_block
= ir3_block_create(ir
);
2034 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2036 new_end_block
= ir3_block_create(ir
);
2037 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2039 orig_end_block
->successors
[0] = stream_out_block
;
2040 orig_end_block
->successors
[1] = new_end_block
;
2041 stream_out_block
->successors
[0] = new_end_block
;
2043 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2044 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2045 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2046 cond
->cat2
.condition
= IR3_COND_LT
;
2048 /* condition goes on previous block to the conditional,
2049 * since it is used to pick which of the two successor
2052 orig_end_block
->condition
= cond
;
2054 /* switch to stream_out_block to generate the stream-out
2057 ctx
->block
= stream_out_block
;
2059 /* Calculate base addresses based on vtxcnt. Instructions
2060 * generated for bases not used in following loop will be
2061 * stripped out in the backend.
2063 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2064 unsigned stride
= strmout
->stride
[i
];
2065 struct ir3_instruction
*base
, *off
;
2067 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ IR3_TFBOS_OFF
, i
));
2069 /* 24-bit should be enough: */
2070 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2071 create_immed(ctx
->block
, stride
* 4), 0);
2073 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2076 /* Generate the per-output store instructions: */
2077 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2078 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2079 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2080 struct ir3_instruction
*base
, *out
, *stg
;
2082 base
= bases
[strmout
->output
[i
].output_buffer
];
2083 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2085 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2086 create_immed(ctx
->block
, 1), 0);
2087 stg
->cat6
.type
= TYPE_U32
;
2088 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2090 array_insert(ctx
->ir
->keeps
, stg
);
2094 /* and finally switch to the new_end_block: */
2095 ctx
->block
= new_end_block
;
2099 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2101 nir_metadata_require(impl
, nir_metadata_block_index
);
2103 emit_cf_list(ctx
, &impl
->body
);
2104 emit_block(ctx
, impl
->end_block
);
2106 /* at this point, we should have a single empty block,
2107 * into which we emit the 'end' instruction.
2109 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2111 /* If stream-out (aka transform-feedback) enabled, emit the
2112 * stream-out instructions, followed by a new empty block (into
2113 * which the 'end' instruction lands).
2115 * NOTE: it is done in this order, rather than inserting before
2116 * we emit end_block, because NIR guarantees that all blocks
2117 * flow into end_block, and that end_block has no successors.
2118 * So by re-purposing end_block as the first block of stream-
2119 * out, we guarantee that all exit paths flow into the stream-
2122 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2123 !ctx
->so
->key
.binning_pass
) {
2124 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2125 emit_stream_out(ctx
);
2128 ir3_END(ctx
->block
);
2132 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2134 struct ir3_shader_variant
*so
= ctx
->so
;
2135 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2136 unsigned ncomp
= glsl_get_components(in
->type
);
2137 unsigned n
= in
->data
.driver_location
;
2138 unsigned slot
= in
->data
.location
;
2140 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2141 slot
, array_len
, ncomp
, n
);
2143 so
->inputs
[n
].slot
= slot
;
2144 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2145 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2146 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2148 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2149 for (int i
= 0; i
< ncomp
; i
++) {
2150 struct ir3_instruction
*instr
= NULL
;
2151 unsigned idx
= (n
* 4) + i
;
2153 if (slot
== VARYING_SLOT_POS
) {
2154 so
->inputs
[n
].bary
= false;
2155 so
->frag_coord
= true;
2156 instr
= create_frag_coord(ctx
, i
);
2157 } else if (slot
== VARYING_SLOT_FACE
) {
2158 so
->inputs
[n
].bary
= false;
2159 so
->frag_face
= true;
2160 instr
= create_frag_face(ctx
, i
);
2162 bool use_ldlv
= false;
2164 /* detect the special case for front/back colors where
2165 * we need to do flat vs smooth shading depending on
2168 if (in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) {
2170 case VARYING_SLOT_COL0
:
2171 case VARYING_SLOT_COL1
:
2172 case VARYING_SLOT_BFC0
:
2173 case VARYING_SLOT_BFC1
:
2174 so
->inputs
[n
].rasterflat
= true;
2181 if (ctx
->flat_bypass
) {
2182 if ((so
->inputs
[n
].interpolate
== INTERP_QUALIFIER_FLAT
) ||
2183 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2187 so
->inputs
[n
].bary
= true;
2189 instr
= create_frag_input(ctx
, use_ldlv
);
2192 ctx
->ir
->inputs
[idx
] = instr
;
2194 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2195 for (int i
= 0; i
< ncomp
; i
++) {
2196 unsigned idx
= (n
* 4) + i
;
2197 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2200 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2203 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2204 so
->total_in
+= ncomp
;
2209 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2211 struct ir3_shader_variant
*so
= ctx
->so
;
2212 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2213 unsigned ncomp
= glsl_get_components(out
->type
);
2214 unsigned n
= out
->data
.driver_location
;
2215 unsigned slot
= out
->data
.location
;
2218 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2219 slot
, array_len
, ncomp
, n
);
2221 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2223 case FRAG_RESULT_DEPTH
:
2224 comp
= 2; /* tgsi will write to .z component */
2225 so
->writes_pos
= true;
2227 case FRAG_RESULT_COLOR
:
2231 if (slot
>= FRAG_RESULT_DATA0
)
2233 compile_error(ctx
, "unknown FS output name: %s\n",
2234 gl_frag_result_name(slot
));
2236 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2238 case VARYING_SLOT_POS
:
2239 so
->writes_pos
= true;
2241 case VARYING_SLOT_PSIZ
:
2242 so
->writes_psize
= true;
2244 case VARYING_SLOT_COL0
:
2245 case VARYING_SLOT_COL1
:
2246 case VARYING_SLOT_BFC0
:
2247 case VARYING_SLOT_BFC1
:
2248 case VARYING_SLOT_FOGC
:
2249 case VARYING_SLOT_CLIP_DIST0
:
2250 case VARYING_SLOT_CLIP_DIST1
:
2253 if (slot
>= VARYING_SLOT_VAR0
)
2255 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2257 compile_error(ctx
, "unknown VS output name: %s\n",
2258 gl_varying_slot_name(slot
));
2261 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2264 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2266 so
->outputs
[n
].slot
= slot
;
2267 so
->outputs
[n
].regid
= regid(n
, comp
);
2268 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2270 for (int i
= 0; i
< ncomp
; i
++) {
2271 unsigned idx
= (n
* 4) + i
;
2273 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2278 emit_instructions(struct ir3_compile
*ctx
)
2280 unsigned ninputs
, noutputs
;
2281 nir_function_impl
*fxn
= NULL
;
2283 /* Find the main function: */
2284 nir_foreach_function(ctx
->s
, function
) {
2285 compile_assert(ctx
, strcmp(function
->name
, "main") == 0);
2286 compile_assert(ctx
, function
->impl
);
2287 fxn
= function
->impl
;
2291 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2292 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2294 /* or vtx shaders, we need to leave room for sysvals:
2296 if (ctx
->so
->type
== SHADER_VERTEX
) {
2300 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2302 /* Create inputs in first block: */
2303 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2304 ctx
->in_block
= ctx
->block
;
2305 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2307 if (ctx
->so
->type
== SHADER_VERTEX
) {
2308 ctx
->ir
->ninputs
-= 8;
2311 /* for fragment shader, we have a single input register (usually
2312 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2314 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2315 // TODO maybe a helper for fi since we need it a few places..
2316 struct ir3_instruction
*instr
;
2317 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2318 ir3_reg_create(instr
, 0, 0);
2319 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2320 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2321 ctx
->frag_pos
= instr
;
2325 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2326 setup_input(ctx
, var
);
2329 /* Setup outputs: */
2330 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2331 setup_output(ctx
, var
);
2334 /* Setup variables (which should only be arrays): */
2335 nir_foreach_variable(var
, &ctx
->s
->globals
) {
2336 declare_var(ctx
, var
);
2339 /* And emit the body: */
2341 emit_function(ctx
, fxn
);
2343 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2344 resolve_phis(ctx
, block
);
2348 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2349 * for a fragment shader are just bary.f instructions. The *actual* inputs
2350 * from the hw perspective are the frag_pos and optionally frag_coord and
2354 fixup_frag_inputs(struct ir3_compile
*ctx
)
2356 struct ir3_shader_variant
*so
= ctx
->so
;
2357 struct ir3
*ir
= ctx
->ir
;
2358 struct ir3_instruction
**inputs
;
2359 struct ir3_instruction
*instr
;
2364 n
= 4; /* always have frag_pos */
2365 n
+= COND(so
->frag_face
, 4);
2366 n
+= COND(so
->frag_coord
, 4);
2368 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2370 if (so
->frag_face
) {
2371 /* this ultimately gets assigned to hr0.x so doesn't conflict
2372 * with frag_coord/frag_pos..
2374 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2375 ctx
->frag_face
->regs
[0]->num
= 0;
2377 /* remaining channels not used, but let's avoid confusing
2378 * other parts that expect inputs to come in groups of vec4
2380 inputs
[ir
->ninputs
++] = NULL
;
2381 inputs
[ir
->ninputs
++] = NULL
;
2382 inputs
[ir
->ninputs
++] = NULL
;
2385 /* since we don't know where to set the regid for frag_coord,
2386 * we have to use r0.x for it. But we don't want to *always*
2387 * use r1.x for frag_pos as that could increase the register
2388 * footprint on simple shaders:
2390 if (so
->frag_coord
) {
2391 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2392 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2393 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2394 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2396 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2397 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2398 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2399 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2402 /* we always have frag_pos: */
2403 so
->pos_regid
= regid
;
2406 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2407 instr
->regs
[0]->num
= regid
++;
2408 inputs
[ir
->ninputs
++] = instr
;
2409 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2412 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2413 instr
->regs
[0]->num
= regid
++;
2414 inputs
[ir
->ninputs
++] = instr
;
2415 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2417 ir
->inputs
= inputs
;
2421 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2422 struct ir3_shader_variant
*so
)
2424 struct ir3_compile
*ctx
;
2426 struct ir3_instruction
**inputs
;
2427 unsigned i
, j
, actual_in
, inloc
;
2428 int ret
= 0, max_bary
;
2432 ctx
= compile_init(compiler
, so
);
2434 DBG("INIT failed!");
2439 emit_instructions(ctx
);
2442 DBG("EMIT failed!");
2447 ir
= so
->ir
= ctx
->ir
;
2449 /* keep track of the inputs from TGSI perspective.. */
2450 inputs
= ir
->inputs
;
2452 /* but fixup actual inputs for frag shader: */
2453 if (so
->type
== SHADER_FRAGMENT
)
2454 fixup_frag_inputs(ctx
);
2456 /* at this point, for binning pass, throw away unneeded outputs: */
2457 if (so
->key
.binning_pass
) {
2458 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2459 unsigned slot
= so
->outputs
[i
].slot
;
2461 /* throw away everything but first position/psize */
2462 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2464 so
->outputs
[j
] = so
->outputs
[i
];
2465 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2466 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2467 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2468 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2473 so
->outputs_count
= j
;
2474 ir
->noutputs
= j
* 4;
2477 /* if we want half-precision outputs, mark the output registers
2480 if (so
->key
.half_precision
) {
2481 for (i
= 0; i
< ir
->noutputs
; i
++) {
2482 struct ir3_instruction
*out
= ir
->outputs
[i
];
2485 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2486 /* output could be a fanout (ie. texture fetch output)
2487 * in which case we need to propagate the half-reg flag
2488 * up to the definer so that RA sees it:
2490 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2491 out
= out
->regs
[1]->instr
;
2492 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2495 if (out
->category
== 1) {
2496 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2501 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2502 printf("BEFORE CP:\n");
2508 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2509 printf("BEFORE GROUPING:\n");
2513 /* Group left/right neighbors, inserting mov's where needed to
2520 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2521 printf("AFTER DEPTH:\n");
2525 ret
= ir3_sched(ir
);
2527 DBG("SCHED failed!");
2531 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2532 printf("AFTER SCHED:\n");
2536 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2542 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2543 printf("AFTER RA:\n");
2547 /* fixup input/outputs: */
2548 for (i
= 0; i
< so
->outputs_count
; i
++) {
2549 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2550 /* preserve hack for depth output.. tgsi writes depth to .z,
2551 * but what we give the hw is the scalar register:
2553 if ((so
->type
== SHADER_FRAGMENT
) &&
2554 (so
->outputs
[i
].slot
== FRAG_RESULT_DEPTH
))
2555 so
->outputs
[i
].regid
+= 2;
2558 /* Note that some or all channels of an input may be unused: */
2561 for (i
= 0; i
< so
->inputs_count
; i
++) {
2562 unsigned j
, regid
= ~0, compmask
= 0;
2563 so
->inputs
[i
].ncomp
= 0;
2564 so
->inputs
[i
].inloc
= inloc
+ 8;
2565 for (j
= 0; j
< 4; j
++) {
2566 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2567 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2568 compmask
|= (1 << j
);
2569 regid
= in
->regs
[0]->num
- j
;
2571 so
->inputs
[i
].ncomp
++;
2572 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2574 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2575 in
->regs
[1]->iim_val
= inloc
++;
2579 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
)
2581 so
->inputs
[i
].regid
= regid
;
2582 so
->inputs
[i
].compmask
= compmask
;
2585 /* We need to do legalize after (for frag shader's) the "bary.f"
2586 * offsets (inloc) have been assigned.
2588 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2590 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2591 printf("AFTER LEGALIZE:\n");
2595 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2596 if (so
->type
== SHADER_VERTEX
)
2597 so
->total_in
= actual_in
;
2599 so
->total_in
= max_bary
+ 1;
2604 ir3_destroy(so
->ir
);