1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* mapping from nir_register to defining instruction: */
75 struct hash_table
*def_ht
;
79 /* a common pattern for indirect addressing is to request the
80 * same address register multiple times. To avoid generating
81 * duplicate instruction sequences (which our backend does not
82 * try to clean up, since that should be done as the NIR stage)
83 * we cache the address value generated for a given src value:
85 struct hash_table
*addr_ht
;
87 /* maps nir_block to ir3_block, mostly for the purposes of
88 * figuring out the blocks successors
90 struct hash_table
*block_ht
;
92 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
93 * so we need to use ldlv.u32 to load the varying directly:
97 /* on a3xx, we need to add one to # of array levels:
101 /* on a3xx, we need to scale up integer coords for isaml based
104 bool unminify_coords
;
106 /* on a4xx, for array textures we need to add 0.5 to the array
109 bool array_index_add_half
;
111 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
114 unsigned max_texture_index
;
116 /* set if we encounter something we can't handle yet, so we
117 * can bail cleanly and fallback to TGSI compiler f/e
122 /* gpu pointer size in units of 32bit registers/slots */
123 static unsigned pointer_size(struct ir3_compile
*ctx
)
125 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
128 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
129 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
132 static struct ir3_compile
*
133 compile_init(struct ir3_compiler
*compiler
,
134 struct ir3_shader_variant
*so
)
136 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
138 if (compiler
->gpu_id
>= 400) {
139 /* need special handling for "flat" */
140 ctx
->flat_bypass
= true;
141 ctx
->levels_add_one
= false;
142 ctx
->unminify_coords
= false;
143 ctx
->array_index_add_half
= true;
145 if (so
->type
== SHADER_VERTEX
)
146 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
147 else if (so
->type
== SHADER_FRAGMENT
)
148 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
151 /* no special handling for "flat" */
152 ctx
->flat_bypass
= false;
153 ctx
->levels_add_one
= true;
154 ctx
->unminify_coords
= true;
155 ctx
->array_index_add_half
= false;
158 ctx
->compiler
= compiler
;
161 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
162 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
163 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
164 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
166 /* TODO: maybe generate some sort of bitmask of what key
167 * lowers vs what shader has (ie. no need to lower
168 * texture clamp lowering if no texture sample instrs)..
169 * although should be done further up the stack to avoid
170 * creating duplicate variants..
173 if (ir3_key_lowers_nir(&so
->key
)) {
174 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
175 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
177 /* fast-path for shader key that lowers nothing in NIR: */
178 ctx
->s
= so
->shader
->nir
;
181 if (fd_mesa_debug
& FD_DBG_DISASM
) {
182 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
183 so
->shader
->id
, so
->id
, so
->type
,
184 so
->key
.binning_pass
, so
->key
.color_two_side
,
185 so
->key
.half_precision
);
186 nir_print_shader(ctx
->s
, stdout
);
189 so
->num_uniforms
= ctx
->s
->num_uniforms
;
190 so
->num_ubos
= ctx
->s
->info
->num_ubos
;
192 /* Layout of constant registers, each section aligned to vec4. Note
193 * that pointer size (ubo, etc) changes depending on generation.
197 * if (vertex shader) {
198 * driver params (IR3_DP_*)
199 * if (stream_output.num_outputs > 0)
200 * stream-out addresses
204 * Immediates go last mostly because they are inserted in the CP pass
205 * after the nir -> ir3 frontend.
207 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
208 unsigned ptrsz
= pointer_size(ctx
);
210 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
212 if (so
->num_ubos
> 0) {
213 so
->constbase
.ubo
= constoff
;
214 constoff
+= align(ctx
->s
->info
->num_ubos
* ptrsz
, 4) / 4;
217 if (so
->type
== SHADER_VERTEX
) {
218 so
->constbase
.driver_param
= constoff
;
219 constoff
+= align(IR3_DP_COUNT
, 4) / 4;
221 if (so
->shader
->stream_output
.num_outputs
> 0) {
222 so
->constbase
.tfbo
= constoff
;
223 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
227 so
->constbase
.immediate
= constoff
;
233 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
236 va_start(ap
, format
);
237 _debug_vprintf(format
, ap
);
239 nir_print_shader(ctx
->s
, stdout
);
244 #define compile_assert(ctx, cond) do { \
245 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
249 compile_free(struct ir3_compile
*ctx
)
255 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
257 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
258 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
259 arr
->id
= ++ctx
->num_arrays
;
260 arr
->length
= length
;
262 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
265 static struct ir3_array
*
266 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
268 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
272 compile_error(ctx
, "bogus var: %s\n", var
->name
);
276 /* allocate a n element value array (to be populated by caller) and
279 static struct ir3_instruction
**
280 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
282 struct ir3_instruction
**value
=
283 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
284 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
288 static struct ir3_instruction
**
289 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
291 compile_assert(ctx
, dst
->is_ssa
);
293 return __get_dst(ctx
, &dst
->ssa
, n
);
295 return __get_dst(ctx
, dst
->reg
.reg
, n
);
299 static struct ir3_instruction
**
300 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
302 return __get_dst(ctx
, dst
, n
);
305 static struct ir3_instruction
* const *
306 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
308 struct hash_entry
*entry
;
309 compile_assert(ctx
, src
->is_ssa
);
311 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
313 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
315 compile_assert(ctx
, entry
);
319 static struct ir3_instruction
*
320 create_immed(struct ir3_block
*block
, uint32_t val
)
322 struct ir3_instruction
*mov
;
324 mov
= ir3_instr_create(block
, OPC_MOV
);
325 mov
->cat1
.src_type
= TYPE_U32
;
326 mov
->cat1
.dst_type
= TYPE_U32
;
327 ir3_reg_create(mov
, 0, 0);
328 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
333 static struct ir3_instruction
*
334 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
336 struct ir3_instruction
*instr
, *immed
;
338 /* TODO in at least some cases, the backend could probably be
339 * made clever enough to propagate IR3_REG_HALF..
341 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
342 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
344 immed
= create_immed(block
, 2);
345 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
347 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
348 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
349 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
351 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
352 instr
->regs
[0]->num
= regid(REG_A0
, 0);
353 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
354 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
359 /* caches addr values to avoid generating multiple cov/shl/mova
360 * sequences for each use of a given NIR level src as address
362 static struct ir3_instruction
*
363 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
365 struct ir3_instruction
*addr
;
368 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
369 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
371 struct hash_entry
*entry
;
372 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
377 addr
= create_addr(ctx
->block
, src
);
378 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
383 static struct ir3_instruction
*
384 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
386 struct ir3_block
*b
= ctx
->block
;
387 struct ir3_instruction
*cond
;
389 /* NOTE: only cmps.*.* can write p0.x: */
390 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
391 cond
->cat2
.condition
= IR3_COND_NE
;
393 /* condition always goes in predicate register: */
394 cond
->regs
[0]->num
= regid(REG_P0
, 0);
399 static struct ir3_instruction
*
400 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
402 struct ir3_instruction
*mov
;
404 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
405 /* TODO get types right? */
406 mov
->cat1
.src_type
= TYPE_F32
;
407 mov
->cat1
.dst_type
= TYPE_F32
;
408 ir3_reg_create(mov
, 0, 0);
409 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
414 static struct ir3_instruction
*
415 create_uniform_indirect(struct ir3_compile
*ctx
, int n
,
416 struct ir3_instruction
*address
)
418 struct ir3_instruction
*mov
;
420 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
421 mov
->cat1
.src_type
= TYPE_U32
;
422 mov
->cat1
.dst_type
= TYPE_U32
;
423 ir3_reg_create(mov
, 0, 0);
424 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
426 ir3_instr_set_address(mov
, address
);
431 static struct ir3_instruction
*
432 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
435 struct ir3_instruction
*collect
;
440 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
441 ir3_reg_create(collect
, 0, 0); /* dst */
442 for (unsigned i
= 0; i
< arrsz
; i
++)
443 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
448 static struct ir3_instruction
*
449 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, int n
,
450 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
452 struct ir3_block
*block
= ctx
->block
;
453 struct ir3_instruction
*mov
;
454 struct ir3_register
*src
;
456 mov
= ir3_instr_create(block
, OPC_MOV
);
457 mov
->cat1
.src_type
= TYPE_U32
;
458 mov
->cat1
.dst_type
= TYPE_U32
;
459 ir3_reg_create(mov
, 0, 0);
460 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
461 src
->instr
= collect
;
463 src
->array
.offset
= n
;
465 ir3_instr_set_address(mov
, address
);
470 /* relative (indirect) if address!=NULL */
471 static struct ir3_instruction
*
472 create_var_load(struct ir3_compile
*ctx
, struct ir3_array
*arr
, int n
,
473 struct ir3_instruction
*address
)
475 struct ir3_block
*block
= ctx
->block
;
476 struct ir3_instruction
*mov
;
477 struct ir3_register
*src
;
479 mov
= ir3_instr_create(block
, OPC_MOV
);
480 mov
->cat1
.src_type
= TYPE_U32
;
481 mov
->cat1
.dst_type
= TYPE_U32
;
482 ir3_reg_create(mov
, 0, 0);
483 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
484 COND(address
, IR3_REG_RELATIV
));
485 src
->instr
= arr
->last_write
;
486 src
->size
= arr
->length
;
487 src
->array
.id
= arr
->id
;
488 src
->array
.offset
= n
;
491 ir3_instr_set_address(mov
, address
);
493 arr
->last_access
= mov
;
498 /* relative (indirect) if address!=NULL */
499 static struct ir3_instruction
*
500 create_var_store(struct ir3_compile
*ctx
, struct ir3_array
*arr
, int n
,
501 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
503 struct ir3_block
*block
= ctx
->block
;
504 struct ir3_instruction
*mov
;
505 struct ir3_register
*dst
;
507 mov
= ir3_instr_create(block
, OPC_MOV
);
508 mov
->cat1
.src_type
= TYPE_U32
;
509 mov
->cat1
.dst_type
= TYPE_U32
;
510 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
511 COND(address
, IR3_REG_RELATIV
));
512 dst
->instr
= arr
->last_access
;
513 dst
->size
= arr
->length
;
514 dst
->array
.id
= arr
->id
;
515 dst
->array
.offset
= n
;
516 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
518 ir3_instr_set_address(mov
, address
);
520 arr
->last_write
= arr
->last_access
= mov
;
525 static struct ir3_instruction
*
526 create_input(struct ir3_block
*block
, unsigned n
)
528 struct ir3_instruction
*in
;
530 in
= ir3_instr_create(block
, OPC_META_INPUT
);
531 in
->inout
.block
= block
;
532 ir3_reg_create(in
, n
, 0);
537 static struct ir3_instruction
*
538 create_frag_input(struct ir3_compile
*ctx
, bool use_ldlv
)
540 struct ir3_block
*block
= ctx
->block
;
541 struct ir3_instruction
*instr
;
542 /* actual inloc is assigned and fixed up later: */
543 struct ir3_instruction
*inloc
= create_immed(block
, 0);
546 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
547 instr
->cat6
.type
= TYPE_U32
;
548 instr
->cat6
.iim_val
= 1;
550 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
551 instr
->regs
[2]->wrmask
= 0x3;
557 static struct ir3_instruction
*
558 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
560 struct ir3_block
*block
= ctx
->block
;
561 struct ir3_instruction
*instr
;
563 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
565 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
570 /* for frag_coord, we get unsigned values.. we need
571 * to subtract (integer) 8 and divide by 16 (right-
572 * shift by 4) then convert to float:
576 * mov.u32f32 dst, tmp
579 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
580 create_immed(block
, 8), 0);
581 instr
= ir3_SHR_B(block
, instr
, 0,
582 create_immed(block
, 4), 0);
583 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
589 /* seems that we can use these as-is: */
590 return ctx
->frag_coord
[comp
];
594 static struct ir3_instruction
*
595 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
597 /* first four vec4 sysval's reserved for UBOs: */
598 /* NOTE: dp is in scalar, but there can be >4 dp components: */
599 unsigned n
= ctx
->so
->constbase
.driver_param
;
600 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
601 return create_uniform(ctx
, r
);
604 /* helper for instructions that produce multiple consecutive scalar
605 * outputs which need to have a split/fanout meta instruction inserted
608 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
609 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
611 struct ir3_instruction
*prev
= NULL
;
612 for (int i
= 0, j
= 0; i
< n
; i
++) {
613 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
614 ir3_reg_create(split
, 0, IR3_REG_SSA
);
615 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
616 split
->fo
.off
= i
+ base
;
619 split
->cp
.left
= prev
;
620 split
->cp
.left_cnt
++;
621 prev
->cp
.right
= split
;
622 prev
->cp
.right_cnt
++;
626 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
632 * Adreno uses uint rather than having dedicated bool type,
633 * which (potentially) requires some conversion, in particular
634 * when using output of an bool instr to int input, or visa
638 * -------+---------+-------+-
642 * To convert from an adreno bool (uint) to nir, use:
644 * absneg.s dst, (neg)src
646 * To convert back in the other direction:
648 * absneg.s dst, (abs)arc
650 * The CP step can clean up the absneg.s that cancel each other
651 * out, and with a slight bit of extra cleverness (to recognize
652 * the instructions which produce either a 0 or 1) can eliminate
653 * the absneg.s's completely when an instruction that wants
654 * 0/1 consumes the result. For example, when a nir 'bcsel'
655 * consumes the result of 'feq'. So we should be able to get by
656 * without a boolean resolve step, and without incuring any
657 * extra penalty in instruction count.
660 /* NIR bool -> native (adreno): */
661 static struct ir3_instruction
*
662 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
664 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
667 /* native (adreno) -> NIR bool: */
668 static struct ir3_instruction
*
669 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
671 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
675 * alu/sfu instructions:
679 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
681 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
682 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
683 struct ir3_block
*b
= ctx
->block
;
685 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
687 /* Vectors are special in that they have non-scalarized writemasks,
688 * and just take the first swizzle channel for each argument in
689 * order into each writemask channel.
691 if ((alu
->op
== nir_op_vec2
) ||
692 (alu
->op
== nir_op_vec3
) ||
693 (alu
->op
== nir_op_vec4
)) {
695 for (int i
= 0; i
< info
->num_inputs
; i
++) {
696 nir_alu_src
*asrc
= &alu
->src
[i
];
698 compile_assert(ctx
, !asrc
->abs
);
699 compile_assert(ctx
, !asrc
->negate
);
701 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
703 src
[i
] = create_immed(ctx
->block
, 0);
704 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
710 /* General case: We can just grab the one used channel per src. */
711 for (int i
= 0; i
< info
->num_inputs
; i
++) {
712 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
713 nir_alu_src
*asrc
= &alu
->src
[i
];
715 compile_assert(ctx
, !asrc
->abs
);
716 compile_assert(ctx
, !asrc
->negate
);
718 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
720 compile_assert(ctx
, src
[i
]);
725 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
728 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
731 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
734 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
737 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
740 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
743 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
744 dst
[0]->cat2
.condition
= IR3_COND_NE
;
745 dst
[0] = ir3_n2b(b
, dst
[0]);
748 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
751 dst
[0] = ir3_b2n(b
, src
[0]);
754 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
755 dst
[0]->cat2
.condition
= IR3_COND_NE
;
756 dst
[0] = ir3_n2b(b
, dst
[0]);
760 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
763 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
766 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
769 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
772 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
775 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
778 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
781 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
784 dst
[0] = ir3_DSX(b
, src
[0], 0);
785 dst
[0]->cat5
.type
= TYPE_F32
;
788 dst
[0] = ir3_DSY(b
, src
[0], 0);
789 dst
[0]->cat5
.type
= TYPE_F32
;
793 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
794 dst
[0]->cat2
.condition
= IR3_COND_LT
;
795 dst
[0] = ir3_n2b(b
, dst
[0]);
798 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
799 dst
[0]->cat2
.condition
= IR3_COND_GE
;
800 dst
[0] = ir3_n2b(b
, dst
[0]);
803 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
804 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
805 dst
[0] = ir3_n2b(b
, dst
[0]);
808 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
809 dst
[0]->cat2
.condition
= IR3_COND_NE
;
810 dst
[0] = ir3_n2b(b
, dst
[0]);
813 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
816 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
819 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
821 case nir_op_fround_even
:
822 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
825 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
829 dst
[0] = ir3_SIN(b
, src
[0], 0);
832 dst
[0] = ir3_COS(b
, src
[0], 0);
835 dst
[0] = ir3_RSQ(b
, src
[0], 0);
838 dst
[0] = ir3_RCP(b
, src
[0], 0);
841 dst
[0] = ir3_LOG2(b
, src
[0], 0);
844 dst
[0] = ir3_EXP2(b
, src
[0], 0);
847 dst
[0] = ir3_SQRT(b
, src
[0], 0);
851 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
854 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
857 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
860 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
863 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
866 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
869 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
873 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
874 * mull.u tmp0, a, b ; mul low, i.e. al * bl
875 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
876 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
878 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
879 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
880 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
883 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
886 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
889 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
892 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
895 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
898 /* maybe this would be sane to lower in nir.. */
899 struct ir3_instruction
*neg
, *pos
;
901 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
902 neg
->cat2
.condition
= IR3_COND_LT
;
904 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
905 pos
->cat2
.condition
= IR3_COND_GT
;
907 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
912 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
915 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
918 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
921 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
922 dst
[0]->cat2
.condition
= IR3_COND_LT
;
923 dst
[0] = ir3_n2b(b
, dst
[0]);
926 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
927 dst
[0]->cat2
.condition
= IR3_COND_GE
;
928 dst
[0] = ir3_n2b(b
, dst
[0]);
931 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
932 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
933 dst
[0] = ir3_n2b(b
, dst
[0]);
936 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
937 dst
[0]->cat2
.condition
= IR3_COND_NE
;
938 dst
[0] = ir3_n2b(b
, dst
[0]);
941 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
942 dst
[0]->cat2
.condition
= IR3_COND_LT
;
943 dst
[0] = ir3_n2b(b
, dst
[0]);
946 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
947 dst
[0]->cat2
.condition
= IR3_COND_GE
;
948 dst
[0] = ir3_n2b(b
, dst
[0]);
952 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
955 case nir_op_bit_count
:
956 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
958 case nir_op_ifind_msb
: {
959 struct ir3_instruction
*cmp
;
960 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
961 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
962 cmp
->cat2
.condition
= IR3_COND_GE
;
963 dst
[0] = ir3_SEL_B32(b
,
964 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
968 case nir_op_ufind_msb
:
969 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
970 dst
[0] = ir3_SEL_B32(b
,
971 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
972 src
[0], 0, dst
[0], 0);
974 case nir_op_find_lsb
:
975 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
976 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
978 case nir_op_bitfield_reverse
:
979 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
983 compile_error(ctx
, "Unhandled ALU op: %s\n",
984 nir_op_infos
[alu
->op
].name
);
989 /* handles direct/indirect UBO reads: */
991 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
992 struct ir3_instruction
**dst
)
994 struct ir3_block
*b
= ctx
->block
;
995 struct ir3_instruction
*addr
, *src0
, *src1
;
996 nir_const_value
*const_offset
;
997 /* UBO addresses are the first driver params: */
998 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1001 /* First src is ubo index, which could either be an immed or not: */
1002 src0
= get_src(ctx
, &intr
->src
[0])[0];
1003 if (is_same_type_mov(src0
) &&
1004 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1005 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1007 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1010 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1012 off
+= const_offset
->u32
[0];
1014 /* For load_ubo_indirect, second src is indirect offset: */
1015 src1
= get_src(ctx
, &intr
->src
[1])[0];
1017 /* and add offset to addr: */
1018 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1021 /* if offset is to large to encode in the ldg, split it out: */
1022 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1023 /* split out the minimal amount to improve the odds that
1024 * cp can fit the immediate in the add.s instruction:
1026 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1027 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1031 for (int i
= 0; i
< intr
->num_components
; i
++) {
1032 struct ir3_instruction
*load
=
1033 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1034 load
->cat6
.type
= TYPE_U32
;
1035 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1040 /* handles array reads: */
1042 emit_intrinsic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1043 struct ir3_instruction
**dst
)
1045 nir_deref_var
*dvar
= intr
->variables
[0];
1046 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1047 struct ir3_array
*arr
= get_var(ctx
, dvar
->var
);
1049 compile_assert(ctx
, dvar
->deref
.child
&&
1050 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1052 switch (darr
->deref_array_type
) {
1053 case nir_deref_array_type_direct
:
1054 /* direct access does not require anything special: */
1055 for (int i
= 0; i
< intr
->num_components
; i
++) {
1056 unsigned n
= darr
->base_offset
* 4 + i
;
1057 compile_assert(ctx
, n
< arr
->length
);
1058 dst
[i
] = create_var_load(ctx
, arr
, n
, NULL
);
1061 case nir_deref_array_type_indirect
: {
1062 /* for indirect, we need to collect all the array elements: */
1063 struct ir3_instruction
*addr
=
1064 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1065 for (int i
= 0; i
< intr
->num_components
; i
++) {
1066 unsigned n
= darr
->base_offset
* 4 + i
;
1067 compile_assert(ctx
, n
< arr
->length
);
1068 dst
[i
] = create_var_load(ctx
, arr
, n
, addr
);
1073 compile_error(ctx
, "Unhandled load deref type: %u\n",
1074 darr
->deref_array_type
);
1079 /* handles array writes: */
1081 emit_intrinsic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1083 nir_deref_var
*dvar
= intr
->variables
[0];
1084 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1085 struct ir3_array
*arr
= get_var(ctx
, dvar
->var
);
1086 struct ir3_instruction
*addr
;
1087 struct ir3_instruction
* const *src
;
1088 unsigned wrmask
= nir_intrinsic_write_mask(intr
);
1090 compile_assert(ctx
, dvar
->deref
.child
&&
1091 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1093 src
= get_src(ctx
, &intr
->src
[0]);
1095 switch (darr
->deref_array_type
) {
1096 case nir_deref_array_type_direct
:
1099 case nir_deref_array_type_indirect
:
1100 addr
= get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1103 compile_error(ctx
, "Unhandled store deref type: %u\n",
1104 darr
->deref_array_type
);
1108 for (int i
= 0; i
< intr
->num_components
; i
++) {
1109 if (!(wrmask
& (1 << i
)))
1111 unsigned n
= darr
->base_offset
* 4 + i
;
1112 compile_assert(ctx
, n
< arr
->length
);
1113 create_var_store(ctx
, arr
, n
, src
[i
], addr
);
1117 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1118 struct ir3_instruction
*instr
)
1120 struct ir3_shader_variant
*so
= ctx
->so
;
1121 unsigned r
= regid(so
->inputs_count
, 0);
1122 unsigned n
= so
->inputs_count
++;
1124 so
->inputs
[n
].sysval
= true;
1125 so
->inputs
[n
].slot
= slot
;
1126 so
->inputs
[n
].compmask
= 1;
1127 so
->inputs
[n
].regid
= r
;
1128 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1131 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1132 ctx
->ir
->inputs
[r
] = instr
;
1136 emit_intrinsic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1138 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1139 struct ir3_instruction
**dst
;
1140 struct ir3_instruction
* const *src
;
1141 struct ir3_block
*b
= ctx
->block
;
1142 nir_const_value
*const_offset
;
1145 if (info
->has_dest
) {
1146 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1151 switch (intr
->intrinsic
) {
1152 case nir_intrinsic_load_uniform
:
1153 idx
= nir_intrinsic_base(intr
);
1154 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1156 idx
+= const_offset
->u32
[0];
1157 for (int i
= 0; i
< intr
->num_components
; i
++) {
1158 unsigned n
= idx
* 4 + i
;
1159 dst
[i
] = create_uniform(ctx
, n
);
1162 src
= get_src(ctx
, &intr
->src
[0]);
1163 for (int i
= 0; i
< intr
->num_components
; i
++) {
1164 int n
= idx
* 4 + i
;
1165 dst
[i
] = create_uniform_indirect(ctx
, n
,
1166 get_addr(ctx
, src
[0]));
1168 /* NOTE: if relative addressing is used, we set
1169 * constlen in the compiler (to worst-case value)
1170 * since we don't know in the assembler what the max
1171 * addr reg value can be:
1173 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1176 case nir_intrinsic_load_ubo
:
1177 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1179 case nir_intrinsic_load_input
:
1180 idx
= nir_intrinsic_base(intr
);
1181 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1183 idx
+= const_offset
->u32
[0];
1184 for (int i
= 0; i
< intr
->num_components
; i
++) {
1185 unsigned n
= idx
* 4 + i
;
1186 dst
[i
] = ctx
->ir
->inputs
[n
];
1189 src
= get_src(ctx
, &intr
->src
[0]);
1190 struct ir3_instruction
*collect
=
1191 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1192 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1193 for (int i
= 0; i
< intr
->num_components
; i
++) {
1194 unsigned n
= idx
* 4 + i
;
1195 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1200 case nir_intrinsic_load_var
:
1201 emit_intrinsic_load_var(ctx
, intr
, dst
);
1203 case nir_intrinsic_store_var
:
1204 emit_intrinsic_store_var(ctx
, intr
);
1206 case nir_intrinsic_store_output
:
1207 idx
= nir_intrinsic_base(intr
);
1208 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1209 compile_assert(ctx
, const_offset
!= NULL
);
1210 idx
+= const_offset
->u32
[0];
1212 src
= get_src(ctx
, &intr
->src
[0]);
1213 for (int i
= 0; i
< intr
->num_components
; i
++) {
1214 unsigned n
= idx
* 4 + i
;
1215 ctx
->ir
->outputs
[n
] = src
[i
];
1218 case nir_intrinsic_load_base_vertex
:
1219 if (!ctx
->basevertex
) {
1220 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1221 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1224 dst
[0] = ctx
->basevertex
;
1226 case nir_intrinsic_load_vertex_id_zero_base
:
1227 if (!ctx
->vertex_id
) {
1228 ctx
->vertex_id
= create_input(b
, 0);
1229 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
1232 dst
[0] = ctx
->vertex_id
;
1234 case nir_intrinsic_load_instance_id
:
1235 if (!ctx
->instance_id
) {
1236 ctx
->instance_id
= create_input(b
, 0);
1237 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1240 dst
[0] = ctx
->instance_id
;
1242 case nir_intrinsic_load_user_clip_plane
:
1243 idx
= nir_intrinsic_ucp_id(intr
);
1244 for (int i
= 0; i
< intr
->num_components
; i
++) {
1245 unsigned n
= idx
* 4 + i
;
1246 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1249 case nir_intrinsic_load_front_face
:
1250 if (!ctx
->frag_face
) {
1251 ctx
->so
->frag_face
= true;
1252 ctx
->frag_face
= create_input(b
, 0);
1253 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1255 /* for fragface, we always get -1 or 0, but that is inverse
1256 * of what nir expects (where ~0 is true). Unfortunately
1257 * trying to widen from half to full in add.s seems to do a
1258 * non-sign-extending widen (resulting in something that
1259 * gets interpreted as float Inf??)
1261 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1262 dst
[0] = ir3_ADD_S(b
, dst
[0], 0, create_immed(b
, 1), 0);
1264 case nir_intrinsic_discard_if
:
1265 case nir_intrinsic_discard
: {
1266 struct ir3_instruction
*cond
, *kill
;
1268 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1269 /* conditional discard: */
1270 src
= get_src(ctx
, &intr
->src
[0]);
1271 cond
= ir3_b2n(b
, src
[0]);
1273 /* unconditional discard: */
1274 cond
= create_immed(b
, 1);
1277 /* NOTE: only cmps.*.* can write p0.x: */
1278 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1279 cond
->cat2
.condition
= IR3_COND_NE
;
1281 /* condition always goes in predicate register: */
1282 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1284 kill
= ir3_KILL(b
, cond
, 0);
1285 array_insert(ctx
->ir
->predicates
, kill
);
1287 array_insert(ctx
->ir
->keeps
, kill
);
1288 ctx
->so
->has_kill
= true;
1293 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1294 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1300 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1302 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1303 instr
->def
.num_components
);
1304 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1305 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
1309 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1311 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1312 undef
->def
.num_components
);
1313 /* backend doesn't want undefined instructions, so just plug
1316 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1317 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1321 * texture fetch/sample instructions:
1325 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1327 unsigned coords
, flags
= 0;
1329 /* note: would use tex->coord_components.. except txs.. also,
1330 * since array index goes after shadow ref, we don't want to
1333 switch (tex
->sampler_dim
) {
1334 case GLSL_SAMPLER_DIM_1D
:
1335 case GLSL_SAMPLER_DIM_BUF
:
1338 case GLSL_SAMPLER_DIM_2D
:
1339 case GLSL_SAMPLER_DIM_RECT
:
1340 case GLSL_SAMPLER_DIM_EXTERNAL
:
1341 case GLSL_SAMPLER_DIM_MS
:
1344 case GLSL_SAMPLER_DIM_3D
:
1345 case GLSL_SAMPLER_DIM_CUBE
:
1347 flags
|= IR3_INSTR_3D
;
1350 unreachable("bad sampler_dim");
1353 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1354 flags
|= IR3_INSTR_S
;
1356 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1357 flags
|= IR3_INSTR_A
;
1364 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1366 struct ir3_block
*b
= ctx
->block
;
1367 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1368 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1369 struct ir3_instruction
*lod
, *compare
, *proj
;
1370 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1371 unsigned i
, coords
, flags
;
1372 unsigned nsrc0
= 0, nsrc1
= 0;
1376 coord
= off
= ddx
= ddy
= NULL
;
1377 lod
= proj
= compare
= NULL
;
1379 /* TODO: might just be one component for gathers? */
1380 dst
= get_dst(ctx
, &tex
->dest
, 4);
1382 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1383 switch (tex
->src
[i
].src_type
) {
1384 case nir_tex_src_coord
:
1385 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1387 case nir_tex_src_bias
:
1388 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1391 case nir_tex_src_lod
:
1392 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1395 case nir_tex_src_comparator
: /* shadow comparator */
1396 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1398 case nir_tex_src_projector
:
1399 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1402 case nir_tex_src_offset
:
1403 off
= get_src(ctx
, &tex
->src
[i
].src
);
1406 case nir_tex_src_ddx
:
1407 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1409 case nir_tex_src_ddy
:
1410 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1413 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
1414 tex
->src
[i
].src_type
);
1420 case nir_texop_tex
: opc
= OPC_SAM
; break;
1421 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1422 case nir_texop_txl
: opc
= OPC_SAML
; break;
1423 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1424 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1425 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1426 case nir_texop_txf_ms
:
1429 case nir_texop_query_levels
:
1430 case nir_texop_texture_samples
:
1431 case nir_texop_samples_identical
:
1432 case nir_texop_txf_ms_mcs
:
1433 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1437 tex_info(tex
, &flags
, &coords
);
1440 * lay out the first argument in the proper order:
1441 * - actual coordinates first
1442 * - shadow reference
1445 * - starting at offset 4, dpdx.xy, dpdy.xy
1447 * bias/lod go into the second arg
1450 /* insert tex coords: */
1451 for (i
= 0; i
< coords
; i
++)
1456 /* scale up integer coords for TXF based on the LOD */
1457 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1459 for (i
= 0; i
< coords
; i
++)
1460 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
1464 /* hw doesn't do 1d, so we treat it as 2d with
1465 * height of 1, and patch up the y coord.
1466 * TODO: y coord should be (int)0 in some cases..
1468 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1471 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1472 src0
[nsrc0
++] = compare
;
1474 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
1475 struct ir3_instruction
*idx
= coord
[coords
];
1477 /* the array coord for cube arrays needs 0.5 added to it */
1478 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
1479 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
1481 src0
[nsrc0
++] = idx
;
1485 src0
[nsrc0
++] = proj
;
1486 flags
|= IR3_INSTR_P
;
1489 /* pad to 4, then ddx/ddy: */
1490 if (tex
->op
== nir_texop_txd
) {
1492 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1493 for (i
= 0; i
< coords
; i
++)
1494 src0
[nsrc0
++] = ddx
[i
];
1496 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1497 for (i
= 0; i
< coords
; i
++)
1498 src0
[nsrc0
++] = ddy
[i
];
1500 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1504 * second argument (if applicable):
1509 if (has_off
| has_lod
| has_bias
) {
1511 for (i
= 0; i
< coords
; i
++)
1512 src1
[nsrc1
++] = off
[i
];
1514 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1515 flags
|= IR3_INSTR_O
;
1518 if (has_lod
| has_bias
)
1519 src1
[nsrc1
++] = lod
;
1522 switch (tex
->dest_type
) {
1523 case nir_type_invalid
:
1524 case nir_type_float
:
1535 unreachable("bad dest_type");
1538 if (opc
== OPC_GETLOD
)
1541 unsigned tex_idx
= tex
->texture_index
;
1543 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
1545 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
1546 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
1548 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1549 tex_idx
, tex_idx
, col0
, col1
);
1551 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
1552 /* only need first 3 components: */
1553 sam
->regs
[0]->wrmask
= 0x7;
1554 split_dest(b
, dst
, sam
, 0, 3);
1556 /* we need to sample the alpha separately with a non-ASTC
1559 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
1560 tex_idx
, tex_idx
, col0
, col1
);
1562 array_insert(ctx
->ir
->astc_srgb
, sam
);
1564 /* fixup .w component: */
1565 split_dest(b
, &dst
[3], sam
, 3, 1);
1567 /* normal (non-workaround) case: */
1568 split_dest(b
, dst
, sam
, 0, 4);
1571 /* GETLOD returns results in 4.8 fixed point */
1572 if (opc
== OPC_GETLOD
) {
1573 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1575 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1576 for (i
= 0; i
< 2; i
++) {
1577 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1584 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1586 struct ir3_block
*b
= ctx
->block
;
1587 struct ir3_instruction
**dst
, *sam
;
1589 dst
= get_dst(ctx
, &tex
->dest
, 1);
1591 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1592 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
1594 /* even though there is only one component, since it ends
1595 * up in .z rather than .x, we need a split_dest()
1597 split_dest(b
, dst
, sam
, 0, 3);
1599 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1600 * the value in TEX_CONST_0 is zero-based.
1602 if (ctx
->levels_add_one
)
1603 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1607 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1609 struct ir3_block
*b
= ctx
->block
;
1610 struct ir3_instruction
**dst
, *sam
;
1611 struct ir3_instruction
*lod
;
1612 unsigned flags
, coords
;
1614 tex_info(tex
, &flags
, &coords
);
1616 /* Actually we want the number of dimensions, not coordinates. This
1617 * distinction only matters for cubes.
1619 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1622 dst
= get_dst(ctx
, &tex
->dest
, 4);
1624 compile_assert(ctx
, tex
->num_srcs
== 1);
1625 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1627 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1629 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1630 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
1632 split_dest(b
, dst
, sam
, 0, 4);
1634 /* Array size actually ends up in .w rather than .z. This doesn't
1635 * matter for miplevel 0, but for higher mips the value in z is
1636 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1637 * returned, which means that we have to add 1 to it for arrays.
1639 if (tex
->is_array
) {
1640 if (ctx
->levels_add_one
) {
1641 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1643 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1649 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1651 struct ir3_instruction
*phi
, **dst
;
1653 /* NOTE: phi's should be lowered to scalar at this point */
1654 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1656 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1658 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
1659 1 + exec_list_length(&nphi
->srcs
));
1660 ir3_reg_create(phi
, 0, 0); /* dst */
1661 phi
->phi
.nphi
= nphi
;
1666 /* phi instructions are left partially constructed. We don't resolve
1667 * their srcs until the end of the block, since (eg. loops) one of
1668 * the phi's srcs might be defined after the phi due to back edges in
1672 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1674 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1675 nir_phi_instr
*nphi
;
1677 /* phi's only come at start of block: */
1678 if (instr
->opc
!= OPC_META_PHI
)
1681 if (!instr
->phi
.nphi
)
1684 nphi
= instr
->phi
.nphi
;
1685 instr
->phi
.nphi
= NULL
;
1687 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1688 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1690 /* NOTE: src might not be in the same block as it comes from
1691 * according to the phi.. but in the end the backend assumes
1692 * it will be able to assign the same register to each (which
1693 * only works if it is assigned in the src block), so insert
1694 * an extra mov to make sure the phi src is assigned in the
1695 * block it comes from:
1697 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
1699 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1705 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1707 switch (jump
->type
) {
1708 case nir_jump_break
:
1709 case nir_jump_continue
:
1710 /* I *think* we can simply just ignore this, and use the
1711 * successor block link to figure out where we need to
1712 * jump to for break/continue
1716 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1722 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1724 switch (instr
->type
) {
1725 case nir_instr_type_alu
:
1726 emit_alu(ctx
, nir_instr_as_alu(instr
));
1728 case nir_instr_type_intrinsic
:
1729 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1731 case nir_instr_type_load_const
:
1732 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1734 case nir_instr_type_ssa_undef
:
1735 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1737 case nir_instr_type_tex
: {
1738 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1739 /* couple tex instructions get special-cased:
1743 emit_tex_txs(ctx
, tex
);
1745 case nir_texop_query_levels
:
1746 emit_tex_query_levels(ctx
, tex
);
1754 case nir_instr_type_phi
:
1755 emit_phi(ctx
, nir_instr_as_phi(instr
));
1757 case nir_instr_type_jump
:
1758 emit_jump(ctx
, nir_instr_as_jump(instr
));
1760 case nir_instr_type_call
:
1761 case nir_instr_type_parallel_copy
:
1762 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1767 static struct ir3_block
*
1768 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1770 struct ir3_block
*block
;
1771 struct hash_entry
*entry
;
1772 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1776 block
= ir3_block_create(ctx
->ir
);
1777 block
->nblock
= nblock
;
1778 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1784 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1786 struct ir3_block
*block
= get_block(ctx
, nblock
);
1788 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1789 if (nblock
->successors
[i
]) {
1790 block
->successors
[i
] =
1791 get_block(ctx
, nblock
->successors
[i
]);
1796 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1798 /* re-emit addr register in each block if needed: */
1799 _mesa_hash_table_destroy(ctx
->addr_ht
, NULL
);
1800 ctx
->addr_ht
= NULL
;
1802 nir_foreach_instr(instr
, nblock
) {
1803 emit_instr(ctx
, instr
);
1809 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1812 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1814 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1816 ctx
->block
->condition
=
1817 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1819 emit_cf_list(ctx
, &nif
->then_list
);
1820 emit_cf_list(ctx
, &nif
->else_list
);
1824 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1826 emit_cf_list(ctx
, &nloop
->body
);
1830 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1832 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1833 switch (node
->type
) {
1834 case nir_cf_node_block
:
1835 emit_block(ctx
, nir_cf_node_as_block(node
));
1837 case nir_cf_node_if
:
1838 emit_if(ctx
, nir_cf_node_as_if(node
));
1840 case nir_cf_node_loop
:
1841 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1843 case nir_cf_node_function
:
1844 compile_error(ctx
, "TODO\n");
1850 /* emit stream-out code. At this point, the current block is the original
1851 * (nir) end block, and nir ensures that all flow control paths terminate
1852 * into the end block. We re-purpose the original end block to generate
1853 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
1854 * block holding stream-out write instructions, followed by the new end
1858 * p0.x = (vtxcnt < maxvtxcnt)
1859 * // succs: blockStreamOut, blockNewEnd
1862 * ... stream-out instructions ...
1863 * // succs: blockNewEnd
1869 emit_stream_out(struct ir3_compile
*ctx
)
1871 struct ir3_shader_variant
*v
= ctx
->so
;
1872 struct ir3
*ir
= ctx
->ir
;
1873 struct pipe_stream_output_info
*strmout
=
1874 &ctx
->so
->shader
->stream_output
;
1875 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
1876 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
1877 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
1879 /* create vtxcnt input in input block at top of shader,
1880 * so that it is seen as live over the entire duration
1883 vtxcnt
= create_input(ctx
->in_block
, 0);
1884 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
1886 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
1888 /* at this point, we are at the original 'end' block,
1889 * re-purpose this block to stream-out condition, then
1890 * append stream-out block and new-end block
1892 orig_end_block
= ctx
->block
;
1894 stream_out_block
= ir3_block_create(ir
);
1895 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
1897 new_end_block
= ir3_block_create(ir
);
1898 list_addtail(&new_end_block
->node
, &ir
->block_list
);
1900 orig_end_block
->successors
[0] = stream_out_block
;
1901 orig_end_block
->successors
[1] = new_end_block
;
1902 stream_out_block
->successors
[0] = new_end_block
;
1904 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
1905 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
1906 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1907 cond
->cat2
.condition
= IR3_COND_LT
;
1909 /* condition goes on previous block to the conditional,
1910 * since it is used to pick which of the two successor
1913 orig_end_block
->condition
= cond
;
1915 /* switch to stream_out_block to generate the stream-out
1918 ctx
->block
= stream_out_block
;
1920 /* Calculate base addresses based on vtxcnt. Instructions
1921 * generated for bases not used in following loop will be
1922 * stripped out in the backend.
1924 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1925 unsigned stride
= strmout
->stride
[i
];
1926 struct ir3_instruction
*base
, *off
;
1928 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
1930 /* 24-bit should be enough: */
1931 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
1932 create_immed(ctx
->block
, stride
* 4), 0);
1934 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
1937 /* Generate the per-output store instructions: */
1938 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
1939 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
1940 unsigned c
= j
+ strmout
->output
[i
].start_component
;
1941 struct ir3_instruction
*base
, *out
, *stg
;
1943 base
= bases
[strmout
->output
[i
].output_buffer
];
1944 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
1946 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
1947 create_immed(ctx
->block
, 1), 0);
1948 stg
->cat6
.type
= TYPE_U32
;
1949 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
1951 array_insert(ctx
->ir
->keeps
, stg
);
1955 /* and finally switch to the new_end_block: */
1956 ctx
->block
= new_end_block
;
1960 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
1962 nir_metadata_require(impl
, nir_metadata_block_index
);
1964 emit_cf_list(ctx
, &impl
->body
);
1965 emit_block(ctx
, impl
->end_block
);
1967 /* at this point, we should have a single empty block,
1968 * into which we emit the 'end' instruction.
1970 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
1972 /* If stream-out (aka transform-feedback) enabled, emit the
1973 * stream-out instructions, followed by a new empty block (into
1974 * which the 'end' instruction lands).
1976 * NOTE: it is done in this order, rather than inserting before
1977 * we emit end_block, because NIR guarantees that all blocks
1978 * flow into end_block, and that end_block has no successors.
1979 * So by re-purposing end_block as the first block of stream-
1980 * out, we guarantee that all exit paths flow into the stream-
1983 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
1984 !ctx
->so
->key
.binning_pass
) {
1985 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
1986 emit_stream_out(ctx
);
1989 ir3_END(ctx
->block
);
1993 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
1995 struct ir3_shader_variant
*so
= ctx
->so
;
1996 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
1997 unsigned ncomp
= glsl_get_components(in
->type
);
1998 unsigned n
= in
->data
.driver_location
;
1999 unsigned slot
= in
->data
.location
;
2001 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2002 slot
, array_len
, ncomp
, n
);
2004 /* let's pretend things other than vec4 don't exist: */
2005 ncomp
= MAX2(ncomp
, 4);
2006 compile_assert(ctx
, ncomp
== 4);
2008 so
->inputs
[n
].slot
= slot
;
2009 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2010 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2011 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2013 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2014 for (int i
= 0; i
< ncomp
; i
++) {
2015 struct ir3_instruction
*instr
= NULL
;
2016 unsigned idx
= (n
* 4) + i
;
2018 if (slot
== VARYING_SLOT_POS
) {
2019 so
->inputs
[n
].bary
= false;
2020 so
->frag_coord
= true;
2021 instr
= create_frag_coord(ctx
, i
);
2022 } else if (slot
== VARYING_SLOT_PNTC
) {
2023 /* see for example st_get_generic_varying_index().. this is
2024 * maybe a bit mesa/st specific. But we need things to line
2025 * up for this in fdN_program:
2026 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2027 * if (emit->sprite_coord_enable & texmask) {
2031 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2032 so
->inputs
[n
].bary
= true;
2033 instr
= create_frag_input(ctx
, false);
2035 bool use_ldlv
= false;
2037 /* detect the special case for front/back colors where
2038 * we need to do flat vs smooth shading depending on
2041 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2043 case VARYING_SLOT_COL0
:
2044 case VARYING_SLOT_COL1
:
2045 case VARYING_SLOT_BFC0
:
2046 case VARYING_SLOT_BFC1
:
2047 so
->inputs
[n
].rasterflat
= true;
2054 if (ctx
->flat_bypass
) {
2055 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2056 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2060 so
->inputs
[n
].bary
= true;
2062 instr
= create_frag_input(ctx
, use_ldlv
);
2065 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2067 ctx
->ir
->inputs
[idx
] = instr
;
2069 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2070 for (int i
= 0; i
< ncomp
; i
++) {
2071 unsigned idx
= (n
* 4) + i
;
2072 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2073 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2076 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2079 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2080 so
->total_in
+= ncomp
;
2085 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2087 struct ir3_shader_variant
*so
= ctx
->so
;
2088 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2089 unsigned ncomp
= glsl_get_components(out
->type
);
2090 unsigned n
= out
->data
.driver_location
;
2091 unsigned slot
= out
->data
.location
;
2094 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2095 slot
, array_len
, ncomp
, n
);
2097 /* let's pretend things other than vec4 don't exist: */
2098 ncomp
= MAX2(ncomp
, 4);
2099 compile_assert(ctx
, ncomp
== 4);
2101 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2103 case FRAG_RESULT_DEPTH
:
2104 comp
= 2; /* tgsi will write to .z component */
2105 so
->writes_pos
= true;
2107 case FRAG_RESULT_COLOR
:
2111 if (slot
>= FRAG_RESULT_DATA0
)
2113 compile_error(ctx
, "unknown FS output name: %s\n",
2114 gl_frag_result_name(slot
));
2116 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2118 case VARYING_SLOT_POS
:
2119 so
->writes_pos
= true;
2121 case VARYING_SLOT_PSIZ
:
2122 so
->writes_psize
= true;
2124 case VARYING_SLOT_COL0
:
2125 case VARYING_SLOT_COL1
:
2126 case VARYING_SLOT_BFC0
:
2127 case VARYING_SLOT_BFC1
:
2128 case VARYING_SLOT_FOGC
:
2129 case VARYING_SLOT_CLIP_DIST0
:
2130 case VARYING_SLOT_CLIP_DIST1
:
2132 case VARYING_SLOT_CLIP_VERTEX
:
2133 /* handled entirely in nir_lower_clip: */
2136 if (slot
>= VARYING_SLOT_VAR0
)
2138 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2140 compile_error(ctx
, "unknown VS output name: %s\n",
2141 gl_varying_slot_name(slot
));
2144 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2147 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2149 so
->outputs
[n
].slot
= slot
;
2150 so
->outputs
[n
].regid
= regid(n
, comp
);
2151 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2153 for (int i
= 0; i
< ncomp
; i
++) {
2154 unsigned idx
= (n
* 4) + i
;
2155 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
2156 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2161 max_drvloc(struct exec_list
*vars
)
2164 nir_foreach_variable(var
, vars
) {
2165 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2171 emit_instructions(struct ir3_compile
*ctx
)
2173 unsigned ninputs
, noutputs
;
2174 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2176 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2177 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2179 /* or vtx shaders, we need to leave room for sysvals:
2181 if (ctx
->so
->type
== SHADER_VERTEX
) {
2185 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2187 /* Create inputs in first block: */
2188 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2189 ctx
->in_block
= ctx
->block
;
2190 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2192 if (ctx
->so
->type
== SHADER_VERTEX
) {
2193 ctx
->ir
->ninputs
-= 16;
2196 /* for fragment shader, we have a single input register (usually
2197 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2199 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2200 // TODO maybe a helper for fi since we need it a few places..
2201 struct ir3_instruction
*instr
;
2202 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
2203 ir3_reg_create(instr
, 0, 0);
2204 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2205 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2206 ctx
->frag_pos
= instr
;
2210 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2211 setup_input(ctx
, var
);
2214 /* Setup outputs: */
2215 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2216 setup_output(ctx
, var
);
2219 /* Setup global variables (which should only be arrays): */
2220 nir_foreach_variable(var
, &ctx
->s
->globals
) {
2221 declare_var(ctx
, var
);
2224 /* Setup local variables (which should only be arrays): */
2225 /* NOTE: need to do something more clever when we support >1 fxn */
2226 nir_foreach_variable(var
, &fxn
->locals
) {
2227 declare_var(ctx
, var
);
2230 /* And emit the body: */
2232 emit_function(ctx
, fxn
);
2234 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2235 resolve_phis(ctx
, block
);
2239 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2240 * for a fragment shader are just bary.f instructions. The *actual* inputs
2241 * from the hw perspective are the frag_pos and optionally frag_coord and
2245 fixup_frag_inputs(struct ir3_compile
*ctx
)
2247 struct ir3_shader_variant
*so
= ctx
->so
;
2248 struct ir3
*ir
= ctx
->ir
;
2249 struct ir3_instruction
**inputs
;
2250 struct ir3_instruction
*instr
;
2255 n
= 4; /* always have frag_pos */
2256 n
+= COND(so
->frag_face
, 4);
2257 n
+= COND(so
->frag_coord
, 4);
2259 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2261 if (so
->frag_face
) {
2262 /* this ultimately gets assigned to hr0.x so doesn't conflict
2263 * with frag_coord/frag_pos..
2265 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2266 ctx
->frag_face
->regs
[0]->num
= 0;
2268 /* remaining channels not used, but let's avoid confusing
2269 * other parts that expect inputs to come in groups of vec4
2271 inputs
[ir
->ninputs
++] = NULL
;
2272 inputs
[ir
->ninputs
++] = NULL
;
2273 inputs
[ir
->ninputs
++] = NULL
;
2276 /* since we don't know where to set the regid for frag_coord,
2277 * we have to use r0.x for it. But we don't want to *always*
2278 * use r1.x for frag_pos as that could increase the register
2279 * footprint on simple shaders:
2281 if (so
->frag_coord
) {
2282 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2283 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2284 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2285 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2287 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2288 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2289 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2290 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2293 /* we always have frag_pos: */
2294 so
->pos_regid
= regid
;
2297 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2298 instr
->regs
[0]->num
= regid
++;
2299 inputs
[ir
->ninputs
++] = instr
;
2300 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2303 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2304 instr
->regs
[0]->num
= regid
++;
2305 inputs
[ir
->ninputs
++] = instr
;
2306 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2308 ir
->inputs
= inputs
;
2311 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2312 * need to assign the tex state indexes for these after we know the
2316 fixup_astc_srgb(struct ir3_compile
*ctx
)
2318 struct ir3_shader_variant
*so
= ctx
->so
;
2319 /* indexed by original tex idx, value is newly assigned alpha sampler
2320 * state tex idx. Zero is invalid since there is at least one sampler
2323 unsigned alt_tex_state
[16] = {0};
2324 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2327 so
->astc_srgb
.base
= tex_idx
;
2329 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2330 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2332 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2334 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2335 /* assign new alternate/alpha tex state slot: */
2336 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2337 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2338 so
->astc_srgb
.count
++;
2341 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2346 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2347 struct ir3_shader_variant
*so
)
2349 struct ir3_compile
*ctx
;
2351 struct ir3_instruction
**inputs
;
2352 unsigned i
, j
, actual_in
, inloc
;
2353 int ret
= 0, max_bary
;
2357 ctx
= compile_init(compiler
, so
);
2359 DBG("INIT failed!");
2364 emit_instructions(ctx
);
2367 DBG("EMIT failed!");
2372 ir
= so
->ir
= ctx
->ir
;
2374 /* keep track of the inputs from TGSI perspective.. */
2375 inputs
= ir
->inputs
;
2377 /* but fixup actual inputs for frag shader: */
2378 if (so
->type
== SHADER_FRAGMENT
)
2379 fixup_frag_inputs(ctx
);
2381 /* at this point, for binning pass, throw away unneeded outputs: */
2382 if (so
->key
.binning_pass
) {
2383 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2384 unsigned slot
= so
->outputs
[i
].slot
;
2386 /* throw away everything but first position/psize */
2387 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2389 so
->outputs
[j
] = so
->outputs
[i
];
2390 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2391 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2392 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2393 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2398 so
->outputs_count
= j
;
2399 ir
->noutputs
= j
* 4;
2402 /* if we want half-precision outputs, mark the output registers
2405 if (so
->key
.half_precision
) {
2406 for (i
= 0; i
< ir
->noutputs
; i
++) {
2407 struct ir3_instruction
*out
= ir
->outputs
[i
];
2410 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2411 /* output could be a fanout (ie. texture fetch output)
2412 * in which case we need to propagate the half-reg flag
2413 * up to the definer so that RA sees it:
2415 if (out
->opc
== OPC_META_FO
) {
2416 out
= out
->regs
[1]->instr
;
2417 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2420 if (out
->opc
== OPC_MOV
) {
2421 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2426 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2427 printf("BEFORE CP:\n");
2433 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2434 printf("BEFORE GROUPING:\n");
2438 /* Group left/right neighbors, inserting mov's where needed to
2445 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2446 printf("AFTER DEPTH:\n");
2450 ret
= ir3_sched(ir
);
2452 DBG("SCHED failed!");
2456 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2457 printf("AFTER SCHED:\n");
2461 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2467 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2468 printf("AFTER RA:\n");
2472 /* fixup input/outputs: */
2473 for (i
= 0; i
< so
->outputs_count
; i
++) {
2474 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2477 /* Note that some or all channels of an input may be unused: */
2480 for (i
= 0; i
< so
->inputs_count
; i
++) {
2481 unsigned j
, regid
= ~0, compmask
= 0;
2482 so
->inputs
[i
].ncomp
= 0;
2483 so
->inputs
[i
].inloc
= inloc
;
2484 for (j
= 0; j
< 4; j
++) {
2485 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2486 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2487 compmask
|= (1 << j
);
2488 regid
= in
->regs
[0]->num
- j
;
2490 so
->inputs
[i
].ncomp
++;
2491 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2493 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2494 in
->regs
[1]->iim_val
= inloc
++;
2498 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
)
2500 so
->inputs
[i
].regid
= regid
;
2501 so
->inputs
[i
].compmask
= compmask
;
2505 fixup_astc_srgb(ctx
);
2507 /* We need to do legalize after (for frag shader's) the "bary.f"
2508 * offsets (inloc) have been assigned.
2510 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2512 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2513 printf("AFTER LEGALIZE:\n");
2517 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2518 if (so
->type
== SHADER_VERTEX
)
2519 so
->total_in
= actual_in
;
2521 so
->total_in
= max_bary
+ 1;
2526 ir3_destroy(so
->ir
);