2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "ir3/ir3_nir.h"
29 /* This has to reach into the fd_context a bit more than the rest of
30 * ir3, but it needs to be aligned with the compiler, so both agree
31 * on which const regs hold what. And the logic is identical between
32 * ir3 generations, the only difference is small details in the actual
33 * CP_LOAD_STATE packets (which is handled inside the generation
34 * specific ctx->emit_const(_bo)() fxns)
36 * This file should be included in only a single .c file per gen, which
37 * defines the following functions:
40 static bool is_stateobj(struct fd_ringbuffer
*ring
);
42 static void emit_const(struct fd_ringbuffer
*ring
,
43 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
44 uint32_t offset
, uint32_t size
,
45 const void *user_buffer
, struct pipe_resource
*buffer
);
47 static void emit_const_bo(struct fd_ringbuffer
*ring
,
48 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
49 uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
);
53 ring_wfi(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
55 /* when we emit const state via ring (IB2) we need a WFI, but when
56 * it is emit'd via stateobj, we don't
58 if (is_stateobj(ring
))
65 * Indirectly calculates size of cmdstream needed for ir3_emit_user_consts().
66 * Returns number of packets, and total size of all the payload.
68 * The value can be a worst-case, ie. some shader variants may not read all
71 * Returns size in dwords.
74 ir3_user_consts_size(struct ir3_ubo_analysis_state
*state
,
75 unsigned *packets
, unsigned *size
)
79 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->range
); i
++) {
80 if (state
->range
[i
].start
< state
->range
[i
].end
) {
81 *size
+= state
->range
[i
].end
- state
->range
[i
].start
;
88 * Uploads sub-ranges of UBOs to the hardware's constant buffer (UBO access
89 * outside of these ranges will be done using full UBO accesses in the
93 ir3_emit_user_consts(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
94 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
96 const struct ir3_const_state
*const_state
= ir3_const_state(v
);
97 const struct ir3_ubo_analysis_state
*state
= &const_state
->ubo_state
;
99 for (unsigned i
= 0; i
< state
->num_enabled
; i
++) {
100 assert(!state
->range
[i
].ubo
.bindless
);
101 unsigned ubo
= state
->range
[i
].ubo
.block
;
102 if (!(constbuf
->enabled_mask
& (1 << ubo
)))
104 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[ubo
];
106 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
107 uint32_t offset
= cb
->buffer_offset
+ state
->range
[i
].start
;
109 /* Pre-a6xx, we might have ranges enabled in the shader that aren't
110 * used in the binning variant.
112 if (16 * v
->constlen
<= state
->range
[i
].offset
)
115 /* and even if the start of the const buffer is before
116 * first_immediate, the end may not be:
118 size
= MIN2(size
, (16 * v
->constlen
) - state
->range
[i
].offset
);
123 /* things should be aligned to vec4: */
124 debug_assert((state
->range
[i
].offset
% 16) == 0);
125 debug_assert((size
% 16) == 0);
126 debug_assert((offset
% 16) == 0);
128 emit_const(ring
, v
, state
->range
[i
].offset
/ 4,
129 offset
, size
/ 4, cb
->user_buffer
, cb
->buffer
);
134 ir3_emit_ubos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
135 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
137 const struct ir3_const_state
*const_state
= ir3_const_state(v
);
138 uint32_t offset
= const_state
->offsets
.ubo
;
140 /* a6xx+ uses UBO state and ldc instead of pointers emitted in
141 * const state and ldg:
143 if (ctx
->screen
->gpu_id
>= 600)
146 if (v
->constlen
> offset
) {
147 uint32_t params
= const_state
->num_ubos
;
148 uint32_t offsets
[params
];
149 struct pipe_resource
*prscs
[params
];
151 for (uint32_t i
= 0; i
< params
; i
++) {
152 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[i
];
154 /* If we have user pointers (constbuf 0, aka GL uniforms), upload
155 * them to a buffer now, and save it in the constbuf so that we
156 * don't have to reupload until they get changed.
158 if (cb
->user_buffer
) {
159 struct pipe_context
*pctx
= &ctx
->base
;
160 u_upload_data(pctx
->stream_uploader
, 0,
164 &cb
->buffer_offset
, &cb
->buffer
);
165 cb
->user_buffer
= NULL
;
168 if ((constbuf
->enabled_mask
& (1 << i
)) && cb
->buffer
) {
169 offsets
[i
] = cb
->buffer_offset
;
170 prscs
[i
] = cb
->buffer
;
177 assert(offset
* 4 + params
<= v
->constlen
* 4);
179 emit_const_bo(ring
, v
, offset
* 4, params
, prscs
, offsets
);
184 ir3_emit_ssbo_sizes(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
185 struct fd_ringbuffer
*ring
, struct fd_shaderbuf_stateobj
*sb
)
187 const struct ir3_const_state
*const_state
= ir3_const_state(v
);
188 uint32_t offset
= const_state
->offsets
.ssbo_sizes
;
189 if (v
->constlen
> offset
) {
190 uint32_t sizes
[align(const_state
->ssbo_size
.count
, 4)];
191 unsigned mask
= const_state
->ssbo_size
.mask
;
194 unsigned index
= u_bit_scan(&mask
);
195 unsigned off
= const_state
->ssbo_size
.off
[index
];
196 sizes
[off
] = sb
->sb
[index
].buffer_size
;
199 emit_const(ring
, v
, offset
* 4, 0, ARRAY_SIZE(sizes
), sizes
, NULL
);
204 ir3_emit_image_dims(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
205 struct fd_ringbuffer
*ring
, struct fd_shaderimg_stateobj
*si
)
207 const struct ir3_const_state
*const_state
= ir3_const_state(v
);
208 uint32_t offset
= const_state
->offsets
.image_dims
;
209 if (v
->constlen
> offset
) {
210 uint32_t dims
[align(const_state
->image_dims
.count
, 4)];
211 unsigned mask
= const_state
->image_dims
.mask
;
214 struct pipe_image_view
*img
;
215 struct fd_resource
*rsc
;
216 unsigned index
= u_bit_scan(&mask
);
217 unsigned off
= const_state
->image_dims
.off
[index
];
219 img
= &si
->si
[index
];
220 rsc
= fd_resource(img
->resource
);
222 dims
[off
+ 0] = util_format_get_blocksize(img
->format
);
223 if (img
->resource
->target
!= PIPE_BUFFER
) {
224 struct fdl_slice
*slice
=
225 fd_resource_slice(rsc
, img
->u
.tex
.level
);
226 /* note for 2d/cube/etc images, even if re-interpreted
227 * as a different color format, the pixel size should
228 * be the same, so use original dimensions for y and z
231 dims
[off
+ 1] = slice
->pitch
;
232 /* see corresponding logic in fd_resource_offset(): */
233 if (rsc
->layout
.layer_first
) {
234 dims
[off
+ 2] = rsc
->layout
.layer_size
;
236 dims
[off
+ 2] = slice
->size0
;
239 /* For buffer-backed images, the log2 of the format's
240 * bytes-per-pixel is placed on the 2nd slot. This is useful
241 * when emitting image_size instructions, for which we need
242 * to divide by bpp for image buffers. Since the bpp
243 * can only be power-of-two, the division is implemented
244 * as a SHR, and for that it is handy to have the log2 of
245 * bpp as a constant. (log2 = first-set-bit - 1)
247 dims
[off
+ 1] = ffs(dims
[off
+ 0]) - 1;
250 uint32_t size
= MIN2(ARRAY_SIZE(dims
), v
->constlen
* 4 - offset
* 4);
252 emit_const(ring
, v
, offset
* 4, 0, size
, dims
, NULL
);
257 ir3_emit_immediates(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
258 struct fd_ringbuffer
*ring
)
260 const struct ir3_const_state
*const_state
= ir3_const_state(v
);
261 uint32_t base
= const_state
->offsets
.immediate
;
262 int size
= const_state
->immediates_count
;
264 /* truncate size to avoid writing constants that shader
267 size
= MIN2(size
+ base
, v
->constlen
) - base
;
269 /* convert out of vec4: */
274 emit_const(ring
, v
, base
, 0, size
, const_state
->immediates
[0].val
, NULL
);
278 ir3_emit_link_map(struct fd_screen
*screen
,
279 const struct ir3_shader_variant
*producer
,
280 const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
)
282 const struct ir3_const_state
*const_state
= ir3_const_state(v
);
283 uint32_t base
= const_state
->offsets
.primitive_map
;
284 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
286 num_loc
= ir3_link_geometry_stages(producer
, v
, patch_locs
);
288 int size
= DIV_ROUND_UP(num_loc
, 4);
290 /* truncate size to avoid writing constants that shader
293 size
= MIN2(size
+ base
, v
->constlen
) - base
;
295 /* convert out of vec4: */
300 emit_const(ring
, v
, base
, 0, size
, patch_locs
, NULL
);
303 /* emit stream-out buffers: */
305 emit_tfbos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
306 struct fd_ringbuffer
*ring
)
308 /* streamout addresses after driver-params: */
309 const struct ir3_const_state
*const_state
= ir3_const_state(v
);
310 uint32_t offset
= const_state
->offsets
.tfbo
;
311 if (v
->constlen
> offset
) {
312 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
313 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
315 uint32_t offsets
[params
];
316 struct pipe_resource
*prscs
[params
];
318 for (uint32_t i
= 0; i
< params
; i
++) {
319 struct pipe_stream_output_target
*target
= so
->targets
[i
];
322 offsets
[i
] = (so
->offsets
[i
] * info
->stride
[i
] * 4) +
323 target
->buffer_offset
;
324 prscs
[i
] = target
->buffer
;
331 assert(offset
* 4 + params
<= v
->constlen
* 4);
333 emit_const_bo(ring
, v
, offset
* 4, params
, prscs
, offsets
);
337 static inline uint32_t
338 max_tf_vtx(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
)
340 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
341 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
342 uint32_t maxvtxcnt
= 0x7fffffff;
344 if (ctx
->screen
->gpu_id
>= 500)
348 if (v
->shader
->stream_output
.num_outputs
== 0)
350 if (so
->num_targets
== 0)
353 /* offset to write to is:
355 * total_vtxcnt = vtxcnt + offsets[i]
356 * offset = total_vtxcnt * stride[i]
358 * offset = vtxcnt * stride[i] ; calculated in shader
359 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
361 * assuming for each vtx, each target buffer will have data written
362 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
364 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
365 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
367 * but shader is actually doing a less-than (rather than less-than-
368 * equal) check, so we can drop the -stride[i].
370 * TODO is assumption about `offset + stride[i]` legit?
372 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
373 struct pipe_stream_output_target
*target
= so
->targets
[i
];
374 unsigned stride
= info
->stride
[i
] * 4; /* convert dwords->bytes */
376 uint32_t max
= target
->buffer_size
/ stride
;
377 maxvtxcnt
= MIN2(maxvtxcnt
, max
);
385 emit_common_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
386 struct fd_context
*ctx
, enum pipe_shader_type t
)
388 enum fd_dirty_shader_state dirty
= ctx
->dirty_shader
[t
];
390 /* When we use CP_SET_DRAW_STATE objects to emit constant state,
391 * if we emit any of it we need to emit all. This is because
392 * we are using the same state-group-id each time for uniform
393 * state, and if previous update is never evaluated (due to no
394 * visible primitives in the current tile) then the new stateobj
395 * completely replaces the old one.
397 * Possibly if we split up different parts of the const state to
398 * different state-objects we could avoid this.
400 if (dirty
&& is_stateobj(ring
))
403 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_CONST
)) {
404 struct fd_constbuf_stateobj
*constbuf
;
407 constbuf
= &ctx
->constbuf
[t
];
408 shader_dirty
= !!(dirty
& FD_DIRTY_SHADER_PROG
);
410 ring_wfi(ctx
->batch
, ring
);
412 ir3_emit_user_consts(ctx
->screen
, v
, ring
, constbuf
);
413 ir3_emit_ubos(ctx
, v
, ring
, constbuf
);
415 ir3_emit_immediates(ctx
->screen
, v
, ring
);
418 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_SSBO
)) {
419 struct fd_shaderbuf_stateobj
*sb
= &ctx
->shaderbuf
[t
];
420 ring_wfi(ctx
->batch
, ring
);
421 ir3_emit_ssbo_sizes(ctx
->screen
, v
, ring
, sb
);
424 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_IMAGE
)) {
425 struct fd_shaderimg_stateobj
*si
= &ctx
->shaderimg
[t
];
426 ring_wfi(ctx
->batch
, ring
);
427 ir3_emit_image_dims(ctx
->screen
, v
, ring
, si
);
432 ir3_needs_vs_driver_params(const struct ir3_shader_variant
*v
)
434 const struct ir3_const_state
*const_state
= ir3_const_state(v
);
435 uint32_t offset
= const_state
->offsets
.driver_param
;
437 return v
->constlen
> offset
;
441 ir3_emit_vs_driver_params(const struct ir3_shader_variant
*v
,
442 struct fd_ringbuffer
*ring
, struct fd_context
*ctx
,
443 const struct pipe_draw_info
*info
)
445 debug_assert(ir3_needs_vs_driver_params(v
));
447 const struct ir3_const_state
*const_state
= ir3_const_state(v
);
448 uint32_t offset
= const_state
->offsets
.driver_param
;
449 uint32_t vertex_params
[IR3_DP_VS_COUNT
] = {
450 [IR3_DP_VTXID_BASE
] = info
->index_size
?
451 info
->index_bias
: info
->start
,
452 [IR3_DP_VTXCNT_MAX
] = max_tf_vtx(ctx
, v
),
454 /* if no user-clip-planes, we don't need to emit the
457 uint32_t vertex_params_size
= 4;
459 if (v
->key
.ucp_enables
) {
460 struct pipe_clip_state
*ucp
= &ctx
->ucp
;
461 unsigned pos
= IR3_DP_UCP0_X
;
462 for (unsigned i
= 0; pos
<= IR3_DP_UCP7_W
; i
++) {
463 for (unsigned j
= 0; j
< 4; j
++) {
464 vertex_params
[pos
] = fui(ucp
->ucp
[i
][j
]);
468 vertex_params_size
= ARRAY_SIZE(vertex_params
);
471 vertex_params_size
= MAX2(vertex_params_size
, const_state
->num_driver_params
);
473 bool needs_vtxid_base
=
474 ir3_find_sysval_regid(v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) != regid(63, 0);
476 /* for indirect draw, we need to copy VTXID_BASE from
477 * indirect-draw parameters buffer.. which is annoying
478 * and means we can't easily emit these consts in cmd
479 * stream so need to copy them to bo.
481 if (info
->indirect
&& needs_vtxid_base
) {
482 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
483 struct pipe_resource
*vertex_params_rsc
=
484 pipe_buffer_create(&ctx
->screen
->base
,
485 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
,
486 vertex_params_size
* 4);
487 unsigned src_off
= info
->indirect
->offset
;;
490 ptr
= fd_bo_map(fd_resource(vertex_params_rsc
)->bo
);
491 memcpy(ptr
, vertex_params
, vertex_params_size
* 4);
493 if (info
->index_size
) {
494 /* indexed draw, index_bias is 4th field: */
497 /* non-indexed draw, start is 3rd field: */
501 /* copy index_bias or start from draw params: */
502 ctx
->screen
->mem_to_mem(ring
, vertex_params_rsc
, 0,
503 indirect
->buffer
, src_off
, 1);
505 emit_const(ring
, v
, offset
* 4, 0,
506 vertex_params_size
, NULL
, vertex_params_rsc
);
508 pipe_resource_reference(&vertex_params_rsc
, NULL
);
510 emit_const(ring
, v
, offset
* 4, 0,
511 vertex_params_size
, vertex_params
, NULL
);
514 /* if needed, emit stream-out buffer addresses: */
515 if (vertex_params
[IR3_DP_VTXCNT_MAX
] > 0) {
516 emit_tfbos(ctx
, v
, ring
);
521 ir3_emit_vs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
522 struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
524 debug_assert(v
->type
== MESA_SHADER_VERTEX
);
526 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_VERTEX
);
528 /* emit driver params every time: */
529 if (info
&& ir3_needs_vs_driver_params(v
)) {
530 ring_wfi(ctx
->batch
, ring
);
531 ir3_emit_vs_driver_params(v
, ring
, ctx
, info
);
536 ir3_emit_fs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
537 struct fd_context
*ctx
)
539 debug_assert(v
->type
== MESA_SHADER_FRAGMENT
);
541 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_FRAGMENT
);
544 /* emit compute-shader consts: */
546 ir3_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
547 struct fd_context
*ctx
, const struct pipe_grid_info
*info
)
549 debug_assert(gl_shader_stage_is_compute(v
->type
));
551 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_COMPUTE
);
553 /* emit compute-shader driver-params: */
554 const struct ir3_const_state
*const_state
= ir3_const_state(v
);
555 uint32_t offset
= const_state
->offsets
.driver_param
;
556 if (v
->constlen
> offset
) {
557 ring_wfi(ctx
->batch
, ring
);
559 if (info
->indirect
) {
560 struct pipe_resource
*indirect
= NULL
;
561 unsigned indirect_offset
;
563 /* This is a bit awkward, but CP_LOAD_STATE.EXT_SRC_ADDR needs
564 * to be aligned more strongly than 4 bytes. So in this case
565 * we need a temporary buffer to copy NumWorkGroups.xyz to.
567 * TODO if previous compute job is writing to info->indirect,
568 * we might need a WFI.. but since we currently flush for each
569 * compute job, we are probably ok for now.
571 if (info
->indirect_offset
& 0xf) {
572 indirect
= pipe_buffer_create(&ctx
->screen
->base
,
573 PIPE_BIND_COMMAND_ARGS_BUFFER
, PIPE_USAGE_STREAM
,
577 ctx
->screen
->mem_to_mem(ring
, indirect
, 0, info
->indirect
,
578 info
->indirect_offset
, 3);
580 pipe_resource_reference(&indirect
, info
->indirect
);
581 indirect_offset
= info
->indirect_offset
;
584 emit_const(ring
, v
, offset
* 4, indirect_offset
, 4, NULL
, indirect
);
586 pipe_resource_reference(&indirect
, NULL
);
588 uint32_t compute_params
[IR3_DP_CS_COUNT
] = {
589 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->grid
[0],
590 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->grid
[1],
591 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->grid
[2],
592 [IR3_DP_LOCAL_GROUP_SIZE_X
] = info
->block
[0],
593 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = info
->block
[1],
594 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = info
->block
[2],
596 uint32_t size
= MIN2(const_state
->num_driver_params
,
597 v
->constlen
* 4 - offset
* 4);
599 emit_const(ring
, v
, offset
* 4, 0, size
, compute_params
, NULL
);