2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "freedreno_util.h"
30 #include "ir3_shader.h"
38 struct ir3_shader_variant
*so
;
39 unsigned immediate_idx
;
42 /* is it a type preserving mov, with ok flags? */
43 static bool is_eligible_mov(struct ir3_instruction
*instr
, bool allow_flags
)
45 if (is_same_type_mov(instr
)) {
46 struct ir3_register
*dst
= instr
->regs
[0];
47 struct ir3_register
*src
= instr
->regs
[1];
48 struct ir3_instruction
*src_instr
= ssa(src
);
50 /* only if mov src is SSA (not const/immed): */
55 if (dst
->flags
& IR3_REG_RELATIV
)
57 if (src
->flags
& IR3_REG_RELATIV
)
60 if (src
->flags
& IR3_REG_ARRAY
)
64 if (src
->flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
65 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
68 /* TODO: remove this hack: */
69 if (src_instr
->opc
== OPC_META_FO
)
77 static unsigned cp_flags(unsigned flags
)
79 /* only considering these flags (at least for now): */
80 flags
&= (IR3_REG_CONST
| IR3_REG_IMMED
|
81 IR3_REG_FNEG
| IR3_REG_FABS
|
82 IR3_REG_SNEG
| IR3_REG_SABS
|
83 IR3_REG_BNOT
| IR3_REG_RELATIV
);
87 static bool valid_flags(struct ir3_instruction
*instr
, unsigned n
,
91 flags
= cp_flags(flags
);
93 /* If destination is indirect, then source cannot be.. at least
96 if ((instr
->regs
[0]->flags
& IR3_REG_RELATIV
) &&
97 (flags
& IR3_REG_RELATIV
))
100 /* TODO it seems to *mostly* work to cp RELATIV, except we get some
101 * intermittent piglit variable-indexing fails. Newer blob driver
102 * doesn't seem to cp these. Possibly this is hw workaround? Not
103 * sure, but until that is understood better, lets just switch off
104 * cp for indirect src's:
106 if (flags
& IR3_REG_RELATIV
)
109 switch (opc_cat(instr
->opc
)) {
111 valid_flags
= IR3_REG_IMMED
| IR3_REG_CONST
| IR3_REG_RELATIV
;
112 if (flags
& ~valid_flags
)
116 valid_flags
= ir3_cat2_absneg(instr
->opc
) |
117 IR3_REG_CONST
| IR3_REG_RELATIV
;
119 if (ir3_cat2_int(instr
->opc
))
120 valid_flags
|= IR3_REG_IMMED
;
122 if (flags
& ~valid_flags
)
125 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
)) {
126 unsigned m
= (n
^ 1) + 1;
127 /* cannot deal w/ const in both srcs:
128 * (note that some cat2 actually only have a single src)
130 if (m
< instr
->regs_count
) {
131 struct ir3_register
*reg
= instr
->regs
[m
];
132 if ((flags
& IR3_REG_CONST
) && (reg
->flags
& IR3_REG_CONST
))
134 if ((flags
& IR3_REG_IMMED
) && (reg
->flags
& IR3_REG_IMMED
))
137 /* cannot be const + ABS|NEG: */
138 if (flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
139 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
144 valid_flags
= ir3_cat3_absneg(instr
->opc
) |
145 IR3_REG_CONST
| IR3_REG_RELATIV
;
147 if (flags
& ~valid_flags
)
150 if (flags
& (IR3_REG_CONST
| IR3_REG_RELATIV
)) {
151 /* cannot deal w/ const/relativ in 2nd src: */
156 if (flags
& IR3_REG_CONST
) {
157 /* cannot be const + ABS|NEG: */
158 if (flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
159 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
164 /* seems like blob compiler avoids const as src.. */
165 /* TODO double check if this is still the case on a4xx */
166 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
168 if (flags
& (IR3_REG_SABS
| IR3_REG_SNEG
))
172 /* no flags allowed */
177 valid_flags
= IR3_REG_IMMED
;
178 if (flags
& ~valid_flags
)
181 if (flags
& IR3_REG_IMMED
) {
182 /* doesn't seem like we can have immediate src for store
185 * TODO this restriction could also apply to load instructions,
186 * but for load instructions this arg is the address (and not
187 * really sure any good way to test a hard-coded immed addr src)
189 if (is_store(instr
) && (n
== 1))
192 if ((instr
->opc
== OPC_LDL
) && (n
!= 1))
195 if ((instr
->opc
== OPC_STL
) && (n
!= 2))
198 /* disallow CP into anything but the SSBO slot argument for
201 if (is_atomic(instr
->opc
) && (n
!= 0))
204 if (is_atomic(instr
->opc
) && !(instr
->flags
& IR3_INSTR_G
))
214 /* propagate register flags from src to dst.. negates need special
215 * handling to cancel each other out.
217 static void combine_flags(unsigned *dstflags
, struct ir3_instruction
*src
)
219 unsigned srcflags
= src
->regs
[1]->flags
;
221 /* if what we are combining into already has (abs) flags,
222 * we can drop (neg) from src:
224 if (*dstflags
& IR3_REG_FABS
)
225 srcflags
&= ~IR3_REG_FNEG
;
226 if (*dstflags
& IR3_REG_SABS
)
227 srcflags
&= ~IR3_REG_SNEG
;
229 if (srcflags
& IR3_REG_FABS
)
230 *dstflags
|= IR3_REG_FABS
;
231 if (srcflags
& IR3_REG_SABS
)
232 *dstflags
|= IR3_REG_SABS
;
233 if (srcflags
& IR3_REG_FNEG
)
234 *dstflags
^= IR3_REG_FNEG
;
235 if (srcflags
& IR3_REG_SNEG
)
236 *dstflags
^= IR3_REG_SNEG
;
237 if (srcflags
& IR3_REG_BNOT
)
238 *dstflags
^= IR3_REG_BNOT
;
240 *dstflags
&= ~IR3_REG_SSA
;
241 *dstflags
|= srcflags
& IR3_REG_SSA
;
242 *dstflags
|= srcflags
& IR3_REG_CONST
;
243 *dstflags
|= srcflags
& IR3_REG_IMMED
;
244 *dstflags
|= srcflags
& IR3_REG_RELATIV
;
245 *dstflags
|= srcflags
& IR3_REG_ARRAY
;
247 /* if src of the src is boolean we can drop the (abs) since we know
248 * the source value is already a postitive integer. This cleans
249 * up the absnegs that get inserted when converting between nir and
250 * native boolean (see ir3_b2n/n2b)
252 struct ir3_instruction
*srcsrc
= ssa(src
->regs
[1]);
253 if (srcsrc
&& is_bool(srcsrc
))
254 *dstflags
&= ~IR3_REG_SABS
;
257 static struct ir3_register
*
258 lower_immed(struct ir3_cp_ctx
*ctx
, struct ir3_register
*reg
, unsigned new_flags
)
260 unsigned swiz
, idx
, i
;
262 reg
= ir3_reg_clone(ctx
->shader
, reg
);
264 /* in some cases, there are restrictions on (abs)/(neg) plus const..
265 * so just evaluate those and clear the flags:
267 if (new_flags
& IR3_REG_SABS
) {
268 reg
->iim_val
= abs(reg
->iim_val
);
269 new_flags
&= ~IR3_REG_SABS
;
272 if (new_flags
& IR3_REG_FABS
) {
273 reg
->fim_val
= fabs(reg
->fim_val
);
274 new_flags
&= ~IR3_REG_FABS
;
277 if (new_flags
& IR3_REG_SNEG
) {
278 reg
->iim_val
= -reg
->iim_val
;
279 new_flags
&= ~IR3_REG_SNEG
;
282 if (new_flags
& IR3_REG_FNEG
) {
283 reg
->fim_val
= -reg
->fim_val
;
284 new_flags
&= ~IR3_REG_FNEG
;
287 /* Reallocate for 4 more elements whenever it's necessary */
288 if (ctx
->immediate_idx
== ctx
->so
->immediates_size
* 4) {
289 ctx
->so
->immediates_size
+= 4;
290 ctx
->so
->immediates
= realloc (ctx
->so
->immediates
,
291 ctx
->so
->immediates_size
* sizeof (ctx
->so
->immediates
[0]));
294 for (i
= 0; i
< ctx
->immediate_idx
; i
++) {
298 if (ctx
->so
->immediates
[idx
].val
[swiz
] == reg
->uim_val
) {
303 if (i
== ctx
->immediate_idx
) {
304 /* need to generate a new immediate: */
307 ctx
->so
->immediates
[idx
].val
[swiz
] = reg
->uim_val
;
308 ctx
->so
->immediates_count
= idx
+ 1;
309 ctx
->immediate_idx
++;
312 new_flags
&= ~IR3_REG_IMMED
;
313 new_flags
|= IR3_REG_CONST
;
314 reg
->flags
= new_flags
;
315 reg
->num
= i
+ (4 * ctx
->so
->constbase
.immediate
);
321 unuse(struct ir3_instruction
*instr
)
323 debug_assert(instr
->use_count
> 0);
325 if (--instr
->use_count
== 0) {
326 struct ir3_block
*block
= instr
->block
;
328 instr
->barrier_class
= 0;
329 instr
->barrier_conflict
= 0;
331 /* we don't want to remove anything in keeps (which could
332 * be things like array store's)
334 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
335 debug_assert(block
->keeps
[i
] != instr
);
341 * Handle cp for a given src register. This additionally handles
342 * the cases of collapsing immedate/const (which replace the src
343 * register with a non-ssa src) or collapsing mov's from relative
344 * src (which needs to also fixup the address src reference by the
348 reg_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
,
349 struct ir3_register
*reg
, unsigned n
)
351 struct ir3_instruction
*src
= ssa(reg
);
353 if (is_eligible_mov(src
, true)) {
354 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
355 struct ir3_register
*src_reg
= src
->regs
[1];
356 unsigned new_flags
= reg
->flags
;
358 combine_flags(&new_flags
, src
);
360 if (valid_flags(instr
, n
, new_flags
)) {
361 if (new_flags
& IR3_REG_ARRAY
) {
362 debug_assert(!(reg
->flags
& IR3_REG_ARRAY
));
363 reg
->array
= src_reg
->array
;
365 reg
->flags
= new_flags
;
366 reg
->instr
= ssa(src_reg
);
368 instr
->barrier_class
|= src
->barrier_class
;
369 instr
->barrier_conflict
|= src
->barrier_conflict
;
372 reg
->instr
->use_count
++;
375 } else if (is_same_type_mov(src
) &&
376 /* cannot collapse const/immed/etc into meta instrs: */
378 /* immed/const/etc cases, which require some special handling: */
379 struct ir3_register
*src_reg
= src
->regs
[1];
380 unsigned new_flags
= reg
->flags
;
382 combine_flags(&new_flags
, src
);
384 if (!valid_flags(instr
, n
, new_flags
)) {
385 /* See if lowering an immediate to const would help. */
386 if (valid_flags(instr
, n
, (new_flags
& ~IR3_REG_IMMED
) | IR3_REG_CONST
)) {
387 debug_assert(new_flags
& IR3_REG_IMMED
);
388 instr
->regs
[n
+ 1] = lower_immed(ctx
, src_reg
, new_flags
);
392 /* special case for "normal" mad instructions, we can
393 * try swapping the first two args if that fits better.
395 * the "plain" MAD's (ie. the ones that don't shift first
396 * src prior to multiply) can swap their first two srcs if
397 * src[0] is !CONST and src[1] is CONST:
399 if ((n
== 1) && is_mad(instr
->opc
) &&
400 !(instr
->regs
[0 + 1]->flags
& (IR3_REG_CONST
| IR3_REG_RELATIV
)) &&
401 valid_flags(instr
, 0, new_flags
& ~IR3_REG_IMMED
)) {
402 /* swap src[0] and src[1]: */
403 struct ir3_register
*tmp
;
404 tmp
= instr
->regs
[0 + 1];
405 instr
->regs
[0 + 1] = instr
->regs
[1 + 1];
406 instr
->regs
[1 + 1] = tmp
;
414 /* Here we handle the special case of mov from
415 * CONST and/or RELATIV. These need to be handled
416 * specially, because in the case of move from CONST
417 * there is no src ir3_instruction so we need to
418 * replace the ir3_register. And in the case of
419 * RELATIV we need to handle the address register
422 if (src_reg
->flags
& IR3_REG_CONST
) {
423 /* an instruction cannot reference two different
426 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
427 conflicts(instr
->address
, reg
->instr
->address
))
430 /* This seems to be a hw bug, or something where the timings
431 * just somehow don't work out. This restriction may only
432 * apply if the first src is also CONST.
434 if ((opc_cat(instr
->opc
) == 3) && (n
== 2) &&
435 (src_reg
->flags
& IR3_REG_RELATIV
) &&
436 (src_reg
->array
.offset
== 0))
439 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
440 src_reg
->flags
= new_flags
;
441 instr
->regs
[n
+1] = src_reg
;
443 if (src_reg
->flags
& IR3_REG_RELATIV
)
444 ir3_instr_set_address(instr
, reg
->instr
->address
);
449 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
450 !conflicts(instr
->address
, reg
->instr
->address
)) {
451 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
452 src_reg
->flags
= new_flags
;
453 instr
->regs
[n
+1] = src_reg
;
454 ir3_instr_set_address(instr
, reg
->instr
->address
);
459 /* NOTE: seems we can only do immed integers, so don't
460 * need to care about float. But we do need to handle
461 * abs/neg *before* checking that the immediate requires
462 * few enough bits to encode:
464 * TODO: do we need to do something to avoid accidentally
465 * catching a float immed?
467 if (src_reg
->flags
& IR3_REG_IMMED
) {
468 int32_t iim_val
= src_reg
->iim_val
;
470 debug_assert((opc_cat(instr
->opc
) == 1) ||
471 (opc_cat(instr
->opc
) == 6) ||
472 ir3_cat2_int(instr
->opc
) ||
473 (is_mad(instr
->opc
) && (n
== 0)));
475 if (new_flags
& IR3_REG_SABS
)
476 iim_val
= abs(iim_val
);
478 if (new_flags
& IR3_REG_SNEG
)
481 if (new_flags
& IR3_REG_BNOT
)
484 /* other than category 1 (mov) we can only encode up to 10 bits: */
485 if ((instr
->opc
== OPC_MOV
) ||
486 !((iim_val
& ~0x3ff) && (-iim_val
& ~0x3ff))) {
487 new_flags
&= ~(IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
);
488 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
489 src_reg
->flags
= new_flags
;
490 src_reg
->iim_val
= iim_val
;
491 instr
->regs
[n
+1] = src_reg
;
492 } else if (valid_flags(instr
, n
, (new_flags
& ~IR3_REG_IMMED
) | IR3_REG_CONST
)) {
493 /* See if lowering an immediate to const would help. */
494 instr
->regs
[n
+1] = lower_immed(ctx
, src_reg
, new_flags
);
502 /* Handle special case of eliminating output mov, and similar cases where
503 * there isn't a normal "consuming" instruction. In this case we cannot
504 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
507 static struct ir3_instruction
*
508 eliminate_output_mov(struct ir3_instruction
*instr
)
510 if (is_eligible_mov(instr
, false)) {
511 struct ir3_register
*reg
= instr
->regs
[1];
512 if (!(reg
->flags
& IR3_REG_ARRAY
)) {
513 struct ir3_instruction
*src_instr
= ssa(reg
);
514 debug_assert(src_instr
);
522 * Find instruction src's which are mov's that can be collapsed, replacing
523 * the mov dst with the mov src
526 instr_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
)
528 struct ir3_register
*reg
;
530 if (instr
->regs_count
== 0)
533 if (ir3_instr_check_mark(instr
))
536 /* walk down the graph from each src: */
537 foreach_src_n(reg
, n
, instr
) {
538 struct ir3_instruction
*src
= ssa(reg
);
545 /* TODO non-indirect access we could figure out which register
546 * we actually want and allow cp..
548 if (reg
->flags
& IR3_REG_ARRAY
)
551 /* Don't CP absneg into meta instructions, that won't end well: */
552 if (is_meta(instr
) && (src
->opc
!= OPC_MOV
))
555 reg_cp(ctx
, instr
, reg
, n
);
558 if (instr
->regs
[0]->flags
& IR3_REG_ARRAY
) {
559 struct ir3_instruction
*src
= ssa(instr
->regs
[0]);
564 if (instr
->address
) {
565 instr_cp(ctx
, instr
->address
);
566 ir3_instr_set_address(instr
, eliminate_output_mov(instr
->address
));
569 /* we can end up with extra cmps.s from frontend, which uses a
571 * cmps.s p0.x, cond, 0
573 * as a way to mov into the predicate register. But frequently 'cond'
574 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case and
575 * just re-write the instruction writing predicate register to get rid
576 * of the double cmps.
578 if ((instr
->opc
== OPC_CMPS_S
) &&
579 (instr
->regs
[0]->num
== regid(REG_P0
, 0)) &&
580 ssa(instr
->regs
[1]) &&
581 (instr
->regs
[2]->flags
& IR3_REG_IMMED
) &&
582 (instr
->regs
[2]->iim_val
== 0)) {
583 struct ir3_instruction
*cond
= ssa(instr
->regs
[1]);
588 instr
->opc
= cond
->opc
;
589 instr
->flags
= cond
->flags
;
590 instr
->cat2
= cond
->cat2
;
591 instr
->address
= cond
->address
;
592 instr
->regs
[1] = cond
->regs
[1];
593 instr
->regs
[2] = cond
->regs
[2];
594 instr
->barrier_class
|= cond
->barrier_class
;
595 instr
->barrier_conflict
|= cond
->barrier_conflict
;
605 ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
)
607 struct ir3_cp_ctx ctx
= {
612 /* This is a bit annoying, and probably wouldn't be necessary if we
613 * tracked a reverse link from producing instruction to consumer.
614 * But we need to know when we've eliminated the last consumer of
615 * a mov, so we need to do a pass to first count consumers of a
618 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
619 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
620 struct ir3_instruction
*src
;
622 /* by the way, we don't account for false-dep's, so the CP
623 * pass should always happen before false-dep's are inserted
625 debug_assert(instr
->deps_count
== 0);
627 foreach_ssa_src(src
, instr
) {
635 for (unsigned i
= 0; i
< ir
->noutputs
; i
++) {
636 if (ir
->outputs
[i
]) {
637 instr_cp(&ctx
, ir
->outputs
[i
]);
638 ir
->outputs
[i
] = eliminate_output_mov(ir
->outputs
[i
]);
642 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
643 if (block
->condition
) {
644 instr_cp(&ctx
, block
->condition
);
645 block
->condition
= eliminate_output_mov(block
->condition
);
648 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
649 instr_cp(&ctx
, block
->keeps
[i
]);
650 block
->keeps
[i
] = eliminate_output_mov(block
->keeps
[i
]);