src/gallium/drivers/freedreno/ir3/ir3_cp.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "freedreno_util.h"
  30
  31 #include "ir3.h"
  32 #include "ir3_shader.h"
  33
  34 /*
  35  * Copy Propagate:
  36  */
  37
  38 struct ir3_cp_ctx {
  39         struct ir3 *shader;
  40         struct ir3_shader_variant *so;
  41         unsigned immediate_idx;
  42 };
  43
  44 /* is it a type preserving mov, with ok flags? */
  45 static bool is_eligible_mov(struct ir3_instruction *instr, bool allow_flags)
  46 {
  47         if (is_same_type_mov(instr)) {
  48                 struct ir3_register *dst = instr->regs[0];
  49                 struct ir3_register *src = instr->regs[1];
  50                 struct ir3_instruction *src_instr = ssa(src);
  51
  52                 /* only if mov src is SSA (not const/immed): */
  53                 if (!src_instr)
  54                         return false;
  55
  56                 /* no indirect: */
  57                 if (dst->flags & IR3_REG_RELATIV)
  58                         return false;
  59                 if (src->flags & IR3_REG_RELATIV)
  60                         return false;
  61
  62                 if (!allow_flags)
  63                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  64                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  65                                 return false;
  66
  67                 /* TODO: remove this hack: */
  68                 if (src_instr->opc == OPC_META_FO)
  69                         return false;
  70
  71                 return true;
  72         }
  73         return false;
  74 }
  75
  76 static unsigned cp_flags(unsigned flags)
  77 {
  78         /* only considering these flags (at least for now): */
  79         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
  80                         IR3_REG_FNEG | IR3_REG_FABS |
  81                         IR3_REG_SNEG | IR3_REG_SABS |
  82                         IR3_REG_BNOT | IR3_REG_RELATIV);
  83         return flags;
  84 }
  85
  86 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
  87                 unsigned flags)
  88 {
  89         unsigned valid_flags;
  90         flags = cp_flags(flags);
  91
  92         /* If destination is indirect, then source cannot be.. at least
  93          * I don't think so..
  94          */
  95         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
  96                         (flags & IR3_REG_RELATIV))
  97                 return false;
  98
  99         /* TODO it seems to *mostly* work to cp RELATIV, except we get some
 100          * intermittent piglit variable-indexing fails.  Newer blob driver
 101          * doesn't seem to cp these.  Possibly this is hw workaround?  Not
 102          * sure, but until that is understood better, lets just switch off
 103          * cp for indirect src's:
 104          */
 105         if (flags & IR3_REG_RELATIV)
 106                 return false;
 107
 108         switch (opc_cat(instr->opc)) {
 109         case 1:
 110                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 111                 if (flags & ~valid_flags)
 112                         return false;
 113                 break;
 114         case 2:
 115                 valid_flags = ir3_cat2_absneg(instr->opc) |
 116                                 IR3_REG_CONST | IR3_REG_RELATIV;
 117
 118                 if (ir3_cat2_int(instr->opc))
 119                         valid_flags |= IR3_REG_IMMED;
 120
 121                 if (flags & ~valid_flags)
 122                         return false;
 123
 124                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 125                         unsigned m = (n ^ 1) + 1;
 126                         /* cannot deal w/ const in both srcs:
 127                          * (note that some cat2 actually only have a single src)
 128                          */
 129                         if (m < instr->regs_count) {
 130                                 struct ir3_register *reg = instr->regs[m];
 131                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 132                                         return false;
 133                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 134                                         return false;
 135                         }
 136                         /* cannot be const + ABS|NEG: */
 137                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 138                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 139                                 return false;
 140                 }
 141                 break;
 142         case 3:
 143                 valid_flags = ir3_cat3_absneg(instr->opc) |
 144                                 IR3_REG_CONST | IR3_REG_RELATIV;
 145
 146                 if (flags & ~valid_flags)
 147                         return false;
 148
 149                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 150                         /* cannot deal w/ const/relativ in 2nd src: */
 151                         if (n == 1)
 152                                 return false;
 153                 }
 154
 155                 if (flags & IR3_REG_CONST) {
 156                         /* cannot be const + ABS|NEG: */
 157                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 158                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 159                                 return false;
 160                 }
 161                 break;
 162         case 4:
 163                 /* seems like blob compiler avoids const as src.. */
 164                 /* TODO double check if this is still the case on a4xx */
 165                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 166                         return false;
 167                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 168                         return false;
 169                 break;
 170         case 5:
 171                 /* no flags allowed */
 172                 if (flags)
 173                         return false;
 174                 break;
 175         case 6:
 176                 valid_flags = IR3_REG_IMMED;
 177                 if (flags & ~valid_flags)
 178                         return false;
 179
 180                 if (flags & IR3_REG_IMMED) {
 181                         /* doesn't seem like we can have immediate src for store
 182                          * instructions:
 183                          *
 184                          * TODO this restriction could also apply to load instructions,
 185                          * but for load instructions this arg is the address (and not
 186                          * really sure any good way to test a hard-coded immed addr src)
 187                          */
 188                         if (is_store(instr) && (n == 1))
 189                                 return false;
 190
 191                         if ((instr->opc == OPC_LDL) && (n != 1))
 192                                 return false;
 193
 194                         if ((instr->opc == OPC_STL) && (n != 2))
 195                                 return false;
 196
 197                         /* disallow CP into anything but the SSBO slot argument for
 198                          * atomics:
 199                          */
 200                         if (is_atomic(instr->opc) && (n != 0))
 201                                 return false;
 202
 203                         if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
 204                                 return false;
 205                 }
 206
 207                 break;
 208         }
 209
 210         return true;
 211 }
 212
 213 /* propagate register flags from src to dst.. negates need special
 214  * handling to cancel each other out.
 215  */
 216 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 217 {
 218         unsigned srcflags = src->regs[1]->flags;
 219
 220         /* if what we are combining into already has (abs) flags,
 221          * we can drop (neg) from src:
 222          */
 223         if (*dstflags & IR3_REG_FABS)
 224                 srcflags &= ~IR3_REG_FNEG;
 225         if (*dstflags & IR3_REG_SABS)
 226                 srcflags &= ~IR3_REG_SNEG;
 227
 228         if (srcflags & IR3_REG_FABS)
 229                 *dstflags |= IR3_REG_FABS;
 230         if (srcflags & IR3_REG_SABS)
 231                 *dstflags |= IR3_REG_SABS;
 232         if (srcflags & IR3_REG_FNEG)
 233                 *dstflags ^= IR3_REG_FNEG;
 234         if (srcflags & IR3_REG_SNEG)
 235                 *dstflags ^= IR3_REG_SNEG;
 236         if (srcflags & IR3_REG_BNOT)
 237                 *dstflags ^= IR3_REG_BNOT;
 238
 239         *dstflags &= ~IR3_REG_SSA;
 240         *dstflags |= srcflags & IR3_REG_SSA;
 241         *dstflags |= srcflags & IR3_REG_CONST;
 242         *dstflags |= srcflags & IR3_REG_IMMED;
 243         *dstflags |= srcflags & IR3_REG_RELATIV;
 244         *dstflags |= srcflags & IR3_REG_ARRAY;
 245
 246         /* if src of the src is boolean we can drop the (abs) since we know
 247          * the source value is already a postitive integer.  This cleans
 248          * up the absnegs that get inserted when converting between nir and
 249          * native boolean (see ir3_b2n/n2b)
 250          */
 251         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 252         if (srcsrc && is_bool(srcsrc))
 253                 *dstflags &= ~IR3_REG_SABS;
 254 }
 255
 256 static struct ir3_register *
 257 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags)
 258 {
 259         unsigned swiz, idx, i;
 260
 261         reg = ir3_reg_clone(ctx->shader, reg);
 262
 263         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 264          * so just evaluate those and clear the flags:
 265          */
 266         if (new_flags & IR3_REG_SABS) {
 267                 reg->iim_val = abs(reg->iim_val);
 268                 new_flags &= ~IR3_REG_SABS;
 269         }
 270
 271         if (new_flags & IR3_REG_FABS) {
 272                 reg->fim_val = fabs(reg->fim_val);
 273                 new_flags &= ~IR3_REG_FABS;
 274         }
 275
 276         if (new_flags & IR3_REG_SNEG) {
 277                 reg->iim_val = -reg->iim_val;
 278                 new_flags &= ~IR3_REG_SNEG;
 279         }
 280
 281         if (new_flags & IR3_REG_FNEG) {
 282                 reg->fim_val = -reg->fim_val;
 283                 new_flags &= ~IR3_REG_FNEG;
 284         }
 285
 286         for (i = 0; i < ctx->immediate_idx; i++) {
 287                 swiz = i % 4;
 288                 idx  = i / 4;
 289
 290                 if (ctx->so->immediates[idx].val[swiz] == reg->uim_val) {
 291                         break;
 292                 }
 293         }
 294
 295         if (i == ctx->immediate_idx) {
 296                 /* need to generate a new immediate: */
 297                 swiz = i % 4;
 298                 idx  = i / 4;
 299                 ctx->so->immediates[idx].val[swiz] = reg->uim_val;
 300                 ctx->so->immediates_count = idx + 1;
 301                 ctx->immediate_idx++;
 302         }
 303
 304         new_flags &= ~IR3_REG_IMMED;
 305         new_flags |= IR3_REG_CONST;
 306         reg->flags = new_flags;
 307         reg->num = i + (4 * ctx->so->constbase.immediate);
 308
 309         return reg;
 310 }
 311
 312 static void
 313 unuse(struct ir3_instruction *instr)
 314 {
 315         debug_assert(instr->use_count > 0);
 316
 317         if (--instr->use_count == 0) {
 318                 struct ir3_block *block = instr->block;
 319
 320                 instr->barrier_class = 0;
 321                 instr->barrier_conflict = 0;
 322
 323                 /* we don't want to remove anything in keeps (which could
 324                  * be things like array store's)
 325                  */
 326                 for (unsigned i = 0; i < block->keeps_count; i++) {
 327                         debug_assert(block->keeps[i] != instr);
 328                 }
 329         }
 330 }
 331
 332 /**
 333  * Handle cp for a given src register.  This additionally handles
 334  * the cases of collapsing immedate/const (which replace the src
 335  * register with a non-ssa src) or collapsing mov's from relative
 336  * src (which needs to also fixup the address src reference by the
 337  * instruction).
 338  */
 339 static void
 340 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 341                 struct ir3_register *reg, unsigned n)
 342 {
 343         struct ir3_instruction *src = ssa(reg);
 344
 345         if (is_eligible_mov(src, true)) {
 346                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 347                 struct ir3_register *src_reg = src->regs[1];
 348                 unsigned new_flags = reg->flags;
 349
 350                 combine_flags(&new_flags, src);
 351
 352                 if (valid_flags(instr, n, new_flags)) {
 353                         if (new_flags & IR3_REG_ARRAY) {
 354                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 355                                 reg->array = src_reg->array;
 356                         }
 357                         reg->flags = new_flags;
 358                         reg->instr = ssa(src_reg);
 359
 360                         instr->barrier_class |= src->barrier_class;
 361                         instr->barrier_conflict |= src->barrier_conflict;
 362
 363                         unuse(src);
 364                         reg->instr->use_count++;
 365                 }
 366
 367         } else if (is_same_type_mov(src) &&
 368                         /* cannot collapse const/immed/etc into meta instrs: */
 369                         !is_meta(instr)) {
 370                 /* immed/const/etc cases, which require some special handling: */
 371                 struct ir3_register *src_reg = src->regs[1];
 372                 unsigned new_flags = reg->flags;
 373
 374                 combine_flags(&new_flags, src);
 375
 376                 if (!valid_flags(instr, n, new_flags)) {
 377                         /* See if lowering an immediate to const would help. */
 378                         if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 379                                 debug_assert(new_flags & IR3_REG_IMMED);
 380                                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags);
 381                                 return;
 382                         }
 383
 384                         /* special case for "normal" mad instructions, we can
 385                          * try swapping the first two args if that fits better.
 386                          *
 387                          * the "plain" MAD's (ie. the ones that don't shift first
 388                          * src prior to multiply) can swap their first two srcs if
 389                          * src[0] is !CONST and src[1] is CONST:
 390                          */
 391                         if ((n == 1) && is_mad(instr->opc) &&
 392                                         !(instr->regs[0 + 1]->flags & (IR3_REG_CONST | IR3_REG_RELATIV)) &&
 393                                         valid_flags(instr, 0, new_flags & ~IR3_REG_IMMED)) {
 394                                 /* swap src[0] and src[1]: */
 395                                 struct ir3_register *tmp;
 396                                 tmp = instr->regs[0 + 1];
 397                                 instr->regs[0 + 1] = instr->regs[1 + 1];
 398                                 instr->regs[1 + 1] = tmp;
 399
 400                                 n = 0;
 401                         } else {
 402                                 return;
 403                         }
 404                 }
 405
 406                 /* Here we handle the special case of mov from
 407                  * CONST and/or RELATIV.  These need to be handled
 408                  * specially, because in the case of move from CONST
 409                  * there is no src ir3_instruction so we need to
 410                  * replace the ir3_register.  And in the case of
 411                  * RELATIV we need to handle the address register
 412                  * dependency.
 413                  */
 414                 if (src_reg->flags & IR3_REG_CONST) {
 415                         /* an instruction cannot reference two different
 416                          * address registers:
 417                          */
 418                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 419                                         conflicts(instr->address, reg->instr->address))
 420                                 return;
 421
 422                         /* This seems to be a hw bug, or something where the timings
 423                          * just somehow don't work out.  This restriction may only
 424                          * apply if the first src is also CONST.
 425                          */
 426                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 427                                         (src_reg->flags & IR3_REG_RELATIV) &&
 428                                         (src_reg->array.offset == 0))
 429                                 return;
 430
 431                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 432                         src_reg->flags = new_flags;
 433                         instr->regs[n+1] = src_reg;
 434
 435                         if (src_reg->flags & IR3_REG_RELATIV)
 436                                 ir3_instr_set_address(instr, reg->instr->address);
 437
 438                         return;
 439                 }
 440
 441                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 442                                 !conflicts(instr->address, reg->instr->address)) {
 443                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 444                         src_reg->flags = new_flags;
 445                         instr->regs[n+1] = src_reg;
 446                         ir3_instr_set_address(instr, reg->instr->address);
 447
 448                         return;
 449                 }
 450
 451                 /* NOTE: seems we can only do immed integers, so don't
 452                  * need to care about float.  But we do need to handle
 453                  * abs/neg *before* checking that the immediate requires
 454                  * few enough bits to encode:
 455                  *
 456                  * TODO: do we need to do something to avoid accidentally
 457                  * catching a float immed?
 458                  */
 459                 if (src_reg->flags & IR3_REG_IMMED) {
 460                         int32_t iim_val = src_reg->iim_val;
 461
 462                         debug_assert((opc_cat(instr->opc) == 1) ||
 463                                         (opc_cat(instr->opc) == 6) ||
 464                                         ir3_cat2_int(instr->opc) ||
 465                                         (is_mad(instr->opc) && (n == 0)));
 466
 467                         if (new_flags & IR3_REG_SABS)
 468                                 iim_val = abs(iim_val);
 469
 470                         if (new_flags & IR3_REG_SNEG)
 471                                 iim_val = -iim_val;
 472
 473                         if (new_flags & IR3_REG_BNOT)
 474                                 iim_val = ~iim_val;
 475
 476                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 477                         if ((instr->opc == OPC_MOV) ||
 478                                         !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff))) {
 479                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 480                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 481                                 src_reg->flags = new_flags;
 482                                 src_reg->iim_val = iim_val;
 483                                 instr->regs[n+1] = src_reg;
 484                         } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 485                                 /* See if lowering an immediate to const would help. */
 486                                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags);
 487                         }
 488
 489                         return;
 490                 }
 491         }
 492 }
 493
 494 /* Handle special case of eliminating output mov, and similar cases where
 495  * there isn't a normal "consuming" instruction.  In this case we cannot
 496  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 497  * be eliminated)
 498  */
 499 static struct ir3_instruction *
 500 eliminate_output_mov(struct ir3_instruction *instr)
 501 {
 502         if (is_eligible_mov(instr, false)) {
 503                 struct ir3_register *reg = instr->regs[1];
 504                 if (!(reg->flags & IR3_REG_ARRAY)) {
 505                         struct ir3_instruction *src_instr = ssa(reg);
 506                         debug_assert(src_instr);
 507                         return src_instr;
 508                 }
 509         }
 510         return instr;
 511 }
 512
 513 /**
 514  * Find instruction src's which are mov's that can be collapsed, replacing
 515  * the mov dst with the mov src
 516  */
 517 static void
 518 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 519 {
 520         struct ir3_register *reg;
 521
 522         if (instr->regs_count == 0)
 523                 return;
 524
 525         if (ir3_instr_check_mark(instr))
 526                 return;
 527
 528         /* walk down the graph from each src: */
 529         foreach_src_n(reg, n, instr) {
 530                 struct ir3_instruction *src = ssa(reg);
 531
 532                 if (!src)
 533                         continue;
 534
 535                 instr_cp(ctx, src);
 536
 537                 /* TODO non-indirect access we could figure out which register
 538                  * we actually want and allow cp..
 539                  */
 540                 if (reg->flags & IR3_REG_ARRAY)
 541                         continue;
 542
 543                 reg_cp(ctx, instr, reg, n);
 544         }
 545
 546         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 547                 struct ir3_instruction *src = ssa(instr->regs[0]);
 548                 if (src)
 549                         instr_cp(ctx, src);
 550         }
 551
 552         if (instr->address) {
 553                 instr_cp(ctx, instr->address);
 554                 ir3_instr_set_address(instr, eliminate_output_mov(instr->address));
 555         }
 556
 557         /* we can end up with extra cmps.s from frontend, which uses a
 558          *
 559          *    cmps.s p0.x, cond, 0
 560          *
 561          * as a way to mov into the predicate register.  But frequently 'cond'
 562          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 563          * just re-write the instruction writing predicate register to get rid
 564          * of the double cmps.
 565          */
 566         if ((instr->opc == OPC_CMPS_S) &&
 567                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 568                         ssa(instr->regs[1]) &&
 569                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 570                         (instr->regs[2]->iim_val == 0)) {
 571                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 572                 switch (cond->opc) {
 573                 case OPC_CMPS_S:
 574                 case OPC_CMPS_F:
 575                 case OPC_CMPS_U:
 576                         instr->opc   = cond->opc;
 577                         instr->flags = cond->flags;
 578                         instr->cat2  = cond->cat2;
 579                         instr->address = cond->address;
 580                         instr->regs[1] = cond->regs[1];
 581                         instr->regs[2] = cond->regs[2];
 582                         instr->barrier_class |= cond->barrier_class;
 583                         instr->barrier_conflict |= cond->barrier_conflict;
 584                         unuse(cond);
 585                         break;
 586                 default:
 587                         break;
 588                 }
 589         }
 590 }
 591
 592 void
 593 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 594 {
 595         struct ir3_cp_ctx ctx = {
 596                         .shader = ir,
 597                         .so = so,
 598         };
 599
 600         /* This is a bit annoying, and probably wouldn't be necessary if we
 601          * tracked a reverse link from producing instruction to consumer.
 602          * But we need to know when we've eliminated the last consumer of
 603          * a mov, so we need to do a pass to first count consumers of a
 604          * mov.
 605          */
 606         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 607                 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
 608                         struct ir3_instruction *src;
 609
 610                         /* by the way, we don't acount for false-dep's, so the CP
 611                          * pass should always happen before false-dep's are inserted
 612                          */
 613                         debug_assert(instr->deps_count == 0);
 614
 615                         foreach_ssa_src(src, instr) {
 616                                 src->use_count++;
 617                         }
 618                 }
 619         }
 620
 621         ir3_clear_mark(ir);
 622
 623         for (unsigned i = 0; i < ir->noutputs; i++) {
 624                 if (ir->outputs[i]) {
 625                         instr_cp(&ctx, ir->outputs[i]);
 626                         ir->outputs[i] = eliminate_output_mov(ir->outputs[i]);
 627                 }
 628         }
 629
 630         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 631                 if (block->condition) {
 632                         instr_cp(&ctx, block->condition);
 633                         block->condition = eliminate_output_mov(block->condition);
 634                 }
 635
 636                 for (unsigned i = 0; i < block->keeps_count; i++) {
 637                         instr_cp(&ctx, block->keeps[i]);
 638                         block->keeps[i] = eliminate_output_mov(block->keeps[i]);
 639                 }
 640         }
 641 }