src/gallium/drivers/freedreno/ir3/ir3_cp.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "freedreno_util.h"
  30
  31 #include "ir3.h"
  32 #include "ir3_shader.h"
  33
  34 /*
  35  * Copy Propagate:
  36  */
  37
  38 struct ir3_cp_ctx {
  39         struct ir3 *shader;
  40         struct ir3_shader_variant *so;
  41         unsigned immediate_idx;
  42 };
  43
  44 /* is it a type preserving mov, with ok flags? */
  45 static bool is_eligible_mov(struct ir3_instruction *instr, bool allow_flags)
  46 {
  47         if (is_same_type_mov(instr)) {
  48                 struct ir3_register *dst = instr->regs[0];
  49                 struct ir3_register *src = instr->regs[1];
  50                 struct ir3_instruction *src_instr = ssa(src);
  51
  52                 /* only if mov src is SSA (not const/immed): */
  53                 if (!src_instr)
  54                         return false;
  55
  56                 /* no indirect: */
  57                 if (dst->flags & IR3_REG_RELATIV)
  58                         return false;
  59                 if (src->flags & IR3_REG_RELATIV)
  60                         return false;
  61
  62                 if (!allow_flags)
  63                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  64                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  65                                 return false;
  66
  67                 /* TODO: remove this hack: */
  68                 if (src_instr->opc == OPC_META_FO)
  69                         return false;
  70                 /* TODO: we currently don't handle left/right neighbors
  71                  * very well when inserting parallel-copies into phi..
  72                  * to avoid problems don't eliminate a mov coming out
  73                  * of phi..
  74                  */
  75                 if (src_instr->opc == OPC_META_PHI)
  76                         return false;
  77                 return true;
  78         }
  79         return false;
  80 }
  81
  82 static unsigned cp_flags(unsigned flags)
  83 {
  84         /* only considering these flags (at least for now): */
  85         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
  86                         IR3_REG_FNEG | IR3_REG_FABS |
  87                         IR3_REG_SNEG | IR3_REG_SABS |
  88                         IR3_REG_BNOT | IR3_REG_RELATIV);
  89         return flags;
  90 }
  91
  92 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
  93                 unsigned flags)
  94 {
  95         unsigned valid_flags;
  96         flags = cp_flags(flags);
  97
  98         /* If destination is indirect, then source cannot be.. at least
  99          * I don't think so..
 100          */
 101         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
 102                         (flags & IR3_REG_RELATIV))
 103                 return false;
 104
 105         /* clear flags that are 'ok' */
 106         switch (opc_cat(instr->opc)) {
 107         case 1:
 108                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 109                 if (flags & ~valid_flags)
 110                         return false;
 111                 break;
 112         case 5:
 113                 /* no flags allowed */
 114                 if (flags)
 115                         return false;
 116                 break;
 117         case 6:
 118                 valid_flags = IR3_REG_IMMED;
 119                 if (flags & ~valid_flags)
 120                         return false;
 121
 122                 if (flags & IR3_REG_IMMED) {
 123                         /* doesn't seem like we can have immediate src for store
 124                          * instructions:
 125                          *
 126                          * TODO this restriction could also apply to load instructions,
 127                          * but for load instructions this arg is the address (and not
 128                          * really sure any good way to test a hard-coded immed addr src)
 129                          */
 130                         if (is_store(instr) && (n == 1))
 131                                 return false;
 132                 }
 133
 134                 break;
 135         case 2:
 136                 valid_flags = ir3_cat2_absneg(instr->opc) |
 137                                 IR3_REG_CONST | IR3_REG_RELATIV;
 138
 139                 if (ir3_cat2_int(instr->opc))
 140                         valid_flags |= IR3_REG_IMMED;
 141
 142                 if (flags & ~valid_flags)
 143                         return false;
 144
 145                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 146                         unsigned m = (n ^ 1) + 1;
 147                         /* cannot deal w/ const in both srcs:
 148                          * (note that some cat2 actually only have a single src)
 149                          */
 150                         if (m < instr->regs_count) {
 151                                 struct ir3_register *reg = instr->regs[m];
 152                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 153                                         return false;
 154                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 155                                         return false;
 156                         }
 157                         /* cannot be const + ABS|NEG: */
 158                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 159                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 160                                 return false;
 161                 }
 162                 break;
 163         case 3:
 164                 valid_flags = ir3_cat3_absneg(instr->opc) |
 165                                 IR3_REG_CONST | IR3_REG_RELATIV;
 166
 167                 if (flags & ~valid_flags)
 168                         return false;
 169
 170                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 171                         /* cannot deal w/ const/relativ in 2nd src: */
 172                         if (n == 1)
 173                                 return false;
 174                 }
 175
 176                 if (flags & IR3_REG_CONST) {
 177                         /* cannot be const + ABS|NEG: */
 178                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 179                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 180                                 return false;
 181                 }
 182                 break;
 183         case 4:
 184                 /* seems like blob compiler avoids const as src.. */
 185                 /* TODO double check if this is still the case on a4xx */
 186                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 187                         return false;
 188                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 189                         return false;
 190                 break;
 191         }
 192
 193         return true;
 194 }
 195
 196 /* propagate register flags from src to dst.. negates need special
 197  * handling to cancel each other out.
 198  */
 199 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 200 {
 201         unsigned srcflags = src->regs[1]->flags;
 202
 203         /* if what we are combining into already has (abs) flags,
 204          * we can drop (neg) from src:
 205          */
 206         if (*dstflags & IR3_REG_FABS)
 207                 srcflags &= ~IR3_REG_FNEG;
 208         if (*dstflags & IR3_REG_SABS)
 209                 srcflags &= ~IR3_REG_SNEG;
 210
 211         if (srcflags & IR3_REG_FABS)
 212                 *dstflags |= IR3_REG_FABS;
 213         if (srcflags & IR3_REG_SABS)
 214                 *dstflags |= IR3_REG_SABS;
 215         if (srcflags & IR3_REG_FNEG)
 216                 *dstflags ^= IR3_REG_FNEG;
 217         if (srcflags & IR3_REG_SNEG)
 218                 *dstflags ^= IR3_REG_SNEG;
 219         if (srcflags & IR3_REG_BNOT)
 220                 *dstflags ^= IR3_REG_BNOT;
 221
 222         *dstflags &= ~IR3_REG_SSA;
 223         *dstflags |= srcflags & IR3_REG_SSA;
 224         *dstflags |= srcflags & IR3_REG_CONST;
 225         *dstflags |= srcflags & IR3_REG_IMMED;
 226         *dstflags |= srcflags & IR3_REG_RELATIV;
 227         *dstflags |= srcflags & IR3_REG_ARRAY;
 228
 229         /* if src of the src is boolean we can drop the (abs) since we know
 230          * the source value is already a postitive integer.  This cleans
 231          * up the absnegs that get inserted when converting between nir and
 232          * native boolean (see ir3_b2n/n2b)
 233          */
 234         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 235         if (srcsrc && is_bool(srcsrc))
 236                 *dstflags &= ~IR3_REG_SABS;
 237 }
 238
 239 static struct ir3_register *
 240 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags)
 241 {
 242         unsigned swiz, idx, i;
 243
 244         reg = ir3_reg_clone(ctx->shader, reg);
 245
 246         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 247          * so just evaluate those and clear the flags:
 248          */
 249         if (new_flags & IR3_REG_SABS) {
 250                 reg->iim_val = abs(reg->iim_val);
 251                 new_flags &= ~IR3_REG_SABS;
 252         }
 253
 254         if (new_flags & IR3_REG_FABS) {
 255                 reg->fim_val = fabs(reg->fim_val);
 256                 new_flags &= ~IR3_REG_FABS;
 257         }
 258
 259         if (new_flags & IR3_REG_SNEG) {
 260                 reg->iim_val = -reg->iim_val;
 261                 new_flags &= ~IR3_REG_SNEG;
 262         }
 263
 264         if (new_flags & IR3_REG_FNEG) {
 265                 reg->fim_val = -reg->fim_val;
 266                 new_flags &= ~IR3_REG_FNEG;
 267         }
 268
 269         for (i = 0; i < ctx->immediate_idx; i++) {
 270                 swiz = i % 4;
 271                 idx  = i / 4;
 272
 273                 if (ctx->so->immediates[idx].val[swiz] == reg->uim_val) {
 274                         break;
 275                 }
 276         }
 277
 278         if (i == ctx->immediate_idx) {
 279                 /* need to generate a new immediate: */
 280                 swiz = i % 4;
 281                 idx  = i / 4;
 282                 ctx->so->immediates[idx].val[swiz] = reg->uim_val;
 283                 ctx->so->immediates_count = idx + 1;
 284                 ctx->immediate_idx++;
 285         }
 286
 287         new_flags &= ~IR3_REG_IMMED;
 288         new_flags |= IR3_REG_CONST;
 289         reg->flags = new_flags;
 290         reg->num = i + (4 * ctx->so->first_immediate);
 291
 292         return reg;
 293 }
 294
 295 /**
 296  * Handle cp for a given src register.  This additionally handles
 297  * the cases of collapsing immedate/const (which replace the src
 298  * register with a non-ssa src) or collapsing mov's from relative
 299  * src (which needs to also fixup the address src reference by the
 300  * instruction).
 301  */
 302 static void
 303 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 304                 struct ir3_register *reg, unsigned n)
 305 {
 306         struct ir3_instruction *src = ssa(reg);
 307
 308         /* don't propagate copies into a PHI, since we don't know if the
 309          * src block executed:
 310          */
 311         if (instr->opc == OPC_META_PHI)
 312                 return;
 313
 314         if (is_eligible_mov(src, true)) {
 315                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 316                 struct ir3_register *src_reg = src->regs[1];
 317                 unsigned new_flags = reg->flags;
 318
 319                 combine_flags(&new_flags, src);
 320
 321                 if (valid_flags(instr, n, new_flags)) {
 322                         if (new_flags & IR3_REG_ARRAY) {
 323                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 324                                 reg->array = src_reg->array;
 325                         }
 326                         reg->flags = new_flags;
 327                         reg->instr = ssa(src_reg);
 328                 }
 329
 330                 src = ssa(reg);      /* could be null for IR3_REG_ARRAY case */
 331                 if (!src)
 332                         return;
 333         } else if (is_same_type_mov(src) &&
 334                         /* cannot collapse const/immed/etc into meta instrs: */
 335                         !is_meta(instr)) {
 336                 /* immed/const/etc cases, which require some special handling: */
 337                 struct ir3_register *src_reg = src->regs[1];
 338                 unsigned new_flags = reg->flags;
 339
 340                 combine_flags(&new_flags, src);
 341
 342                 if (!valid_flags(instr, n, new_flags)) {
 343                         /* See if lowering an immediate to const would help. */
 344                         if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 345                                 debug_assert(new_flags & IR3_REG_IMMED);
 346                                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags);
 347                                 return;
 348                         }
 349
 350                         /* special case for "normal" mad instructions, we can
 351                          * try swapping the first two args if that fits better.
 352                          *
 353                          * the "plain" MAD's (ie. the ones that don't shift first
 354                          * src prior to multiply) can swap their first two srcs if
 355                          * src[0] is !CONST and src[1] is CONST:
 356                          */
 357                         if ((n == 1) && is_mad(instr->opc) &&
 358                                         !(instr->regs[0 + 1]->flags & (IR3_REG_CONST | IR3_REG_RELATIV)) &&
 359                                         valid_flags(instr, 0, new_flags)) {
 360                                 /* swap src[0] and src[1]: */
 361                                 struct ir3_register *tmp;
 362                                 tmp = instr->regs[0 + 1];
 363                                 instr->regs[0 + 1] = instr->regs[1 + 1];
 364                                 instr->regs[1 + 1] = tmp;
 365                                 n = 0;
 366                         } else {
 367                                 return;
 368                         }
 369                 }
 370
 371                 /* Here we handle the special case of mov from
 372                  * CONST and/or RELATIV.  These need to be handled
 373                  * specially, because in the case of move from CONST
 374                  * there is no src ir3_instruction so we need to
 375                  * replace the ir3_register.  And in the case of
 376                  * RELATIV we need to handle the address register
 377                  * dependency.
 378                  */
 379                 if (src_reg->flags & IR3_REG_CONST) {
 380                         /* an instruction cannot reference two different
 381                          * address registers:
 382                          */
 383                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 384                                         conflicts(instr->address, reg->instr->address))
 385                                 return;
 386
 387                         /* This seems to be a hw bug, or something where the timings
 388                          * just somehow don't work out.  This restriction may only
 389                          * apply if the first src is also CONST.
 390                          */
 391                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 392                                         (src_reg->flags & IR3_REG_RELATIV) &&
 393                                         (src_reg->array.offset == 0))
 394                                 return;
 395
 396                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 397                         src_reg->flags = new_flags;
 398                         instr->regs[n+1] = src_reg;
 399
 400                         if (src_reg->flags & IR3_REG_RELATIV)
 401                                 ir3_instr_set_address(instr, reg->instr->address);
 402
 403                         return;
 404                 }
 405
 406                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 407                                 !conflicts(instr->address, reg->instr->address)) {
 408                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 409                         src_reg->flags = new_flags;
 410                         instr->regs[n+1] = src_reg;
 411                         ir3_instr_set_address(instr, reg->instr->address);
 412
 413                         return;
 414                 }
 415
 416                 /* NOTE: seems we can only do immed integers, so don't
 417                  * need to care about float.  But we do need to handle
 418                  * abs/neg *before* checking that the immediate requires
 419                  * few enough bits to encode:
 420                  *
 421                  * TODO: do we need to do something to avoid accidentally
 422                  * catching a float immed?
 423                  */
 424                 if (src_reg->flags & IR3_REG_IMMED) {
 425                         int32_t iim_val = src_reg->iim_val;
 426
 427                         debug_assert((opc_cat(instr->opc) == 1) ||
 428                                         (opc_cat(instr->opc) == 6) ||
 429                                         ir3_cat2_int(instr->opc));
 430
 431                         if (new_flags & IR3_REG_SABS)
 432                                 iim_val = abs(iim_val);
 433
 434                         if (new_flags & IR3_REG_SNEG)
 435                                 iim_val = -iim_val;
 436
 437                         if (new_flags & IR3_REG_BNOT)
 438                                 iim_val = ~iim_val;
 439
 440                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 441                         if ((instr->opc == OPC_MOV) ||
 442                                         !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff))) {
 443                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 444                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 445                                 src_reg->flags = new_flags;
 446                                 src_reg->iim_val = iim_val;
 447                                 instr->regs[n+1] = src_reg;
 448                         } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 449                                 /* See if lowering an immediate to const would help. */
 450                                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags);
 451                         }
 452
 453                         return;
 454                 }
 455         }
 456 }
 457
 458 /* Handle special case of eliminating output mov, and similar cases where
 459  * there isn't a normal "consuming" instruction.  In this case we cannot
 460  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 461  * be eliminated)
 462  */
 463 static struct ir3_instruction *
 464 eliminate_output_mov(struct ir3_instruction *instr)
 465 {
 466         if (is_eligible_mov(instr, false)) {
 467                 struct ir3_register *reg = instr->regs[1];
 468                 if (!(reg->flags & IR3_REG_ARRAY)) {
 469                         struct ir3_instruction *src_instr = ssa(reg);
 470                         debug_assert(src_instr);
 471                         return src_instr;
 472                 }
 473         }
 474         return instr;
 475 }
 476
 477 /**
 478  * Find instruction src's which are mov's that can be collapsed, replacing
 479  * the mov dst with the mov src
 480  */
 481 static void
 482 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 483 {
 484         struct ir3_register *reg;
 485
 486         if (instr->regs_count == 0)
 487                 return;
 488
 489         if (ir3_instr_check_mark(instr))
 490                 return;
 491
 492         /* walk down the graph from each src: */
 493         foreach_src_n(reg, n, instr) {
 494                 struct ir3_instruction *src = ssa(reg);
 495
 496                 if (!src)
 497                         continue;
 498
 499                 instr_cp(ctx, src);
 500
 501                 /* TODO non-indirect access we could figure out which register
 502                  * we actually want and allow cp..
 503                  */
 504                 if (reg->flags & IR3_REG_ARRAY)
 505                         continue;
 506
 507                 reg_cp(ctx, instr, reg, n);
 508         }
 509
 510         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 511                 struct ir3_instruction *src = ssa(instr->regs[0]);
 512                 if (src)
 513                         instr_cp(ctx, src);
 514         }
 515
 516         if (instr->address) {
 517                 instr_cp(ctx, instr->address);
 518                 ir3_instr_set_address(instr, eliminate_output_mov(instr->address));
 519         }
 520
 521         /* we can end up with extra cmps.s from frontend, which uses a
 522          *
 523          *    cmps.s p0.x, cond, 0
 524          *
 525          * as a way to mov into the predicate register.  But frequently 'cond'
 526          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 527          * just re-write the instruction writing predicate register to get rid
 528          * of the double cmps.
 529          */
 530         if ((instr->opc == OPC_CMPS_S) &&
 531                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 532                         ssa(instr->regs[1]) &&
 533                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 534                         (instr->regs[2]->iim_val == 0)) {
 535                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 536                 switch (cond->opc) {
 537                 case OPC_CMPS_S:
 538                 case OPC_CMPS_F:
 539                 case OPC_CMPS_U:
 540                         instr->opc   = cond->opc;
 541                         instr->flags = cond->flags;
 542                         instr->cat2  = cond->cat2;
 543                         instr->address = cond->address;
 544                         instr->regs[1] = cond->regs[1];
 545                         instr->regs[2] = cond->regs[2];
 546                         break;
 547                 default:
 548                         break;
 549                 }
 550         }
 551 }
 552
 553 void
 554 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 555 {
 556         struct ir3_cp_ctx ctx = {
 557                         .shader = ir,
 558                         .so = so,
 559         };
 560
 561         ir3_clear_mark(ir);
 562
 563         for (unsigned i = 0; i < ir->noutputs; i++) {
 564                 if (ir->outputs[i]) {
 565                         instr_cp(&ctx, ir->outputs[i]);
 566                         ir->outputs[i] = eliminate_output_mov(ir->outputs[i]);
 567                 }
 568         }
 569
 570         for (unsigned i = 0; i < ir->keeps_count; i++) {
 571                 instr_cp(&ctx, ir->keeps[i]);
 572                 ir->keeps[i] = eliminate_output_mov(ir->keeps[i]);
 573         }
 574
 575         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 576                 if (block->condition) {
 577                         instr_cp(&ctx, block->condition);
 578                         block->condition = eliminate_output_mov(block->condition);
 579                 }
 580         }
 581 }