src/gallium/drivers/freedreno/ir3/ir3_cp.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "freedreno_util.h"
  30
  31 #include "ir3.h"
  32 #include "ir3_shader.h"
  33
  34 /*
  35  * Copy Propagate:
  36  */
  37
  38 struct ir3_cp_ctx {
  39         struct ir3 *shader;
  40         struct ir3_shader_variant *so;
  41         unsigned immediate_idx;
  42 };
  43
  44 /* is it a type preserving mov, with ok flags? */
  45 static bool is_eligible_mov(struct ir3_instruction *instr, bool allow_flags)
  46 {
  47         if (is_same_type_mov(instr)) {
  48                 struct ir3_register *dst = instr->regs[0];
  49                 struct ir3_register *src = instr->regs[1];
  50                 struct ir3_instruction *src_instr = ssa(src);
  51
  52                 /* only if mov src is SSA (not const/immed): */
  53                 if (!src_instr)
  54                         return false;
  55
  56                 /* no indirect: */
  57                 if (dst->flags & IR3_REG_RELATIV)
  58                         return false;
  59                 if (src->flags & IR3_REG_RELATIV)
  60                         return false;
  61
  62                 if (!allow_flags)
  63                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  64                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  65                                 return false;
  66
  67                 /* TODO: remove this hack: */
  68                 if (src_instr->opc == OPC_META_FO)
  69                         return false;
  70                 /* TODO: we currently don't handle left/right neighbors
  71                  * very well when inserting parallel-copies into phi..
  72                  * to avoid problems don't eliminate a mov coming out
  73                  * of phi..
  74                  */
  75                 if (src_instr->opc == OPC_META_PHI)
  76                         return false;
  77                 return true;
  78         }
  79         return false;
  80 }
  81
  82 static unsigned cp_flags(unsigned flags)
  83 {
  84         /* only considering these flags (at least for now): */
  85         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
  86                         IR3_REG_FNEG | IR3_REG_FABS |
  87                         IR3_REG_SNEG | IR3_REG_SABS |
  88                         IR3_REG_BNOT | IR3_REG_RELATIV);
  89         return flags;
  90 }
  91
  92 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
  93                 unsigned flags)
  94 {
  95         unsigned valid_flags;
  96         flags = cp_flags(flags);
  97
  98         /* If destination is indirect, then source cannot be.. at least
  99          * I don't think so..
 100          */
 101         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
 102                         (flags & IR3_REG_RELATIV))
 103                 return false;
 104
 105         /* TODO it seems to *mostly* work to cp RELATIV, except we get some
 106          * intermittent piglit variable-indexing fails.  Newer blob driver
 107          * doesn't seem to cp these.  Possibly this is hw workaround?  Not
 108          * sure, but until that is understood better, lets just switch off
 109          * cp for indirect src's:
 110          */
 111         if (flags & IR3_REG_RELATIV)
 112                 return false;
 113
 114         switch (opc_cat(instr->opc)) {
 115         case 1:
 116                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 117                 if (flags & ~valid_flags)
 118                         return false;
 119                 break;
 120         case 2:
 121                 valid_flags = ir3_cat2_absneg(instr->opc) |
 122                                 IR3_REG_CONST | IR3_REG_RELATIV;
 123
 124                 if (ir3_cat2_int(instr->opc))
 125                         valid_flags |= IR3_REG_IMMED;
 126
 127                 if (flags & ~valid_flags)
 128                         return false;
 129
 130                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 131                         unsigned m = (n ^ 1) + 1;
 132                         /* cannot deal w/ const in both srcs:
 133                          * (note that some cat2 actually only have a single src)
 134                          */
 135                         if (m < instr->regs_count) {
 136                                 struct ir3_register *reg = instr->regs[m];
 137                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 138                                         return false;
 139                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 140                                         return false;
 141                         }
 142                         /* cannot be const + ABS|NEG: */
 143                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 144                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 145                                 return false;
 146                 }
 147                 break;
 148         case 3:
 149                 valid_flags = ir3_cat3_absneg(instr->opc) |
 150                                 IR3_REG_CONST | IR3_REG_RELATIV;
 151
 152                 if (flags & ~valid_flags)
 153                         return false;
 154
 155                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 156                         /* cannot deal w/ const/relativ in 2nd src: */
 157                         if (n == 1)
 158                                 return false;
 159                 }
 160
 161                 if (flags & IR3_REG_CONST) {
 162                         /* cannot be const + ABS|NEG: */
 163                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 164                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 165                                 return false;
 166                 }
 167                 break;
 168         case 4:
 169                 /* seems like blob compiler avoids const as src.. */
 170                 /* TODO double check if this is still the case on a4xx */
 171                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 172                         return false;
 173                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 174                         return false;
 175                 break;
 176         case 5:
 177                 /* no flags allowed */
 178                 if (flags)
 179                         return false;
 180                 break;
 181         case 6:
 182                 valid_flags = IR3_REG_IMMED;
 183                 if (flags & ~valid_flags)
 184                         return false;
 185
 186                 if (flags & IR3_REG_IMMED) {
 187                         /* doesn't seem like we can have immediate src for store
 188                          * instructions:
 189                          *
 190                          * TODO this restriction could also apply to load instructions,
 191                          * but for load instructions this arg is the address (and not
 192                          * really sure any good way to test a hard-coded immed addr src)
 193                          */
 194                         if (is_store(instr) && (n == 1))
 195                                 return false;
 196
 197                         /* disallow CP into anything but the SSBO slot argument for
 198                          * atomics:
 199                          */
 200                         if (is_atomic(instr->opc) && (n != 0))
 201                                 return false;
 202                 }
 203
 204                 break;
 205         }
 206
 207         return true;
 208 }
 209
 210 /* propagate register flags from src to dst.. negates need special
 211  * handling to cancel each other out.
 212  */
 213 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 214 {
 215         unsigned srcflags = src->regs[1]->flags;
 216
 217         /* if what we are combining into already has (abs) flags,
 218          * we can drop (neg) from src:
 219          */
 220         if (*dstflags & IR3_REG_FABS)
 221                 srcflags &= ~IR3_REG_FNEG;
 222         if (*dstflags & IR3_REG_SABS)
 223                 srcflags &= ~IR3_REG_SNEG;
 224
 225         if (srcflags & IR3_REG_FABS)
 226                 *dstflags |= IR3_REG_FABS;
 227         if (srcflags & IR3_REG_SABS)
 228                 *dstflags |= IR3_REG_SABS;
 229         if (srcflags & IR3_REG_FNEG)
 230                 *dstflags ^= IR3_REG_FNEG;
 231         if (srcflags & IR3_REG_SNEG)
 232                 *dstflags ^= IR3_REG_SNEG;
 233         if (srcflags & IR3_REG_BNOT)
 234                 *dstflags ^= IR3_REG_BNOT;
 235
 236         *dstflags &= ~IR3_REG_SSA;
 237         *dstflags |= srcflags & IR3_REG_SSA;
 238         *dstflags |= srcflags & IR3_REG_CONST;
 239         *dstflags |= srcflags & IR3_REG_IMMED;
 240         *dstflags |= srcflags & IR3_REG_RELATIV;
 241         *dstflags |= srcflags & IR3_REG_ARRAY;
 242
 243         /* if src of the src is boolean we can drop the (abs) since we know
 244          * the source value is already a postitive integer.  This cleans
 245          * up the absnegs that get inserted when converting between nir and
 246          * native boolean (see ir3_b2n/n2b)
 247          */
 248         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 249         if (srcsrc && is_bool(srcsrc))
 250                 *dstflags &= ~IR3_REG_SABS;
 251 }
 252
 253 static struct ir3_register *
 254 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags)
 255 {
 256         unsigned swiz, idx, i;
 257
 258         reg = ir3_reg_clone(ctx->shader, reg);
 259
 260         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 261          * so just evaluate those and clear the flags:
 262          */
 263         if (new_flags & IR3_REG_SABS) {
 264                 reg->iim_val = abs(reg->iim_val);
 265                 new_flags &= ~IR3_REG_SABS;
 266         }
 267
 268         if (new_flags & IR3_REG_FABS) {
 269                 reg->fim_val = fabs(reg->fim_val);
 270                 new_flags &= ~IR3_REG_FABS;
 271         }
 272
 273         if (new_flags & IR3_REG_SNEG) {
 274                 reg->iim_val = -reg->iim_val;
 275                 new_flags &= ~IR3_REG_SNEG;
 276         }
 277
 278         if (new_flags & IR3_REG_FNEG) {
 279                 reg->fim_val = -reg->fim_val;
 280                 new_flags &= ~IR3_REG_FNEG;
 281         }
 282
 283         for (i = 0; i < ctx->immediate_idx; i++) {
 284                 swiz = i % 4;
 285                 idx  = i / 4;
 286
 287                 if (ctx->so->immediates[idx].val[swiz] == reg->uim_val) {
 288                         break;
 289                 }
 290         }
 291
 292         if (i == ctx->immediate_idx) {
 293                 /* need to generate a new immediate: */
 294                 swiz = i % 4;
 295                 idx  = i / 4;
 296                 ctx->so->immediates[idx].val[swiz] = reg->uim_val;
 297                 ctx->so->immediates_count = idx + 1;
 298                 ctx->immediate_idx++;
 299         }
 300
 301         new_flags &= ~IR3_REG_IMMED;
 302         new_flags |= IR3_REG_CONST;
 303         reg->flags = new_flags;
 304         reg->num = i + (4 * ctx->so->constbase.immediate);
 305
 306         return reg;
 307 }
 308
 309 /**
 310  * Handle cp for a given src register.  This additionally handles
 311  * the cases of collapsing immedate/const (which replace the src
 312  * register with a non-ssa src) or collapsing mov's from relative
 313  * src (which needs to also fixup the address src reference by the
 314  * instruction).
 315  */
 316 static void
 317 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 318                 struct ir3_register *reg, unsigned n)
 319 {
 320         struct ir3_instruction *src = ssa(reg);
 321
 322         /* don't propagate copies into a PHI, since we don't know if the
 323          * src block executed:
 324          */
 325         if (instr->opc == OPC_META_PHI)
 326                 return;
 327
 328         if (is_eligible_mov(src, true)) {
 329                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 330                 struct ir3_register *src_reg = src->regs[1];
 331                 unsigned new_flags = reg->flags;
 332
 333                 combine_flags(&new_flags, src);
 334
 335                 if (valid_flags(instr, n, new_flags)) {
 336                         if (new_flags & IR3_REG_ARRAY) {
 337                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 338                                 reg->array = src_reg->array;
 339                         }
 340                         reg->flags = new_flags;
 341                         reg->instr = ssa(src_reg);
 342                 }
 343
 344                 src = ssa(reg);      /* could be null for IR3_REG_ARRAY case */
 345                 if (!src)
 346                         return;
 347         } else if (is_same_type_mov(src) &&
 348                         /* cannot collapse const/immed/etc into meta instrs: */
 349                         !is_meta(instr)) {
 350                 /* immed/const/etc cases, which require some special handling: */
 351                 struct ir3_register *src_reg = src->regs[1];
 352                 unsigned new_flags = reg->flags;
 353
 354                 combine_flags(&new_flags, src);
 355
 356                 if (!valid_flags(instr, n, new_flags)) {
 357                         /* See if lowering an immediate to const would help. */
 358                         if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 359                                 debug_assert(new_flags & IR3_REG_IMMED);
 360                                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags);
 361                                 return;
 362                         }
 363
 364                         /* special case for "normal" mad instructions, we can
 365                          * try swapping the first two args if that fits better.
 366                          *
 367                          * the "plain" MAD's (ie. the ones that don't shift first
 368                          * src prior to multiply) can swap their first two srcs if
 369                          * src[0] is !CONST and src[1] is CONST:
 370                          */
 371                         if ((n == 1) && is_mad(instr->opc) &&
 372                                         !(instr->regs[0 + 1]->flags & (IR3_REG_CONST | IR3_REG_RELATIV)) &&
 373                                         valid_flags(instr, 0, new_flags)) {
 374                                 /* swap src[0] and src[1]: */
 375                                 struct ir3_register *tmp;
 376                                 tmp = instr->regs[0 + 1];
 377                                 instr->regs[0 + 1] = instr->regs[1 + 1];
 378                                 instr->regs[1 + 1] = tmp;
 379                                 n = 0;
 380                         } else {
 381                                 return;
 382                         }
 383                 }
 384
 385                 /* Here we handle the special case of mov from
 386                  * CONST and/or RELATIV.  These need to be handled
 387                  * specially, because in the case of move from CONST
 388                  * there is no src ir3_instruction so we need to
 389                  * replace the ir3_register.  And in the case of
 390                  * RELATIV we need to handle the address register
 391                  * dependency.
 392                  */
 393                 if (src_reg->flags & IR3_REG_CONST) {
 394                         /* an instruction cannot reference two different
 395                          * address registers:
 396                          */
 397                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 398                                         conflicts(instr->address, reg->instr->address))
 399                                 return;
 400
 401                         /* This seems to be a hw bug, or something where the timings
 402                          * just somehow don't work out.  This restriction may only
 403                          * apply if the first src is also CONST.
 404                          */
 405                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 406                                         (src_reg->flags & IR3_REG_RELATIV) &&
 407                                         (src_reg->array.offset == 0))
 408                                 return;
 409
 410                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 411                         src_reg->flags = new_flags;
 412                         instr->regs[n+1] = src_reg;
 413
 414                         if (src_reg->flags & IR3_REG_RELATIV)
 415                                 ir3_instr_set_address(instr, reg->instr->address);
 416
 417                         return;
 418                 }
 419
 420                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 421                                 !conflicts(instr->address, reg->instr->address)) {
 422                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 423                         src_reg->flags = new_flags;
 424                         instr->regs[n+1] = src_reg;
 425                         ir3_instr_set_address(instr, reg->instr->address);
 426
 427                         return;
 428                 }
 429
 430                 /* NOTE: seems we can only do immed integers, so don't
 431                  * need to care about float.  But we do need to handle
 432                  * abs/neg *before* checking that the immediate requires
 433                  * few enough bits to encode:
 434                  *
 435                  * TODO: do we need to do something to avoid accidentally
 436                  * catching a float immed?
 437                  */
 438                 if (src_reg->flags & IR3_REG_IMMED) {
 439                         int32_t iim_val = src_reg->iim_val;
 440
 441                         debug_assert((opc_cat(instr->opc) == 1) ||
 442                                         (opc_cat(instr->opc) == 6) ||
 443                                         ir3_cat2_int(instr->opc));
 444
 445                         if (new_flags & IR3_REG_SABS)
 446                                 iim_val = abs(iim_val);
 447
 448                         if (new_flags & IR3_REG_SNEG)
 449                                 iim_val = -iim_val;
 450
 451                         if (new_flags & IR3_REG_BNOT)
 452                                 iim_val = ~iim_val;
 453
 454                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 455                         if ((instr->opc == OPC_MOV) ||
 456                                         !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff))) {
 457                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 458                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 459                                 src_reg->flags = new_flags;
 460                                 src_reg->iim_val = iim_val;
 461                                 instr->regs[n+1] = src_reg;
 462                         } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 463                                 /* See if lowering an immediate to const would help. */
 464                                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags);
 465                         }
 466
 467                         return;
 468                 }
 469         }
 470 }
 471
 472 /* Handle special case of eliminating output mov, and similar cases where
 473  * there isn't a normal "consuming" instruction.  In this case we cannot
 474  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 475  * be eliminated)
 476  */
 477 static struct ir3_instruction *
 478 eliminate_output_mov(struct ir3_instruction *instr)
 479 {
 480         if (is_eligible_mov(instr, false)) {
 481                 struct ir3_register *reg = instr->regs[1];
 482                 if (!(reg->flags & IR3_REG_ARRAY)) {
 483                         struct ir3_instruction *src_instr = ssa(reg);
 484                         debug_assert(src_instr);
 485                         return src_instr;
 486                 }
 487         }
 488         return instr;
 489 }
 490
 491 /**
 492  * Find instruction src's which are mov's that can be collapsed, replacing
 493  * the mov dst with the mov src
 494  */
 495 static void
 496 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 497 {
 498         struct ir3_register *reg;
 499
 500         if (instr->regs_count == 0)
 501                 return;
 502
 503         if (ir3_instr_check_mark(instr))
 504                 return;
 505
 506         /* walk down the graph from each src: */
 507         foreach_src_n(reg, n, instr) {
 508                 struct ir3_instruction *src = ssa(reg);
 509
 510                 if (!src)
 511                         continue;
 512
 513                 instr_cp(ctx, src);
 514
 515                 /* TODO non-indirect access we could figure out which register
 516                  * we actually want and allow cp..
 517                  */
 518                 if (reg->flags & IR3_REG_ARRAY)
 519                         continue;
 520
 521                 reg_cp(ctx, instr, reg, n);
 522         }
 523
 524         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 525                 struct ir3_instruction *src = ssa(instr->regs[0]);
 526                 if (src)
 527                         instr_cp(ctx, src);
 528         }
 529
 530         if (instr->address) {
 531                 instr_cp(ctx, instr->address);
 532                 ir3_instr_set_address(instr, eliminate_output_mov(instr->address));
 533         }
 534
 535         /* we can end up with extra cmps.s from frontend, which uses a
 536          *
 537          *    cmps.s p0.x, cond, 0
 538          *
 539          * as a way to mov into the predicate register.  But frequently 'cond'
 540          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 541          * just re-write the instruction writing predicate register to get rid
 542          * of the double cmps.
 543          */
 544         if ((instr->opc == OPC_CMPS_S) &&
 545                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 546                         ssa(instr->regs[1]) &&
 547                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 548                         (instr->regs[2]->iim_val == 0)) {
 549                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 550                 switch (cond->opc) {
 551                 case OPC_CMPS_S:
 552                 case OPC_CMPS_F:
 553                 case OPC_CMPS_U:
 554                         instr->opc   = cond->opc;
 555                         instr->flags = cond->flags;
 556                         instr->cat2  = cond->cat2;
 557                         instr->address = cond->address;
 558                         instr->regs[1] = cond->regs[1];
 559                         instr->regs[2] = cond->regs[2];
 560                         break;
 561                 default:
 562                         break;
 563                 }
 564         }
 565 }
 566
 567 void
 568 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 569 {
 570         struct ir3_cp_ctx ctx = {
 571                         .shader = ir,
 572                         .so = so,
 573         };
 574
 575         ir3_clear_mark(ir);
 576
 577         for (unsigned i = 0; i < ir->noutputs; i++) {
 578                 if (ir->outputs[i]) {
 579                         instr_cp(&ctx, ir->outputs[i]);
 580                         ir->outputs[i] = eliminate_output_mov(ir->outputs[i]);
 581                 }
 582         }
 583
 584         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 585                 if (block->condition) {
 586                         instr_cp(&ctx, block->condition);
 587                         block->condition = eliminate_output_mov(block->condition);
 588                 }
 589
 590                 for (unsigned i = 0; i < block->keeps_count; i++) {
 591                         instr_cp(&ctx, block->keeps[i]);
 592                         block->keeps[i] = eliminate_output_mov(block->keeps[i]);
 593                 }
 594         }
 595 }