e3a3a9db690758f53f330555ff57114158e8bb69
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "freedreno_util.h"
32 #include "ir3_shader.h"
40 struct ir3_shader_variant
*so
;
41 unsigned immediate_idx
;
44 /* is it a type preserving mov, with ok flags? */
45 static bool is_eligible_mov(struct ir3_instruction
*instr
, bool allow_flags
)
47 if (is_same_type_mov(instr
)) {
48 struct ir3_register
*dst
= instr
->regs
[0];
49 struct ir3_register
*src
= instr
->regs
[1];
50 struct ir3_instruction
*src_instr
= ssa(src
);
52 /* only if mov src is SSA (not const/immed): */
57 if (dst
->flags
& IR3_REG_RELATIV
)
59 if (src
->flags
& IR3_REG_RELATIV
)
62 if (src
->flags
& IR3_REG_ARRAY
)
66 if (src
->flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
67 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
70 /* TODO: remove this hack: */
71 if (src_instr
->opc
== OPC_META_FO
)
79 static unsigned cp_flags(unsigned flags
)
81 /* only considering these flags (at least for now): */
82 flags
&= (IR3_REG_CONST
| IR3_REG_IMMED
|
83 IR3_REG_FNEG
| IR3_REG_FABS
|
84 IR3_REG_SNEG
| IR3_REG_SABS
|
85 IR3_REG_BNOT
| IR3_REG_RELATIV
);
89 static bool valid_flags(struct ir3_instruction
*instr
, unsigned n
,
93 flags
= cp_flags(flags
);
95 /* If destination is indirect, then source cannot be.. at least
98 if ((instr
->regs
[0]->flags
& IR3_REG_RELATIV
) &&
99 (flags
& IR3_REG_RELATIV
))
102 /* TODO it seems to *mostly* work to cp RELATIV, except we get some
103 * intermittent piglit variable-indexing fails. Newer blob driver
104 * doesn't seem to cp these. Possibly this is hw workaround? Not
105 * sure, but until that is understood better, lets just switch off
106 * cp for indirect src's:
108 if (flags
& IR3_REG_RELATIV
)
111 switch (opc_cat(instr
->opc
)) {
113 valid_flags
= IR3_REG_IMMED
| IR3_REG_CONST
| IR3_REG_RELATIV
;
114 if (flags
& ~valid_flags
)
118 valid_flags
= ir3_cat2_absneg(instr
->opc
) |
119 IR3_REG_CONST
| IR3_REG_RELATIV
;
121 if (ir3_cat2_int(instr
->opc
))
122 valid_flags
|= IR3_REG_IMMED
;
124 if (flags
& ~valid_flags
)
127 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
)) {
128 unsigned m
= (n
^ 1) + 1;
129 /* cannot deal w/ const in both srcs:
130 * (note that some cat2 actually only have a single src)
132 if (m
< instr
->regs_count
) {
133 struct ir3_register
*reg
= instr
->regs
[m
];
134 if ((flags
& IR3_REG_CONST
) && (reg
->flags
& IR3_REG_CONST
))
136 if ((flags
& IR3_REG_IMMED
) && (reg
->flags
& IR3_REG_IMMED
))
139 /* cannot be const + ABS|NEG: */
140 if (flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
141 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
146 valid_flags
= ir3_cat3_absneg(instr
->opc
) |
147 IR3_REG_CONST
| IR3_REG_RELATIV
;
149 if (flags
& ~valid_flags
)
152 if (flags
& (IR3_REG_CONST
| IR3_REG_RELATIV
)) {
153 /* cannot deal w/ const/relativ in 2nd src: */
158 if (flags
& IR3_REG_CONST
) {
159 /* cannot be const + ABS|NEG: */
160 if (flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
161 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
166 /* seems like blob compiler avoids const as src.. */
167 /* TODO double check if this is still the case on a4xx */
168 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
170 if (flags
& (IR3_REG_SABS
| IR3_REG_SNEG
))
174 /* no flags allowed */
179 valid_flags
= IR3_REG_IMMED
;
180 if (flags
& ~valid_flags
)
183 if (flags
& IR3_REG_IMMED
) {
184 /* doesn't seem like we can have immediate src for store
187 * TODO this restriction could also apply to load instructions,
188 * but for load instructions this arg is the address (and not
189 * really sure any good way to test a hard-coded immed addr src)
191 if (is_store(instr
) && (n
== 1))
194 if ((instr
->opc
== OPC_LDL
) && (n
!= 1))
197 if ((instr
->opc
== OPC_STL
) && (n
!= 2))
200 /* disallow CP into anything but the SSBO slot argument for
203 if (is_atomic(instr
->opc
) && (n
!= 0))
206 if (is_atomic(instr
->opc
) && !(instr
->flags
& IR3_INSTR_G
))
216 /* propagate register flags from src to dst.. negates need special
217 * handling to cancel each other out.
219 static void combine_flags(unsigned *dstflags
, struct ir3_instruction
*src
)
221 unsigned srcflags
= src
->regs
[1]->flags
;
223 /* if what we are combining into already has (abs) flags,
224 * we can drop (neg) from src:
226 if (*dstflags
& IR3_REG_FABS
)
227 srcflags
&= ~IR3_REG_FNEG
;
228 if (*dstflags
& IR3_REG_SABS
)
229 srcflags
&= ~IR3_REG_SNEG
;
231 if (srcflags
& IR3_REG_FABS
)
232 *dstflags
|= IR3_REG_FABS
;
233 if (srcflags
& IR3_REG_SABS
)
234 *dstflags
|= IR3_REG_SABS
;
235 if (srcflags
& IR3_REG_FNEG
)
236 *dstflags
^= IR3_REG_FNEG
;
237 if (srcflags
& IR3_REG_SNEG
)
238 *dstflags
^= IR3_REG_SNEG
;
239 if (srcflags
& IR3_REG_BNOT
)
240 *dstflags
^= IR3_REG_BNOT
;
242 *dstflags
&= ~IR3_REG_SSA
;
243 *dstflags
|= srcflags
& IR3_REG_SSA
;
244 *dstflags
|= srcflags
& IR3_REG_CONST
;
245 *dstflags
|= srcflags
& IR3_REG_IMMED
;
246 *dstflags
|= srcflags
& IR3_REG_RELATIV
;
247 *dstflags
|= srcflags
& IR3_REG_ARRAY
;
249 /* if src of the src is boolean we can drop the (abs) since we know
250 * the source value is already a postitive integer. This cleans
251 * up the absnegs that get inserted when converting between nir and
252 * native boolean (see ir3_b2n/n2b)
254 struct ir3_instruction
*srcsrc
= ssa(src
->regs
[1]);
255 if (srcsrc
&& is_bool(srcsrc
))
256 *dstflags
&= ~IR3_REG_SABS
;
259 static struct ir3_register
*
260 lower_immed(struct ir3_cp_ctx
*ctx
, struct ir3_register
*reg
, unsigned new_flags
)
262 unsigned swiz
, idx
, i
;
264 reg
= ir3_reg_clone(ctx
->shader
, reg
);
266 /* in some cases, there are restrictions on (abs)/(neg) plus const..
267 * so just evaluate those and clear the flags:
269 if (new_flags
& IR3_REG_SABS
) {
270 reg
->iim_val
= abs(reg
->iim_val
);
271 new_flags
&= ~IR3_REG_SABS
;
274 if (new_flags
& IR3_REG_FABS
) {
275 reg
->fim_val
= fabs(reg
->fim_val
);
276 new_flags
&= ~IR3_REG_FABS
;
279 if (new_flags
& IR3_REG_SNEG
) {
280 reg
->iim_val
= -reg
->iim_val
;
281 new_flags
&= ~IR3_REG_SNEG
;
284 if (new_flags
& IR3_REG_FNEG
) {
285 reg
->fim_val
= -reg
->fim_val
;
286 new_flags
&= ~IR3_REG_FNEG
;
289 for (i
= 0; i
< ctx
->immediate_idx
; i
++) {
293 if (ctx
->so
->immediates
[idx
].val
[swiz
] == reg
->uim_val
) {
298 if (i
== ctx
->immediate_idx
) {
299 /* need to generate a new immediate: */
302 ctx
->so
->immediates
[idx
].val
[swiz
] = reg
->uim_val
;
303 ctx
->so
->immediates_count
= idx
+ 1;
304 ctx
->immediate_idx
++;
307 new_flags
&= ~IR3_REG_IMMED
;
308 new_flags
|= IR3_REG_CONST
;
309 reg
->flags
= new_flags
;
310 reg
->num
= i
+ (4 * ctx
->so
->constbase
.immediate
);
316 unuse(struct ir3_instruction
*instr
)
318 debug_assert(instr
->use_count
> 0);
320 if (--instr
->use_count
== 0) {
321 struct ir3_block
*block
= instr
->block
;
323 instr
->barrier_class
= 0;
324 instr
->barrier_conflict
= 0;
326 /* we don't want to remove anything in keeps (which could
327 * be things like array store's)
329 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
330 debug_assert(block
->keeps
[i
] != instr
);
336 * Handle cp for a given src register. This additionally handles
337 * the cases of collapsing immedate/const (which replace the src
338 * register with a non-ssa src) or collapsing mov's from relative
339 * src (which needs to also fixup the address src reference by the
343 reg_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
,
344 struct ir3_register
*reg
, unsigned n
)
346 struct ir3_instruction
*src
= ssa(reg
);
348 if (is_eligible_mov(src
, true)) {
349 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
350 struct ir3_register
*src_reg
= src
->regs
[1];
351 unsigned new_flags
= reg
->flags
;
353 combine_flags(&new_flags
, src
);
355 if (valid_flags(instr
, n
, new_flags
)) {
356 if (new_flags
& IR3_REG_ARRAY
) {
357 debug_assert(!(reg
->flags
& IR3_REG_ARRAY
));
358 reg
->array
= src_reg
->array
;
360 reg
->flags
= new_flags
;
361 reg
->instr
= ssa(src_reg
);
363 instr
->barrier_class
|= src
->barrier_class
;
364 instr
->barrier_conflict
|= src
->barrier_conflict
;
367 reg
->instr
->use_count
++;
370 } else if (is_same_type_mov(src
) &&
371 /* cannot collapse const/immed/etc into meta instrs: */
373 /* immed/const/etc cases, which require some special handling: */
374 struct ir3_register
*src_reg
= src
->regs
[1];
375 unsigned new_flags
= reg
->flags
;
377 combine_flags(&new_flags
, src
);
379 if (!valid_flags(instr
, n
, new_flags
)) {
380 /* See if lowering an immediate to const would help. */
381 if (valid_flags(instr
, n
, (new_flags
& ~IR3_REG_IMMED
) | IR3_REG_CONST
)) {
382 debug_assert(new_flags
& IR3_REG_IMMED
);
383 instr
->regs
[n
+ 1] = lower_immed(ctx
, src_reg
, new_flags
);
387 /* special case for "normal" mad instructions, we can
388 * try swapping the first two args if that fits better.
390 * the "plain" MAD's (ie. the ones that don't shift first
391 * src prior to multiply) can swap their first two srcs if
392 * src[0] is !CONST and src[1] is CONST:
394 if ((n
== 1) && is_mad(instr
->opc
) &&
395 !(instr
->regs
[0 + 1]->flags
& (IR3_REG_CONST
| IR3_REG_RELATIV
)) &&
396 valid_flags(instr
, 0, new_flags
& ~IR3_REG_IMMED
)) {
397 /* swap src[0] and src[1]: */
398 struct ir3_register
*tmp
;
399 tmp
= instr
->regs
[0 + 1];
400 instr
->regs
[0 + 1] = instr
->regs
[1 + 1];
401 instr
->regs
[1 + 1] = tmp
;
409 /* Here we handle the special case of mov from
410 * CONST and/or RELATIV. These need to be handled
411 * specially, because in the case of move from CONST
412 * there is no src ir3_instruction so we need to
413 * replace the ir3_register. And in the case of
414 * RELATIV we need to handle the address register
417 if (src_reg
->flags
& IR3_REG_CONST
) {
418 /* an instruction cannot reference two different
421 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
422 conflicts(instr
->address
, reg
->instr
->address
))
425 /* This seems to be a hw bug, or something where the timings
426 * just somehow don't work out. This restriction may only
427 * apply if the first src is also CONST.
429 if ((opc_cat(instr
->opc
) == 3) && (n
== 2) &&
430 (src_reg
->flags
& IR3_REG_RELATIV
) &&
431 (src_reg
->array
.offset
== 0))
434 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
435 src_reg
->flags
= new_flags
;
436 instr
->regs
[n
+1] = src_reg
;
438 if (src_reg
->flags
& IR3_REG_RELATIV
)
439 ir3_instr_set_address(instr
, reg
->instr
->address
);
444 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
445 !conflicts(instr
->address
, reg
->instr
->address
)) {
446 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
447 src_reg
->flags
= new_flags
;
448 instr
->regs
[n
+1] = src_reg
;
449 ir3_instr_set_address(instr
, reg
->instr
->address
);
454 /* NOTE: seems we can only do immed integers, so don't
455 * need to care about float. But we do need to handle
456 * abs/neg *before* checking that the immediate requires
457 * few enough bits to encode:
459 * TODO: do we need to do something to avoid accidentally
460 * catching a float immed?
462 if (src_reg
->flags
& IR3_REG_IMMED
) {
463 int32_t iim_val
= src_reg
->iim_val
;
465 debug_assert((opc_cat(instr
->opc
) == 1) ||
466 (opc_cat(instr
->opc
) == 6) ||
467 ir3_cat2_int(instr
->opc
) ||
468 (is_mad(instr
->opc
) && (n
== 0)));
470 if (new_flags
& IR3_REG_SABS
)
471 iim_val
= abs(iim_val
);
473 if (new_flags
& IR3_REG_SNEG
)
476 if (new_flags
& IR3_REG_BNOT
)
479 /* other than category 1 (mov) we can only encode up to 10 bits: */
480 if ((instr
->opc
== OPC_MOV
) ||
481 !((iim_val
& ~0x3ff) && (-iim_val
& ~0x3ff))) {
482 new_flags
&= ~(IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
);
483 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
484 src_reg
->flags
= new_flags
;
485 src_reg
->iim_val
= iim_val
;
486 instr
->regs
[n
+1] = src_reg
;
487 } else if (valid_flags(instr
, n
, (new_flags
& ~IR3_REG_IMMED
) | IR3_REG_CONST
)) {
488 /* See if lowering an immediate to const would help. */
489 instr
->regs
[n
+1] = lower_immed(ctx
, src_reg
, new_flags
);
497 /* Handle special case of eliminating output mov, and similar cases where
498 * there isn't a normal "consuming" instruction. In this case we cannot
499 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
502 static struct ir3_instruction
*
503 eliminate_output_mov(struct ir3_instruction
*instr
)
505 if (is_eligible_mov(instr
, false)) {
506 struct ir3_register
*reg
= instr
->regs
[1];
507 if (!(reg
->flags
& IR3_REG_ARRAY
)) {
508 struct ir3_instruction
*src_instr
= ssa(reg
);
509 debug_assert(src_instr
);
517 * Find instruction src's which are mov's that can be collapsed, replacing
518 * the mov dst with the mov src
521 instr_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
)
523 struct ir3_register
*reg
;
525 if (instr
->regs_count
== 0)
528 if (ir3_instr_check_mark(instr
))
531 /* walk down the graph from each src: */
532 foreach_src_n(reg
, n
, instr
) {
533 struct ir3_instruction
*src
= ssa(reg
);
540 /* TODO non-indirect access we could figure out which register
541 * we actually want and allow cp..
543 if (reg
->flags
& IR3_REG_ARRAY
)
546 reg_cp(ctx
, instr
, reg
, n
);
549 if (instr
->regs
[0]->flags
& IR3_REG_ARRAY
) {
550 struct ir3_instruction
*src
= ssa(instr
->regs
[0]);
555 if (instr
->address
) {
556 instr_cp(ctx
, instr
->address
);
557 ir3_instr_set_address(instr
, eliminate_output_mov(instr
->address
));
560 /* we can end up with extra cmps.s from frontend, which uses a
562 * cmps.s p0.x, cond, 0
564 * as a way to mov into the predicate register. But frequently 'cond'
565 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case and
566 * just re-write the instruction writing predicate register to get rid
567 * of the double cmps.
569 if ((instr
->opc
== OPC_CMPS_S
) &&
570 (instr
->regs
[0]->num
== regid(REG_P0
, 0)) &&
571 ssa(instr
->regs
[1]) &&
572 (instr
->regs
[2]->flags
& IR3_REG_IMMED
) &&
573 (instr
->regs
[2]->iim_val
== 0)) {
574 struct ir3_instruction
*cond
= ssa(instr
->regs
[1]);
579 instr
->opc
= cond
->opc
;
580 instr
->flags
= cond
->flags
;
581 instr
->cat2
= cond
->cat2
;
582 instr
->address
= cond
->address
;
583 instr
->regs
[1] = cond
->regs
[1];
584 instr
->regs
[2] = cond
->regs
[2];
585 instr
->barrier_class
|= cond
->barrier_class
;
586 instr
->barrier_conflict
|= cond
->barrier_conflict
;
596 ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
)
598 struct ir3_cp_ctx ctx
= {
603 /* This is a bit annoying, and probably wouldn't be necessary if we
604 * tracked a reverse link from producing instruction to consumer.
605 * But we need to know when we've eliminated the last consumer of
606 * a mov, so we need to do a pass to first count consumers of a
609 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
610 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
611 struct ir3_instruction
*src
;
613 /* by the way, we don't account for false-dep's, so the CP
614 * pass should always happen before false-dep's are inserted
616 debug_assert(instr
->deps_count
== 0);
618 foreach_ssa_src(src
, instr
) {
626 for (unsigned i
= 0; i
< ir
->noutputs
; i
++) {
627 if (ir
->outputs
[i
]) {
628 instr_cp(&ctx
, ir
->outputs
[i
]);
629 ir
->outputs
[i
] = eliminate_output_mov(ir
->outputs
[i
]);
633 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
634 if (block
->condition
) {
635 instr_cp(&ctx
, block
->condition
);
636 block
->condition
= eliminate_output_mov(block
->condition
);
639 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
640 instr_cp(&ctx
, block
->keeps
[i
]);
641 block
->keeps
[i
] = eliminate_output_mov(block
->keeps
[i
]);