2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "tgsi/tgsi_parse.h"
36 #include "nir/tgsi_to_nir.h"
38 #include "freedreno_context.h"
39 #include "freedreno_util.h"
41 #include "ir3/ir3_shader.h"
42 #include "ir3/ir3_gallium.h"
43 #include "ir3/ir3_compiler.h"
44 #include "ir3/ir3_nir.h"
47 dump_shader_info(struct ir3_shader_variant
*v
, bool binning_pass
,
48 struct pipe_debug_callback
*debug
)
50 if (!unlikely(fd_mesa_debug
& FD_DBG_SHADERDB
))
53 pipe_debug_message(debug
, SHADER_INFO
,
54 "%s%s shader: %u inst, %u dwords, "
55 "%u half, %u full, %u const, %u constlen, "
56 "%u (ss), %u (sy), %d max_sun, %d loops\n",
57 binning_pass
? "B" : "",
58 ir3_shader_stage(v
->shader
),
61 v
->info
.max_half_reg
+ 1,
63 v
->info
.max_const
+ 1,
65 v
->info
.ss
, v
->info
.sy
,
66 v
->max_sun
, v
->loops
);
69 struct ir3_shader_variant
*
70 ir3_shader_variant(struct ir3_shader
*shader
, struct ir3_shader_key key
,
71 bool binning_pass
, struct pipe_debug_callback
*debug
)
73 struct ir3_shader_variant
*v
;
76 /* some shader key values only apply to vertex or frag shader,
77 * so normalize the key to avoid constructing multiple identical
80 ir3_normalize_key(&key
, shader
->type
);
82 v
= ir3_shader_get_variant(shader
, &key
, binning_pass
, &created
);
85 dump_shader_info(v
, binning_pass
, debug
);
92 copy_stream_out(struct ir3_stream_output_info
*i
,
93 const struct pipe_stream_output_info
*p
)
95 STATIC_ASSERT(ARRAY_SIZE(i
->stride
) == ARRAY_SIZE(p
->stride
));
96 STATIC_ASSERT(ARRAY_SIZE(i
->output
) == ARRAY_SIZE(p
->output
));
98 i
->num_outputs
= p
->num_outputs
;
99 for (int n
= 0; n
< ARRAY_SIZE(i
->stride
); n
++)
100 i
->stride
[n
] = p
->stride
[n
];
102 for (int n
= 0; n
< ARRAY_SIZE(i
->output
); n
++) {
103 i
->output
[n
].register_index
= p
->output
[n
].register_index
;
104 i
->output
[n
].start_component
= p
->output
[n
].start_component
;
105 i
->output
[n
].num_components
= p
->output
[n
].num_components
;
106 i
->output
[n
].output_buffer
= p
->output
[n
].output_buffer
;
107 i
->output
[n
].dst_offset
= p
->output
[n
].dst_offset
;
108 i
->output
[n
].stream
= p
->output
[n
].stream
;
113 ir3_shader_create(struct ir3_compiler
*compiler
,
114 const struct pipe_shader_state
*cso
, gl_shader_stage type
,
115 struct pipe_debug_callback
*debug
,
116 struct pipe_screen
*screen
)
119 if (cso
->type
== PIPE_SHADER_IR_NIR
) {
120 /* we take ownership of the reference: */
123 debug_assert(cso
->type
== PIPE_SHADER_IR_TGSI
);
124 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
125 tgsi_dump(cso
->tokens
, 0);
127 nir
= tgsi_to_nir(cso
->tokens
, screen
);
130 struct ir3_shader
*shader
= ir3_shader_from_nir(compiler
, nir
);
132 copy_stream_out(&shader
->stream_output
, &cso
->stream_output
);
134 if (fd_mesa_debug
& FD_DBG_SHADERDB
) {
135 /* if shader-db run, create a standard variant immediately
136 * (as otherwise nothing will trigger the shader to be
139 static struct ir3_shader_key key
;
140 memset(&key
, 0, sizeof(key
));
141 ir3_shader_variant(shader
, key
, false, debug
);
143 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
144 ir3_shader_variant(shader
, key
, true, debug
);
149 /* a bit annoying that compute-shader and normal shader state objects
150 * aren't a bit more aligned.
153 ir3_shader_create_compute(struct ir3_compiler
*compiler
,
154 const struct pipe_compute_state
*cso
,
155 struct pipe_debug_callback
*debug
,
156 struct pipe_screen
*screen
)
159 if (cso
->ir_type
== PIPE_SHADER_IR_NIR
) {
160 /* we take ownership of the reference: */
161 nir
= (nir_shader
*)cso
->prog
;
163 debug_assert(cso
->ir_type
== PIPE_SHADER_IR_TGSI
);
164 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
165 tgsi_dump(cso
->prog
, 0);
167 nir
= tgsi_to_nir(cso
->prog
, screen
);
170 struct ir3_shader
*shader
= ir3_shader_from_nir(compiler
, nir
);
175 /* This has to reach into the fd_context a bit more than the rest of
176 * ir3, but it needs to be aligned with the compiler, so both agree
177 * on which const regs hold what. And the logic is identical between
178 * a3xx/a4xx, the only difference is small details in the actual
179 * CP_LOAD_STATE packets (which is handled inside the generation
180 * specific ctx->emit_const(_bo)() fxns)
183 #include "freedreno_resource.h"
186 is_stateobj(struct fd_ringbuffer
*ring
)
188 /* XXX this is an ugly way to differentiate.. */
189 return !!(ring
->flags
& FD_RINGBUFFER_STREAMING
);
193 ring_wfi(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
195 /* when we emit const state via ring (IB2) we need a WFI, but when
196 * it is emit'd via stateobj, we don't
198 if (is_stateobj(ring
))
205 emit_user_consts(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
206 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
208 const unsigned index
= 0; /* user consts are index 0 */
210 if (constbuf
->enabled_mask
& (1 << index
)) {
211 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
212 /* size in dwords, aligned to vec4. (This works at least
213 * with mesa/st, which seems to align constant buffer to
216 unsigned size
= align(cb
->buffer_size
, 16) / 4;
218 /* in particular, with binning shader we may end up with
219 * unused consts, ie. we could end up w/ constlen that is
220 * smaller than first_driver_param. In that case truncate
221 * the user consts early to avoid HLSQ lockup caused by
222 * writing too many consts
224 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
225 uint32_t max_const
= MIN2(const_state
->num_uniforms
, v
->constlen
);
227 /* and even if the start of the const buffer is before
228 * first_immediate, the end may not be:
230 size
= MIN2(size
, 4 * max_const
);
233 ring_wfi(ctx
->batch
, ring
);
234 ctx
->emit_const(ring
, v
->type
, 0,
235 cb
->buffer_offset
, size
,
236 cb
->user_buffer
, cb
->buffer
);
240 struct ir3_ubo_analysis_state
*state
;
241 state
= &v
->shader
->ubo_state
;
243 for (uint32_t i
= 1; i
< ARRAY_SIZE(state
->range
); i
++) {
244 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[i
];
246 if (state
->range
[i
].start
< state
->range
[i
].end
&&
247 constbuf
->enabled_mask
& (1 << i
)) {
249 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
250 uint32_t offset
= cb
->buffer_offset
+ state
->range
[i
].start
;
251 debug_assert((state
->range
[i
].offset
% 16) == 0);
252 debug_assert((size
% 16) == 0);
253 debug_assert((offset
% 16) == 0);
254 ctx
->emit_const(ring
, v
->type
, state
->range
[i
].offset
/ 4,
255 offset
, size
/ 4, cb
->user_buffer
, cb
->buffer
);
261 emit_ubos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
262 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
264 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
265 uint32_t offset
= const_state
->offsets
.ubo
;
266 if (v
->constlen
> offset
) {
267 uint32_t params
= const_state
->num_ubos
;
268 uint32_t offsets
[params
];
269 struct pipe_resource
*prscs
[params
];
271 for (uint32_t i
= 0; i
< params
; i
++) {
272 const uint32_t index
= i
+ 1; /* UBOs start at index 1 */
273 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
274 assert(!cb
->user_buffer
);
276 if ((constbuf
->enabled_mask
& (1 << index
)) && cb
->buffer
) {
277 offsets
[i
] = cb
->buffer_offset
;
278 prscs
[i
] = cb
->buffer
;
285 ring_wfi(ctx
->batch
, ring
);
286 ctx
->emit_const_bo(ring
, v
->type
, false, offset
* 4, params
, prscs
, offsets
);
291 emit_ssbo_sizes(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
292 struct fd_ringbuffer
*ring
, struct fd_shaderbuf_stateobj
*sb
)
294 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
295 uint32_t offset
= const_state
->offsets
.ssbo_sizes
;
296 if (v
->constlen
> offset
) {
297 uint32_t sizes
[align(const_state
->ssbo_size
.count
, 4)];
298 unsigned mask
= const_state
->ssbo_size
.mask
;
301 unsigned index
= u_bit_scan(&mask
);
302 unsigned off
= const_state
->ssbo_size
.off
[index
];
303 sizes
[off
] = sb
->sb
[index
].buffer_size
;
306 ring_wfi(ctx
->batch
, ring
);
307 ctx
->emit_const(ring
, v
->type
, offset
* 4,
308 0, ARRAY_SIZE(sizes
), sizes
, NULL
);
313 emit_image_dims(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
314 struct fd_ringbuffer
*ring
, struct fd_shaderimg_stateobj
*si
)
316 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
317 uint32_t offset
= const_state
->offsets
.image_dims
;
318 if (v
->constlen
> offset
) {
319 uint32_t dims
[align(const_state
->image_dims
.count
, 4)];
320 unsigned mask
= const_state
->image_dims
.mask
;
323 struct pipe_image_view
*img
;
324 struct fd_resource
*rsc
;
325 unsigned index
= u_bit_scan(&mask
);
326 unsigned off
= const_state
->image_dims
.off
[index
];
328 img
= &si
->si
[index
];
329 rsc
= fd_resource(img
->resource
);
331 dims
[off
+ 0] = util_format_get_blocksize(img
->format
);
332 if (img
->resource
->target
!= PIPE_BUFFER
) {
333 unsigned lvl
= img
->u
.tex
.level
;
334 /* note for 2d/cube/etc images, even if re-interpreted
335 * as a different color format, the pixel size should
336 * be the same, so use original dimensions for y and z
339 dims
[off
+ 1] = rsc
->slices
[lvl
].pitch
* rsc
->cpp
;
340 /* see corresponding logic in fd_resource_offset(): */
341 if (rsc
->layer_first
) {
342 dims
[off
+ 2] = rsc
->layer_size
;
344 dims
[off
+ 2] = rsc
->slices
[lvl
].size0
;
347 /* For buffer-backed images, the log2 of the format's
348 * bytes-per-pixel is placed on the 2nd slot. This is useful
349 * when emitting image_size instructions, for which we need
350 * to divide by bpp for image buffers. Since the bpp
351 * can only be power-of-two, the division is implemented
352 * as a SHR, and for that it is handy to have the log2 of
353 * bpp as a constant. (log2 = first-set-bit - 1)
355 dims
[off
+ 1] = ffs(dims
[off
+ 0]) - 1;
359 ring_wfi(ctx
->batch
, ring
);
360 ctx
->emit_const(ring
, v
->type
, offset
* 4,
361 0, ARRAY_SIZE(dims
), dims
, NULL
);
366 emit_immediates(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
367 struct fd_ringbuffer
*ring
)
369 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
370 uint32_t base
= const_state
->offsets
.immediate
;
371 int size
= const_state
->immediates_count
;
373 /* truncate size to avoid writing constants that shader
376 size
= MIN2(size
+ base
, v
->constlen
) - base
;
378 /* convert out of vec4: */
383 ring_wfi(ctx
->batch
, ring
);
384 ctx
->emit_const(ring
, v
->type
, base
,
385 0, size
, const_state
->immediates
[0].val
, NULL
);
389 /* emit stream-out buffers: */
391 emit_tfbos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
392 struct fd_ringbuffer
*ring
)
394 /* streamout addresses after driver-params: */
395 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
396 uint32_t offset
= const_state
->offsets
.tfbo
;
397 if (v
->constlen
> offset
) {
398 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
399 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
401 uint32_t offsets
[params
];
402 struct pipe_resource
*prscs
[params
];
404 for (uint32_t i
= 0; i
< params
; i
++) {
405 struct pipe_stream_output_target
*target
= so
->targets
[i
];
408 offsets
[i
] = (so
->offsets
[i
] * info
->stride
[i
] * 4) +
409 target
->buffer_offset
;
410 prscs
[i
] = target
->buffer
;
417 ring_wfi(ctx
->batch
, ring
);
418 ctx
->emit_const_bo(ring
, v
->type
, true, offset
* 4, params
, prscs
, offsets
);
423 max_tf_vtx(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
)
425 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
426 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
427 uint32_t maxvtxcnt
= 0x7fffffff;
429 if (ctx
->screen
->gpu_id
>= 500)
433 if (v
->shader
->stream_output
.num_outputs
== 0)
435 if (so
->num_targets
== 0)
438 /* offset to write to is:
440 * total_vtxcnt = vtxcnt + offsets[i]
441 * offset = total_vtxcnt * stride[i]
443 * offset = vtxcnt * stride[i] ; calculated in shader
444 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
446 * assuming for each vtx, each target buffer will have data written
447 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
449 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
450 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
452 * but shader is actually doing a less-than (rather than less-than-
453 * equal) check, so we can drop the -stride[i].
455 * TODO is assumption about `offset + stride[i]` legit?
457 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
458 struct pipe_stream_output_target
*target
= so
->targets
[i
];
459 unsigned stride
= info
->stride
[i
] * 4; /* convert dwords->bytes */
461 uint32_t max
= target
->buffer_size
/ stride
;
462 maxvtxcnt
= MIN2(maxvtxcnt
, max
);
470 emit_common_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
471 struct fd_context
*ctx
, enum pipe_shader_type t
)
473 enum fd_dirty_shader_state dirty
= ctx
->dirty_shader
[t
];
475 /* When we use CP_SET_DRAW_STATE objects to emit constant state,
476 * if we emit any of it we need to emit all. This is because
477 * we are using the same state-group-id each time for uniform
478 * state, and if previous update is never evaluated (due to no
479 * visible primitives in the current tile) then the new stateobj
480 * completely replaces the old one.
482 * Possibly if we split up different parts of the const state to
483 * different state-objects we could avoid this.
485 if (dirty
&& is_stateobj(ring
))
488 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_CONST
)) {
489 struct fd_constbuf_stateobj
*constbuf
;
492 constbuf
= &ctx
->constbuf
[t
];
493 shader_dirty
= !!(dirty
& FD_DIRTY_SHADER_PROG
);
495 emit_user_consts(ctx
, v
, ring
, constbuf
);
496 emit_ubos(ctx
, v
, ring
, constbuf
);
498 emit_immediates(ctx
, v
, ring
);
501 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_SSBO
)) {
502 struct fd_shaderbuf_stateobj
*sb
= &ctx
->shaderbuf
[t
];
503 emit_ssbo_sizes(ctx
, v
, ring
, sb
);
506 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_IMAGE
)) {
507 struct fd_shaderimg_stateobj
*si
= &ctx
->shaderimg
[t
];
508 emit_image_dims(ctx
, v
, ring
, si
);
513 ir3_emit_vs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
514 struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
516 debug_assert(v
->type
== MESA_SHADER_VERTEX
);
518 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_VERTEX
);
520 /* emit driver params every time: */
521 /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
523 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
524 uint32_t offset
= const_state
->offsets
.driver_param
;
525 if (v
->constlen
> offset
) {
526 uint32_t vertex_params
[IR3_DP_VS_COUNT
] = {
527 [IR3_DP_VTXID_BASE
] = info
->index_size
?
528 info
->index_bias
: info
->start
,
529 [IR3_DP_VTXCNT_MAX
] = max_tf_vtx(ctx
, v
),
531 /* if no user-clip-planes, we don't need to emit the
534 uint32_t vertex_params_size
= 4;
536 if (v
->key
.ucp_enables
) {
537 struct pipe_clip_state
*ucp
= &ctx
->ucp
;
538 unsigned pos
= IR3_DP_UCP0_X
;
539 for (unsigned i
= 0; pos
<= IR3_DP_UCP7_W
; i
++) {
540 for (unsigned j
= 0; j
< 4; j
++) {
541 vertex_params
[pos
] = fui(ucp
->ucp
[i
][j
]);
545 vertex_params_size
= ARRAY_SIZE(vertex_params
);
548 ring_wfi(ctx
->batch
, ring
);
550 bool needs_vtxid_base
=
551 ir3_find_sysval_regid(v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) != regid(63, 0);
553 /* for indirect draw, we need to copy VTXID_BASE from
554 * indirect-draw parameters buffer.. which is annoying
555 * and means we can't easily emit these consts in cmd
556 * stream so need to copy them to bo.
558 if (info
->indirect
&& needs_vtxid_base
) {
559 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
560 struct pipe_resource
*vertex_params_rsc
=
561 pipe_buffer_create(&ctx
->screen
->base
,
562 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
,
563 vertex_params_size
* 4);
564 unsigned src_off
= info
->indirect
->offset
;;
567 ptr
= fd_bo_map(fd_resource(vertex_params_rsc
)->bo
);
568 memcpy(ptr
, vertex_params
, vertex_params_size
* 4);
570 if (info
->index_size
) {
571 /* indexed draw, index_bias is 4th field: */
574 /* non-indexed draw, start is 3rd field: */
578 /* copy index_bias or start from draw params: */
579 ctx
->mem_to_mem(ring
, vertex_params_rsc
, 0,
580 indirect
->buffer
, src_off
, 1);
582 ctx
->emit_const(ring
, MESA_SHADER_VERTEX
, offset
* 4, 0,
583 vertex_params_size
, NULL
, vertex_params_rsc
);
585 pipe_resource_reference(&vertex_params_rsc
, NULL
);
587 ctx
->emit_const(ring
, MESA_SHADER_VERTEX
, offset
* 4, 0,
588 vertex_params_size
, vertex_params
, NULL
);
591 /* if needed, emit stream-out buffer addresses: */
592 if (vertex_params
[IR3_DP_VTXCNT_MAX
] > 0) {
593 emit_tfbos(ctx
, v
, ring
);
600 ir3_emit_fs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
601 struct fd_context
*ctx
)
603 debug_assert(v
->type
== MESA_SHADER_FRAGMENT
);
605 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_FRAGMENT
);
608 /* emit compute-shader consts: */
610 ir3_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
611 struct fd_context
*ctx
, const struct pipe_grid_info
*info
)
613 debug_assert(gl_shader_stage_is_compute(v
->type
));
615 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_COMPUTE
);
617 /* emit compute-shader driver-params: */
618 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
619 uint32_t offset
= const_state
->offsets
.driver_param
;
620 if (v
->constlen
> offset
) {
621 ring_wfi(ctx
->batch
, ring
);
623 if (info
->indirect
) {
624 struct pipe_resource
*indirect
= NULL
;
625 unsigned indirect_offset
;
627 /* This is a bit awkward, but CP_LOAD_STATE.EXT_SRC_ADDR needs
628 * to be aligned more strongly than 4 bytes. So in this case
629 * we need a temporary buffer to copy NumWorkGroups.xyz to.
631 * TODO if previous compute job is writing to info->indirect,
632 * we might need a WFI.. but since we currently flush for each
633 * compute job, we are probably ok for now.
635 if (info
->indirect_offset
& 0xf) {
636 indirect
= pipe_buffer_create(&ctx
->screen
->base
,
637 PIPE_BIND_COMMAND_ARGS_BUFFER
, PIPE_USAGE_STREAM
,
641 ctx
->mem_to_mem(ring
, indirect
, 0, info
->indirect
,
642 info
->indirect_offset
, 3);
644 pipe_resource_reference(&indirect
, info
->indirect
);
645 indirect_offset
= info
->indirect_offset
;
648 ctx
->emit_const(ring
, MESA_SHADER_COMPUTE
, offset
* 4,
649 indirect_offset
, 4, NULL
, indirect
);
651 pipe_resource_reference(&indirect
, NULL
);
653 uint32_t compute_params
[IR3_DP_CS_COUNT
] = {
654 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->grid
[0],
655 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->grid
[1],
656 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->grid
[2],
657 [IR3_DP_LOCAL_GROUP_SIZE_X
] = info
->block
[0],
658 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = info
->block
[1],
659 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = info
->block
[2],
662 ctx
->emit_const(ring
, MESA_SHADER_COMPUTE
, offset
* 4, 0,
663 ARRAY_SIZE(compute_params
), compute_params
, NULL
);