2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "tgsi/tgsi_parse.h"
36 #include "nir/tgsi_to_nir.h"
38 #include "freedreno_context.h"
39 #include "freedreno_util.h"
41 #include "ir3/ir3_shader.h"
42 #include "ir3/ir3_gallium.h"
43 #include "ir3/ir3_compiler.h"
44 #include "ir3/ir3_nir.h"
47 dump_shader_info(struct ir3_shader_variant
*v
, bool binning_pass
,
48 struct pipe_debug_callback
*debug
)
50 if (!unlikely(fd_mesa_debug
& FD_DBG_SHADERDB
))
53 pipe_debug_message(debug
, SHADER_INFO
,
54 "%s shader: %u inst, %u nops, %u non-nops, %u dwords, "
55 "%u last-baryf, %u half, %u full, %u constlen, "
56 "%u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
60 v
->info
.instrs_count
- v
->info
.nops_count
,
63 v
->info
.max_half_reg
+ 1,
67 v
->info
.ss
, v
->info
.sy
,
68 v
->max_sun
, v
->loops
);
71 struct ir3_shader_variant
*
72 ir3_shader_variant(struct ir3_shader
*shader
, struct ir3_shader_key key
,
73 bool binning_pass
, struct pipe_debug_callback
*debug
)
75 struct ir3_shader_variant
*v
;
78 /* some shader key values only apply to vertex or frag shader,
79 * so normalize the key to avoid constructing multiple identical
82 ir3_normalize_key(&key
, shader
->type
);
84 v
= ir3_shader_get_variant(shader
, &key
, binning_pass
, &created
);
87 dump_shader_info(v
, binning_pass
, debug
);
94 copy_stream_out(struct ir3_stream_output_info
*i
,
95 const struct pipe_stream_output_info
*p
)
97 STATIC_ASSERT(ARRAY_SIZE(i
->stride
) == ARRAY_SIZE(p
->stride
));
98 STATIC_ASSERT(ARRAY_SIZE(i
->output
) == ARRAY_SIZE(p
->output
));
100 i
->num_outputs
= p
->num_outputs
;
101 for (int n
= 0; n
< ARRAY_SIZE(i
->stride
); n
++)
102 i
->stride
[n
] = p
->stride
[n
];
104 for (int n
= 0; n
< ARRAY_SIZE(i
->output
); n
++) {
105 i
->output
[n
].register_index
= p
->output
[n
].register_index
;
106 i
->output
[n
].start_component
= p
->output
[n
].start_component
;
107 i
->output
[n
].num_components
= p
->output
[n
].num_components
;
108 i
->output
[n
].output_buffer
= p
->output
[n
].output_buffer
;
109 i
->output
[n
].dst_offset
= p
->output
[n
].dst_offset
;
110 i
->output
[n
].stream
= p
->output
[n
].stream
;
115 ir3_shader_create(struct ir3_compiler
*compiler
,
116 const struct pipe_shader_state
*cso
,
117 struct pipe_debug_callback
*debug
,
118 struct pipe_screen
*screen
)
121 if (cso
->type
== PIPE_SHADER_IR_NIR
) {
122 /* we take ownership of the reference: */
125 debug_assert(cso
->type
== PIPE_SHADER_IR_TGSI
);
126 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
127 tgsi_dump(cso
->tokens
, 0);
129 nir
= tgsi_to_nir(cso
->tokens
, screen
);
132 struct ir3_shader
*shader
= ir3_shader_from_nir(compiler
, nir
);
134 copy_stream_out(&shader
->stream_output
, &cso
->stream_output
);
136 if (fd_mesa_debug
& FD_DBG_SHADERDB
) {
137 /* if shader-db run, create a standard variant immediately
138 * (as otherwise nothing will trigger the shader to be
141 static struct ir3_shader_key key
; /* static is implicitly zeroed */
142 ir3_shader_variant(shader
, key
, false, debug
);
144 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
145 ir3_shader_variant(shader
, key
, true, debug
);
151 /* a bit annoying that compute-shader and normal shader state objects
152 * aren't a bit more aligned.
155 ir3_shader_create_compute(struct ir3_compiler
*compiler
,
156 const struct pipe_compute_state
*cso
,
157 struct pipe_debug_callback
*debug
,
158 struct pipe_screen
*screen
)
161 if (cso
->ir_type
== PIPE_SHADER_IR_NIR
) {
162 /* we take ownership of the reference: */
163 nir
= (nir_shader
*)cso
->prog
;
165 debug_assert(cso
->ir_type
== PIPE_SHADER_IR_TGSI
);
166 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
167 tgsi_dump(cso
->prog
, 0);
169 nir
= tgsi_to_nir(cso
->prog
, screen
);
172 struct ir3_shader
*shader
= ir3_shader_from_nir(compiler
, nir
);
174 if (fd_mesa_debug
& FD_DBG_SHADERDB
) {
175 /* if shader-db run, create a standard variant immediately
176 * (as otherwise nothing will trigger the shader to be
179 static struct ir3_shader_key key
; /* static is implicitly zeroed */
180 ir3_shader_variant(shader
, key
, false, debug
);
186 /* This has to reach into the fd_context a bit more than the rest of
187 * ir3, but it needs to be aligned with the compiler, so both agree
188 * on which const regs hold what. And the logic is identical between
189 * a3xx/a4xx, the only difference is small details in the actual
190 * CP_LOAD_STATE packets (which is handled inside the generation
191 * specific ctx->emit_const(_bo)() fxns)
194 #include "freedreno_resource.h"
197 is_stateobj(struct fd_ringbuffer
*ring
)
199 /* XXX this is an ugly way to differentiate.. */
200 return !!(ring
->flags
& FD_RINGBUFFER_STREAMING
);
204 ring_wfi(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
206 /* when we emit const state via ring (IB2) we need a WFI, but when
207 * it is emit'd via stateobj, we don't
209 if (is_stateobj(ring
))
216 emit_const(struct fd_screen
*screen
, struct fd_ringbuffer
*ring
,
217 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
218 uint32_t offset
, uint32_t size
,
219 const void *user_buffer
, struct pipe_resource
*buffer
)
221 assert(dst_offset
+ size
<= v
->constlen
* 4);
223 screen
->emit_const(ring
, v
->type
, dst_offset
,
224 offset
, size
, user_buffer
, buffer
);
228 * Indirectly calculates size of cmdstream needed for ir3_emit_user_consts().
229 * Returns number of packets, and total size of all the payload.
231 * The value can be a worst-case, ie. some shader variants may not read all
234 * Returns size in dwords.
237 ir3_user_consts_size(struct ir3_ubo_analysis_state
*state
,
238 unsigned *packets
, unsigned *size
)
240 *packets
= *size
= 0;
242 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->range
); i
++) {
243 if (state
->range
[i
].start
< state
->range
[i
].end
) {
244 *size
+= state
->range
[i
].end
- state
->range
[i
].start
;
251 * Uploads sub-ranges of UBOs to the hardware's constant buffer (UBO access
252 * outside of these ranges will be done using full UBO accesses in the
256 ir3_emit_user_consts(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
257 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
259 struct ir3_ubo_analysis_state
*state
;
260 state
= &v
->shader
->ubo_state
;
263 foreach_bit(i
, state
->enabled
& constbuf
->enabled_mask
) {
264 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[i
];
266 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
267 uint32_t offset
= cb
->buffer_offset
+ state
->range
[i
].start
;
269 /* and even if the start of the const buffer is before
270 * first_immediate, the end may not be:
272 size
= MIN2(size
, (16 * v
->constlen
) - state
->range
[i
].offset
);
277 /* things should be aligned to vec4: */
278 debug_assert((state
->range
[i
].offset
% 16) == 0);
279 debug_assert((size
% 16) == 0);
280 debug_assert((offset
% 16) == 0);
282 emit_const(screen
, ring
, v
, state
->range
[i
].offset
/ 4,
283 offset
, size
/ 4, cb
->user_buffer
, cb
->buffer
);
288 ir3_emit_ubos(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
289 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
291 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
292 uint32_t offset
= const_state
->offsets
.ubo
;
293 if (v
->constlen
> offset
) {
294 uint32_t params
= const_state
->num_ubos
;
295 uint32_t offsets
[params
];
296 struct pipe_resource
*prscs
[params
];
298 for (uint32_t i
= 0; i
< params
; i
++) {
299 const uint32_t index
= i
+ 1; /* UBOs start at index 1 */
300 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
301 assert(!cb
->user_buffer
);
303 if ((constbuf
->enabled_mask
& (1 << index
)) && cb
->buffer
) {
304 offsets
[i
] = cb
->buffer_offset
;
305 prscs
[i
] = cb
->buffer
;
312 assert(offset
* 4 + params
< v
->constlen
* 4);
314 screen
->emit_const_bo(ring
, v
->type
, false, offset
* 4, params
, prscs
, offsets
);
319 ir3_emit_ssbo_sizes(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
320 struct fd_ringbuffer
*ring
, struct fd_shaderbuf_stateobj
*sb
)
322 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
323 uint32_t offset
= const_state
->offsets
.ssbo_sizes
;
324 if (v
->constlen
> offset
) {
325 uint32_t sizes
[align(const_state
->ssbo_size
.count
, 4)];
326 unsigned mask
= const_state
->ssbo_size
.mask
;
329 unsigned index
= u_bit_scan(&mask
);
330 unsigned off
= const_state
->ssbo_size
.off
[index
];
331 sizes
[off
] = sb
->sb
[index
].buffer_size
;
334 emit_const(screen
, ring
, v
, offset
* 4,
335 0, ARRAY_SIZE(sizes
), sizes
, NULL
);
340 ir3_emit_image_dims(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
341 struct fd_ringbuffer
*ring
, struct fd_shaderimg_stateobj
*si
)
343 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
344 uint32_t offset
= const_state
->offsets
.image_dims
;
345 if (v
->constlen
> offset
) {
346 uint32_t dims
[align(const_state
->image_dims
.count
, 4)];
347 unsigned mask
= const_state
->image_dims
.mask
;
350 struct pipe_image_view
*img
;
351 struct fd_resource
*rsc
;
352 unsigned index
= u_bit_scan(&mask
);
353 unsigned off
= const_state
->image_dims
.off
[index
];
355 img
= &si
->si
[index
];
356 rsc
= fd_resource(img
->resource
);
358 dims
[off
+ 0] = util_format_get_blocksize(img
->format
);
359 if (img
->resource
->target
!= PIPE_BUFFER
) {
360 struct fdl_slice
*slice
=
361 fd_resource_slice(rsc
, img
->u
.tex
.level
);
362 /* note for 2d/cube/etc images, even if re-interpreted
363 * as a different color format, the pixel size should
364 * be the same, so use original dimensions for y and z
367 dims
[off
+ 1] = slice
->pitch
* rsc
->layout
.cpp
;
368 /* see corresponding logic in fd_resource_offset(): */
369 if (rsc
->layout
.layer_first
) {
370 dims
[off
+ 2] = rsc
->layout
.layer_size
;
372 dims
[off
+ 2] = slice
->size0
;
375 /* For buffer-backed images, the log2 of the format's
376 * bytes-per-pixel is placed on the 2nd slot. This is useful
377 * when emitting image_size instructions, for which we need
378 * to divide by bpp for image buffers. Since the bpp
379 * can only be power-of-two, the division is implemented
380 * as a SHR, and for that it is handy to have the log2 of
381 * bpp as a constant. (log2 = first-set-bit - 1)
383 dims
[off
+ 1] = ffs(dims
[off
+ 0]) - 1;
386 uint32_t size
= MIN2(ARRAY_SIZE(dims
), v
->constlen
* 4 - offset
* 4);
388 emit_const(screen
, ring
, v
, offset
* 4, 0, size
, dims
, NULL
);
393 ir3_emit_immediates(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
394 struct fd_ringbuffer
*ring
)
396 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
397 uint32_t base
= const_state
->offsets
.immediate
;
398 int size
= const_state
->immediates_count
;
400 /* truncate size to avoid writing constants that shader
403 size
= MIN2(size
+ base
, v
->constlen
) - base
;
405 /* convert out of vec4: */
410 emit_const(screen
, ring
, v
, base
,
411 0, size
, const_state
->immediates
[0].val
, NULL
);
416 ir3_emit_link_map(struct fd_screen
*screen
,
417 const struct ir3_shader_variant
*producer
,
418 const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
)
420 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
421 uint32_t base
= const_state
->offsets
.primitive_map
;
422 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
424 num_loc
= ir3_link_geometry_stages(producer
, v
, patch_locs
);
426 int size
= DIV_ROUND_UP(num_loc
, 4);
428 /* truncate size to avoid writing constants that shader
431 size
= MIN2(size
+ base
, v
->constlen
) - base
;
433 /* convert out of vec4: */
438 emit_const(screen
, ring
, v
, base
, 0, size
, patch_locs
, NULL
);
441 /* emit stream-out buffers: */
443 emit_tfbos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
444 struct fd_ringbuffer
*ring
)
446 /* streamout addresses after driver-params: */
447 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
448 uint32_t offset
= const_state
->offsets
.tfbo
;
449 if (v
->constlen
> offset
) {
450 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
451 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
453 uint32_t offsets
[params
];
454 struct pipe_resource
*prscs
[params
];
456 for (uint32_t i
= 0; i
< params
; i
++) {
457 struct pipe_stream_output_target
*target
= so
->targets
[i
];
460 offsets
[i
] = (so
->offsets
[i
] * info
->stride
[i
] * 4) +
461 target
->buffer_offset
;
462 prscs
[i
] = target
->buffer
;
469 assert(offset
* 4 + params
< v
->constlen
* 4);
471 ctx
->screen
->emit_const_bo(ring
, v
->type
, true, offset
* 4, params
, prscs
, offsets
);
476 max_tf_vtx(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
)
478 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
479 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
480 uint32_t maxvtxcnt
= 0x7fffffff;
482 if (ctx
->screen
->gpu_id
>= 500)
486 if (v
->shader
->stream_output
.num_outputs
== 0)
488 if (so
->num_targets
== 0)
491 /* offset to write to is:
493 * total_vtxcnt = vtxcnt + offsets[i]
494 * offset = total_vtxcnt * stride[i]
496 * offset = vtxcnt * stride[i] ; calculated in shader
497 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
499 * assuming for each vtx, each target buffer will have data written
500 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
502 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
503 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
505 * but shader is actually doing a less-than (rather than less-than-
506 * equal) check, so we can drop the -stride[i].
508 * TODO is assumption about `offset + stride[i]` legit?
510 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
511 struct pipe_stream_output_target
*target
= so
->targets
[i
];
512 unsigned stride
= info
->stride
[i
] * 4; /* convert dwords->bytes */
514 uint32_t max
= target
->buffer_size
/ stride
;
515 maxvtxcnt
= MIN2(maxvtxcnt
, max
);
523 emit_common_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
524 struct fd_context
*ctx
, enum pipe_shader_type t
)
526 enum fd_dirty_shader_state dirty
= ctx
->dirty_shader
[t
];
528 /* When we use CP_SET_DRAW_STATE objects to emit constant state,
529 * if we emit any of it we need to emit all. This is because
530 * we are using the same state-group-id each time for uniform
531 * state, and if previous update is never evaluated (due to no
532 * visible primitives in the current tile) then the new stateobj
533 * completely replaces the old one.
535 * Possibly if we split up different parts of the const state to
536 * different state-objects we could avoid this.
538 if (dirty
&& is_stateobj(ring
))
541 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_CONST
)) {
542 struct fd_constbuf_stateobj
*constbuf
;
545 constbuf
= &ctx
->constbuf
[t
];
546 shader_dirty
= !!(dirty
& FD_DIRTY_SHADER_PROG
);
548 ring_wfi(ctx
->batch
, ring
);
550 ir3_emit_user_consts(ctx
->screen
, v
, ring
, constbuf
);
551 ir3_emit_ubos(ctx
->screen
, v
, ring
, constbuf
);
553 ir3_emit_immediates(ctx
->screen
, v
, ring
);
556 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_SSBO
)) {
557 struct fd_shaderbuf_stateobj
*sb
= &ctx
->shaderbuf
[t
];
558 ring_wfi(ctx
->batch
, ring
);
559 ir3_emit_ssbo_sizes(ctx
->screen
, v
, ring
, sb
);
562 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_IMAGE
)) {
563 struct fd_shaderimg_stateobj
*si
= &ctx
->shaderimg
[t
];
564 ring_wfi(ctx
->batch
, ring
);
565 ir3_emit_image_dims(ctx
->screen
, v
, ring
, si
);
570 ir3_emit_vs_driver_params(const struct ir3_shader_variant
*v
,
571 struct fd_ringbuffer
*ring
, struct fd_context
*ctx
,
572 const struct pipe_draw_info
*info
)
574 debug_assert(ir3_needs_vs_driver_params(v
));
576 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
577 uint32_t offset
= const_state
->offsets
.driver_param
;
578 uint32_t vertex_params
[IR3_DP_VS_COUNT
] = {
579 [IR3_DP_VTXID_BASE
] = info
->index_size
?
580 info
->index_bias
: info
->start
,
581 [IR3_DP_VTXCNT_MAX
] = max_tf_vtx(ctx
, v
),
583 /* if no user-clip-planes, we don't need to emit the
586 uint32_t vertex_params_size
= 4;
588 if (v
->key
.ucp_enables
) {
589 struct pipe_clip_state
*ucp
= &ctx
->ucp
;
590 unsigned pos
= IR3_DP_UCP0_X
;
591 for (unsigned i
= 0; pos
<= IR3_DP_UCP7_W
; i
++) {
592 for (unsigned j
= 0; j
< 4; j
++) {
593 vertex_params
[pos
] = fui(ucp
->ucp
[i
][j
]);
597 vertex_params_size
= ARRAY_SIZE(vertex_params
);
600 vertex_params_size
= MAX2(vertex_params_size
, const_state
->num_driver_params
);
602 bool needs_vtxid_base
=
603 ir3_find_sysval_regid(v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) != regid(63, 0);
605 /* for indirect draw, we need to copy VTXID_BASE from
606 * indirect-draw parameters buffer.. which is annoying
607 * and means we can't easily emit these consts in cmd
608 * stream so need to copy them to bo.
610 if (info
->indirect
&& needs_vtxid_base
) {
611 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
612 struct pipe_resource
*vertex_params_rsc
=
613 pipe_buffer_create(&ctx
->screen
->base
,
614 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
,
615 vertex_params_size
* 4);
616 unsigned src_off
= info
->indirect
->offset
;;
619 ptr
= fd_bo_map(fd_resource(vertex_params_rsc
)->bo
);
620 memcpy(ptr
, vertex_params
, vertex_params_size
* 4);
622 if (info
->index_size
) {
623 /* indexed draw, index_bias is 4th field: */
626 /* non-indexed draw, start is 3rd field: */
630 /* copy index_bias or start from draw params: */
631 ctx
->screen
->mem_to_mem(ring
, vertex_params_rsc
, 0,
632 indirect
->buffer
, src_off
, 1);
634 emit_const(ctx
->screen
, ring
, v
, offset
* 4, 0,
635 vertex_params_size
, NULL
, vertex_params_rsc
);
637 pipe_resource_reference(&vertex_params_rsc
, NULL
);
639 emit_const(ctx
->screen
, ring
, v
, offset
* 4, 0,
640 vertex_params_size
, vertex_params
, NULL
);
643 /* if needed, emit stream-out buffer addresses: */
644 if (vertex_params
[IR3_DP_VTXCNT_MAX
] > 0) {
645 emit_tfbos(ctx
, v
, ring
);
650 ir3_emit_vs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
651 struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
653 debug_assert(v
->type
== MESA_SHADER_VERTEX
);
655 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_VERTEX
);
657 /* emit driver params every time: */
658 if (info
&& ir3_needs_vs_driver_params(v
)) {
659 ring_wfi(ctx
->batch
, ring
);
660 ir3_emit_vs_driver_params(v
, ring
, ctx
, info
);
665 ir3_emit_fs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
666 struct fd_context
*ctx
)
668 debug_assert(v
->type
== MESA_SHADER_FRAGMENT
);
670 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_FRAGMENT
);
673 /* emit compute-shader consts: */
675 ir3_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
676 struct fd_context
*ctx
, const struct pipe_grid_info
*info
)
678 debug_assert(gl_shader_stage_is_compute(v
->type
));
680 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_COMPUTE
);
682 /* emit compute-shader driver-params: */
683 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
684 uint32_t offset
= const_state
->offsets
.driver_param
;
685 if (v
->constlen
> offset
) {
686 ring_wfi(ctx
->batch
, ring
);
688 if (info
->indirect
) {
689 struct pipe_resource
*indirect
= NULL
;
690 unsigned indirect_offset
;
692 /* This is a bit awkward, but CP_LOAD_STATE.EXT_SRC_ADDR needs
693 * to be aligned more strongly than 4 bytes. So in this case
694 * we need a temporary buffer to copy NumWorkGroups.xyz to.
696 * TODO if previous compute job is writing to info->indirect,
697 * we might need a WFI.. but since we currently flush for each
698 * compute job, we are probably ok for now.
700 if (info
->indirect_offset
& 0xf) {
701 indirect
= pipe_buffer_create(&ctx
->screen
->base
,
702 PIPE_BIND_COMMAND_ARGS_BUFFER
, PIPE_USAGE_STREAM
,
706 ctx
->screen
->mem_to_mem(ring
, indirect
, 0, info
->indirect
,
707 info
->indirect_offset
, 3);
709 pipe_resource_reference(&indirect
, info
->indirect
);
710 indirect_offset
= info
->indirect_offset
;
713 emit_const(ctx
->screen
, ring
, v
, offset
* 4,
714 indirect_offset
, 4, NULL
, indirect
);
716 pipe_resource_reference(&indirect
, NULL
);
718 uint32_t compute_params
[IR3_DP_CS_COUNT
] = {
719 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->grid
[0],
720 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->grid
[1],
721 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->grid
[2],
722 [IR3_DP_LOCAL_GROUP_SIZE_X
] = info
->block
[0],
723 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = info
->block
[1],
724 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = info
->block
[2],
726 uint32_t size
= MIN2(const_state
->num_driver_params
,
727 v
->constlen
* 4 - offset
* 4);
729 emit_const(ctx
->screen
, ring
, v
, offset
* 4, 0, size
,
730 compute_params
, NULL
);
736 ir3_shader_state_create(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
)
738 struct fd_context
*ctx
= fd_context(pctx
);
739 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
740 return ir3_shader_create(compiler
, cso
, &ctx
->debug
, pctx
->screen
);
744 ir3_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
746 struct ir3_shader
*so
= hwcso
;
747 ir3_shader_destroy(so
);
751 ir3_prog_init(struct pipe_context
*pctx
)
753 pctx
->create_vs_state
= ir3_shader_state_create
;
754 pctx
->delete_vs_state
= ir3_shader_state_delete
;
756 pctx
->create_tcs_state
= ir3_shader_state_create
;
757 pctx
->delete_tcs_state
= ir3_shader_state_delete
;
759 pctx
->create_tes_state
= ir3_shader_state_create
;
760 pctx
->delete_tes_state
= ir3_shader_state_delete
;
762 pctx
->create_gs_state
= ir3_shader_state_create
;
763 pctx
->delete_gs_state
= ir3_shader_state_delete
;
765 pctx
->create_fs_state
= ir3_shader_state_create
;
766 pctx
->delete_fs_state
= ir3_shader_state_delete
;