2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "tgsi/tgsi_parse.h"
36 #include "nir/tgsi_to_nir.h"
38 #include "freedreno_context.h"
39 #include "freedreno_util.h"
41 #include "ir3/ir3_shader.h"
42 #include "ir3/ir3_gallium.h"
43 #include "ir3/ir3_compiler.h"
44 #include "ir3/ir3_nir.h"
47 dump_shader_info(struct ir3_shader_variant
*v
, bool binning_pass
,
48 struct pipe_debug_callback
*debug
)
50 if (!unlikely(fd_mesa_debug
& FD_DBG_SHADERDB
))
53 pipe_debug_message(debug
, SHADER_INFO
,
54 "%s shader: %u inst, %u dwords, "
55 "%u half, %u full, %u constlen, "
56 "%u (ss), %u (sy), %d max_sun, %d loops\n",
60 v
->info
.max_half_reg
+ 1,
63 v
->info
.ss
, v
->info
.sy
,
64 v
->max_sun
, v
->loops
);
67 struct ir3_shader_variant
*
68 ir3_shader_variant(struct ir3_shader
*shader
, struct ir3_shader_key key
,
69 bool binning_pass
, struct pipe_debug_callback
*debug
)
71 struct ir3_shader_variant
*v
;
74 /* some shader key values only apply to vertex or frag shader,
75 * so normalize the key to avoid constructing multiple identical
78 ir3_normalize_key(&key
, shader
->type
);
80 v
= ir3_shader_get_variant(shader
, &key
, binning_pass
, &created
);
83 dump_shader_info(v
, binning_pass
, debug
);
90 copy_stream_out(struct ir3_stream_output_info
*i
,
91 const struct pipe_stream_output_info
*p
)
93 STATIC_ASSERT(ARRAY_SIZE(i
->stride
) == ARRAY_SIZE(p
->stride
));
94 STATIC_ASSERT(ARRAY_SIZE(i
->output
) == ARRAY_SIZE(p
->output
));
96 i
->num_outputs
= p
->num_outputs
;
97 for (int n
= 0; n
< ARRAY_SIZE(i
->stride
); n
++)
98 i
->stride
[n
] = p
->stride
[n
];
100 for (int n
= 0; n
< ARRAY_SIZE(i
->output
); n
++) {
101 i
->output
[n
].register_index
= p
->output
[n
].register_index
;
102 i
->output
[n
].start_component
= p
->output
[n
].start_component
;
103 i
->output
[n
].num_components
= p
->output
[n
].num_components
;
104 i
->output
[n
].output_buffer
= p
->output
[n
].output_buffer
;
105 i
->output
[n
].dst_offset
= p
->output
[n
].dst_offset
;
106 i
->output
[n
].stream
= p
->output
[n
].stream
;
111 ir3_shader_create(struct ir3_compiler
*compiler
,
112 const struct pipe_shader_state
*cso
,
113 struct pipe_debug_callback
*debug
,
114 struct pipe_screen
*screen
)
117 if (cso
->type
== PIPE_SHADER_IR_NIR
) {
118 /* we take ownership of the reference: */
121 debug_assert(cso
->type
== PIPE_SHADER_IR_TGSI
);
122 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
123 tgsi_dump(cso
->tokens
, 0);
125 nir
= tgsi_to_nir(cso
->tokens
, screen
);
128 struct ir3_shader
*shader
= ir3_shader_from_nir(compiler
, nir
);
130 copy_stream_out(&shader
->stream_output
, &cso
->stream_output
);
132 if (fd_mesa_debug
& FD_DBG_SHADERDB
) {
133 /* if shader-db run, create a standard variant immediately
134 * (as otherwise nothing will trigger the shader to be
137 static struct ir3_shader_key key
; /* static is implicitly zeroed */
138 ir3_shader_variant(shader
, key
, false, debug
);
140 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
141 ir3_shader_variant(shader
, key
, true, debug
);
146 /* a bit annoying that compute-shader and normal shader state objects
147 * aren't a bit more aligned.
150 ir3_shader_create_compute(struct ir3_compiler
*compiler
,
151 const struct pipe_compute_state
*cso
,
152 struct pipe_debug_callback
*debug
,
153 struct pipe_screen
*screen
)
156 if (cso
->ir_type
== PIPE_SHADER_IR_NIR
) {
157 /* we take ownership of the reference: */
158 nir
= (nir_shader
*)cso
->prog
;
160 debug_assert(cso
->ir_type
== PIPE_SHADER_IR_TGSI
);
161 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
162 tgsi_dump(cso
->prog
, 0);
164 nir
= tgsi_to_nir(cso
->prog
, screen
);
167 struct ir3_shader
*shader
= ir3_shader_from_nir(compiler
, nir
);
172 /* This has to reach into the fd_context a bit more than the rest of
173 * ir3, but it needs to be aligned with the compiler, so both agree
174 * on which const regs hold what. And the logic is identical between
175 * a3xx/a4xx, the only difference is small details in the actual
176 * CP_LOAD_STATE packets (which is handled inside the generation
177 * specific ctx->emit_const(_bo)() fxns)
180 #include "freedreno_resource.h"
183 is_stateobj(struct fd_ringbuffer
*ring
)
185 /* XXX this is an ugly way to differentiate.. */
186 return !!(ring
->flags
& FD_RINGBUFFER_STREAMING
);
190 ring_wfi(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
192 /* when we emit const state via ring (IB2) we need a WFI, but when
193 * it is emit'd via stateobj, we don't
195 if (is_stateobj(ring
))
202 emit_const(struct fd_screen
*screen
, struct fd_ringbuffer
*ring
,
203 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
204 uint32_t offset
, uint32_t size
,
205 const void *user_buffer
, struct pipe_resource
*buffer
)
207 assert(dst_offset
+ size
<= v
->constlen
* 4);
209 screen
->emit_const(ring
, v
->type
, dst_offset
,
210 offset
, size
, user_buffer
, buffer
);
214 * Indirectly calculates size of cmdstream needed for ir3_emit_user_consts().
215 * Returns number of packets, and total size of all the payload.
217 * The value can be a worst-case, ie. some shader variants may not read all
220 * Returns size in dwords.
223 ir3_user_consts_size(struct ir3_ubo_analysis_state
*state
,
224 unsigned *packets
, unsigned *size
)
226 *packets
= *size
= 0;
228 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->range
); i
++) {
229 if (state
->range
[i
].start
< state
->range
[i
].end
) {
230 *size
+= state
->range
[i
].end
- state
->range
[i
].start
;
237 ir3_emit_user_consts(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
238 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
240 struct ir3_ubo_analysis_state
*state
;
241 state
= &v
->shader
->ubo_state
;
243 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->range
); i
++) {
244 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[i
];
246 if (state
->range
[i
].start
< state
->range
[i
].end
&&
247 constbuf
->enabled_mask
& (1 << i
)) {
249 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
250 uint32_t offset
= cb
->buffer_offset
+ state
->range
[i
].start
;
252 /* and even if the start of the const buffer is before
253 * first_immediate, the end may not be:
255 size
= MIN2(size
, (16 * v
->constlen
) - state
->range
[i
].offset
);
260 /* things should be aligned to vec4: */
261 debug_assert((state
->range
[i
].offset
% 16) == 0);
262 debug_assert((size
% 16) == 0);
263 debug_assert((offset
% 16) == 0);
265 emit_const(screen
, ring
, v
, state
->range
[i
].offset
/ 4,
266 offset
, size
/ 4, cb
->user_buffer
, cb
->buffer
);
272 ir3_emit_ubos(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
273 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
275 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
276 uint32_t offset
= const_state
->offsets
.ubo
;
277 if (v
->constlen
> offset
) {
278 uint32_t params
= const_state
->num_ubos
;
279 uint32_t offsets
[params
];
280 struct pipe_resource
*prscs
[params
];
282 for (uint32_t i
= 0; i
< params
; i
++) {
283 const uint32_t index
= i
+ 1; /* UBOs start at index 1 */
284 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
285 assert(!cb
->user_buffer
);
287 if ((constbuf
->enabled_mask
& (1 << index
)) && cb
->buffer
) {
288 offsets
[i
] = cb
->buffer_offset
;
289 prscs
[i
] = cb
->buffer
;
296 assert(offset
* 4 + params
< v
->constlen
* 4);
298 screen
->emit_const_bo(ring
, v
->type
, false, offset
* 4, params
, prscs
, offsets
);
303 ir3_emit_ssbo_sizes(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
304 struct fd_ringbuffer
*ring
, struct fd_shaderbuf_stateobj
*sb
)
306 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
307 uint32_t offset
= const_state
->offsets
.ssbo_sizes
;
308 if (v
->constlen
> offset
) {
309 uint32_t sizes
[align(const_state
->ssbo_size
.count
, 4)];
310 unsigned mask
= const_state
->ssbo_size
.mask
;
313 unsigned index
= u_bit_scan(&mask
);
314 unsigned off
= const_state
->ssbo_size
.off
[index
];
315 sizes
[off
] = sb
->sb
[index
].buffer_size
;
318 emit_const(screen
, ring
, v
, offset
* 4,
319 0, ARRAY_SIZE(sizes
), sizes
, NULL
);
324 ir3_emit_image_dims(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
325 struct fd_ringbuffer
*ring
, struct fd_shaderimg_stateobj
*si
)
327 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
328 uint32_t offset
= const_state
->offsets
.image_dims
;
329 if (v
->constlen
> offset
) {
330 uint32_t dims
[align(const_state
->image_dims
.count
, 4)];
331 unsigned mask
= const_state
->image_dims
.mask
;
334 struct pipe_image_view
*img
;
335 struct fd_resource
*rsc
;
336 unsigned index
= u_bit_scan(&mask
);
337 unsigned off
= const_state
->image_dims
.off
[index
];
339 img
= &si
->si
[index
];
340 rsc
= fd_resource(img
->resource
);
342 dims
[off
+ 0] = util_format_get_blocksize(img
->format
);
343 if (img
->resource
->target
!= PIPE_BUFFER
) {
344 unsigned lvl
= img
->u
.tex
.level
;
345 /* note for 2d/cube/etc images, even if re-interpreted
346 * as a different color format, the pixel size should
347 * be the same, so use original dimensions for y and z
350 dims
[off
+ 1] = rsc
->slices
[lvl
].pitch
* rsc
->cpp
;
351 /* see corresponding logic in fd_resource_offset(): */
352 if (rsc
->layer_first
) {
353 dims
[off
+ 2] = rsc
->layer_size
;
355 dims
[off
+ 2] = rsc
->slices
[lvl
].size0
;
358 /* For buffer-backed images, the log2 of the format's
359 * bytes-per-pixel is placed on the 2nd slot. This is useful
360 * when emitting image_size instructions, for which we need
361 * to divide by bpp for image buffers. Since the bpp
362 * can only be power-of-two, the division is implemented
363 * as a SHR, and for that it is handy to have the log2 of
364 * bpp as a constant. (log2 = first-set-bit - 1)
366 dims
[off
+ 1] = ffs(dims
[off
+ 0]) - 1;
369 uint32_t size
= MIN2(ARRAY_SIZE(dims
), v
->constlen
* 4 - offset
* 4);
371 emit_const(screen
, ring
, v
, offset
* 4, 0, size
, dims
, NULL
);
376 ir3_emit_immediates(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
377 struct fd_ringbuffer
*ring
)
379 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
380 uint32_t base
= const_state
->offsets
.immediate
;
381 int size
= const_state
->immediates_count
;
383 /* truncate size to avoid writing constants that shader
386 size
= MIN2(size
+ base
, v
->constlen
) - base
;
388 /* convert out of vec4: */
393 emit_const(screen
, ring
, v
, base
,
394 0, size
, const_state
->immediates
[0].val
, NULL
);
399 link_geometry_stages(const struct ir3_shader_variant
*producer
,
400 const struct ir3_shader_variant
*consumer
,
403 uint32_t num_loc
= 0, factor
;
405 switch (consumer
->type
) {
406 case MESA_SHADER_TESS_CTRL
:
407 case MESA_SHADER_GEOMETRY
:
408 /* These stages load with ldlw, which expects byte offsets. */
411 case MESA_SHADER_TESS_EVAL
:
412 /* The tess eval shader uses ldg, which takes dword offsets. */
416 unreachable("bad shader stage");
419 nir_foreach_variable(in_var
, &consumer
->shader
->nir
->inputs
) {
420 nir_foreach_variable(out_var
, &producer
->shader
->nir
->outputs
) {
421 if (in_var
->data
.location
== out_var
->data
.location
) {
422 locs
[in_var
->data
.driver_location
] =
423 producer
->shader
->output_loc
[out_var
->data
.driver_location
] * factor
;
425 debug_assert(num_loc
<= in_var
->data
.driver_location
+ 1);
426 num_loc
= in_var
->data
.driver_location
+ 1;
435 ir3_emit_link_map(struct fd_screen
*screen
,
436 const struct ir3_shader_variant
*producer
,
437 const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
)
439 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
440 uint32_t base
= const_state
->offsets
.primitive_map
;
441 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
443 num_loc
= link_geometry_stages(producer
, v
, patch_locs
);
445 int size
= DIV_ROUND_UP(num_loc
, 4);
447 /* truncate size to avoid writing constants that shader
450 size
= MIN2(size
+ base
, v
->constlen
) - base
;
452 /* convert out of vec4: */
457 emit_const(screen
, ring
, v
, base
, 0, size
, patch_locs
, NULL
);
460 /* emit stream-out buffers: */
462 emit_tfbos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
463 struct fd_ringbuffer
*ring
)
465 /* streamout addresses after driver-params: */
466 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
467 uint32_t offset
= const_state
->offsets
.tfbo
;
468 if (v
->constlen
> offset
) {
469 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
470 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
472 uint32_t offsets
[params
];
473 struct pipe_resource
*prscs
[params
];
475 for (uint32_t i
= 0; i
< params
; i
++) {
476 struct pipe_stream_output_target
*target
= so
->targets
[i
];
479 offsets
[i
] = (so
->offsets
[i
] * info
->stride
[i
] * 4) +
480 target
->buffer_offset
;
481 prscs
[i
] = target
->buffer
;
488 assert(offset
* 4 + params
< v
->constlen
* 4);
490 ctx
->screen
->emit_const_bo(ring
, v
->type
, true, offset
* 4, params
, prscs
, offsets
);
495 max_tf_vtx(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
)
497 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
498 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
499 uint32_t maxvtxcnt
= 0x7fffffff;
501 if (ctx
->screen
->gpu_id
>= 500)
505 if (v
->shader
->stream_output
.num_outputs
== 0)
507 if (so
->num_targets
== 0)
510 /* offset to write to is:
512 * total_vtxcnt = vtxcnt + offsets[i]
513 * offset = total_vtxcnt * stride[i]
515 * offset = vtxcnt * stride[i] ; calculated in shader
516 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
518 * assuming for each vtx, each target buffer will have data written
519 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
521 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
522 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
524 * but shader is actually doing a less-than (rather than less-than-
525 * equal) check, so we can drop the -stride[i].
527 * TODO is assumption about `offset + stride[i]` legit?
529 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
530 struct pipe_stream_output_target
*target
= so
->targets
[i
];
531 unsigned stride
= info
->stride
[i
] * 4; /* convert dwords->bytes */
533 uint32_t max
= target
->buffer_size
/ stride
;
534 maxvtxcnt
= MIN2(maxvtxcnt
, max
);
542 emit_common_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
543 struct fd_context
*ctx
, enum pipe_shader_type t
)
545 enum fd_dirty_shader_state dirty
= ctx
->dirty_shader
[t
];
547 /* When we use CP_SET_DRAW_STATE objects to emit constant state,
548 * if we emit any of it we need to emit all. This is because
549 * we are using the same state-group-id each time for uniform
550 * state, and if previous update is never evaluated (due to no
551 * visible primitives in the current tile) then the new stateobj
552 * completely replaces the old one.
554 * Possibly if we split up different parts of the const state to
555 * different state-objects we could avoid this.
557 if (dirty
&& is_stateobj(ring
))
560 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_CONST
)) {
561 struct fd_constbuf_stateobj
*constbuf
;
564 constbuf
= &ctx
->constbuf
[t
];
565 shader_dirty
= !!(dirty
& FD_DIRTY_SHADER_PROG
);
567 ring_wfi(ctx
->batch
, ring
);
569 ir3_emit_user_consts(ctx
->screen
, v
, ring
, constbuf
);
570 ir3_emit_ubos(ctx
->screen
, v
, ring
, constbuf
);
572 ir3_emit_immediates(ctx
->screen
, v
, ring
);
575 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_SSBO
)) {
576 struct fd_shaderbuf_stateobj
*sb
= &ctx
->shaderbuf
[t
];
577 ring_wfi(ctx
->batch
, ring
);
578 ir3_emit_ssbo_sizes(ctx
->screen
, v
, ring
, sb
);
581 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_IMAGE
)) {
582 struct fd_shaderimg_stateobj
*si
= &ctx
->shaderimg
[t
];
583 ring_wfi(ctx
->batch
, ring
);
584 ir3_emit_image_dims(ctx
->screen
, v
, ring
, si
);
589 ir3_emit_vs_driver_params(const struct ir3_shader_variant
*v
,
590 struct fd_ringbuffer
*ring
, struct fd_context
*ctx
,
591 const struct pipe_draw_info
*info
)
593 debug_assert(ir3_needs_vs_driver_params(v
));
595 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
596 uint32_t offset
= const_state
->offsets
.driver_param
;
597 uint32_t vertex_params
[IR3_DP_VS_COUNT
] = {
598 [IR3_DP_VTXID_BASE
] = info
->index_size
?
599 info
->index_bias
: info
->start
,
600 [IR3_DP_VTXCNT_MAX
] = max_tf_vtx(ctx
, v
),
602 /* if no user-clip-planes, we don't need to emit the
605 uint32_t vertex_params_size
= 4;
607 if (v
->key
.ucp_enables
) {
608 struct pipe_clip_state
*ucp
= &ctx
->ucp
;
609 unsigned pos
= IR3_DP_UCP0_X
;
610 for (unsigned i
= 0; pos
<= IR3_DP_UCP7_W
; i
++) {
611 for (unsigned j
= 0; j
< 4; j
++) {
612 vertex_params
[pos
] = fui(ucp
->ucp
[i
][j
]);
616 vertex_params_size
= ARRAY_SIZE(vertex_params
);
619 vertex_params_size
= MAX2(vertex_params_size
, const_state
->num_driver_params
);
621 bool needs_vtxid_base
=
622 ir3_find_sysval_regid(v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) != regid(63, 0);
624 /* for indirect draw, we need to copy VTXID_BASE from
625 * indirect-draw parameters buffer.. which is annoying
626 * and means we can't easily emit these consts in cmd
627 * stream so need to copy them to bo.
629 if (info
->indirect
&& needs_vtxid_base
) {
630 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
631 struct pipe_resource
*vertex_params_rsc
=
632 pipe_buffer_create(&ctx
->screen
->base
,
633 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
,
634 vertex_params_size
* 4);
635 unsigned src_off
= info
->indirect
->offset
;;
638 ptr
= fd_bo_map(fd_resource(vertex_params_rsc
)->bo
);
639 memcpy(ptr
, vertex_params
, vertex_params_size
* 4);
641 if (info
->index_size
) {
642 /* indexed draw, index_bias is 4th field: */
645 /* non-indexed draw, start is 3rd field: */
649 /* copy index_bias or start from draw params: */
650 ctx
->screen
->mem_to_mem(ring
, vertex_params_rsc
, 0,
651 indirect
->buffer
, src_off
, 1);
653 emit_const(ctx
->screen
, ring
, v
, offset
* 4, 0,
654 vertex_params_size
, NULL
, vertex_params_rsc
);
656 pipe_resource_reference(&vertex_params_rsc
, NULL
);
658 emit_const(ctx
->screen
, ring
, v
, offset
* 4, 0,
659 vertex_params_size
, vertex_params
, NULL
);
662 /* if needed, emit stream-out buffer addresses: */
663 if (vertex_params
[IR3_DP_VTXCNT_MAX
] > 0) {
664 emit_tfbos(ctx
, v
, ring
);
669 ir3_emit_vs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
670 struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
672 debug_assert(v
->type
== MESA_SHADER_VERTEX
);
674 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_VERTEX
);
676 /* emit driver params every time: */
677 if (info
&& ir3_needs_vs_driver_params(v
)) {
678 ring_wfi(ctx
->batch
, ring
);
679 ir3_emit_vs_driver_params(v
, ring
, ctx
, info
);
684 ir3_emit_fs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
685 struct fd_context
*ctx
)
687 debug_assert(v
->type
== MESA_SHADER_FRAGMENT
);
689 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_FRAGMENT
);
692 /* emit compute-shader consts: */
694 ir3_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
695 struct fd_context
*ctx
, const struct pipe_grid_info
*info
)
697 debug_assert(gl_shader_stage_is_compute(v
->type
));
699 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_COMPUTE
);
701 /* emit compute-shader driver-params: */
702 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
703 uint32_t offset
= const_state
->offsets
.driver_param
;
704 if (v
->constlen
> offset
) {
705 ring_wfi(ctx
->batch
, ring
);
707 if (info
->indirect
) {
708 struct pipe_resource
*indirect
= NULL
;
709 unsigned indirect_offset
;
711 /* This is a bit awkward, but CP_LOAD_STATE.EXT_SRC_ADDR needs
712 * to be aligned more strongly than 4 bytes. So in this case
713 * we need a temporary buffer to copy NumWorkGroups.xyz to.
715 * TODO if previous compute job is writing to info->indirect,
716 * we might need a WFI.. but since we currently flush for each
717 * compute job, we are probably ok for now.
719 if (info
->indirect_offset
& 0xf) {
720 indirect
= pipe_buffer_create(&ctx
->screen
->base
,
721 PIPE_BIND_COMMAND_ARGS_BUFFER
, PIPE_USAGE_STREAM
,
725 ctx
->screen
->mem_to_mem(ring
, indirect
, 0, info
->indirect
,
726 info
->indirect_offset
, 3);
728 pipe_resource_reference(&indirect
, info
->indirect
);
729 indirect_offset
= info
->indirect_offset
;
732 emit_const(ctx
->screen
, ring
, v
, offset
* 4,
733 indirect_offset
, 4, NULL
, indirect
);
735 pipe_resource_reference(&indirect
, NULL
);
737 uint32_t compute_params
[IR3_DP_CS_COUNT
] = {
738 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->grid
[0],
739 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->grid
[1],
740 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->grid
[2],
741 [IR3_DP_LOCAL_GROUP_SIZE_X
] = info
->block
[0],
742 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = info
->block
[1],
743 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = info
->block
[2],
745 uint32_t size
= MIN2(const_state
->num_driver_params
,
746 v
->constlen
* 4 - offset
* 4);
748 emit_const(ctx
->screen
, ring
, v
, offset
* 4, 0, size
,
749 compute_params
, NULL
);
755 ir3_shader_state_create(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
)
757 struct fd_context
*ctx
= fd_context(pctx
);
758 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
759 return ir3_shader_create(compiler
, cso
, &ctx
->debug
, pctx
->screen
);
763 ir3_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
765 struct ir3_shader
*so
= hwcso
;
766 ir3_shader_destroy(so
);
770 ir3_prog_init(struct pipe_context
*pctx
)
772 pctx
->create_vs_state
= ir3_shader_state_create
;
773 pctx
->delete_vs_state
= ir3_shader_state_delete
;
775 pctx
->create_tcs_state
= ir3_shader_state_create
;
776 pctx
->delete_tcs_state
= ir3_shader_state_delete
;
778 pctx
->create_tes_state
= ir3_shader_state_create
;
779 pctx
->delete_tes_state
= ir3_shader_state_delete
;
781 pctx
->create_gs_state
= ir3_shader_state_create
;
782 pctx
->delete_gs_state
= ir3_shader_state_delete
;
784 pctx
->create_fs_state
= ir3_shader_state_create
;
785 pctx
->delete_fs_state
= ir3_shader_state_delete
;