2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "tgsi/tgsi_parse.h"
36 #include "nir/tgsi_to_nir.h"
38 #include "freedreno_context.h"
39 #include "freedreno_util.h"
41 #include "ir3/ir3_shader.h"
42 #include "ir3/ir3_gallium.h"
43 #include "ir3/ir3_compiler.h"
44 #include "ir3/ir3_nir.h"
47 dump_shader_info(struct ir3_shader_variant
*v
, struct pipe_debug_callback
*debug
)
49 if (!unlikely(fd_mesa_debug
& FD_DBG_SHADERDB
))
52 pipe_debug_message(debug
, SHADER_INFO
,
53 "%s shader: %u inst, %u dwords, "
54 "%u half, %u full, %u const, %u constlen, "
55 "%u (ss), %u (sy), %d max_sun\n",
56 ir3_shader_stage(v
->shader
),
59 v
->info
.max_half_reg
+ 1,
61 v
->info
.max_const
+ 1,
63 v
->info
.ss
, v
->info
.sy
,
67 struct ir3_shader_variant
*
68 ir3_shader_variant(struct ir3_shader
*shader
, struct ir3_shader_key key
,
69 bool binning_pass
, struct pipe_debug_callback
*debug
)
71 struct ir3_shader_variant
*v
;
74 /* some shader key values only apply to vertex or frag shader,
75 * so normalize the key to avoid constructing multiple identical
78 ir3_normalize_key(&key
, shader
->type
);
80 v
= ir3_shader_get_variant(shader
, &key
, binning_pass
, &created
);
83 dump_shader_info(v
, debug
);
90 copy_stream_out(struct ir3_stream_output_info
*i
,
91 const struct pipe_stream_output_info
*p
)
93 STATIC_ASSERT(ARRAY_SIZE(i
->stride
) == ARRAY_SIZE(p
->stride
));
94 STATIC_ASSERT(ARRAY_SIZE(i
->output
) == ARRAY_SIZE(p
->output
));
96 i
->num_outputs
= p
->num_outputs
;
97 for (int n
= 0; n
< ARRAY_SIZE(i
->stride
); n
++)
98 i
->stride
[n
] = p
->stride
[n
];
100 for (int n
= 0; n
< ARRAY_SIZE(i
->output
); n
++) {
101 i
->output
[n
].register_index
= p
->output
[n
].register_index
;
102 i
->output
[n
].start_component
= p
->output
[n
].start_component
;
103 i
->output
[n
].num_components
= p
->output
[n
].num_components
;
104 i
->output
[n
].output_buffer
= p
->output
[n
].output_buffer
;
105 i
->output
[n
].dst_offset
= p
->output
[n
].dst_offset
;
106 i
->output
[n
].stream
= p
->output
[n
].stream
;
111 ir3_shader_create(struct ir3_compiler
*compiler
,
112 const struct pipe_shader_state
*cso
, gl_shader_stage type
,
113 struct pipe_debug_callback
*debug
,
114 struct pipe_screen
*screen
)
117 if (cso
->type
== PIPE_SHADER_IR_NIR
) {
118 /* we take ownership of the reference: */
121 debug_assert(cso
->type
== PIPE_SHADER_IR_TGSI
);
122 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
123 tgsi_dump(cso
->tokens
, 0);
125 nir
= tgsi_to_nir(cso
->tokens
, screen
);
128 struct ir3_shader
*shader
= ir3_shader_from_nir(compiler
, nir
);
130 copy_stream_out(&shader
->stream_output
, &cso
->stream_output
);
132 if (fd_mesa_debug
& FD_DBG_SHADERDB
) {
133 /* if shader-db run, create a standard variant immediately
134 * (as otherwise nothing will trigger the shader to be
137 static struct ir3_shader_key key
;
138 memset(&key
, 0, sizeof(key
));
139 ir3_shader_variant(shader
, key
, false, debug
);
144 /* a bit annoying that compute-shader and normal shader state objects
145 * aren't a bit more aligned.
148 ir3_shader_create_compute(struct ir3_compiler
*compiler
,
149 const struct pipe_compute_state
*cso
,
150 struct pipe_debug_callback
*debug
,
151 struct pipe_screen
*screen
)
154 if (cso
->ir_type
== PIPE_SHADER_IR_NIR
) {
155 /* we take ownership of the reference: */
156 nir
= (nir_shader
*)cso
->prog
;
158 debug_assert(cso
->ir_type
== PIPE_SHADER_IR_TGSI
);
159 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
160 tgsi_dump(cso
->prog
, 0);
162 nir
= tgsi_to_nir(cso
->prog
, screen
);
165 struct ir3_shader
*shader
= ir3_shader_from_nir(compiler
, nir
);
170 /* This has to reach into the fd_context a bit more than the rest of
171 * ir3, but it needs to be aligned with the compiler, so both agree
172 * on which const regs hold what. And the logic is identical between
173 * a3xx/a4xx, the only difference is small details in the actual
174 * CP_LOAD_STATE packets (which is handled inside the generation
175 * specific ctx->emit_const(_bo)() fxns)
178 #include "freedreno_resource.h"
181 is_stateobj(struct fd_ringbuffer
*ring
)
183 /* XXX this is an ugly way to differentiate.. */
184 return !!(ring
->flags
& FD_RINGBUFFER_STREAMING
);
188 ring_wfi(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
190 /* when we emit const state via ring (IB2) we need a WFI, but when
191 * it is emit'd via stateobj, we don't
193 if (is_stateobj(ring
))
200 emit_user_consts(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
201 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
203 const unsigned index
= 0; /* user consts are index 0 */
205 if (constbuf
->enabled_mask
& (1 << index
)) {
206 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
207 /* size in dwords, aligned to vec4. (This works at least
208 * with mesa/st, which seems to align constant buffer to
211 unsigned size
= align(cb
->buffer_size
, 16) / 4;
213 /* in particular, with binning shader we may end up with
214 * unused consts, ie. we could end up w/ constlen that is
215 * smaller than first_driver_param. In that case truncate
216 * the user consts early to avoid HLSQ lockup caused by
217 * writing too many consts
219 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
220 uint32_t max_const
= MIN2(const_state
->num_uniforms
, v
->constlen
);
222 /* and even if the start of the const buffer is before
223 * first_immediate, the end may not be:
225 size
= MIN2(size
, 4 * max_const
);
228 ring_wfi(ctx
->batch
, ring
);
229 ctx
->emit_const(ring
, v
->type
, 0,
230 cb
->buffer_offset
, size
,
231 cb
->user_buffer
, cb
->buffer
);
235 struct ir3_ubo_analysis_state
*state
;
236 state
= &v
->shader
->ubo_state
;
238 for (uint32_t i
= 1; i
< ARRAY_SIZE(state
->range
); i
++) {
239 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[i
];
241 if (state
->range
[i
].start
< state
->range
[i
].end
&&
242 constbuf
->enabled_mask
& (1 << i
)) {
244 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
245 uint32_t offset
= cb
->buffer_offset
+ state
->range
[i
].start
;
246 debug_assert((state
->range
[i
].offset
% 16) == 0);
247 debug_assert((size
% 16) == 0);
248 debug_assert((offset
% 16) == 0);
249 ctx
->emit_const(ring
, v
->type
, state
->range
[i
].offset
/ 4,
250 offset
, size
/ 4, cb
->user_buffer
, cb
->buffer
);
256 emit_ubos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
257 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
259 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
260 uint32_t offset
= const_state
->offsets
.ubo
;
261 if (v
->constlen
> offset
) {
262 uint32_t params
= const_state
->num_ubos
;
263 uint32_t offsets
[params
];
264 struct pipe_resource
*prscs
[params
];
266 for (uint32_t i
= 0; i
< params
; i
++) {
267 const uint32_t index
= i
+ 1; /* UBOs start at index 1 */
268 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
269 assert(!cb
->user_buffer
);
271 if ((constbuf
->enabled_mask
& (1 << index
)) && cb
->buffer
) {
272 offsets
[i
] = cb
->buffer_offset
;
273 prscs
[i
] = cb
->buffer
;
280 ring_wfi(ctx
->batch
, ring
);
281 ctx
->emit_const_bo(ring
, v
->type
, false, offset
* 4, params
, prscs
, offsets
);
286 emit_ssbo_sizes(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
287 struct fd_ringbuffer
*ring
, struct fd_shaderbuf_stateobj
*sb
)
289 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
290 uint32_t offset
= const_state
->offsets
.ssbo_sizes
;
291 if (v
->constlen
> offset
) {
292 uint32_t sizes
[align(const_state
->ssbo_size
.count
, 4)];
293 unsigned mask
= const_state
->ssbo_size
.mask
;
296 unsigned index
= u_bit_scan(&mask
);
297 unsigned off
= const_state
->ssbo_size
.off
[index
];
298 sizes
[off
] = sb
->sb
[index
].buffer_size
;
301 ring_wfi(ctx
->batch
, ring
);
302 ctx
->emit_const(ring
, v
->type
, offset
* 4,
303 0, ARRAY_SIZE(sizes
), sizes
, NULL
);
308 emit_image_dims(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
309 struct fd_ringbuffer
*ring
, struct fd_shaderimg_stateobj
*si
)
311 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
312 uint32_t offset
= const_state
->offsets
.image_dims
;
313 if (v
->constlen
> offset
) {
314 uint32_t dims
[align(const_state
->image_dims
.count
, 4)];
315 unsigned mask
= const_state
->image_dims
.mask
;
318 struct pipe_image_view
*img
;
319 struct fd_resource
*rsc
;
320 unsigned index
= u_bit_scan(&mask
);
321 unsigned off
= const_state
->image_dims
.off
[index
];
323 img
= &si
->si
[index
];
324 rsc
= fd_resource(img
->resource
);
326 dims
[off
+ 0] = util_format_get_blocksize(img
->format
);
327 if (img
->resource
->target
!= PIPE_BUFFER
) {
328 unsigned lvl
= img
->u
.tex
.level
;
329 /* note for 2d/cube/etc images, even if re-interpreted
330 * as a different color format, the pixel size should
331 * be the same, so use original dimensions for y and z
334 dims
[off
+ 1] = rsc
->slices
[lvl
].pitch
* rsc
->cpp
;
335 /* see corresponding logic in fd_resource_offset(): */
336 if (rsc
->layer_first
) {
337 dims
[off
+ 2] = rsc
->layer_size
;
339 dims
[off
+ 2] = rsc
->slices
[lvl
].size0
;
342 /* For buffer-backed images, the log2 of the format's
343 * bytes-per-pixel is placed on the 2nd slot. This is useful
344 * when emitting image_size instructions, for which we need
345 * to divide by bpp for image buffers. Since the bpp
346 * can only be power-of-two, the division is implemented
347 * as a SHR, and for that it is handy to have the log2 of
348 * bpp as a constant. (log2 = first-set-bit - 1)
350 dims
[off
+ 1] = ffs(dims
[off
+ 0]) - 1;
354 ring_wfi(ctx
->batch
, ring
);
355 ctx
->emit_const(ring
, v
->type
, offset
* 4,
356 0, ARRAY_SIZE(dims
), dims
, NULL
);
361 emit_immediates(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
362 struct fd_ringbuffer
*ring
)
364 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
365 uint32_t base
= const_state
->offsets
.immediate
;
366 int size
= const_state
->immediates_count
;
368 /* truncate size to avoid writing constants that shader
371 size
= MIN2(size
+ base
, v
->constlen
) - base
;
373 /* convert out of vec4: */
378 ring_wfi(ctx
->batch
, ring
);
379 ctx
->emit_const(ring
, v
->type
, base
,
380 0, size
, const_state
->immediates
[0].val
, NULL
);
384 /* emit stream-out buffers: */
386 emit_tfbos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
387 struct fd_ringbuffer
*ring
)
389 /* streamout addresses after driver-params: */
390 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
391 uint32_t offset
= const_state
->offsets
.tfbo
;
392 if (v
->constlen
> offset
) {
393 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
394 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
396 uint32_t offsets
[params
];
397 struct pipe_resource
*prscs
[params
];
399 for (uint32_t i
= 0; i
< params
; i
++) {
400 struct pipe_stream_output_target
*target
= so
->targets
[i
];
403 offsets
[i
] = (so
->offsets
[i
] * info
->stride
[i
] * 4) +
404 target
->buffer_offset
;
405 prscs
[i
] = target
->buffer
;
412 ring_wfi(ctx
->batch
, ring
);
413 ctx
->emit_const_bo(ring
, v
->type
, true, offset
* 4, params
, prscs
, offsets
);
418 max_tf_vtx(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
)
420 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
421 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
422 uint32_t maxvtxcnt
= 0x7fffffff;
424 if (ctx
->screen
->gpu_id
>= 500)
428 if (v
->shader
->stream_output
.num_outputs
== 0)
430 if (so
->num_targets
== 0)
433 /* offset to write to is:
435 * total_vtxcnt = vtxcnt + offsets[i]
436 * offset = total_vtxcnt * stride[i]
438 * offset = vtxcnt * stride[i] ; calculated in shader
439 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
441 * assuming for each vtx, each target buffer will have data written
442 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
444 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
445 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
447 * but shader is actually doing a less-than (rather than less-than-
448 * equal) check, so we can drop the -stride[i].
450 * TODO is assumption about `offset + stride[i]` legit?
452 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
453 struct pipe_stream_output_target
*target
= so
->targets
[i
];
454 unsigned stride
= info
->stride
[i
] * 4; /* convert dwords->bytes */
456 uint32_t max
= target
->buffer_size
/ stride
;
457 maxvtxcnt
= MIN2(maxvtxcnt
, max
);
465 emit_common_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
466 struct fd_context
*ctx
, enum pipe_shader_type t
)
468 enum fd_dirty_shader_state dirty
= ctx
->dirty_shader
[t
];
470 /* When we use CP_SET_DRAW_STATE objects to emit constant state,
471 * if we emit any of it we need to emit all. This is because
472 * we are using the same state-group-id each time for uniform
473 * state, and if previous update is never evaluated (due to no
474 * visible primitives in the current tile) then the new stateobj
475 * completely replaces the old one.
477 * Possibly if we split up different parts of the const state to
478 * different state-objects we could avoid this.
480 if (dirty
&& is_stateobj(ring
))
483 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_CONST
)) {
484 struct fd_constbuf_stateobj
*constbuf
;
487 constbuf
= &ctx
->constbuf
[t
];
488 shader_dirty
= !!(dirty
& FD_DIRTY_SHADER_PROG
);
490 emit_user_consts(ctx
, v
, ring
, constbuf
);
491 emit_ubos(ctx
, v
, ring
, constbuf
);
493 emit_immediates(ctx
, v
, ring
);
496 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_SSBO
)) {
497 struct fd_shaderbuf_stateobj
*sb
= &ctx
->shaderbuf
[t
];
498 emit_ssbo_sizes(ctx
, v
, ring
, sb
);
501 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_IMAGE
)) {
502 struct fd_shaderimg_stateobj
*si
= &ctx
->shaderimg
[t
];
503 emit_image_dims(ctx
, v
, ring
, si
);
508 ir3_emit_vs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
509 struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
511 debug_assert(v
->type
== MESA_SHADER_VERTEX
);
513 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_VERTEX
);
515 /* emit driver params every time: */
516 /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
518 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
519 uint32_t offset
= const_state
->offsets
.driver_param
;
520 if (v
->constlen
> offset
) {
521 uint32_t vertex_params
[IR3_DP_VS_COUNT
] = {
522 [IR3_DP_VTXID_BASE
] = info
->index_size
?
523 info
->index_bias
: info
->start
,
524 [IR3_DP_VTXCNT_MAX
] = max_tf_vtx(ctx
, v
),
526 /* if no user-clip-planes, we don't need to emit the
529 uint32_t vertex_params_size
= 4;
531 if (v
->key
.ucp_enables
) {
532 struct pipe_clip_state
*ucp
= &ctx
->ucp
;
533 unsigned pos
= IR3_DP_UCP0_X
;
534 for (unsigned i
= 0; pos
<= IR3_DP_UCP7_W
; i
++) {
535 for (unsigned j
= 0; j
< 4; j
++) {
536 vertex_params
[pos
] = fui(ucp
->ucp
[i
][j
]);
540 vertex_params_size
= ARRAY_SIZE(vertex_params
);
543 ring_wfi(ctx
->batch
, ring
);
545 bool needs_vtxid_base
=
546 ir3_find_sysval_regid(v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) != regid(63, 0);
548 /* for indirect draw, we need to copy VTXID_BASE from
549 * indirect-draw parameters buffer.. which is annoying
550 * and means we can't easily emit these consts in cmd
551 * stream so need to copy them to bo.
553 if (info
->indirect
&& needs_vtxid_base
) {
554 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
555 struct pipe_resource
*vertex_params_rsc
=
556 pipe_buffer_create(&ctx
->screen
->base
,
557 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
,
558 vertex_params_size
* 4);
559 unsigned src_off
= info
->indirect
->offset
;;
562 ptr
= fd_bo_map(fd_resource(vertex_params_rsc
)->bo
);
563 memcpy(ptr
, vertex_params
, vertex_params_size
* 4);
565 if (info
->index_size
) {
566 /* indexed draw, index_bias is 4th field: */
569 /* non-indexed draw, start is 3rd field: */
573 /* copy index_bias or start from draw params: */
574 ctx
->mem_to_mem(ring
, vertex_params_rsc
, 0,
575 indirect
->buffer
, src_off
, 1);
577 ctx
->emit_const(ring
, MESA_SHADER_VERTEX
, offset
* 4, 0,
578 vertex_params_size
, NULL
, vertex_params_rsc
);
580 pipe_resource_reference(&vertex_params_rsc
, NULL
);
582 ctx
->emit_const(ring
, MESA_SHADER_VERTEX
, offset
* 4, 0,
583 vertex_params_size
, vertex_params
, NULL
);
586 /* if needed, emit stream-out buffer addresses: */
587 if (vertex_params
[IR3_DP_VTXCNT_MAX
] > 0) {
588 emit_tfbos(ctx
, v
, ring
);
595 ir3_emit_fs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
596 struct fd_context
*ctx
)
598 debug_assert(v
->type
== MESA_SHADER_FRAGMENT
);
600 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_FRAGMENT
);
603 /* emit compute-shader consts: */
605 ir3_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
606 struct fd_context
*ctx
, const struct pipe_grid_info
*info
)
608 debug_assert(gl_shader_stage_is_compute(v
->type
));
610 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_COMPUTE
);
612 /* emit compute-shader driver-params: */
613 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
614 uint32_t offset
= const_state
->offsets
.driver_param
;
615 if (v
->constlen
> offset
) {
616 ring_wfi(ctx
->batch
, ring
);
618 if (info
->indirect
) {
619 struct pipe_resource
*indirect
= NULL
;
620 unsigned indirect_offset
;
622 /* This is a bit awkward, but CP_LOAD_STATE.EXT_SRC_ADDR needs
623 * to be aligned more strongly than 4 bytes. So in this case
624 * we need a temporary buffer to copy NumWorkGroups.xyz to.
626 * TODO if previous compute job is writing to info->indirect,
627 * we might need a WFI.. but since we currently flush for each
628 * compute job, we are probably ok for now.
630 if (info
->indirect_offset
& 0xf) {
631 indirect
= pipe_buffer_create(&ctx
->screen
->base
,
632 PIPE_BIND_COMMAND_ARGS_BUFFER
, PIPE_USAGE_STREAM
,
636 ctx
->mem_to_mem(ring
, indirect
, 0, info
->indirect
,
637 info
->indirect_offset
, 3);
639 pipe_resource_reference(&indirect
, info
->indirect
);
640 indirect_offset
= info
->indirect_offset
;
643 ctx
->emit_const(ring
, MESA_SHADER_COMPUTE
, offset
* 4,
644 indirect_offset
, 4, NULL
, indirect
);
646 pipe_resource_reference(&indirect
, NULL
);
648 uint32_t compute_params
[IR3_DP_CS_COUNT
] = {
649 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->grid
[0],
650 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->grid
[1],
651 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->grid
[2],
652 [IR3_DP_LOCAL_GROUP_SIZE_X
] = info
->block
[0],
653 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = info
->block
[1],
654 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = info
->block
[2],
657 ctx
->emit_const(ring
, MESA_SHADER_COMPUTE
, offset
* 4, 0,
658 ARRAY_SIZE(compute_params
), compute_params
, NULL
);