src/gallium/drivers/freedreno/ir3/ir3_legalize.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_shader_tokens.h"
  30 #include "util/u_math.h"
  31
  32 #include "freedreno_util.h"
  33
  34 #include "ir3.h"
  35
  36 /*
  37  * Legalize:
  38  *
  39  * We currently require that scheduling ensures that we have enough nop's
  40  * in all the right places.  The legalize step mostly handles fixing up
  41  * instruction flags ((ss)/(sy)/(ei)), and collapses sequences of nop's
  42  * into fewer nop's w/ rpt flag.
  43  */
  44
  45 struct ir3_legalize_ctx {
  46         struct ir3_block *block;
  47         bool has_samp;
  48         int max_bary;
  49 };
  50
  51 static void legalize(struct ir3_legalize_ctx *ctx)
  52 {
  53         struct ir3_block *block = ctx->block;
  54         struct ir3_instruction *n;
  55         struct ir3 *shader = block->shader;
  56         struct ir3_instruction *end =
  57                         ir3_instr_create(block, 0, OPC_END);
  58         struct ir3_instruction *last_input = NULL;
  59         struct ir3_instruction *last_rel = NULL;
  60         regmask_t needs_ss_war;       /* write after read */
  61         regmask_t needs_ss;
  62         regmask_t needs_sy;
  63
  64         regmask_init(&needs_ss_war);
  65         regmask_init(&needs_ss);
  66         regmask_init(&needs_sy);
  67
  68         shader->instrs_count = 0;
  69
  70         for (n = block->head; n; n = n->next) {
  71                 struct ir3_register *reg;
  72                 unsigned i;
  73
  74                 if (is_meta(n))
  75                         continue;
  76
  77                 if (is_input(n)) {
  78                         struct ir3_register *inloc = n->regs[1];
  79                         assert(inloc->flags & IR3_REG_IMMED);
  80                         ctx->max_bary = MAX2(ctx->max_bary, inloc->iim_val);
  81                 }
  82
  83                 for (i = 1; i < n->regs_count; i++) {
  84                         reg = n->regs[i];
  85
  86                         if (reg_gpr(reg)) {
  87
  88                                 /* TODO: we probably only need (ss) for alu
  89                                  * instr consuming sfu result.. need to make
  90                                  * some tests for both this and (sy)..
  91                                  */
  92                                 if (regmask_get(&needs_ss, reg)) {
  93                                         n->flags |= IR3_INSTR_SS;
  94                                         regmask_init(&needs_ss);
  95                                 }
  96
  97                                 if (regmask_get(&needs_sy, reg)) {
  98                                         n->flags |= IR3_INSTR_SY;
  99                                         regmask_init(&needs_sy);
 100                                 }
 101                         }
 102
 103                         /* TODO: is it valid to have address reg loaded from a
 104                          * relative src (ie. mova a0, c<a0.x+4>)?  If so, the
 105                          * last_rel check below should be moved ahead of this:
 106                          */
 107                         if (reg->flags & IR3_REG_RELATIV)
 108                                 last_rel = n;
 109                 }
 110
 111                 if (n->regs_count > 0) {
 112                         reg = n->regs[0];
 113                         if (regmask_get(&needs_ss_war, reg)) {
 114                                 n->flags |= IR3_INSTR_SS;
 115                                 regmask_init(&needs_ss_war); // ??? I assume?
 116                         }
 117
 118                         if (last_rel && (reg->num == regid(REG_A0, 0))) {
 119                                 last_rel->flags |= IR3_INSTR_UL;
 120                                 last_rel = NULL;
 121                         }
 122                 }
 123
 124                 /* cat5+ does not have an (ss) bit, if needed we need to
 125                  * insert a nop to carry the sync flag.  Would be kinda
 126                  * clever if we were aware of this during scheduling, but
 127                  * this should be a pretty rare case:
 128                  */
 129                 if ((n->flags & IR3_INSTR_SS) && (n->category >= 5)) {
 130                         struct ir3_instruction *nop;
 131                         nop = ir3_instr_create(block, 0, OPC_NOP);
 132                         nop->flags |= IR3_INSTR_SS;
 133                         n->flags &= ~IR3_INSTR_SS;
 134                 }
 135
 136                 /* need to be able to set (ss) on first instruction: */
 137                 if ((shader->instrs_count == 0) && (n->category >= 5))
 138                         ir3_instr_create(block, 0, OPC_NOP);
 139
 140                 if (is_nop(n) && shader->instrs_count) {
 141                         struct ir3_instruction *last =
 142                                         shader->instrs[shader->instrs_count-1];
 143                         if (is_nop(last) && (last->repeat < 5)) {
 144                                 last->repeat++;
 145                                 last->flags |= n->flags;
 146                                 continue;
 147                         }
 148                 }
 149
 150                 shader->instrs[shader->instrs_count++] = n;
 151
 152                 if (is_sfu(n))
 153                         regmask_set(&needs_ss, n->regs[0]);
 154
 155                 if (is_tex(n)) {
 156                         /* this ends up being the # of samp instructions.. but that
 157                          * is ok, everything else only cares whether it is zero or
 158                          * not.  We do this here, rather than when we encounter a
 159                          * SAMP decl, because (especially in binning pass shader)
 160                          * the samp instruction(s) could get eliminated if the
 161                          * result is not used.
 162                          */
 163                         ctx->has_samp = true;
 164                         regmask_set(&needs_sy, n->regs[0]);
 165                 }
 166
 167                 /* both tex/sfu appear to not always immediately consume
 168                  * their src register(s):
 169                  */
 170                 if (is_tex(n) || is_sfu(n)) {
 171                         for (i = 1; i < n->regs_count; i++) {
 172                                 reg = n->regs[i];
 173                                 if (reg_gpr(reg))
 174                                         regmask_set(&needs_ss_war, reg);
 175                         }
 176                 }
 177
 178                 if (is_input(n))
 179                         last_input = n;
 180         }
 181
 182         if (last_input)
 183                 last_input->regs[0]->flags |= IR3_REG_EI;
 184
 185         if (last_rel)
 186                 last_rel->flags |= IR3_INSTR_UL;
 187
 188         shader->instrs[shader->instrs_count++] = end;
 189
 190         shader->instrs[0]->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
 191 }
 192
 193 void ir3_block_legalize(struct ir3_block *block,
 194                 bool *has_samp, int *max_bary)
 195 {
 196         struct ir3_legalize_ctx ctx = {
 197                         .block = block,
 198                         .max_bary = -1,
 199         };
 200
 201         legalize(&ctx);
 202
 203         *has_samp = ctx.has_samp;
 204         *max_bary = ctx.max_bary;
 205 }