src/gallium/drivers/freedreno/ir3/ir3_legalize.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_math.h"
  28
  29 #include "freedreno_util.h"
  30
  31 #include "ir3.h"
  32
  33 /*
  34  * Legalize:
  35  *
  36  * We currently require that scheduling ensures that we have enough nop's
  37  * in all the right places.  The legalize step mostly handles fixing up
  38  * instruction flags ((ss)/(sy)/(ei)), and collapses sequences of nop's
  39  * into fewer nop's w/ rpt flag.
  40  */
  41
  42 struct ir3_legalize_ctx {
  43         bool has_samp;
  44         bool has_ssbo;
  45         int max_bary;
  46 };
  47
  48 struct ir3_legalize_state {
  49         regmask_t needs_ss;
  50         regmask_t needs_ss_war;       /* write after read */
  51         regmask_t needs_sy;
  52 };
  53
  54 struct ir3_legalize_block_data {
  55         bool valid;
  56         struct ir3_legalize_state state;
  57 };
  58
  59 /* We want to evaluate each block from the position of any other
  60  * predecessor block, in order that the flags set are the union of
  61  * all possible program paths.
  62  *
  63  * To do this, we need to know the output state (needs_ss/ss_war/sy)
  64  * of all predecessor blocks.  The tricky thing is loops, which mean
  65  * that we can't simply recursively process each predecessor block
  66  * before legalizing the current block.
  67  *
  68  * How we handle that is by looping over all the blocks until the
  69  * results converge.  If the output state of a given block changes
  70  * in a given pass, this means that all successor blocks are not
  71  * yet fully legalized.
  72  */
  73
  74 static bool
  75 legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
  76 {
  77         struct ir3_legalize_block_data *bd = block->data;
  78
  79         if (bd->valid)
  80                 return false;
  81
  82         struct ir3_instruction *last_input = NULL;
  83         struct ir3_instruction *last_rel = NULL;
  84         struct ir3_instruction *last_n = NULL;
  85         struct list_head instr_list;
  86         struct ir3_legalize_state prev_state = bd->state;
  87         struct ir3_legalize_state *state = &bd->state;
  88
  89         /* our input state is the OR of all predecessor blocks' state: */
  90         for (unsigned i = 0; i < block->predecessors_count; i++) {
  91                 struct ir3_legalize_block_data *pbd = block->predecessors[i]->data;
  92                 struct ir3_legalize_state *pstate = &pbd->state;
  93
  94                 /* Our input (ss)/(sy) state is based on OR'ing the output
  95                  * state of all our predecessor blocks
  96                  */
  97                 regmask_or(&state->needs_ss,
  98                                 &state->needs_ss, &pstate->needs_ss);
  99                 regmask_or(&state->needs_ss_war,
 100                                 &state->needs_ss_war, &pstate->needs_ss_war);
 101                 regmask_or(&state->needs_sy,
 102                                 &state->needs_sy, &pstate->needs_sy);
 103         }
 104
 105         /* remove all the instructions from the list, we'll be adding
 106          * them back in as we go
 107          */
 108         list_replace(&block->instr_list, &instr_list);
 109         list_inithead(&block->instr_list);
 110
 111         list_for_each_entry_safe (struct ir3_instruction, n, &instr_list, node) {
 112                 struct ir3_register *reg;
 113                 unsigned i;
 114
 115                 n->flags &= ~(IR3_INSTR_SS | IR3_INSTR_SY);
 116
 117                 if (is_meta(n))
 118                         continue;
 119
 120                 if (is_input(n)) {
 121                         struct ir3_register *inloc = n->regs[1];
 122                         assert(inloc->flags & IR3_REG_IMMED);
 123                         ctx->max_bary = MAX2(ctx->max_bary, inloc->iim_val);
 124                 }
 125
 126                 if (last_n && is_barrier(last_n))
 127                         n->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
 128
 129                 /* NOTE: consider dst register too.. it could happen that
 130                  * texture sample instruction (for example) writes some
 131                  * components which are unused.  A subsequent instruction
 132                  * that writes the same register can race w/ the sam instr
 133                  * resulting in undefined results:
 134                  */
 135                 for (i = 0; i < n->regs_count; i++) {
 136                         reg = n->regs[i];
 137
 138                         if (reg_gpr(reg)) {
 139
 140                                 /* TODO: we probably only need (ss) for alu
 141                                  * instr consuming sfu result.. need to make
 142                                  * some tests for both this and (sy)..
 143                                  */
 144                                 if (regmask_get(&state->needs_ss, reg)) {
 145                                         n->flags |= IR3_INSTR_SS;
 146                                         regmask_init(&state->needs_ss_war);
 147                                         regmask_init(&state->needs_ss);
 148                                 }
 149
 150                                 if (regmask_get(&state->needs_sy, reg)) {
 151                                         n->flags |= IR3_INSTR_SY;
 152                                         regmask_init(&state->needs_sy);
 153                                 }
 154                         }
 155
 156                         /* TODO: is it valid to have address reg loaded from a
 157                          * relative src (ie. mova a0, c<a0.x+4>)?  If so, the
 158                          * last_rel check below should be moved ahead of this:
 159                          */
 160                         if (reg->flags & IR3_REG_RELATIV)
 161                                 last_rel = n;
 162                 }
 163
 164                 if (n->regs_count > 0) {
 165                         reg = n->regs[0];
 166                         if (regmask_get(&state->needs_ss_war, reg)) {
 167                                 n->flags |= IR3_INSTR_SS;
 168                                 regmask_init(&state->needs_ss_war);
 169                                 regmask_init(&state->needs_ss);
 170                         }
 171
 172                         if (last_rel && (reg->num == regid(REG_A0, 0))) {
 173                                 last_rel->flags |= IR3_INSTR_UL;
 174                                 last_rel = NULL;
 175                         }
 176                 }
 177
 178                 /* cat5+ does not have an (ss) bit, if needed we need to
 179                  * insert a nop to carry the sync flag.  Would be kinda
 180                  * clever if we were aware of this during scheduling, but
 181                  * this should be a pretty rare case:
 182                  */
 183                 if ((n->flags & IR3_INSTR_SS) && (opc_cat(n->opc) >= 5)) {
 184                         struct ir3_instruction *nop;
 185                         nop = ir3_NOP(block);
 186                         nop->flags |= IR3_INSTR_SS;
 187                         n->flags &= ~IR3_INSTR_SS;
 188                 }
 189
 190                 /* need to be able to set (ss) on first instruction: */
 191                 if (list_empty(&block->instr_list) && (opc_cat(n->opc) >= 5))
 192                         ir3_NOP(block);
 193
 194                 if (is_nop(n) && !list_empty(&block->instr_list)) {
 195                         struct ir3_instruction *last = list_last_entry(&block->instr_list,
 196                                         struct ir3_instruction, node);
 197                         if (is_nop(last) && (last->repeat < 5)) {
 198                                 last->repeat++;
 199                                 last->flags |= n->flags;
 200                                 continue;
 201                         }
 202                 }
 203
 204                 list_addtail(&n->node, &block->instr_list);
 205
 206                 if (is_sfu(n))
 207                         regmask_set(&state->needs_ss, n->regs[0]);
 208
 209                 if (is_tex(n)) {
 210                         /* this ends up being the # of samp instructions.. but that
 211                          * is ok, everything else only cares whether it is zero or
 212                          * not.  We do this here, rather than when we encounter a
 213                          * SAMP decl, because (especially in binning pass shader)
 214                          * the samp instruction(s) could get eliminated if the
 215                          * result is not used.
 216                          */
 217                         ctx->has_samp = true;
 218                         regmask_set(&state->needs_sy, n->regs[0]);
 219                 } else if (n->opc == OPC_RESINFO) {
 220                         regmask_set(&state->needs_ss, n->regs[0]);
 221                         ir3_NOP(block)->flags |= IR3_INSTR_SS;
 222                 } else if (is_load(n)) {
 223                         /* seems like ldlv needs (ss) bit instead??  which is odd but
 224                          * makes a bunch of flat-varying tests start working on a4xx.
 225                          */
 226                         if ((n->opc == OPC_LDLV) || (n->opc == OPC_LDL))
 227                                 regmask_set(&state->needs_ss, n->regs[0]);
 228                         else
 229                                 regmask_set(&state->needs_sy, n->regs[0]);
 230                 } else if (is_atomic(n->opc)) {
 231                         if (n->flags & IR3_INSTR_G)
 232                                 regmask_set(&state->needs_sy, n->regs[0]);
 233                         else
 234                                 regmask_set(&state->needs_ss, n->regs[0]);
 235                 }
 236
 237                 if (is_ssbo(n->opc) || (is_atomic(n->opc) && (n->flags & IR3_INSTR_G)))
 238                         ctx->has_ssbo = true;
 239
 240                 /* both tex/sfu appear to not always immediately consume
 241                  * their src register(s):
 242                  */
 243                 if (is_tex(n) || is_sfu(n) || is_mem(n)) {
 244                         foreach_src(reg, n) {
 245                                 if (reg_gpr(reg))
 246                                         regmask_set(&state->needs_ss_war, reg);
 247                         }
 248                 }
 249
 250                 if (is_input(n))
 251                         last_input = n;
 252
 253                 last_n = n;
 254         }
 255
 256         if (last_input) {
 257                 /* special hack.. if using ldlv to bypass interpolation,
 258                  * we need to insert a dummy bary.f on which we can set
 259                  * the (ei) flag:
 260                  */
 261                 if (is_mem(last_input) && (last_input->opc == OPC_LDLV)) {
 262                         struct ir3_instruction *baryf;
 263
 264                         /* (ss)bary.f (ei)r63.x, 0, r0.x */
 265                         baryf = ir3_instr_create(block, OPC_BARY_F);
 266                         baryf->flags |= IR3_INSTR_SS;
 267                         ir3_reg_create(baryf, regid(63, 0), 0);
 268                         ir3_reg_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0;
 269                         ir3_reg_create(baryf, regid(0, 0), 0);
 270
 271                         /* insert the dummy bary.f after last_input: */
 272                         list_delinit(&baryf->node);
 273                         list_add(&baryf->node, &last_input->node);
 274
 275                         last_input = baryf;
 276                 }
 277                 last_input->regs[0]->flags |= IR3_REG_EI;
 278         }
 279
 280         if (last_rel)
 281                 last_rel->flags |= IR3_INSTR_UL;
 282
 283         bd->valid = true;
 284
 285         if (memcmp(&prev_state, state, sizeof(*state))) {
 286                 /* our output state changed, this invalidates all of our
 287                  * successors:
 288                  */
 289                 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); i++) {
 290                         if (!block->successors[i])
 291                                 break;
 292                         struct ir3_legalize_block_data *pbd = block->successors[i]->data;
 293                         pbd->valid = false;
 294                 }
 295         }
 296
 297         return true;
 298 }
 299
 300 /* NOTE: branch instructions are always the last instruction(s)
 301  * in the block.  We take advantage of this as we resolve the
 302  * branches, since "if (foo) break;" constructs turn into
 303  * something like:
 304  *
 305  *   block3 {
 306  *      ...
 307  *      0029:021: mov.s32s32 r62.x, r1.y
 308  *      0082:022: br !p0.x, target=block5
 309  *      0083:023: br p0.x, target=block4
 310  *      // succs: if _[0029:021: mov.s32s32] block4; else block5;
 311  *   }
 312  *   block4 {
 313  *      0084:024: jump, target=block6
 314  *      // succs: block6;
 315  *   }
 316  *   block5 {
 317  *      0085:025: jump, target=block7
 318  *      // succs: block7;
 319  *   }
 320  *
 321  * ie. only instruction in block4/block5 is a jump, so when
 322  * resolving branches we can easily detect this by checking
 323  * that the first instruction in the target block is itself
 324  * a jump, and setup the br directly to the jump's target
 325  * (and strip back out the now unreached jump)
 326  *
 327  * TODO sometimes we end up with things like:
 328  *
 329  *    br !p0.x, #2
 330  *    br p0.x, #12
 331  *    add.u r0.y, r0.y, 1
 332  *
 333  * If we swapped the order of the branches, we could drop one.
 334  */
 335 static struct ir3_block *
 336 resolve_dest_block(struct ir3_block *block)
 337 {
 338         /* special case for last block: */
 339         if (!block->successors[0])
 340                 return block;
 341
 342         /* NOTE that we may or may not have inserted the jump
 343          * in the target block yet, so conditions to resolve
 344          * the dest to the dest block's successor are:
 345          *
 346          *   (1) successor[1] == NULL &&
 347          *   (2) (block-is-empty || only-instr-is-jump)
 348          */
 349         if (block->successors[1] == NULL) {
 350                 if (list_empty(&block->instr_list)) {
 351                         return block->successors[0];
 352                 } else if (list_length(&block->instr_list) == 1) {
 353                         struct ir3_instruction *instr = list_first_entry(
 354                                         &block->instr_list, struct ir3_instruction, node);
 355                         if (instr->opc == OPC_JUMP)
 356                                 return block->successors[0];
 357                 }
 358         }
 359         return block;
 360 }
 361
 362 static bool
 363 resolve_jump(struct ir3_instruction *instr)
 364 {
 365         struct ir3_block *tblock =
 366                 resolve_dest_block(instr->cat0.target);
 367         struct ir3_instruction *target;
 368
 369         if (tblock != instr->cat0.target) {
 370                 list_delinit(&instr->cat0.target->node);
 371                 instr->cat0.target = tblock;
 372                 return true;
 373         }
 374
 375         target = list_first_entry(&tblock->instr_list,
 376                                 struct ir3_instruction, node);
 377
 378         /* TODO maybe a less fragile way to do this.  But we are expecting
 379          * a pattern from sched_block() that looks like:
 380          *
 381          *   br !p0.x, #else-block
 382          *   br p0.x, #if-block
 383          *
 384          * if the first branch target is +2, or if 2nd branch target is +1
 385          * then we can just drop the jump.
 386          */
 387         unsigned next_block;
 388         if (instr->cat0.inv == true)
 389                 next_block = 2;
 390         else
 391                 next_block = 1;
 392
 393         if ((!target) || (target->ip == (instr->ip + next_block))) {
 394                 list_delinit(&instr->node);
 395                 return true;
 396         } else {
 397                 instr->cat0.immed =
 398                         (int)target->ip - (int)instr->ip;
 399         }
 400         return false;
 401 }
 402
 403 /* resolve jumps, removing jumps/branches to immediately following
 404  * instruction which we end up with from earlier stages.  Since
 405  * removing an instruction can invalidate earlier instruction's
 406  * branch offsets, we need to do this iteratively until no more
 407  * branches are removed.
 408  */
 409 static bool
 410 resolve_jumps(struct ir3 *ir)
 411 {
 412         list_for_each_entry (struct ir3_block, block, &ir->block_list, node)
 413                 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node)
 414                         if (is_flow(instr) && instr->cat0.target)
 415                                 if (resolve_jump(instr))
 416                                         return true;
 417
 418         return false;
 419 }
 420
 421 /* we want to mark points where divergent flow control re-converges
 422  * with (jp) flags.  For now, since we don't do any optimization for
 423  * things that start out as a 'do {} while()', re-convergence points
 424  * will always be a branch or jump target.  Note that this is overly
 425  * conservative, since unconditional jump targets are not convergence
 426  * points, we are just assuming that the other path to reach the jump
 427  * target was divergent.  If we were clever enough to optimize the
 428  * jump at end of a loop back to a conditional branch into a single
 429  * conditional branch, ie. like:
 430  *
 431  *    add.f r1.w, r0.x, (neg)(r)c2.x   <= loop start
 432  *    mul.f r1.z, r1.z, r0.x
 433  *    mul.f r1.y, r1.y, r0.x
 434  *    mul.f r0.z, r1.x, r0.x
 435  *    mul.f r0.w, r0.y, r0.x
 436  *    cmps.f.ge r0.x, (r)c2.y, (r)r1.w
 437  *    add.s r0.x, (r)r0.x, (r)-1
 438  *    sel.f32 r0.x, (r)c3.y, (r)r0.x, c3.x
 439  *    cmps.f.eq p0.x, r0.x, c3.y
 440  *    mov.f32f32 r0.x, r1.w
 441  *    mov.f32f32 r0.y, r0.w
 442  *    mov.f32f32 r1.x, r0.z
 443  *    (rpt2)nop
 444  *    br !p0.x, #-13
 445  *    (jp)mul.f r0.x, c263.y, r1.y
 446  *
 447  * Then we'd have to be more clever, as the convergence point is no
 448  * longer a branch or jump target.
 449  */
 450 static void
 451 mark_convergence_points(struct ir3 *ir)
 452 {
 453         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 454                 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
 455                         if (is_flow(instr) && instr->cat0.target) {
 456                                 struct ir3_instruction *target =
 457                                         list_first_entry(&instr->cat0.target->instr_list,
 458                                                         struct ir3_instruction, node);
 459                                 target->flags |= IR3_INSTR_JP;
 460                         }
 461                 }
 462         }
 463 }
 464
 465 void
 466 ir3_legalize(struct ir3 *ir, bool *has_samp, bool *has_ssbo, int *max_bary)
 467 {
 468         struct ir3_legalize_ctx *ctx = rzalloc(ir, struct ir3_legalize_ctx);
 469         bool progress;
 470
 471         ctx->max_bary = -1;
 472
 473         /* allocate per-block data: */
 474         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 475                 block->data = rzalloc(ctx, struct ir3_legalize_block_data);
 476         }
 477
 478         /* process each block: */
 479         do {
 480                 progress = false;
 481                 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 482                         progress |= legalize_block(ctx, block);
 483                 }
 484         } while (progress);
 485
 486         *has_samp = ctx->has_samp;
 487         *has_ssbo = ctx->has_ssbo;
 488         *max_bary = ctx->max_bary;
 489
 490         do {
 491                 ir3_count_instructions(ir);
 492         } while(resolve_jumps(ir));
 493
 494         mark_convergence_points(ir);
 495
 496         ralloc_free(ctx);
 497 }