src/gallium/drivers/freedreno/ir3/ir3_sched.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "util/u_math.h"
  31
  32 #include "ir3.h"
  33
  34 enum {
  35         SCHEDULED = -1,
  36         DELAYED = -2,
  37 };
  38
  39 /*
  40  * Instruction Scheduling:
  41  *
  42  * Using the depth sorted list from depth pass, attempt to recursively
  43  * schedule deepest unscheduled path.  The first instruction that cannot
  44  * be scheduled, returns the required delay slots it needs, at which
  45  * point we return back up to the top and attempt to schedule by next
  46  * highest depth.  After a sufficient number of instructions have been
  47  * scheduled, return back to beginning of list and start again.  If you
  48  * reach the end of depth sorted list without being able to insert any
  49  * instruction, insert nop's.  Repeat until no more unscheduled
  50  * instructions.
  51  *
  52  * There are a few special cases that need to be handled, since sched
  53  * is currently independent of register allocation.  Usages of address
  54  * register (a0.x) or predicate register (p0.x) must be serialized.  Ie.
  55  * if you have two pairs of instructions that write the same special
  56  * register and then read it, then those pairs cannot be interleaved.
  57  * To solve this, when we are in such a scheduling "critical section",
  58  * and we encounter a conflicting write to a special register, we try
  59  * to schedule any remaining instructions that use that value first.
  60  */
  61
  62 struct ir3_sched_ctx {
  63         struct ir3_instruction *scheduled; /* last scheduled instr */
  64         struct ir3_instruction *addr;      /* current a0.x user, if any */
  65         struct ir3_instruction *pred;      /* current p0.x user, if any */
  66         unsigned cnt;
  67         bool error;
  68 };
  69
  70 static struct ir3_instruction *
  71 deepest(struct ir3_instruction **srcs, unsigned nsrcs)
  72 {
  73         struct ir3_instruction *d = NULL;
  74         unsigned i = 0, id = 0;
  75
  76         while ((i < nsrcs) && !(d = srcs[id = i]))
  77                 i++;
  78
  79         if (!d)
  80                 return NULL;
  81
  82         for (; i < nsrcs; i++)
  83                 if (srcs[i] && (srcs[i]->depth > d->depth))
  84                         d = srcs[id = i];
  85
  86         srcs[id] = NULL;
  87
  88         return d;
  89 }
  90
  91 static unsigned distance(struct ir3_sched_ctx *ctx,
  92                 struct ir3_instruction *instr, unsigned maxd)
  93 {
  94         struct ir3_instruction *n = ctx->scheduled;
  95         unsigned d = 0;
  96         while (n && (n != instr) && (d < maxd)) {
  97                 if (is_alu(n) || is_flow(n))
  98                         d++;
  99                 n = n->next;
 100         }
 101         return d;
 102 }
 103
 104 /* TODO maybe we want double linked list? */
 105 static struct ir3_instruction * prev(struct ir3_instruction *instr)
 106 {
 107         struct ir3_instruction *p = instr->block->head;
 108         while (p && (p->next != instr))
 109                 p = p->next;
 110         return p;
 111 }
 112
 113 static void schedule(struct ir3_sched_ctx *ctx,
 114                 struct ir3_instruction *instr, bool remove)
 115 {
 116         struct ir3_block *block = instr->block;
 117
 118         /* maybe there is a better way to handle this than just stuffing
 119          * a nop.. ideally we'd know about this constraint in the
 120          * scheduling and depth calculation..
 121          */
 122         if (ctx->scheduled && is_sfu(ctx->scheduled) && is_sfu(instr))
 123                 schedule(ctx, ir3_instr_create(block, 0, OPC_NOP), false);
 124
 125         /* remove from depth list:
 126          */
 127         if (remove) {
 128                 struct ir3_instruction *p = prev(instr);
 129
 130                 /* NOTE: this can happen for inputs which are not
 131                  * read.. in that case there is no need to schedule
 132                  * the input, so just bail:
 133                  */
 134                 if (instr != (p ? p->next : block->head))
 135                         return;
 136
 137                 if (p)
 138                         p->next = instr->next;
 139                 else
 140                         block->head = instr->next;
 141         }
 142
 143         if (writes_addr(instr)) {
 144                 assert(ctx->addr == NULL);
 145                 ctx->addr = instr;
 146         }
 147
 148         if (writes_pred(instr)) {
 149                 assert(ctx->pred == NULL);
 150                 ctx->pred = instr;
 151         }
 152
 153         instr->flags |= IR3_INSTR_MARK;
 154
 155         instr->next = ctx->scheduled;
 156         ctx->scheduled = instr;
 157
 158         ctx->cnt++;
 159 }
 160
 161 /*
 162  * Delay-slot calculation.  Follows fanin/fanout.
 163  */
 164
 165 static unsigned delay_calc2(struct ir3_sched_ctx *ctx,
 166                 struct ir3_instruction *assigner,
 167                 struct ir3_instruction *consumer, unsigned srcn)
 168 {
 169         unsigned delay = 0;
 170
 171         if (is_meta(assigner)) {
 172                 unsigned i;
 173                 for (i = 1; i < assigner->regs_count; i++) {
 174                         struct ir3_register *reg = assigner->regs[i];
 175                         if (reg->flags & IR3_REG_SSA) {
 176                                 unsigned d = delay_calc2(ctx, reg->instr,
 177                                                 consumer, srcn);
 178                                 delay = MAX2(delay, d);
 179                         }
 180                 }
 181         } else {
 182                 delay = ir3_delayslots(assigner, consumer, srcn);
 183                 delay -= distance(ctx, assigner, delay);
 184         }
 185
 186         return delay;
 187 }
 188
 189 static unsigned delay_calc(struct ir3_sched_ctx *ctx,
 190                 struct ir3_instruction *instr)
 191 {
 192         unsigned i, delay = 0;
 193
 194         for (i = 1; i < instr->regs_count; i++) {
 195                 struct ir3_register *reg = instr->regs[i];
 196                 if (reg->flags & IR3_REG_SSA) {
 197                         unsigned d = delay_calc2(ctx, reg->instr,
 198                                         instr, i - 1);
 199                         delay = MAX2(delay, d);
 200                 }
 201         }
 202
 203         return delay;
 204 }
 205
 206 /* A negative return value signals that an instruction has been newly
 207  * scheduled, return back up to the top of the stack (to block_sched())
 208  */
 209 static int trysched(struct ir3_sched_ctx *ctx,
 210                 struct ir3_instruction *instr)
 211 {
 212         struct ir3_instruction *srcs[ARRAY_SIZE(instr->regs) - 1];
 213         struct ir3_instruction *src;
 214         unsigned i, delay, nsrcs = 0;
 215
 216         /* if already scheduled: */
 217         if (instr->flags & IR3_INSTR_MARK)
 218                 return 0;
 219
 220         /* figure out our src's: */
 221         for (i = 1; i < instr->regs_count; i++) {
 222                 struct ir3_register *reg = instr->regs[i];
 223                 if (reg->flags & IR3_REG_SSA)
 224                         srcs[nsrcs++] = reg->instr;
 225         }
 226
 227         /* for each src register in sorted order:
 228          */
 229         delay = 0;
 230         while ((src = deepest(srcs, nsrcs))) {
 231                 delay = trysched(ctx, src);
 232                 if (delay)
 233                         return delay;
 234         }
 235
 236         /* all our dependents are scheduled, figure out if
 237          * we have enough delay slots to schedule ourself:
 238          */
 239         delay = delay_calc(ctx, instr);
 240         if (delay)
 241                 return delay;
 242
 243         /* if this is a write to address/predicate register, and that
 244          * register is currently in use, we need to defer until it is
 245          * free:
 246          */
 247         if (writes_addr(instr) && ctx->addr) {
 248                 assert(ctx->addr != instr);
 249                 return DELAYED;
 250         }
 251         if (writes_pred(instr) && ctx->pred) {
 252                 assert(ctx->pred != instr);
 253                 return DELAYED;
 254         }
 255
 256         schedule(ctx, instr, true);
 257         return SCHEDULED;
 258 }
 259
 260 static struct ir3_instruction * reverse(struct ir3_instruction *instr)
 261 {
 262         struct ir3_instruction *reversed = NULL;
 263         while (instr) {
 264                 struct ir3_instruction *next = instr->next;
 265                 instr->next = reversed;
 266                 reversed = instr;
 267                 instr = next;
 268         }
 269         return reversed;
 270 }
 271
 272 static bool uses_current_addr(struct ir3_sched_ctx *ctx,
 273                 struct ir3_instruction *instr)
 274 {
 275         unsigned i;
 276         for (i = 1; i < instr->regs_count; i++) {
 277                 struct ir3_register *reg = instr->regs[i];
 278                 if (reg->flags & IR3_REG_SSA) {
 279                         if (is_addr(reg->instr)) {
 280                                 struct ir3_instruction *addr;
 281                                 addr = reg->instr->regs[1]->instr; /* the mova */
 282                                 if (ctx->addr == addr)
 283                                         return true;
 284                         }
 285                 }
 286         }
 287         return false;
 288 }
 289
 290 static bool uses_current_pred(struct ir3_sched_ctx *ctx,
 291                 struct ir3_instruction *instr)
 292 {
 293         unsigned i;
 294         for (i = 1; i < instr->regs_count; i++) {
 295                 struct ir3_register *reg = instr->regs[i];
 296                 if ((reg->flags & IR3_REG_SSA) && (ctx->pred == reg->instr))
 297                                 return true;
 298         }
 299         return false;
 300 }
 301
 302 /* when we encounter an instruction that writes to the address register
 303  * when it is in use, we delay that instruction and try to schedule all
 304  * other instructions using the current address register:
 305  */
 306 static int block_sched_undelayed(struct ir3_sched_ctx *ctx,
 307                 struct ir3_block *block)
 308 {
 309         struct ir3_instruction *instr = block->head;
 310         bool addr_in_use = false;
 311         bool pred_in_use = false;
 312         bool all_delayed = true;
 313         unsigned cnt = ~0, attempted = 0;
 314
 315         while (instr) {
 316                 struct ir3_instruction *next = instr->next;
 317                 bool addr = uses_current_addr(ctx, instr);
 318                 bool pred = uses_current_pred(ctx, instr);
 319
 320                 if (addr || pred) {
 321                         int ret = trysched(ctx, instr);
 322
 323                         if (ret != DELAYED)
 324                                 all_delayed = false;
 325
 326                         if (ret == SCHEDULED)
 327                                 cnt = 0;
 328                         else if (ret > 0)
 329                                 cnt = MIN2(cnt, ret);
 330                         if (addr)
 331                                 addr_in_use = true;
 332                         if (pred)
 333                                 pred_in_use = true;
 334
 335                         attempted++;
 336                 }
 337
 338                 instr = next;
 339         }
 340
 341         if (!addr_in_use)
 342                 ctx->addr = NULL;
 343
 344         if (!pred_in_use)
 345                 ctx->pred = NULL;
 346
 347         /* detect if we've gotten ourselves into an impossible situation
 348          * and bail if needed
 349          */
 350         if (all_delayed && (attempted > 0))
 351                 ctx->error = true;
 352
 353         return cnt;
 354 }
 355
 356 static void block_sched(struct ir3_sched_ctx *ctx, struct ir3_block *block)
 357 {
 358         struct ir3_instruction *instr;
 359
 360         /* schedule all the shader input's (meta-instr) first so that
 361          * the RA step sees that the input registers contain a value
 362          * from the start of the shader:
 363          */
 364         if (!block->parent) {
 365                 unsigned i;
 366                 for (i = 0; i < block->ninputs; i++) {
 367                         struct ir3_instruction *in = block->inputs[i];
 368                         if (in)
 369                                 schedule(ctx, in, true);
 370                 }
 371         }
 372
 373         while ((instr = block->head) && !ctx->error) {
 374                 /* NOTE: always grab next *before* trysched(), in case the
 375                  * instruction is actually scheduled (and therefore moved
 376                  * from depth list into scheduled list)
 377                  */
 378                 struct ir3_instruction *next = instr->next;
 379                 int cnt = trysched(ctx, instr);
 380
 381                 if (cnt == DELAYED)
 382                         cnt = block_sched_undelayed(ctx, block);
 383
 384                 /* -1 is signal to return up stack, but to us means same as 0: */
 385                 cnt = MAX2(0, cnt);
 386                 cnt += ctx->cnt;
 387                 instr = next;
 388
 389                 /* if deepest remaining instruction cannot be scheduled, try
 390                  * the increasingly more shallow instructions until needed
 391                  * number of delay slots is filled:
 392                  */
 393                 while (instr && (cnt > ctx->cnt)) {
 394                         next = instr->next;
 395                         trysched(ctx, instr);
 396                         instr = next;
 397                 }
 398
 399                 /* and if we run out of instructions that can be scheduled,
 400                  * then it is time for nop's:
 401                  */
 402                 while (cnt > ctx->cnt)
 403                         schedule(ctx, ir3_instr_create(block, 0, OPC_NOP), false);
 404         }
 405
 406         /* at this point, scheduled list is in reverse order, so fix that: */
 407         block->head = reverse(ctx->scheduled);
 408 }
 409
 410 int ir3_block_sched(struct ir3_block *block)
 411 {
 412         struct ir3_sched_ctx ctx = {0};
 413         ir3_clear_mark(block->shader);
 414         block_sched(&ctx, block);
 415         if (ctx.error)
 416                 return -1;
 417         return 0;
 418 }