src/gallium/drivers/freedreno/ir3/ir3_sched.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "util/u_math.h"
  31
  32 #include "ir3.h"
  33
  34 enum {
  35         SCHEDULED = -1,
  36         DELAYED = -2,
  37 };
  38
  39 /*
  40  * Instruction Scheduling:
  41  *
  42  * Using the depth sorted list from depth pass, attempt to recursively
  43  * schedule deepest unscheduled path.  The first instruction that cannot
  44  * be scheduled, returns the required delay slots it needs, at which
  45  * point we return back up to the top and attempt to schedule by next
  46  * highest depth.  After a sufficient number of instructions have been
  47  * scheduled, return back to beginning of list and start again.  If you
  48  * reach the end of depth sorted list without being able to insert any
  49  * instruction, insert nop's.  Repeat until no more unscheduled
  50  * instructions.
  51  *
  52  * There are a few special cases that need to be handled, since sched
  53  * is currently independent of register allocation.  Usages of address
  54  * register (a0.x) or predicate register (p0.x) must be serialized.  Ie.
  55  * if you have two pairs of instructions that write the same special
  56  * register and then read it, then those pairs cannot be interleaved.
  57  * To solve this, when we are in such a scheduling "critical section",
  58  * and we encounter a conflicting write to a special register, we try
  59  * to schedule any remaining instructions that use that value first.
  60  */
  61
  62 struct ir3_sched_ctx {
  63         struct ir3_instruction *scheduled; /* last scheduled instr */
  64         struct ir3_instruction *addr;      /* current a0.x user, if any */
  65         struct ir3_instruction *pred;      /* current p0.x user, if any */
  66         unsigned cnt;
  67         bool error;
  68 };
  69
  70 static struct ir3_instruction *
  71 deepest(struct ir3_instruction **srcs, unsigned nsrcs)
  72 {
  73         struct ir3_instruction *d = NULL;
  74         unsigned i = 0, id = 0;
  75
  76         while ((i < nsrcs) && !(d = srcs[id = i]))
  77                 i++;
  78
  79         if (!d)
  80                 return NULL;
  81
  82         for (; i < nsrcs; i++)
  83                 if (srcs[i] && (srcs[i]->depth > d->depth))
  84                         d = srcs[id = i];
  85
  86         srcs[id] = NULL;
  87
  88         return d;
  89 }
  90
  91 static unsigned distance(struct ir3_sched_ctx *ctx,
  92                 struct ir3_instruction *instr, unsigned maxd)
  93 {
  94         struct ir3_instruction *n = ctx->scheduled;
  95         unsigned d = 0;
  96         while (n && (n != instr) && (d < maxd)) {
  97                 if (is_alu(n) || is_flow(n))
  98                         d++;
  99                 n = n->next;
 100         }
 101         return d;
 102 }
 103
 104 /* TODO maybe we want double linked list? */
 105 static struct ir3_instruction * prev(struct ir3_instruction *instr)
 106 {
 107         struct ir3_instruction *p = instr->block->head;
 108         while (p && (p->next != instr))
 109                 p = p->next;
 110         return p;
 111 }
 112
 113 static void schedule(struct ir3_sched_ctx *ctx,
 114                 struct ir3_instruction *instr, bool remove)
 115 {
 116         struct ir3_block *block = instr->block;
 117
 118         /* maybe there is a better way to handle this than just stuffing
 119          * a nop.. ideally we'd know about this constraint in the
 120          * scheduling and depth calculation..
 121          */
 122         if (ctx->scheduled && is_sfu(ctx->scheduled) && is_sfu(instr))
 123                 schedule(ctx, ir3_instr_create(block, 0, OPC_NOP), false);
 124
 125         /* remove from depth list:
 126          */
 127         if (remove) {
 128                 struct ir3_instruction *p = prev(instr);
 129
 130                 /* NOTE: this can happen for inputs which are not
 131                  * read.. in that case there is no need to schedule
 132                  * the input, so just bail:
 133                  */
 134                 if (instr != (p ? p->next : block->head))
 135                         return;
 136
 137                 if (p)
 138                         p->next = instr->next;
 139                 else
 140                         block->head = instr->next;
 141         }
 142
 143         if (writes_addr(instr)) {
 144                 assert(ctx->addr == NULL);
 145                 ctx->addr = instr;
 146         }
 147
 148         if (writes_pred(instr)) {
 149                 assert(ctx->pred == NULL);
 150                 ctx->pred = instr;
 151         }
 152
 153         instr->flags |= IR3_INSTR_MARK;
 154
 155         instr->next = ctx->scheduled;
 156         ctx->scheduled = instr;
 157
 158         ctx->cnt++;
 159 }
 160
 161 /*
 162  * Delay-slot calculation.  Follows fanin/fanout.
 163  */
 164
 165 /* calculate delay for specified src: */
 166 static unsigned delay_calc_srcn(struct ir3_sched_ctx *ctx,
 167                 struct ir3_instruction *assigner,
 168                 struct ir3_instruction *consumer, unsigned srcn)
 169 {
 170         unsigned delay = 0;
 171
 172         if (is_meta(assigner)) {
 173                 struct ir3_instruction *src;
 174                 foreach_ssa_src(src, assigner) {
 175                         unsigned d = delay_calc_srcn(ctx, src, consumer, srcn);
 176                         delay = MAX2(delay, d);
 177                 }
 178         } else {
 179                 delay = ir3_delayslots(assigner, consumer, srcn);
 180                 delay -= distance(ctx, assigner, delay);
 181         }
 182
 183         return delay;
 184 }
 185
 186 /* calculate delay for instruction (maximum of delay for all srcs): */
 187 static unsigned delay_calc(struct ir3_sched_ctx *ctx,
 188                 struct ir3_instruction *instr)
 189 {
 190         unsigned delay = 0;
 191         struct ir3_instruction *src;
 192
 193         foreach_ssa_src_n(src, i, instr) {
 194                 unsigned d = delay_calc_srcn(ctx, src, instr, i);
 195                 delay = MAX2(delay, d);
 196         }
 197
 198         return delay;
 199 }
 200
 201 /* A negative return value signals that an instruction has been newly
 202  * SCHEDULED (or DELAYED due to address or predicate register already
 203  * in use), return back up to the top of the stack (to block_sched())
 204  */
 205 static int trysched(struct ir3_sched_ctx *ctx,
 206                 struct ir3_instruction *instr)
 207 {
 208         struct ir3_instruction *srcs[64];
 209         struct ir3_instruction *src;
 210         unsigned delay, nsrcs = 0;
 211
 212         /* if already scheduled: */
 213         if (instr->flags & IR3_INSTR_MARK)
 214                 return 0;
 215
 216         /* figure out our src's, copy 'em out into an array for sorting: */
 217         foreach_ssa_src(src, instr) {
 218                 debug_assert(nsrcs < ARRAY_SIZE(srcs));
 219                 srcs[nsrcs++] = src;
 220         }
 221
 222         /* for each src register in sorted order:
 223          */
 224         delay = 0;
 225         while ((src = deepest(srcs, nsrcs))) {
 226                 delay = trysched(ctx, src);
 227                 if (delay)
 228                         return delay;
 229         }
 230
 231         /* all our dependents are scheduled, figure out if
 232          * we have enough delay slots to schedule ourself:
 233          */
 234         delay = delay_calc(ctx, instr);
 235         if (delay)
 236                 return delay;
 237
 238         /* if the instruction is a kill, we need to ensure *every*
 239          * bary.f is scheduled.  The hw seems unhappy if the thread
 240          * gets killed before the end-input (ei) flag is hit.
 241          *
 242          * We could do this by adding each bary.f instruction as
 243          * virtual ssa src for the kill instruction.  But we have
 244          * fixed length instr->regs[].
 245          *
 246          * TODO this wouldn't be quite right if we had multiple
 247          * basic blocks, if any block was conditional.  We'd need
 248          * to schedule the bary.f's outside of any block which
 249          * was conditional that contained a kill.. I think..
 250          */
 251         if (is_kill(instr)) {
 252                 struct ir3 *ir = instr->block->shader;
 253                 unsigned i;
 254
 255                 for (i = 0; i < ir->baryfs_count; i++) {
 256                         struct ir3_instruction *baryf = ir->baryfs[i];
 257                         if (baryf->depth == DEPTH_UNUSED)
 258                                 continue;
 259                         delay = trysched(ctx, baryf);
 260                         if (delay)
 261                                 return delay;
 262                 }
 263         }
 264
 265         /* if instruction writes address register, we need to ensure
 266          * that the instructions which use the address register value
 267          * have all their other dependencies scheduled.
 268          * TODO we may possibly need to do the same thing with predicate
 269          * register usage, but for now we get by without since the
 270          * predicate usage patterns are more simple
 271          */
 272         if (writes_addr(instr)) {
 273                 struct ir3 *ir = instr->block->shader;
 274                 unsigned i;
 275
 276                 for (i = 0; i < ir->indirects_count; i++) {
 277                         struct ir3_instruction *indirect = ir->indirects[i];
 278                         if (indirect->depth == DEPTH_UNUSED)
 279                                 continue;
 280                         if (indirect->address != instr)
 281                                 continue;
 282                         /* NOTE: avoid recursively scheduling the dependency
 283                          * on ourself (ie. avoid infinite recursion):
 284                          */
 285                         foreach_ssa_src(src, indirect) {
 286                                 if (src == instr)
 287                                         continue;
 288                                 delay = trysched(ctx, src);
 289                                 if (delay)
 290                                         return delay;
 291                         }
 292                 }
 293         }
 294
 295         /* if this is a write to address/predicate register, and that
 296          * register is currently in use, we need to defer until it is
 297          * free:
 298          */
 299         if (writes_addr(instr) && ctx->addr) {
 300                 assert(ctx->addr != instr);
 301                 return DELAYED;
 302         }
 303         if (writes_pred(instr) && ctx->pred) {
 304                 assert(ctx->pred != instr);
 305                 return DELAYED;
 306         }
 307
 308         schedule(ctx, instr, true);
 309         return SCHEDULED;
 310 }
 311
 312 static struct ir3_instruction * reverse(struct ir3_instruction *instr)
 313 {
 314         struct ir3_instruction *reversed = NULL;
 315         while (instr) {
 316                 struct ir3_instruction *next = instr->next;
 317                 instr->next = reversed;
 318                 reversed = instr;
 319                 instr = next;
 320         }
 321         return reversed;
 322 }
 323
 324 static bool uses_current_addr(struct ir3_sched_ctx *ctx,
 325                 struct ir3_instruction *instr)
 326 {
 327         return instr->address && (ctx->addr == instr->address);
 328 }
 329
 330 static bool uses_current_pred(struct ir3_sched_ctx *ctx,
 331                 struct ir3_instruction *instr)
 332 {
 333         struct ir3_instruction *src;
 334         foreach_ssa_src(src, instr)
 335                 if (ctx->pred == src)
 336                         return true;
 337         return false;
 338 }
 339
 340 /* when we encounter an instruction that writes to the address register
 341  * when it is in use, we delay that instruction and try to schedule all
 342  * other instructions using the current address register:
 343  */
 344 static int block_sched_undelayed(struct ir3_sched_ctx *ctx,
 345                 struct ir3_block *block)
 346 {
 347         struct ir3_instruction *instr = block->head;
 348         bool addr_in_use = false;
 349         bool pred_in_use = false;
 350         bool all_delayed = true;
 351         unsigned cnt = ~0, attempted = 0;
 352
 353         while (instr) {
 354                 struct ir3_instruction *next = instr->next;
 355                 bool addr = uses_current_addr(ctx, instr);
 356                 bool pred = uses_current_pred(ctx, instr);
 357
 358                 if (addr || pred) {
 359                         int ret = trysched(ctx, instr);
 360
 361                         if (ret != DELAYED)
 362                                 all_delayed = false;
 363
 364                         if (ret == SCHEDULED)
 365                                 cnt = 0;
 366                         else if (ret > 0)
 367                                 cnt = MIN2(cnt, ret);
 368                         if (addr)
 369                                 addr_in_use = true;
 370                         if (pred)
 371                                 pred_in_use = true;
 372
 373                         attempted++;
 374                 }
 375
 376                 instr = next;
 377         }
 378
 379         if (!addr_in_use)
 380                 ctx->addr = NULL;
 381
 382         if (!pred_in_use)
 383                 ctx->pred = NULL;
 384
 385         /* detect if we've gotten ourselves into an impossible situation
 386          * and bail if needed
 387          */
 388         if (all_delayed && (attempted > 0))
 389                 ctx->error = true;
 390
 391         return cnt;
 392 }
 393
 394 static void block_sched(struct ir3_sched_ctx *ctx, struct ir3_block *block)
 395 {
 396         struct ir3_instruction *instr;
 397
 398         /* schedule all the shader input's (meta-instr) first so that
 399          * the RA step sees that the input registers contain a value
 400          * from the start of the shader:
 401          */
 402         if (!block->parent) {
 403                 unsigned i;
 404                 for (i = 0; i < block->ninputs; i++) {
 405                         struct ir3_instruction *in = block->inputs[i];
 406                         if (in)
 407                                 schedule(ctx, in, true);
 408                 }
 409         }
 410
 411         while ((instr = block->head) && !ctx->error) {
 412                 /* NOTE: always grab next *before* trysched(), in case the
 413                  * instruction is actually scheduled (and therefore moved
 414                  * from depth list into scheduled list)
 415                  */
 416                 struct ir3_instruction *next = instr->next;
 417                 int cnt = trysched(ctx, instr);
 418
 419                 if (cnt == DELAYED)
 420                         cnt = block_sched_undelayed(ctx, block);
 421
 422                 /* -1 is signal to return up stack, but to us means same as 0: */
 423                 cnt = MAX2(0, cnt);
 424                 cnt += ctx->cnt;
 425                 instr = next;
 426
 427                 /* if deepest remaining instruction cannot be scheduled, try
 428                  * the increasingly more shallow instructions until needed
 429                  * number of delay slots is filled:
 430                  */
 431                 while (instr && (cnt > ctx->cnt)) {
 432                         next = instr->next;
 433                         trysched(ctx, instr);
 434                         instr = next;
 435                 }
 436
 437                 /* and if we run out of instructions that can be scheduled,
 438                  * then it is time for nop's:
 439                  */
 440                 while (cnt > ctx->cnt)
 441                         schedule(ctx, ir3_instr_create(block, 0, OPC_NOP), false);
 442         }
 443
 444         /* at this point, scheduled list is in reverse order, so fix that: */
 445         block->head = reverse(ctx->scheduled);
 446 }
 447
 448 int ir3_block_sched(struct ir3_block *block)
 449 {
 450         struct ir3_sched_ctx ctx = {0};
 451         ir3_clear_mark(block->shader);
 452         block_sched(&ctx, block);
 453         if (ctx.error)
 454                 return -1;
 455         return 0;
 456 }