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freedreno/ir3: txf_ms support
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_shader.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
36
37 #include "freedreno_context.h"
38 #include "freedreno_util.h"
39
40 #include "ir3_shader.h"
41 #include "ir3_compiler.h"
42 #include "ir3_nir.h"
43
44 int
45 ir3_glsl_type_size(const struct glsl_type *type)
46 {
47 return glsl_count_attribute_slots(type, false);
48 }
49
50 static void
51 delete_variant(struct ir3_shader_variant *v)
52 {
53 if (v->ir)
54 ir3_destroy(v->ir);
55 if (v->bo)
56 fd_bo_del(v->bo);
57 free(v);
58 }
59
60 /* for vertex shader, the inputs are loaded into registers before the shader
61 * is executed, so max_regs from the shader instructions might not properly
62 * reflect the # of registers actually used, especially in case passthrough
63 * varyings.
64 *
65 * Likewise, for fragment shader, we can have some regs which are passed
66 * input values but never touched by the resulting shader (ie. as result
67 * of dead code elimination or simply because we don't know how to turn
68 * the reg off.
69 */
70 static void
71 fixup_regfootprint(struct ir3_shader_variant *v)
72 {
73 unsigned i;
74
75 for (i = 0; i < v->inputs_count; i++) {
76 /* skip frag inputs fetch via bary.f since their reg's are
77 * not written by gpu before shader starts (and in fact the
78 * regid's might not even be valid)
79 */
80 if (v->inputs[i].bary)
81 continue;
82
83 /* ignore high regs that are global to all threads in a warp
84 * (they exist by default) (a5xx+)
85 */
86 if (v->inputs[i].regid >= regid(48,0))
87 continue;
88
89 if (v->inputs[i].compmask) {
90 unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
91 int32_t regid = (v->inputs[i].regid + n) >> 2;
92 v->info.max_reg = MAX2(v->info.max_reg, regid);
93 }
94 }
95
96 for (i = 0; i < v->outputs_count; i++) {
97 int32_t regid = (v->outputs[i].regid + 3) >> 2;
98 v->info.max_reg = MAX2(v->info.max_reg, regid);
99 }
100
101 if (v->type == SHADER_FRAGMENT) {
102 /* NOTE: not sure how to turn pos_regid off.. but this could
103 * be, for example, r1.x while max reg used by the shader is
104 * r0.*, in which case we need to fixup the reg footprint:
105 */
106 v->info.max_reg = MAX2(v->info.max_reg, v->pos_regid >> 2);
107 if (v->frag_coord)
108 debug_assert(v->info.max_reg >= 0); /* hard coded r0.x */
109 if (v->frag_face)
110 debug_assert(v->info.max_half_reg >= 0); /* hr0.x */
111 }
112 }
113
114 /* wrapper for ir3_assemble() which does some info fixup based on
115 * shader state. Non-static since used by ir3_cmdline too.
116 */
117 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
118 {
119 void *bin;
120
121 bin = ir3_assemble(v->ir, &v->info, gpu_id);
122 if (!bin)
123 return NULL;
124
125 if (gpu_id >= 400) {
126 v->instrlen = v->info.sizedwords / (2 * 16);
127 } else {
128 v->instrlen = v->info.sizedwords / (2 * 4);
129 }
130
131 /* NOTE: if relative addressing is used, we set constlen in
132 * the compiler (to worst-case value) since we don't know in
133 * the assembler what the max addr reg value can be:
134 */
135 v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
136
137 fixup_regfootprint(v);
138
139 return bin;
140 }
141
142 static void
143 assemble_variant(struct ir3_shader_variant *v)
144 {
145 struct ir3_compiler *compiler = v->shader->compiler;
146 uint32_t gpu_id = compiler->gpu_id;
147 uint32_t sz, *bin;
148
149 bin = ir3_shader_assemble(v, gpu_id);
150 sz = v->info.sizedwords * 4;
151
152 v->bo = fd_bo_new(compiler->dev, sz,
153 DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
154 DRM_FREEDRENO_GEM_TYPE_KMEM);
155
156 memcpy(fd_bo_map(v->bo), bin, sz);
157
158 if (fd_mesa_debug & FD_DBG_DISASM) {
159 struct ir3_shader_key key = v->key;
160 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
161 key.binning_pass, key.color_two_side, key.half_precision);
162 ir3_shader_disasm(v, bin);
163 }
164
165 free(bin);
166
167 /* no need to keep the ir around beyond this point: */
168 ir3_destroy(v->ir);
169 v->ir = NULL;
170 }
171
172 static void
173 dump_shader_info(struct ir3_shader_variant *v, struct pipe_debug_callback *debug)
174 {
175 if (!unlikely(fd_mesa_debug & FD_DBG_SHADERDB))
176 return;
177
178 pipe_debug_message(debug, SHADER_INFO, "\n"
179 "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n"
180 "SHADER-DB: %s prog %d/%d: %u half, %u full\n"
181 "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n"
182 "SHADER-DB: %s prog %d/%d: %u (ss), %u (sy)\n",
183 ir3_shader_stage(v->shader),
184 v->shader->id, v->id,
185 v->info.instrs_count,
186 v->info.sizedwords,
187 ir3_shader_stage(v->shader),
188 v->shader->id, v->id,
189 v->info.max_half_reg + 1,
190 v->info.max_reg + 1,
191 ir3_shader_stage(v->shader),
192 v->shader->id, v->id,
193 v->info.max_const + 1,
194 v->constlen,
195 ir3_shader_stage(v->shader),
196 v->shader->id, v->id,
197 v->info.ss, v->info.sy);
198 }
199
200 static struct ir3_shader_variant *
201 create_variant(struct ir3_shader *shader, struct ir3_shader_key key)
202 {
203 struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
204 int ret;
205
206 if (!v)
207 return NULL;
208
209 v->id = ++shader->variant_count;
210 v->shader = shader;
211 v->key = key;
212 v->type = shader->type;
213
214 ret = ir3_compile_shader_nir(shader->compiler, v);
215 if (ret) {
216 debug_error("compile failed!");
217 goto fail;
218 }
219
220 assemble_variant(v);
221 if (!v->bo) {
222 debug_error("assemble failed!");
223 goto fail;
224 }
225
226 return v;
227
228 fail:
229 delete_variant(v);
230 return NULL;
231 }
232
233 struct ir3_shader_variant *
234 ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key,
235 struct pipe_debug_callback *debug)
236 {
237 struct ir3_shader_variant *v;
238
239 /* some shader key values only apply to vertex or frag shader,
240 * so normalize the key to avoid constructing multiple identical
241 * variants:
242 */
243 switch (shader->type) {
244 case SHADER_FRAGMENT:
245 key.binning_pass = false;
246 if (key.has_per_samp) {
247 key.vsaturate_s = 0;
248 key.vsaturate_t = 0;
249 key.vsaturate_r = 0;
250 key.vastc_srgb = 0;
251 key.vsamples = 0;
252 }
253 break;
254 case SHADER_VERTEX:
255 key.color_two_side = false;
256 key.half_precision = false;
257 key.rasterflat = false;
258 if (key.has_per_samp) {
259 key.fsaturate_s = 0;
260 key.fsaturate_t = 0;
261 key.fsaturate_r = 0;
262 key.fastc_srgb = 0;
263 key.fsamples = 0;
264 }
265 break;
266 default:
267 /* TODO */
268 break;
269 }
270
271 for (v = shader->variants; v; v = v->next)
272 if (ir3_shader_key_equal(&key, &v->key))
273 return v;
274
275 /* compile new variant if it doesn't exist already: */
276 v = create_variant(shader, key);
277 if (v) {
278 v->next = shader->variants;
279 shader->variants = v;
280 dump_shader_info(v, debug);
281 }
282
283 return v;
284 }
285
286
287 void
288 ir3_shader_destroy(struct ir3_shader *shader)
289 {
290 struct ir3_shader_variant *v, *t;
291 for (v = shader->variants; v; ) {
292 t = v;
293 v = v->next;
294 delete_variant(t);
295 }
296 ralloc_free(shader->nir);
297 free(shader);
298 }
299
300 struct ir3_shader *
301 ir3_shader_create(struct ir3_compiler *compiler,
302 const struct pipe_shader_state *cso, enum shader_t type,
303 struct pipe_debug_callback *debug)
304 {
305 struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
306 shader->compiler = compiler;
307 shader->id = ++shader->compiler->shader_count;
308 shader->type = type;
309
310 nir_shader *nir;
311 if (cso->type == PIPE_SHADER_IR_NIR) {
312 /* we take ownership of the reference: */
313 nir = cso->ir.nir;
314
315 NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
316 (nir_lower_io_options)0);
317 } else {
318 debug_assert(cso->type == PIPE_SHADER_IR_TGSI);
319 if (fd_mesa_debug & FD_DBG_DISASM) {
320 DBG("dump tgsi: type=%d", shader->type);
321 tgsi_dump(cso->tokens, 0);
322 }
323 nir = ir3_tgsi_to_nir(cso->tokens);
324 }
325 /* do first pass optimization, ignoring the key: */
326 shader->nir = ir3_optimize_nir(shader, nir, NULL);
327 if (fd_mesa_debug & FD_DBG_DISASM) {
328 DBG("dump nir%d: type=%d", shader->id, shader->type);
329 nir_print_shader(shader->nir, stdout);
330 }
331
332 shader->stream_output = cso->stream_output;
333 if (fd_mesa_debug & FD_DBG_SHADERDB) {
334 /* if shader-db run, create a standard variant immediately
335 * (as otherwise nothing will trigger the shader to be
336 * actually compiled)
337 */
338 static struct ir3_shader_key key;
339 memset(&key, 0, sizeof(key));
340 ir3_shader_variant(shader, key, debug);
341 }
342 return shader;
343 }
344
345 /* a bit annoying that compute-shader and normal shader state objects
346 * aren't a bit more aligned.
347 */
348 struct ir3_shader *
349 ir3_shader_create_compute(struct ir3_compiler *compiler,
350 const struct pipe_compute_state *cso,
351 struct pipe_debug_callback *debug)
352 {
353 struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
354
355 shader->compiler = compiler;
356 shader->id = ++shader->compiler->shader_count;
357 shader->type = SHADER_COMPUTE;
358
359 nir_shader *nir;
360 if (cso->ir_type == PIPE_SHADER_IR_NIR) {
361 /* we take ownership of the reference: */
362 nir = (nir_shader *)cso->prog;
363
364 NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
365 (nir_lower_io_options)0);
366 } else {
367 debug_assert(cso->ir_type == PIPE_SHADER_IR_TGSI);
368 if (fd_mesa_debug & FD_DBG_DISASM) {
369 DBG("dump tgsi: type=%d", shader->type);
370 tgsi_dump(cso->prog, 0);
371 }
372 nir = ir3_tgsi_to_nir(cso->prog);
373 }
374
375 /* do first pass optimization, ignoring the key: */
376 shader->nir = ir3_optimize_nir(shader, nir, NULL);
377 if (fd_mesa_debug & FD_DBG_DISASM) {
378 DBG("dump nir%d: type=%d", shader->id, shader->type);
379 nir_print_shader(shader->nir, stdout);
380 }
381
382 return shader;
383 }
384
385 static void dump_reg(const char *name, uint32_t r)
386 {
387 if (r != regid(63,0))
388 debug_printf("; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
389 }
390
391 static void dump_output(struct ir3_shader_variant *so,
392 unsigned slot, const char *name)
393 {
394 uint32_t regid;
395 regid = ir3_find_output_regid(so, slot);
396 dump_reg(name, regid);
397 }
398
399 void
400 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
401 {
402 struct ir3 *ir = so->ir;
403 struct ir3_register *reg;
404 const char *type = ir3_shader_stage(so->shader);
405 uint8_t regid;
406 unsigned i;
407
408 for (i = 0; i < ir->ninputs; i++) {
409 if (!ir->inputs[i]) {
410 debug_printf("; in%d unused\n", i);
411 continue;
412 }
413 reg = ir->inputs[i]->regs[0];
414 regid = reg->num;
415 debug_printf("@in(%sr%d.%c)\tin%d\n",
416 (reg->flags & IR3_REG_HALF) ? "h" : "",
417 (regid >> 2), "xyzw"[regid & 0x3], i);
418 }
419
420 for (i = 0; i < ir->noutputs; i++) {
421 if (!ir->outputs[i]) {
422 debug_printf("; out%d unused\n", i);
423 continue;
424 }
425 /* kill shows up as a virtual output.. skip it! */
426 if (is_kill(ir->outputs[i]))
427 continue;
428 reg = ir->outputs[i]->regs[0];
429 regid = reg->num;
430 debug_printf("@out(%sr%d.%c)\tout%d\n",
431 (reg->flags & IR3_REG_HALF) ? "h" : "",
432 (regid >> 2), "xyzw"[regid & 0x3], i);
433 }
434
435 for (i = 0; i < so->immediates_count; i++) {
436 debug_printf("@const(c%d.x)\t", so->constbase.immediate + i);
437 debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
438 so->immediates[i].val[0],
439 so->immediates[i].val[1],
440 so->immediates[i].val[2],
441 so->immediates[i].val[3]);
442 }
443
444 disasm_a3xx(bin, so->info.sizedwords, 0, so->type);
445
446 switch (so->type) {
447 case SHADER_VERTEX:
448 debug_printf("; %s: outputs:", type);
449 for (i = 0; i < so->outputs_count; i++) {
450 uint8_t regid = so->outputs[i].regid;
451 debug_printf(" r%d.%c (%s)",
452 (regid >> 2), "xyzw"[regid & 0x3],
453 gl_varying_slot_name(so->outputs[i].slot));
454 }
455 debug_printf("\n");
456 debug_printf("; %s: inputs:", type);
457 for (i = 0; i < so->inputs_count; i++) {
458 uint8_t regid = so->inputs[i].regid;
459 debug_printf(" r%d.%c (cm=%x,il=%u,b=%u)",
460 (regid >> 2), "xyzw"[regid & 0x3],
461 so->inputs[i].compmask,
462 so->inputs[i].inloc,
463 so->inputs[i].bary);
464 }
465 debug_printf("\n");
466 break;
467 case SHADER_FRAGMENT:
468 debug_printf("; %s: outputs:", type);
469 for (i = 0; i < so->outputs_count; i++) {
470 uint8_t regid = so->outputs[i].regid;
471 debug_printf(" r%d.%c (%s)",
472 (regid >> 2), "xyzw"[regid & 0x3],
473 gl_frag_result_name(so->outputs[i].slot));
474 }
475 debug_printf("\n");
476 debug_printf("; %s: inputs:", type);
477 for (i = 0; i < so->inputs_count; i++) {
478 uint8_t regid = so->inputs[i].regid;
479 debug_printf(" r%d.%c (%s,cm=%x,il=%u,b=%u)",
480 (regid >> 2), "xyzw"[regid & 0x3],
481 gl_varying_slot_name(so->inputs[i].slot),
482 so->inputs[i].compmask,
483 so->inputs[i].inloc,
484 so->inputs[i].bary);
485 }
486 debug_printf("\n");
487 break;
488 default:
489 /* TODO */
490 break;
491 }
492
493 /* print generic shader info: */
494 debug_printf("; %s prog %d/%d: %u instructions, %d half, %d full\n",
495 type, so->shader->id, so->id,
496 so->info.instrs_count,
497 so->info.max_half_reg + 1,
498 so->info.max_reg + 1);
499
500 debug_printf("; %d const, %u constlen\n",
501 so->info.max_const + 1,
502 so->constlen);
503
504 debug_printf("; %u (ss), %u (sy)\n", so->info.ss, so->info.sy);
505
506 /* print shader type specific info: */
507 switch (so->type) {
508 case SHADER_VERTEX:
509 dump_output(so, VARYING_SLOT_POS, "pos");
510 dump_output(so, VARYING_SLOT_PSIZ, "psize");
511 break;
512 case SHADER_FRAGMENT:
513 dump_reg("pos (bary)", so->pos_regid);
514 dump_output(so, FRAG_RESULT_DEPTH, "posz");
515 if (so->color0_mrt) {
516 dump_output(so, FRAG_RESULT_COLOR, "color");
517 } else {
518 dump_output(so, FRAG_RESULT_DATA0, "data0");
519 dump_output(so, FRAG_RESULT_DATA1, "data1");
520 dump_output(so, FRAG_RESULT_DATA2, "data2");
521 dump_output(so, FRAG_RESULT_DATA3, "data3");
522 dump_output(so, FRAG_RESULT_DATA4, "data4");
523 dump_output(so, FRAG_RESULT_DATA5, "data5");
524 dump_output(so, FRAG_RESULT_DATA6, "data6");
525 dump_output(so, FRAG_RESULT_DATA7, "data7");
526 }
527 /* these two are hard-coded since we don't know how to
528 * program them to anything but all 0's...
529 */
530 if (so->frag_coord)
531 debug_printf("; fragcoord: r0.x\n");
532 if (so->frag_face)
533 debug_printf("; fragface: hr0.x\n");
534 break;
535 default:
536 /* TODO */
537 break;
538 }
539
540 debug_printf("\n");
541 }
542
543 uint64_t
544 ir3_shader_outputs(const struct ir3_shader *so)
545 {
546 return so->nir->info.outputs_written;
547 }
548
549 /* This has to reach into the fd_context a bit more than the rest of
550 * ir3, but it needs to be aligned with the compiler, so both agree
551 * on which const regs hold what. And the logic is identical between
552 * a3xx/a4xx, the only difference is small details in the actual
553 * CP_LOAD_STATE packets (which is handled inside the generation
554 * specific ctx->emit_const(_bo)() fxns)
555 */
556
557 #include "freedreno_resource.h"
558
559 static void
560 emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
561 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
562 {
563 const unsigned index = 0; /* user consts are index 0 */
564
565 if (constbuf->enabled_mask & (1 << index)) {
566 struct pipe_constant_buffer *cb = &constbuf->cb[index];
567 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
568
569 /* in particular, with binning shader we may end up with
570 * unused consts, ie. we could end up w/ constlen that is
571 * smaller than first_driver_param. In that case truncate
572 * the user consts early to avoid HLSQ lockup caused by
573 * writing too many consts
574 */
575 uint32_t max_const = MIN2(v->num_uniforms, v->constlen);
576
577 // I expect that size should be a multiple of vec4's:
578 assert(size == align(size, 4));
579
580 /* and even if the start of the const buffer is before
581 * first_immediate, the end may not be:
582 */
583 size = MIN2(size, 4 * max_const);
584
585 if (size > 0) {
586 fd_wfi(ctx->batch, ring);
587 ctx->emit_const(ring, v->type, 0,
588 cb->buffer_offset, size,
589 cb->user_buffer, cb->buffer);
590 }
591 }
592 }
593
594 static void
595 emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
596 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
597 {
598 uint32_t offset = v->constbase.ubo;
599 if (v->constlen > offset) {
600 uint32_t params = v->num_ubos;
601 uint32_t offsets[params];
602 struct pipe_resource *prscs[params];
603
604 for (uint32_t i = 0; i < params; i++) {
605 const uint32_t index = i + 1; /* UBOs start at index 1 */
606 struct pipe_constant_buffer *cb = &constbuf->cb[index];
607 assert(!cb->user_buffer);
608
609 if ((constbuf->enabled_mask & (1 << index)) && cb->buffer) {
610 offsets[i] = cb->buffer_offset;
611 prscs[i] = cb->buffer;
612 } else {
613 offsets[i] = 0;
614 prscs[i] = NULL;
615 }
616 }
617
618 fd_wfi(ctx->batch, ring);
619 ctx->emit_const_bo(ring, v->type, false, offset * 4, params, prscs, offsets);
620 }
621 }
622
623 static void
624 emit_ssbo_sizes(struct fd_context *ctx, const struct ir3_shader_variant *v,
625 struct fd_ringbuffer *ring, struct fd_shaderbuf_stateobj *sb)
626 {
627 uint32_t offset = v->constbase.ssbo_sizes;
628 if (v->constlen > offset) {
629 uint32_t sizes[align(v->const_layout.ssbo_size.count, 4)];
630 unsigned mask = v->const_layout.ssbo_size.mask;
631
632 while (mask) {
633 unsigned index = u_bit_scan(&mask);
634 unsigned off = v->const_layout.ssbo_size.off[index];
635 sizes[off] = sb->sb[index].buffer_size;
636 }
637
638 fd_wfi(ctx->batch, ring);
639 ctx->emit_const(ring, v->type, offset * 4,
640 0, ARRAY_SIZE(sizes), sizes, NULL);
641 }
642 }
643
644 static void
645 emit_image_dims(struct fd_context *ctx, const struct ir3_shader_variant *v,
646 struct fd_ringbuffer *ring, struct fd_shaderimg_stateobj *si)
647 {
648 uint32_t offset = v->constbase.image_dims;
649 if (v->constlen > offset) {
650 uint32_t dims[align(v->const_layout.image_dims.count, 4)];
651 unsigned mask = v->const_layout.image_dims.mask;
652
653 while (mask) {
654 struct pipe_image_view *img;
655 struct fd_resource *rsc;
656 unsigned index = u_bit_scan(&mask);
657 unsigned off = v->const_layout.image_dims.off[index];
658
659 img = &si->si[index];
660 rsc = fd_resource(img->resource);
661
662 dims[off + 0] = util_format_get_blocksize(img->format);
663 if (img->resource->target != PIPE_BUFFER) {
664 unsigned lvl = img->u.tex.level;
665 /* note for 2d/cube/etc images, even if re-interpreted
666 * as a different color format, the pixel size should
667 * be the same, so use original dimensions for y and z
668 * stride:
669 */
670 dims[off + 1] = rsc->slices[lvl].pitch * rsc->cpp;
671 /* see corresponding logic in fd_resource_offset(): */
672 if (rsc->layer_first) {
673 dims[off + 2] = rsc->layer_size;
674 } else {
675 dims[off + 2] = rsc->slices[lvl].size0;
676 }
677 }
678 }
679
680 fd_wfi(ctx->batch, ring);
681 ctx->emit_const(ring, v->type, offset * 4,
682 0, ARRAY_SIZE(dims), dims, NULL);
683 }
684 }
685
686 static void
687 emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v,
688 struct fd_ringbuffer *ring)
689 {
690 int size = v->immediates_count;
691 uint32_t base = v->constbase.immediate;
692
693 /* truncate size to avoid writing constants that shader
694 * does not use:
695 */
696 size = MIN2(size + base, v->constlen) - base;
697
698 /* convert out of vec4: */
699 base *= 4;
700 size *= 4;
701
702 if (size > 0) {
703 fd_wfi(ctx->batch, ring);
704 ctx->emit_const(ring, v->type, base,
705 0, size, v->immediates[0].val, NULL);
706 }
707 }
708
709 /* emit stream-out buffers: */
710 static void
711 emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
712 struct fd_ringbuffer *ring)
713 {
714 /* streamout addresses after driver-params: */
715 uint32_t offset = v->constbase.tfbo;
716 if (v->constlen > offset) {
717 struct fd_streamout_stateobj *so = &ctx->streamout;
718 struct pipe_stream_output_info *info = &v->shader->stream_output;
719 uint32_t params = 4;
720 uint32_t offsets[params];
721 struct pipe_resource *prscs[params];
722
723 for (uint32_t i = 0; i < params; i++) {
724 struct pipe_stream_output_target *target = so->targets[i];
725
726 if (target) {
727 offsets[i] = (so->offsets[i] * info->stride[i] * 4) +
728 target->buffer_offset;
729 prscs[i] = target->buffer;
730 } else {
731 offsets[i] = 0;
732 prscs[i] = NULL;
733 }
734 }
735
736 fd_wfi(ctx->batch, ring);
737 ctx->emit_const_bo(ring, v->type, true, offset * 4, params, prscs, offsets);
738 }
739 }
740
741 static uint32_t
742 max_tf_vtx(struct fd_context *ctx, const struct ir3_shader_variant *v)
743 {
744 struct fd_streamout_stateobj *so = &ctx->streamout;
745 struct pipe_stream_output_info *info = &v->shader->stream_output;
746 uint32_t maxvtxcnt = 0x7fffffff;
747
748 if (ctx->screen->gpu_id >= 500)
749 return 0;
750 if (v->key.binning_pass)
751 return 0;
752 if (v->shader->stream_output.num_outputs == 0)
753 return 0;
754 if (so->num_targets == 0)
755 return 0;
756
757 /* offset to write to is:
758 *
759 * total_vtxcnt = vtxcnt + offsets[i]
760 * offset = total_vtxcnt * stride[i]
761 *
762 * offset = vtxcnt * stride[i] ; calculated in shader
763 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
764 *
765 * assuming for each vtx, each target buffer will have data written
766 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
767 *
768 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
769 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
770 *
771 * but shader is actually doing a less-than (rather than less-than-
772 * equal) check, so we can drop the -stride[i].
773 *
774 * TODO is assumption about `offset + stride[i]` legit?
775 */
776 for (unsigned i = 0; i < so->num_targets; i++) {
777 struct pipe_stream_output_target *target = so->targets[i];
778 unsigned stride = info->stride[i] * 4; /* convert dwords->bytes */
779 if (target) {
780 uint32_t max = target->buffer_size / stride;
781 maxvtxcnt = MIN2(maxvtxcnt, max);
782 }
783 }
784
785 return maxvtxcnt;
786 }
787
788 static void
789 emit_common_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
790 struct fd_context *ctx, enum pipe_shader_type t)
791 {
792 enum fd_dirty_shader_state dirty = ctx->dirty_shader[t];
793
794 if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST)) {
795 struct fd_constbuf_stateobj *constbuf;
796 bool shader_dirty;
797
798 constbuf = &ctx->constbuf[t];
799 shader_dirty = !!(dirty & FD_DIRTY_SHADER_PROG);
800
801 emit_user_consts(ctx, v, ring, constbuf);
802 emit_ubos(ctx, v, ring, constbuf);
803 if (shader_dirty)
804 emit_immediates(ctx, v, ring);
805 }
806
807 if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_SSBO)) {
808 struct fd_shaderbuf_stateobj *sb = &ctx->shaderbuf[t];
809 emit_ssbo_sizes(ctx, v, ring, sb);
810 }
811
812 if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_IMAGE)) {
813 struct fd_shaderimg_stateobj *si = &ctx->shaderimg[t];
814 emit_image_dims(ctx, v, ring, si);
815 }
816 }
817
818 void
819 ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
820 struct fd_context *ctx, const struct pipe_draw_info *info)
821 {
822 debug_assert(v->type == SHADER_VERTEX);
823
824 emit_common_consts(v, ring, ctx, PIPE_SHADER_VERTEX);
825
826 /* emit driver params every time: */
827 /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
828 if (info) {
829 uint32_t offset = v->constbase.driver_param;
830 if (v->constlen > offset) {
831 uint32_t vertex_params[IR3_DP_VS_COUNT] = {
832 [IR3_DP_VTXID_BASE] = info->index_size ?
833 info->index_bias : info->start,
834 [IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
835 };
836 /* if no user-clip-planes, we don't need to emit the
837 * entire thing:
838 */
839 uint32_t vertex_params_size = 4;
840
841 if (v->key.ucp_enables) {
842 struct pipe_clip_state *ucp = &ctx->ucp;
843 unsigned pos = IR3_DP_UCP0_X;
844 for (unsigned i = 0; pos <= IR3_DP_UCP7_W; i++) {
845 for (unsigned j = 0; j < 4; j++) {
846 vertex_params[pos] = fui(ucp->ucp[i][j]);
847 pos++;
848 }
849 }
850 vertex_params_size = ARRAY_SIZE(vertex_params);
851 }
852
853 fd_wfi(ctx->batch, ring);
854
855 bool needs_vtxid_base =
856 ir3_find_sysval_regid(v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) != regid(63, 0);
857
858 /* for indirect draw, we need to copy VTXID_BASE from
859 * indirect-draw parameters buffer.. which is annoying
860 * and means we can't easily emit these consts in cmd
861 * stream so need to copy them to bo.
862 */
863 if (info->indirect && needs_vtxid_base) {
864 struct pipe_draw_indirect_info *indirect = info->indirect;
865 struct pipe_resource *vertex_params_rsc =
866 pipe_buffer_create(&ctx->screen->base,
867 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM,
868 vertex_params_size * 4);
869 unsigned src_off = info->indirect->offset;;
870 void *ptr;
871
872 ptr = fd_bo_map(fd_resource(vertex_params_rsc)->bo);
873 memcpy(ptr, vertex_params, vertex_params_size * 4);
874
875 if (info->index_size) {
876 /* indexed draw, index_bias is 4th field: */
877 src_off += 3 * 4;
878 } else {
879 /* non-indexed draw, start is 3rd field: */
880 src_off += 2 * 4;
881 }
882
883 /* copy index_bias or start from draw params: */
884 ctx->mem_to_mem(ring, vertex_params_rsc, 0,
885 indirect->buffer, src_off, 1);
886
887 ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
888 vertex_params_size, NULL, vertex_params_rsc);
889
890 pipe_resource_reference(&vertex_params_rsc, NULL);
891 } else {
892 ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
893 vertex_params_size, vertex_params, NULL);
894 }
895
896 /* if needed, emit stream-out buffer addresses: */
897 if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
898 emit_tfbos(ctx, v, ring);
899 }
900 }
901 }
902 }
903
904 void
905 ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
906 struct fd_context *ctx)
907 {
908 debug_assert(v->type == SHADER_FRAGMENT);
909
910 emit_common_consts(v, ring, ctx, PIPE_SHADER_FRAGMENT);
911 }
912
913 /* emit compute-shader consts: */
914 void
915 ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
916 struct fd_context *ctx, const struct pipe_grid_info *info)
917 {
918 debug_assert(v->type == SHADER_COMPUTE);
919
920 emit_common_consts(v, ring, ctx, PIPE_SHADER_COMPUTE);
921
922 /* emit compute-shader driver-params: */
923 uint32_t offset = v->constbase.driver_param;
924 if (v->constlen > offset) {
925 fd_wfi(ctx->batch, ring);
926
927 if (info->indirect) {
928 struct pipe_resource *indirect = NULL;
929 unsigned indirect_offset;
930
931 /* This is a bit awkward, but CP_LOAD_STATE.EXT_SRC_ADDR needs
932 * to be aligned more strongly than 4 bytes. So in this case
933 * we need a temporary buffer to copy NumWorkGroups.xyz to.
934 *
935 * TODO if previous compute job is writing to info->indirect,
936 * we might need a WFI.. but since we currently flush for each
937 * compute job, we are probably ok for now.
938 */
939 if (info->indirect_offset & 0xf) {
940 indirect = pipe_buffer_create(&ctx->screen->base,
941 PIPE_BIND_COMMAND_ARGS_BUFFER, PIPE_USAGE_STREAM,
942 0x1000);
943 indirect_offset = 0;
944
945 ctx->mem_to_mem(ring, indirect, 0, info->indirect,
946 info->indirect_offset, 3);
947 } else {
948 pipe_resource_reference(&indirect, info->indirect);
949 indirect_offset = info->indirect_offset;
950 }
951
952 ctx->emit_const(ring, SHADER_COMPUTE, offset * 4,
953 indirect_offset, 4, NULL, indirect);
954
955 pipe_resource_reference(&indirect, NULL);
956 } else {
957 uint32_t compute_params[IR3_DP_CS_COUNT] = {
958 [IR3_DP_NUM_WORK_GROUPS_X] = info->grid[0],
959 [IR3_DP_NUM_WORK_GROUPS_Y] = info->grid[1],
960 [IR3_DP_NUM_WORK_GROUPS_Z] = info->grid[2],
961 [IR3_DP_LOCAL_GROUP_SIZE_X] = info->block[0],
962 [IR3_DP_LOCAL_GROUP_SIZE_Y] = info->block[1],
963 [IR3_DP_LOCAL_GROUP_SIZE_Z] = info->block[2],
964 };
965
966 ctx->emit_const(ring, SHADER_COMPUTE, offset * 4, 0,
967 ARRAY_SIZE(compute_params), compute_params, NULL);
968 }
969 }
970 }