src/gallium/drivers/freedreno/ir3/ir3_shader.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34 #include "tgsi/tgsi_dump.h"
  35 #include "tgsi/tgsi_parse.h"
  36
  37 #include "freedreno_context.h"
  38 #include "freedreno_util.h"
  39
  40 #include "ir3_shader.h"
  41 #include "ir3_compiler.h"
  42 #include "ir3_nir.h"
  43
  44 static void
  45 delete_variant(struct ir3_shader_variant *v)
  46 {
  47         if (v->ir)
  48                 ir3_destroy(v->ir);
  49         if (v->bo)
  50                 fd_bo_del(v->bo);
  51         free(v);
  52 }
  53
  54 /* for vertex shader, the inputs are loaded into registers before the shader
  55  * is executed, so max_regs from the shader instructions might not properly
  56  * reflect the # of registers actually used, especially in case passthrough
  57  * varyings.
  58  *
  59  * Likewise, for fragment shader, we can have some regs which are passed
  60  * input values but never touched by the resulting shader (ie. as result
  61  * of dead code elimination or simply because we don't know how to turn
  62  * the reg off.
  63  */
  64 static void
  65 fixup_regfootprint(struct ir3_shader_variant *v)
  66 {
  67         if (v->type == SHADER_VERTEX) {
  68                 unsigned i;
  69                 for (i = 0; i < v->inputs_count; i++) {
  70                         /* skip frag inputs fetch via bary.f since their reg's are
  71                          * not written by gpu before shader starts (and in fact the
  72                          * regid's might not even be valid)
  73                          */
  74                         if (v->inputs[i].bary)
  75                                 continue;
  76
  77                         if (v->inputs[i].compmask) {
  78                                 int32_t regid = (v->inputs[i].regid + 3) >> 2;
  79                                 v->info.max_reg = MAX2(v->info.max_reg, regid);
  80                         }
  81                 }
  82                 for (i = 0; i < v->outputs_count; i++) {
  83                         int32_t regid = (v->outputs[i].regid + 3) >> 2;
  84                         v->info.max_reg = MAX2(v->info.max_reg, regid);
  85                 }
  86         } else if (v->type == SHADER_FRAGMENT) {
  87                 /* NOTE: not sure how to turn pos_regid off..  but this could
  88                  * be, for example, r1.x while max reg used by the shader is
  89                  * r0.*, in which case we need to fixup the reg footprint:
  90                  */
  91                 v->info.max_reg = MAX2(v->info.max_reg, v->pos_regid >> 2);
  92                 if (v->frag_coord)
  93                         debug_assert(v->info.max_reg >= 0); /* hard coded r0.x */
  94                 if (v->frag_face)
  95                         debug_assert(v->info.max_half_reg >= 0); /* hr0.x */
  96         }
  97 }
  98
  99 /* wrapper for ir3_assemble() which does some info fixup based on
 100  * shader state.  Non-static since used by ir3_cmdline too.
 101  */
 102 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 103 {
 104         void *bin;
 105
 106         bin = ir3_assemble(v->ir, &v->info, gpu_id);
 107         if (!bin)
 108                 return NULL;
 109
 110         if (gpu_id >= 400) {
 111                 v->instrlen = v->info.sizedwords / (2 * 16);
 112         } else {
 113                 v->instrlen = v->info.sizedwords / (2 * 4);
 114         }
 115
 116         /* NOTE: if relative addressing is used, we set constlen in
 117          * the compiler (to worst-case value) since we don't know in
 118          * the assembler what the max addr reg value can be:
 119          */
 120         v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
 121
 122         fixup_regfootprint(v);
 123
 124         return bin;
 125 }
 126
 127 static void
 128 assemble_variant(struct ir3_shader_variant *v)
 129 {
 130         struct ir3_compiler *compiler = v->shader->compiler;
 131         uint32_t gpu_id = compiler->gpu_id;
 132         uint32_t sz, *bin;
 133
 134         bin = ir3_shader_assemble(v, gpu_id);
 135         sz = v->info.sizedwords * 4;
 136
 137         v->bo = fd_bo_new(compiler->dev, sz,
 138                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 139                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 140
 141         memcpy(fd_bo_map(v->bo), bin, sz);
 142
 143         if (fd_mesa_debug & FD_DBG_DISASM) {
 144                 struct ir3_shader_key key = v->key;
 145                 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
 146                         key.binning_pass, key.color_two_side, key.half_precision);
 147                 ir3_shader_disasm(v, bin);
 148         }
 149
 150         free(bin);
 151
 152         /* no need to keep the ir around beyond this point: */
 153         ir3_destroy(v->ir);
 154         v->ir = NULL;
 155 }
 156
 157 static void
 158 dump_shader_info(struct ir3_shader_variant *v, struct pipe_debug_callback *debug)
 159 {
 160         if (!unlikely(fd_mesa_debug & FD_DBG_SHADERDB))
 161                 return;
 162
 163         pipe_debug_message(debug, SHADER_INFO, "\n"
 164                         "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n"
 165                         "SHADER-DB: %s prog %d/%d: %u half, %u full\n"
 166                         "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n",
 167                         ir3_shader_stage(v->shader),
 168                         v->shader->id, v->id,
 169                         v->info.instrs_count,
 170                         v->info.sizedwords,
 171                         ir3_shader_stage(v->shader),
 172                         v->shader->id, v->id,
 173                         v->info.max_half_reg + 1,
 174                         v->info.max_reg + 1,
 175                         ir3_shader_stage(v->shader),
 176                         v->shader->id, v->id,
 177                         v->info.max_const + 1,
 178                         v->constlen);
 179 }
 180
 181 static struct ir3_shader_variant *
 182 create_variant(struct ir3_shader *shader, struct ir3_shader_key key)
 183 {
 184         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 185         int ret;
 186
 187         if (!v)
 188                 return NULL;
 189
 190         v->id = ++shader->variant_count;
 191         v->shader = shader;
 192         v->key = key;
 193         v->type = shader->type;
 194
 195         ret = ir3_compile_shader_nir(shader->compiler, v);
 196         if (ret) {
 197                 debug_error("compile failed!");
 198                 goto fail;
 199         }
 200
 201         assemble_variant(v);
 202         if (!v->bo) {
 203                 debug_error("assemble failed!");
 204                 goto fail;
 205         }
 206
 207         return v;
 208
 209 fail:
 210         delete_variant(v);
 211         return NULL;
 212 }
 213
 214 struct ir3_shader_variant *
 215 ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key,
 216                 struct pipe_debug_callback *debug)
 217 {
 218         struct ir3_shader_variant *v;
 219
 220         /* some shader key values only apply to vertex or frag shader,
 221          * so normalize the key to avoid constructing multiple identical
 222          * variants:
 223          */
 224         switch (shader->type) {
 225         case SHADER_FRAGMENT:
 226                 key.binning_pass = false;
 227                 if (key.has_per_samp) {
 228                         key.vsaturate_s = 0;
 229                         key.vsaturate_t = 0;
 230                         key.vsaturate_r = 0;
 231                         key.vastc_srgb = 0;
 232                 }
 233                 break;
 234         case SHADER_VERTEX:
 235                 key.color_two_side = false;
 236                 key.half_precision = false;
 237                 key.rasterflat = false;
 238                 if (key.has_per_samp) {
 239                         key.fsaturate_s = 0;
 240                         key.fsaturate_t = 0;
 241                         key.fsaturate_r = 0;
 242                         key.fastc_srgb = 0;
 243                 }
 244                 break;
 245         default:
 246                 /* TODO */
 247                 break;
 248         }
 249
 250         for (v = shader->variants; v; v = v->next)
 251                 if (ir3_shader_key_equal(&key, &v->key))
 252                         return v;
 253
 254         /* compile new variant if it doesn't exist already: */
 255         v = create_variant(shader, key);
 256         if (v) {
 257                 v->next = shader->variants;
 258                 shader->variants = v;
 259                 dump_shader_info(v, debug);
 260         }
 261
 262         return v;
 263 }
 264
 265
 266 void
 267 ir3_shader_destroy(struct ir3_shader *shader)
 268 {
 269         struct ir3_shader_variant *v, *t;
 270         for (v = shader->variants; v; ) {
 271                 t = v;
 272                 v = v->next;
 273                 delete_variant(t);
 274         }
 275         ralloc_free(shader->nir);
 276         free(shader);
 277 }
 278
 279 struct ir3_shader *
 280 ir3_shader_create(struct ir3_compiler *compiler,
 281                 const struct pipe_shader_state *cso, enum shader_t type,
 282                 struct pipe_debug_callback *debug)
 283 {
 284         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 285         shader->compiler = compiler;
 286         shader->id = ++shader->compiler->shader_count;
 287         shader->type = type;
 288
 289         nir_shader *nir;
 290         if (cso->type == PIPE_SHADER_IR_NIR) {
 291                 /* we take ownership of the reference: */
 292                 nir = cso->ir.nir;
 293         } else {
 294                 debug_assert(cso->type == PIPE_SHADER_IR_TGSI);
 295                 if (fd_mesa_debug & FD_DBG_DISASM) {
 296                         DBG("dump tgsi: type=%d", shader->type);
 297                         tgsi_dump(cso->tokens, 0);
 298                 }
 299                 nir = ir3_tgsi_to_nir(cso->tokens);
 300         }
 301         /* do first pass optimization, ignoring the key: */
 302         shader->nir = ir3_optimize_nir(shader, nir, NULL);
 303         if (fd_mesa_debug & FD_DBG_DISASM) {
 304                 DBG("dump nir%d: type=%d", shader->id, shader->type);
 305                 nir_print_shader(shader->nir, stdout);
 306         }
 307
 308         shader->stream_output = cso->stream_output;
 309         if (fd_mesa_debug & FD_DBG_SHADERDB) {
 310                 /* if shader-db run, create a standard variant immediately
 311                  * (as otherwise nothing will trigger the shader to be
 312                  * actually compiled)
 313                  */
 314                 static struct ir3_shader_key key;
 315                 memset(&key, 0, sizeof(key));
 316                 ir3_shader_variant(shader, key, debug);
 317         }
 318         return shader;
 319 }
 320
 321 /* a bit annoying that compute-shader and normal shader state objects
 322  * aren't a bit more aligned.
 323  */
 324 struct ir3_shader *
 325 ir3_shader_create_compute(struct ir3_compiler *compiler,
 326                 const struct pipe_compute_state *cso,
 327                 struct pipe_debug_callback *debug)
 328 {
 329         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 330
 331         shader->compiler = compiler;
 332         shader->id = ++shader->compiler->shader_count;
 333         shader->type = SHADER_COMPUTE;
 334
 335         nir_shader *nir;
 336         if (cso->ir_type == PIPE_SHADER_IR_NIR) {
 337                 /* we take ownership of the reference: */
 338                 nir = (nir_shader *)cso->prog;
 339         } else {
 340                 debug_assert(cso->ir_type == PIPE_SHADER_IR_TGSI);
 341                 if (fd_mesa_debug & FD_DBG_DISASM) {
 342                         DBG("dump tgsi: type=%d", shader->type);
 343                         tgsi_dump(cso->prog, 0);
 344                 }
 345                 nir = ir3_tgsi_to_nir(cso->prog);
 346         }
 347
 348         /* do first pass optimization, ignoring the key: */
 349         shader->nir = ir3_optimize_nir(shader, nir, NULL);
 350         if (fd_mesa_debug & FD_DBG_DISASM) {
 351                 DBG("dump nir%d: type=%d", shader->id, shader->type);
 352                 nir_print_shader(shader->nir, stdout);
 353         }
 354
 355         return shader;
 356 }
 357
 358 static void dump_reg(const char *name, uint32_t r)
 359 {
 360         if (r != regid(63,0))
 361                 debug_printf("; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
 362 }
 363
 364 static void dump_output(struct ir3_shader_variant *so,
 365                 unsigned slot, const char *name)
 366 {
 367         uint32_t regid;
 368         regid = ir3_find_output_regid(so, slot);
 369         dump_reg(name, regid);
 370 }
 371
 372 void
 373 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
 374 {
 375         struct ir3 *ir = so->ir;
 376         struct ir3_register *reg;
 377         const char *type = ir3_shader_stage(so->shader);
 378         uint8_t regid;
 379         unsigned i;
 380
 381         for (i = 0; i < ir->ninputs; i++) {
 382                 if (!ir->inputs[i]) {
 383                         debug_printf("; in%d unused\n", i);
 384                         continue;
 385                 }
 386                 reg = ir->inputs[i]->regs[0];
 387                 regid = reg->num;
 388                 debug_printf("@in(%sr%d.%c)\tin%d\n",
 389                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 390                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 391         }
 392
 393         for (i = 0; i < ir->noutputs; i++) {
 394                 if (!ir->outputs[i]) {
 395                         debug_printf("; out%d unused\n", i);
 396                         continue;
 397                 }
 398                 /* kill shows up as a virtual output.. skip it! */
 399                 if (is_kill(ir->outputs[i]))
 400                         continue;
 401                 reg = ir->outputs[i]->regs[0];
 402                 regid = reg->num;
 403                 debug_printf("@out(%sr%d.%c)\tout%d\n",
 404                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 405                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 406         }
 407
 408         for (i = 0; i < so->immediates_count; i++) {
 409                 debug_printf("@const(c%d.x)\t", so->constbase.immediate + i);
 410                 debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 411                                 so->immediates[i].val[0],
 412                                 so->immediates[i].val[1],
 413                                 so->immediates[i].val[2],
 414                                 so->immediates[i].val[3]);
 415         }
 416
 417         disasm_a3xx(bin, so->info.sizedwords, 0, so->type);
 418
 419         switch (so->type) {
 420         case SHADER_VERTEX:
 421                 debug_printf("; %s: outputs:", type);
 422                 for (i = 0; i < so->outputs_count; i++) {
 423                         uint8_t regid = so->outputs[i].regid;
 424                         debug_printf(" r%d.%c (%s)",
 425                                         (regid >> 2), "xyzw"[regid & 0x3],
 426                                         gl_varying_slot_name(so->outputs[i].slot));
 427                 }
 428                 debug_printf("\n");
 429                 debug_printf("; %s: inputs:", type);
 430                 for (i = 0; i < so->inputs_count; i++) {
 431                         uint8_t regid = so->inputs[i].regid;
 432                         debug_printf(" r%d.%c (cm=%x,il=%u,b=%u)",
 433                                         (regid >> 2), "xyzw"[regid & 0x3],
 434                                         so->inputs[i].compmask,
 435                                         so->inputs[i].inloc,
 436                                         so->inputs[i].bary);
 437                 }
 438                 debug_printf("\n");
 439                 break;
 440         case SHADER_FRAGMENT:
 441                 debug_printf("; %s: outputs:", type);
 442                 for (i = 0; i < so->outputs_count; i++) {
 443                         uint8_t regid = so->outputs[i].regid;
 444                         debug_printf(" r%d.%c (%s)",
 445                                         (regid >> 2), "xyzw"[regid & 0x3],
 446                                         gl_frag_result_name(so->outputs[i].slot));
 447                 }
 448                 debug_printf("\n");
 449                 debug_printf("; %s: inputs:", type);
 450                 for (i = 0; i < so->inputs_count; i++) {
 451                         uint8_t regid = so->inputs[i].regid;
 452                         debug_printf(" r%d.%c (%s,cm=%x,il=%u,b=%u)",
 453                                         (regid >> 2), "xyzw"[regid & 0x3],
 454                                         gl_varying_slot_name(so->inputs[i].slot),
 455                                         so->inputs[i].compmask,
 456                                         so->inputs[i].inloc,
 457                                         so->inputs[i].bary);
 458                 }
 459                 debug_printf("\n");
 460                 break;
 461         default:
 462                 /* TODO */
 463                 break;
 464         }
 465
 466         /* print generic shader info: */
 467         debug_printf("; %s prog %d/%d: %u instructions, %d half, %d full\n",
 468                         type, so->shader->id, so->id,
 469                         so->info.instrs_count,
 470                         so->info.max_half_reg + 1,
 471                         so->info.max_reg + 1);
 472
 473         debug_printf("; %d const, %u constlen\n",
 474                         so->info.max_const + 1,
 475                         so->constlen);
 476
 477         /* print shader type specific info: */
 478         switch (so->type) {
 479         case SHADER_VERTEX:
 480                 dump_output(so, VARYING_SLOT_POS, "pos");
 481                 dump_output(so, VARYING_SLOT_PSIZ, "psize");
 482                 break;
 483         case SHADER_FRAGMENT:
 484                 dump_reg("pos (bary)", so->pos_regid);
 485                 dump_output(so, FRAG_RESULT_DEPTH, "posz");
 486                 if (so->color0_mrt) {
 487                         dump_output(so, FRAG_RESULT_COLOR, "color");
 488                 } else {
 489                         dump_output(so, FRAG_RESULT_DATA0, "data0");
 490                         dump_output(so, FRAG_RESULT_DATA1, "data1");
 491                         dump_output(so, FRAG_RESULT_DATA2, "data2");
 492                         dump_output(so, FRAG_RESULT_DATA3, "data3");
 493                         dump_output(so, FRAG_RESULT_DATA4, "data4");
 494                         dump_output(so, FRAG_RESULT_DATA5, "data5");
 495                         dump_output(so, FRAG_RESULT_DATA6, "data6");
 496                         dump_output(so, FRAG_RESULT_DATA7, "data7");
 497                 }
 498                 /* these two are hard-coded since we don't know how to
 499                  * program them to anything but all 0's...
 500                  */
 501                 if (so->frag_coord)
 502                         debug_printf("; fragcoord: r0.x\n");
 503                 if (so->frag_face)
 504                         debug_printf("; fragface: hr0.x\n");
 505                 break;
 506         default:
 507                 /* TODO */
 508                 break;
 509         }
 510
 511         debug_printf("\n");
 512 }
 513
 514 uint64_t
 515 ir3_shader_outputs(const struct ir3_shader *so)
 516 {
 517         return so->nir->info.outputs_written;
 518 }
 519
 520 /* This has to reach into the fd_context a bit more than the rest of
 521  * ir3, but it needs to be aligned with the compiler, so both agree
 522  * on which const regs hold what.  And the logic is identical between
 523  * a3xx/a4xx, the only difference is small details in the actual
 524  * CP_LOAD_STATE packets (which is handled inside the generation
 525  * specific ctx->emit_const(_bo)() fxns)
 526  */
 527
 528 #include "freedreno_resource.h"
 529
 530 static void
 531 emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
 532                 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 533 {
 534         const unsigned index = 0;     /* user consts are index 0 */
 535         /* TODO save/restore dirty_mask for binning pass instead: */
 536         uint32_t dirty_mask = constbuf->enabled_mask;
 537
 538         if (dirty_mask & (1 << index)) {
 539                 struct pipe_constant_buffer *cb = &constbuf->cb[index];
 540                 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
 541
 542                 /* in particular, with binning shader we may end up with
 543                  * unused consts, ie. we could end up w/ constlen that is
 544                  * smaller than first_driver_param.  In that case truncate
 545                  * the user consts early to avoid HLSQ lockup caused by
 546                  * writing too many consts
 547                  */
 548                 uint32_t max_const = MIN2(v->num_uniforms, v->constlen);
 549
 550                 // I expect that size should be a multiple of vec4's:
 551                 assert(size == align(size, 4));
 552
 553                 /* and even if the start of the const buffer is before
 554                  * first_immediate, the end may not be:
 555                  */
 556                 size = MIN2(size, 4 * max_const);
 557
 558                 if (size > 0) {
 559                         fd_wfi(ctx->batch, ring);
 560                         ctx->emit_const(ring, v->type, 0,
 561                                         cb->buffer_offset, size,
 562                                         cb->user_buffer, cb->buffer);
 563                         constbuf->dirty_mask &= ~(1 << index);
 564                 }
 565         }
 566 }
 567
 568 static void
 569 emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
 570                 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 571 {
 572         uint32_t offset = v->constbase.ubo;
 573         if (v->constlen > offset) {
 574                 uint32_t params = v->num_ubos;
 575                 uint32_t offsets[params];
 576                 struct pipe_resource *prscs[params];
 577
 578                 for (uint32_t i = 0; i < params; i++) {
 579                         const uint32_t index = i + 1;   /* UBOs start at index 1 */
 580                         struct pipe_constant_buffer *cb = &constbuf->cb[index];
 581                         assert(!cb->user_buffer);
 582
 583                         if ((constbuf->enabled_mask & (1 << index)) && cb->buffer) {
 584                                 offsets[i] = cb->buffer_offset;
 585                                 prscs[i] = cb->buffer;
 586                         } else {
 587                                 offsets[i] = 0;
 588                                 prscs[i] = NULL;
 589                         }
 590                 }
 591
 592                 fd_wfi(ctx->batch, ring);
 593                 ctx->emit_const_bo(ring, v->type, false, offset * 4, params, prscs, offsets);
 594         }
 595 }
 596
 597 static void
 598 emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v,
 599                 struct fd_ringbuffer *ring)
 600 {
 601         int size = v->immediates_count;
 602         uint32_t base = v->constbase.immediate;
 603
 604         /* truncate size to avoid writing constants that shader
 605          * does not use:
 606          */
 607         size = MIN2(size + base, v->constlen) - base;
 608
 609         /* convert out of vec4: */
 610         base *= 4;
 611         size *= 4;
 612
 613         if (size > 0) {
 614                 fd_wfi(ctx->batch, ring);
 615                 ctx->emit_const(ring, v->type, base,
 616                         0, size, v->immediates[0].val, NULL);
 617         }
 618 }
 619
 620 /* emit stream-out buffers: */
 621 static void
 622 emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
 623                 struct fd_ringbuffer *ring)
 624 {
 625         /* streamout addresses after driver-params: */
 626         uint32_t offset = v->constbase.tfbo;
 627         if (v->constlen > offset) {
 628                 struct fd_streamout_stateobj *so = &ctx->streamout;
 629                 struct pipe_stream_output_info *info = &v->shader->stream_output;
 630                 uint32_t params = 4;
 631                 uint32_t offsets[params];
 632                 struct pipe_resource *prscs[params];
 633
 634                 for (uint32_t i = 0; i < params; i++) {
 635                         struct pipe_stream_output_target *target = so->targets[i];
 636
 637                         if (target) {
 638                                 offsets[i] = (so->offsets[i] * info->stride[i] * 4) +
 639                                                 target->buffer_offset;
 640                                 prscs[i] = target->buffer;
 641                         } else {
 642                                 offsets[i] = 0;
 643                                 prscs[i] = NULL;
 644                         }
 645                 }
 646
 647                 fd_wfi(ctx->batch, ring);
 648                 ctx->emit_const_bo(ring, v->type, true, offset * 4, params, prscs, offsets);
 649         }
 650 }
 651
 652 static uint32_t
 653 max_tf_vtx(struct fd_context *ctx, const struct ir3_shader_variant *v)
 654 {
 655         struct fd_streamout_stateobj *so = &ctx->streamout;
 656         struct pipe_stream_output_info *info = &v->shader->stream_output;
 657         uint32_t maxvtxcnt = 0x7fffffff;
 658
 659         if (ctx->screen->gpu_id >= 500)
 660                 return 0;
 661         if (v->key.binning_pass)
 662                 return 0;
 663         if (v->shader->stream_output.num_outputs == 0)
 664                 return 0;
 665         if (so->num_targets == 0)
 666                 return 0;
 667
 668         /* offset to write to is:
 669          *
 670          *   total_vtxcnt = vtxcnt + offsets[i]
 671          *   offset = total_vtxcnt * stride[i]
 672          *
 673          *   offset =   vtxcnt * stride[i]       ; calculated in shader
 674          *            + offsets[i] * stride[i]   ; calculated at emit_tfbos()
 675          *
 676          * assuming for each vtx, each target buffer will have data written
 677          * up to 'offset + stride[i]', that leaves maxvtxcnt as:
 678          *
 679          *   buffer_size = (maxvtxcnt * stride[i]) + stride[i]
 680          *   maxvtxcnt   = (buffer_size - stride[i]) / stride[i]
 681          *
 682          * but shader is actually doing a less-than (rather than less-than-
 683          * equal) check, so we can drop the -stride[i].
 684          *
 685          * TODO is assumption about `offset + stride[i]` legit?
 686          */
 687         for (unsigned i = 0; i < so->num_targets; i++) {
 688                 struct pipe_stream_output_target *target = so->targets[i];
 689                 unsigned stride = info->stride[i] * 4;   /* convert dwords->bytes */
 690                 if (target) {
 691                         uint32_t max = target->buffer_size / stride;
 692                         maxvtxcnt = MIN2(maxvtxcnt, max);
 693                 }
 694         }
 695
 696         return maxvtxcnt;
 697 }
 698
 699 void
 700 ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 701                 struct fd_context *ctx, const struct pipe_draw_info *info)
 702 {
 703         enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_VERTEX];
 704
 705         debug_assert(v->type == SHADER_VERTEX);
 706
 707         if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST)) {
 708                 struct fd_constbuf_stateobj *constbuf;
 709                 bool shader_dirty;
 710
 711                 constbuf = &ctx->constbuf[PIPE_SHADER_VERTEX];
 712                 shader_dirty = !!(dirty & FD_DIRTY_SHADER_PROG);
 713
 714                 emit_user_consts(ctx, v, ring, constbuf);
 715                 emit_ubos(ctx, v, ring, constbuf);
 716                 if (shader_dirty)
 717                         emit_immediates(ctx, v, ring);
 718         }
 719
 720         /* emit driver params every time: */
 721         /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
 722         if (info) {
 723                 uint32_t offset = v->constbase.driver_param;
 724                 if (v->constlen > offset) {
 725                         uint32_t vertex_params[IR3_DP_VS_COUNT] = {
 726                                 [IR3_DP_VTXID_BASE] = info->indexed ?
 727                                                 info->index_bias : info->start,
 728                                 [IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
 729                         };
 730                         /* if no user-clip-planes, we don't need to emit the
 731                          * entire thing:
 732                          */
 733                         uint32_t vertex_params_size = 4;
 734
 735                         if (v->key.ucp_enables) {
 736                                 struct pipe_clip_state *ucp = &ctx->ucp;
 737                                 unsigned pos = IR3_DP_UCP0_X;
 738                                 for (unsigned i = 0; pos <= IR3_DP_UCP7_W; i++) {
 739                                         for (unsigned j = 0; j < 4; j++) {
 740                                                 vertex_params[pos] = fui(ucp->ucp[i][j]);
 741                                                 pos++;
 742                                         }
 743                                 }
 744                                 vertex_params_size = ARRAY_SIZE(vertex_params);
 745                         }
 746
 747                         fd_wfi(ctx->batch, ring);
 748                         ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
 749                                         vertex_params_size, vertex_params, NULL);
 750
 751                         /* if needed, emit stream-out buffer addresses: */
 752                         if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
 753                                 emit_tfbos(ctx, v, ring);
 754                         }
 755                 }
 756         }
 757 }
 758
 759 void
 760 ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 761                 struct fd_context *ctx)
 762 {
 763         enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_FRAGMENT];
 764
 765         debug_assert(v->type == SHADER_FRAGMENT);
 766
 767         if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST)) {
 768                 struct fd_constbuf_stateobj *constbuf;
 769                 bool shader_dirty;
 770
 771                 constbuf = &ctx->constbuf[PIPE_SHADER_FRAGMENT];
 772                 shader_dirty = !!(dirty & FD_DIRTY_SHADER_PROG);
 773
 774                 emit_user_consts(ctx, v, ring, constbuf);
 775                 emit_ubos(ctx, v, ring, constbuf);
 776                 if (shader_dirty)
 777                         emit_immediates(ctx, v, ring);
 778         }
 779 }
 780
 781 /* emit compute-shader consts: */
 782 void
 783 ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 784                 struct fd_context *ctx, const struct pipe_grid_info *info)
 785 {
 786         enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
 787
 788         if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST)) {
 789                 struct fd_constbuf_stateobj *constbuf;
 790                 bool shader_dirty;
 791
 792                 constbuf = &ctx->constbuf[PIPE_SHADER_COMPUTE];
 793                 shader_dirty = !!(dirty & FD_DIRTY_SHADER_PROG);
 794
 795                 emit_user_consts(ctx, v, ring, constbuf);
 796                 emit_ubos(ctx, v, ring, constbuf);
 797                 if (shader_dirty)
 798                         emit_immediates(ctx, v, ring);
 799         }
 800
 801         /* emit compute-shader driver-params: */
 802         uint32_t offset = v->constbase.driver_param;
 803         if (v->constlen > offset) {
 804                 uint32_t compute_params[IR3_DP_CS_COUNT] = {
 805                         [IR3_DP_NUM_WORK_GROUPS_X] = info->grid[0],
 806                         [IR3_DP_NUM_WORK_GROUPS_Y] = info->grid[1],
 807                         [IR3_DP_NUM_WORK_GROUPS_Z] = info->grid[2],
 808                         /* do we need work-group-size? */
 809                 };
 810
 811                 fd_wfi(ctx->batch, ring);
 812                 ctx->emit_const(ring, SHADER_COMPUTE, offset * 4, 0,
 813                                 ARRAY_SIZE(compute_params), compute_params, NULL);
 814         }
 815 }