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[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_shader.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
36
37 #include "freedreno_context.h"
38 #include "freedreno_util.h"
39
40 #include "ir3_shader.h"
41 #include "ir3_compiler.h"
42 #include "ir3_nir.h"
43
44 int
45 ir3_glsl_type_size(const struct glsl_type *type)
46 {
47 return glsl_count_attribute_slots(type, false);
48 }
49
50 static void
51 delete_variant(struct ir3_shader_variant *v)
52 {
53 if (v->ir)
54 ir3_destroy(v->ir);
55 if (v->bo)
56 fd_bo_del(v->bo);
57 free(v);
58 }
59
60 /* for vertex shader, the inputs are loaded into registers before the shader
61 * is executed, so max_regs from the shader instructions might not properly
62 * reflect the # of registers actually used, especially in case passthrough
63 * varyings.
64 *
65 * Likewise, for fragment shader, we can have some regs which are passed
66 * input values but never touched by the resulting shader (ie. as result
67 * of dead code elimination or simply because we don't know how to turn
68 * the reg off.
69 */
70 static void
71 fixup_regfootprint(struct ir3_shader_variant *v)
72 {
73 unsigned i;
74
75 for (i = 0; i < v->inputs_count; i++) {
76 /* skip frag inputs fetch via bary.f since their reg's are
77 * not written by gpu before shader starts (and in fact the
78 * regid's might not even be valid)
79 */
80 if (v->inputs[i].bary)
81 continue;
82
83 /* ignore high regs that are global to all threads in a warp
84 * (they exist by default) (a5xx+)
85 */
86 if (v->inputs[i].regid >= regid(48,0))
87 continue;
88
89 if (v->inputs[i].compmask) {
90 unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
91 int32_t regid = (v->inputs[i].regid + n) >> 2;
92 v->info.max_reg = MAX2(v->info.max_reg, regid);
93 }
94 }
95
96 for (i = 0; i < v->outputs_count; i++) {
97 int32_t regid = (v->outputs[i].regid + 3) >> 2;
98 v->info.max_reg = MAX2(v->info.max_reg, regid);
99 }
100
101 if (v->type == SHADER_FRAGMENT) {
102 /* NOTE: not sure how to turn pos_regid off.. but this could
103 * be, for example, r1.x while max reg used by the shader is
104 * r0.*, in which case we need to fixup the reg footprint:
105 */
106 v->info.max_reg = MAX2(v->info.max_reg, v->pos_regid >> 2);
107 if (v->frag_coord)
108 debug_assert(v->info.max_reg >= 0); /* hard coded r0.x */
109 if (v->frag_face)
110 debug_assert(v->info.max_half_reg >= 0); /* hr0.x */
111 }
112 }
113
114 /* wrapper for ir3_assemble() which does some info fixup based on
115 * shader state. Non-static since used by ir3_cmdline too.
116 */
117 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
118 {
119 void *bin;
120
121 bin = ir3_assemble(v->ir, &v->info, gpu_id);
122 if (!bin)
123 return NULL;
124
125 if (gpu_id >= 400) {
126 v->instrlen = v->info.sizedwords / (2 * 16);
127 } else {
128 v->instrlen = v->info.sizedwords / (2 * 4);
129 }
130
131 /* NOTE: if relative addressing is used, we set constlen in
132 * the compiler (to worst-case value) since we don't know in
133 * the assembler what the max addr reg value can be:
134 */
135 v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
136
137 fixup_regfootprint(v);
138
139 return bin;
140 }
141
142 static void
143 assemble_variant(struct ir3_shader_variant *v)
144 {
145 struct ir3_compiler *compiler = v->shader->compiler;
146 uint32_t gpu_id = compiler->gpu_id;
147 uint32_t sz, *bin;
148
149 bin = ir3_shader_assemble(v, gpu_id);
150 sz = v->info.sizedwords * 4;
151
152 v->bo = fd_bo_new(compiler->dev, sz,
153 DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
154 DRM_FREEDRENO_GEM_TYPE_KMEM);
155
156 memcpy(fd_bo_map(v->bo), bin, sz);
157
158 if (fd_mesa_debug & FD_DBG_DISASM) {
159 struct ir3_shader_key key = v->key;
160 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
161 key.binning_pass, key.color_two_side, key.half_precision);
162 ir3_shader_disasm(v, bin);
163 }
164
165 free(bin);
166
167 /* no need to keep the ir around beyond this point: */
168 ir3_destroy(v->ir);
169 v->ir = NULL;
170 }
171
172 static void
173 dump_shader_info(struct ir3_shader_variant *v, struct pipe_debug_callback *debug)
174 {
175 if (!unlikely(fd_mesa_debug & FD_DBG_SHADERDB))
176 return;
177
178 pipe_debug_message(debug, SHADER_INFO, "\n"
179 "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n"
180 "SHADER-DB: %s prog %d/%d: %u half, %u full\n"
181 "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n"
182 "SHADER-DB: %s prog %d/%d: %u (ss), %u (sy)\n",
183 ir3_shader_stage(v->shader),
184 v->shader->id, v->id,
185 v->info.instrs_count,
186 v->info.sizedwords,
187 ir3_shader_stage(v->shader),
188 v->shader->id, v->id,
189 v->info.max_half_reg + 1,
190 v->info.max_reg + 1,
191 ir3_shader_stage(v->shader),
192 v->shader->id, v->id,
193 v->info.max_const + 1,
194 v->constlen,
195 ir3_shader_stage(v->shader),
196 v->shader->id, v->id,
197 v->info.ss, v->info.sy);
198 }
199
200 static struct ir3_shader_variant *
201 create_variant(struct ir3_shader *shader, struct ir3_shader_key key)
202 {
203 struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
204 int ret;
205
206 if (!v)
207 return NULL;
208
209 v->id = ++shader->variant_count;
210 v->shader = shader;
211 v->key = key;
212 v->type = shader->type;
213
214 ret = ir3_compile_shader_nir(shader->compiler, v);
215 if (ret) {
216 debug_error("compile failed!");
217 goto fail;
218 }
219
220 assemble_variant(v);
221 if (!v->bo) {
222 debug_error("assemble failed!");
223 goto fail;
224 }
225
226 return v;
227
228 fail:
229 delete_variant(v);
230 return NULL;
231 }
232
233 struct ir3_shader_variant *
234 ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key,
235 struct pipe_debug_callback *debug)
236 {
237 struct ir3_shader_variant *v;
238
239 /* some shader key values only apply to vertex or frag shader,
240 * so normalize the key to avoid constructing multiple identical
241 * variants:
242 */
243 switch (shader->type) {
244 case SHADER_FRAGMENT:
245 key.binning_pass = false;
246 if (key.has_per_samp) {
247 key.vsaturate_s = 0;
248 key.vsaturate_t = 0;
249 key.vsaturate_r = 0;
250 key.vastc_srgb = 0;
251 }
252 break;
253 case SHADER_VERTEX:
254 key.color_two_side = false;
255 key.half_precision = false;
256 key.rasterflat = false;
257 if (key.has_per_samp) {
258 key.fsaturate_s = 0;
259 key.fsaturate_t = 0;
260 key.fsaturate_r = 0;
261 key.fastc_srgb = 0;
262 }
263 break;
264 default:
265 /* TODO */
266 break;
267 }
268
269 for (v = shader->variants; v; v = v->next)
270 if (ir3_shader_key_equal(&key, &v->key))
271 return v;
272
273 /* compile new variant if it doesn't exist already: */
274 v = create_variant(shader, key);
275 if (v) {
276 v->next = shader->variants;
277 shader->variants = v;
278 dump_shader_info(v, debug);
279 }
280
281 return v;
282 }
283
284
285 void
286 ir3_shader_destroy(struct ir3_shader *shader)
287 {
288 struct ir3_shader_variant *v, *t;
289 for (v = shader->variants; v; ) {
290 t = v;
291 v = v->next;
292 delete_variant(t);
293 }
294 ralloc_free(shader->nir);
295 free(shader);
296 }
297
298 struct ir3_shader *
299 ir3_shader_create(struct ir3_compiler *compiler,
300 const struct pipe_shader_state *cso, enum shader_t type,
301 struct pipe_debug_callback *debug)
302 {
303 struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
304 shader->compiler = compiler;
305 shader->id = ++shader->compiler->shader_count;
306 shader->type = type;
307
308 nir_shader *nir;
309 if (cso->type == PIPE_SHADER_IR_NIR) {
310 /* we take ownership of the reference: */
311 nir = cso->ir.nir;
312
313 NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
314 (nir_lower_io_options)0);
315 } else {
316 debug_assert(cso->type == PIPE_SHADER_IR_TGSI);
317 if (fd_mesa_debug & FD_DBG_DISASM) {
318 DBG("dump tgsi: type=%d", shader->type);
319 tgsi_dump(cso->tokens, 0);
320 }
321 nir = ir3_tgsi_to_nir(cso->tokens);
322 }
323 /* do first pass optimization, ignoring the key: */
324 shader->nir = ir3_optimize_nir(shader, nir, NULL);
325 if (fd_mesa_debug & FD_DBG_DISASM) {
326 DBG("dump nir%d: type=%d", shader->id, shader->type);
327 nir_print_shader(shader->nir, stdout);
328 }
329
330 shader->stream_output = cso->stream_output;
331 if (fd_mesa_debug & FD_DBG_SHADERDB) {
332 /* if shader-db run, create a standard variant immediately
333 * (as otherwise nothing will trigger the shader to be
334 * actually compiled)
335 */
336 static struct ir3_shader_key key;
337 memset(&key, 0, sizeof(key));
338 ir3_shader_variant(shader, key, debug);
339 }
340 return shader;
341 }
342
343 /* a bit annoying that compute-shader and normal shader state objects
344 * aren't a bit more aligned.
345 */
346 struct ir3_shader *
347 ir3_shader_create_compute(struct ir3_compiler *compiler,
348 const struct pipe_compute_state *cso,
349 struct pipe_debug_callback *debug)
350 {
351 struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
352
353 shader->compiler = compiler;
354 shader->id = ++shader->compiler->shader_count;
355 shader->type = SHADER_COMPUTE;
356
357 nir_shader *nir;
358 if (cso->ir_type == PIPE_SHADER_IR_NIR) {
359 /* we take ownership of the reference: */
360 nir = (nir_shader *)cso->prog;
361
362 NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
363 (nir_lower_io_options)0);
364 } else {
365 debug_assert(cso->ir_type == PIPE_SHADER_IR_TGSI);
366 if (fd_mesa_debug & FD_DBG_DISASM) {
367 DBG("dump tgsi: type=%d", shader->type);
368 tgsi_dump(cso->prog, 0);
369 }
370 nir = ir3_tgsi_to_nir(cso->prog);
371 }
372
373 /* do first pass optimization, ignoring the key: */
374 shader->nir = ir3_optimize_nir(shader, nir, NULL);
375 if (fd_mesa_debug & FD_DBG_DISASM) {
376 DBG("dump nir%d: type=%d", shader->id, shader->type);
377 nir_print_shader(shader->nir, stdout);
378 }
379
380 return shader;
381 }
382
383 static void dump_reg(const char *name, uint32_t r)
384 {
385 if (r != regid(63,0))
386 debug_printf("; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
387 }
388
389 static void dump_output(struct ir3_shader_variant *so,
390 unsigned slot, const char *name)
391 {
392 uint32_t regid;
393 regid = ir3_find_output_regid(so, slot);
394 dump_reg(name, regid);
395 }
396
397 void
398 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
399 {
400 struct ir3 *ir = so->ir;
401 struct ir3_register *reg;
402 const char *type = ir3_shader_stage(so->shader);
403 uint8_t regid;
404 unsigned i;
405
406 for (i = 0; i < ir->ninputs; i++) {
407 if (!ir->inputs[i]) {
408 debug_printf("; in%d unused\n", i);
409 continue;
410 }
411 reg = ir->inputs[i]->regs[0];
412 regid = reg->num;
413 debug_printf("@in(%sr%d.%c)\tin%d\n",
414 (reg->flags & IR3_REG_HALF) ? "h" : "",
415 (regid >> 2), "xyzw"[regid & 0x3], i);
416 }
417
418 for (i = 0; i < ir->noutputs; i++) {
419 if (!ir->outputs[i]) {
420 debug_printf("; out%d unused\n", i);
421 continue;
422 }
423 /* kill shows up as a virtual output.. skip it! */
424 if (is_kill(ir->outputs[i]))
425 continue;
426 reg = ir->outputs[i]->regs[0];
427 regid = reg->num;
428 debug_printf("@out(%sr%d.%c)\tout%d\n",
429 (reg->flags & IR3_REG_HALF) ? "h" : "",
430 (regid >> 2), "xyzw"[regid & 0x3], i);
431 }
432
433 for (i = 0; i < so->immediates_count; i++) {
434 debug_printf("@const(c%d.x)\t", so->constbase.immediate + i);
435 debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
436 so->immediates[i].val[0],
437 so->immediates[i].val[1],
438 so->immediates[i].val[2],
439 so->immediates[i].val[3]);
440 }
441
442 disasm_a3xx(bin, so->info.sizedwords, 0, so->type);
443
444 switch (so->type) {
445 case SHADER_VERTEX:
446 debug_printf("; %s: outputs:", type);
447 for (i = 0; i < so->outputs_count; i++) {
448 uint8_t regid = so->outputs[i].regid;
449 debug_printf(" r%d.%c (%s)",
450 (regid >> 2), "xyzw"[regid & 0x3],
451 gl_varying_slot_name(so->outputs[i].slot));
452 }
453 debug_printf("\n");
454 debug_printf("; %s: inputs:", type);
455 for (i = 0; i < so->inputs_count; i++) {
456 uint8_t regid = so->inputs[i].regid;
457 debug_printf(" r%d.%c (cm=%x,il=%u,b=%u)",
458 (regid >> 2), "xyzw"[regid & 0x3],
459 so->inputs[i].compmask,
460 so->inputs[i].inloc,
461 so->inputs[i].bary);
462 }
463 debug_printf("\n");
464 break;
465 case SHADER_FRAGMENT:
466 debug_printf("; %s: outputs:", type);
467 for (i = 0; i < so->outputs_count; i++) {
468 uint8_t regid = so->outputs[i].regid;
469 debug_printf(" r%d.%c (%s)",
470 (regid >> 2), "xyzw"[regid & 0x3],
471 gl_frag_result_name(so->outputs[i].slot));
472 }
473 debug_printf("\n");
474 debug_printf("; %s: inputs:", type);
475 for (i = 0; i < so->inputs_count; i++) {
476 uint8_t regid = so->inputs[i].regid;
477 debug_printf(" r%d.%c (%s,cm=%x,il=%u,b=%u)",
478 (regid >> 2), "xyzw"[regid & 0x3],
479 gl_varying_slot_name(so->inputs[i].slot),
480 so->inputs[i].compmask,
481 so->inputs[i].inloc,
482 so->inputs[i].bary);
483 }
484 debug_printf("\n");
485 break;
486 default:
487 /* TODO */
488 break;
489 }
490
491 /* print generic shader info: */
492 debug_printf("; %s prog %d/%d: %u instructions, %d half, %d full\n",
493 type, so->shader->id, so->id,
494 so->info.instrs_count,
495 so->info.max_half_reg + 1,
496 so->info.max_reg + 1);
497
498 debug_printf("; %d const, %u constlen\n",
499 so->info.max_const + 1,
500 so->constlen);
501
502 debug_printf("; %u (ss), %u (sy)\n", so->info.ss, so->info.sy);
503
504 /* print shader type specific info: */
505 switch (so->type) {
506 case SHADER_VERTEX:
507 dump_output(so, VARYING_SLOT_POS, "pos");
508 dump_output(so, VARYING_SLOT_PSIZ, "psize");
509 break;
510 case SHADER_FRAGMENT:
511 dump_reg("pos (bary)", so->pos_regid);
512 dump_output(so, FRAG_RESULT_DEPTH, "posz");
513 if (so->color0_mrt) {
514 dump_output(so, FRAG_RESULT_COLOR, "color");
515 } else {
516 dump_output(so, FRAG_RESULT_DATA0, "data0");
517 dump_output(so, FRAG_RESULT_DATA1, "data1");
518 dump_output(so, FRAG_RESULT_DATA2, "data2");
519 dump_output(so, FRAG_RESULT_DATA3, "data3");
520 dump_output(so, FRAG_RESULT_DATA4, "data4");
521 dump_output(so, FRAG_RESULT_DATA5, "data5");
522 dump_output(so, FRAG_RESULT_DATA6, "data6");
523 dump_output(so, FRAG_RESULT_DATA7, "data7");
524 }
525 /* these two are hard-coded since we don't know how to
526 * program them to anything but all 0's...
527 */
528 if (so->frag_coord)
529 debug_printf("; fragcoord: r0.x\n");
530 if (so->frag_face)
531 debug_printf("; fragface: hr0.x\n");
532 break;
533 default:
534 /* TODO */
535 break;
536 }
537
538 debug_printf("\n");
539 }
540
541 uint64_t
542 ir3_shader_outputs(const struct ir3_shader *so)
543 {
544 return so->nir->info.outputs_written;
545 }
546
547 /* This has to reach into the fd_context a bit more than the rest of
548 * ir3, but it needs to be aligned with the compiler, so both agree
549 * on which const regs hold what. And the logic is identical between
550 * a3xx/a4xx, the only difference is small details in the actual
551 * CP_LOAD_STATE packets (which is handled inside the generation
552 * specific ctx->emit_const(_bo)() fxns)
553 */
554
555 #include "freedreno_resource.h"
556
557 static void
558 emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
559 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
560 {
561 const unsigned index = 0; /* user consts are index 0 */
562 /* TODO save/restore dirty_mask for binning pass instead: */
563 uint32_t dirty_mask = constbuf->enabled_mask;
564
565 if (dirty_mask & (1 << index)) {
566 struct pipe_constant_buffer *cb = &constbuf->cb[index];
567 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
568
569 /* in particular, with binning shader we may end up with
570 * unused consts, ie. we could end up w/ constlen that is
571 * smaller than first_driver_param. In that case truncate
572 * the user consts early to avoid HLSQ lockup caused by
573 * writing too many consts
574 */
575 uint32_t max_const = MIN2(v->num_uniforms, v->constlen);
576
577 // I expect that size should be a multiple of vec4's:
578 assert(size == align(size, 4));
579
580 /* and even if the start of the const buffer is before
581 * first_immediate, the end may not be:
582 */
583 size = MIN2(size, 4 * max_const);
584
585 if (size > 0) {
586 fd_wfi(ctx->batch, ring);
587 ctx->emit_const(ring, v->type, 0,
588 cb->buffer_offset, size,
589 cb->user_buffer, cb->buffer);
590 constbuf->dirty_mask &= ~(1 << index);
591 }
592 }
593 }
594
595 static void
596 emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
597 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
598 {
599 uint32_t offset = v->constbase.ubo;
600 if (v->constlen > offset) {
601 uint32_t params = v->num_ubos;
602 uint32_t offsets[params];
603 struct pipe_resource *prscs[params];
604
605 for (uint32_t i = 0; i < params; i++) {
606 const uint32_t index = i + 1; /* UBOs start at index 1 */
607 struct pipe_constant_buffer *cb = &constbuf->cb[index];
608 assert(!cb->user_buffer);
609
610 if ((constbuf->enabled_mask & (1 << index)) && cb->buffer) {
611 offsets[i] = cb->buffer_offset;
612 prscs[i] = cb->buffer;
613 } else {
614 offsets[i] = 0;
615 prscs[i] = NULL;
616 }
617 }
618
619 fd_wfi(ctx->batch, ring);
620 ctx->emit_const_bo(ring, v->type, false, offset * 4, params, prscs, offsets);
621 }
622 }
623
624 static void
625 emit_ssbo_sizes(struct fd_context *ctx, const struct ir3_shader_variant *v,
626 struct fd_ringbuffer *ring, struct fd_shaderbuf_stateobj *sb)
627 {
628 uint32_t offset = v->constbase.ssbo_sizes;
629 if (v->constlen > offset) {
630 uint32_t sizes[align(v->const_layout.ssbo_size.count, 4)];
631 unsigned mask = v->const_layout.ssbo_size.mask;
632
633 while (mask) {
634 unsigned index = u_bit_scan(&mask);
635 unsigned off = v->const_layout.ssbo_size.off[index];
636 sizes[off] = sb->sb[index].buffer_size;
637 }
638
639 fd_wfi(ctx->batch, ring);
640 ctx->emit_const(ring, v->type, offset * 4,
641 0, ARRAY_SIZE(sizes), sizes, NULL);
642 }
643 }
644
645 static void
646 emit_image_dims(struct fd_context *ctx, const struct ir3_shader_variant *v,
647 struct fd_ringbuffer *ring, struct fd_shaderimg_stateobj *si)
648 {
649 uint32_t offset = v->constbase.image_dims;
650 if (v->constlen > offset) {
651 uint32_t dims[align(v->const_layout.image_dims.count, 4)];
652 unsigned mask = v->const_layout.image_dims.mask;
653
654 while (mask) {
655 struct pipe_image_view *img;
656 struct fd_resource *rsc;
657 unsigned index = u_bit_scan(&mask);
658 unsigned off = v->const_layout.image_dims.off[index];
659
660 img = &si->si[index];
661 rsc = fd_resource(img->resource);
662
663 dims[off + 0] = util_format_get_blocksize(img->format);
664 if (img->resource->target != PIPE_BUFFER) {
665 unsigned lvl = img->u.tex.level;
666 /* note for 2d/cube/etc images, even if re-interpreted
667 * as a different color format, the pixel size should
668 * be the same, so use original dimensions for y and z
669 * stride:
670 */
671 dims[off + 1] = rsc->slices[lvl].pitch * rsc->cpp;
672 dims[off + 2] = rsc->slices[lvl].size0;
673 }
674 }
675
676 fd_wfi(ctx->batch, ring);
677 ctx->emit_const(ring, v->type, offset * 4,
678 0, ARRAY_SIZE(dims), dims, NULL);
679 }
680 }
681
682 static void
683 emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v,
684 struct fd_ringbuffer *ring)
685 {
686 int size = v->immediates_count;
687 uint32_t base = v->constbase.immediate;
688
689 /* truncate size to avoid writing constants that shader
690 * does not use:
691 */
692 size = MIN2(size + base, v->constlen) - base;
693
694 /* convert out of vec4: */
695 base *= 4;
696 size *= 4;
697
698 if (size > 0) {
699 fd_wfi(ctx->batch, ring);
700 ctx->emit_const(ring, v->type, base,
701 0, size, v->immediates[0].val, NULL);
702 }
703 }
704
705 /* emit stream-out buffers: */
706 static void
707 emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
708 struct fd_ringbuffer *ring)
709 {
710 /* streamout addresses after driver-params: */
711 uint32_t offset = v->constbase.tfbo;
712 if (v->constlen > offset) {
713 struct fd_streamout_stateobj *so = &ctx->streamout;
714 struct pipe_stream_output_info *info = &v->shader->stream_output;
715 uint32_t params = 4;
716 uint32_t offsets[params];
717 struct pipe_resource *prscs[params];
718
719 for (uint32_t i = 0; i < params; i++) {
720 struct pipe_stream_output_target *target = so->targets[i];
721
722 if (target) {
723 offsets[i] = (so->offsets[i] * info->stride[i] * 4) +
724 target->buffer_offset;
725 prscs[i] = target->buffer;
726 } else {
727 offsets[i] = 0;
728 prscs[i] = NULL;
729 }
730 }
731
732 fd_wfi(ctx->batch, ring);
733 ctx->emit_const_bo(ring, v->type, true, offset * 4, params, prscs, offsets);
734 }
735 }
736
737 static uint32_t
738 max_tf_vtx(struct fd_context *ctx, const struct ir3_shader_variant *v)
739 {
740 struct fd_streamout_stateobj *so = &ctx->streamout;
741 struct pipe_stream_output_info *info = &v->shader->stream_output;
742 uint32_t maxvtxcnt = 0x7fffffff;
743
744 if (ctx->screen->gpu_id >= 500)
745 return 0;
746 if (v->key.binning_pass)
747 return 0;
748 if (v->shader->stream_output.num_outputs == 0)
749 return 0;
750 if (so->num_targets == 0)
751 return 0;
752
753 /* offset to write to is:
754 *
755 * total_vtxcnt = vtxcnt + offsets[i]
756 * offset = total_vtxcnt * stride[i]
757 *
758 * offset = vtxcnt * stride[i] ; calculated in shader
759 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
760 *
761 * assuming for each vtx, each target buffer will have data written
762 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
763 *
764 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
765 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
766 *
767 * but shader is actually doing a less-than (rather than less-than-
768 * equal) check, so we can drop the -stride[i].
769 *
770 * TODO is assumption about `offset + stride[i]` legit?
771 */
772 for (unsigned i = 0; i < so->num_targets; i++) {
773 struct pipe_stream_output_target *target = so->targets[i];
774 unsigned stride = info->stride[i] * 4; /* convert dwords->bytes */
775 if (target) {
776 uint32_t max = target->buffer_size / stride;
777 maxvtxcnt = MIN2(maxvtxcnt, max);
778 }
779 }
780
781 return maxvtxcnt;
782 }
783
784 static void
785 emit_common_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
786 struct fd_context *ctx, enum pipe_shader_type t)
787 {
788 enum fd_dirty_shader_state dirty = ctx->dirty_shader[t];
789
790 if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST)) {
791 struct fd_constbuf_stateobj *constbuf;
792 bool shader_dirty;
793
794 constbuf = &ctx->constbuf[t];
795 shader_dirty = !!(dirty & FD_DIRTY_SHADER_PROG);
796
797 emit_user_consts(ctx, v, ring, constbuf);
798 emit_ubos(ctx, v, ring, constbuf);
799 if (shader_dirty)
800 emit_immediates(ctx, v, ring);
801 }
802
803 if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_SSBO)) {
804 struct fd_shaderbuf_stateobj *sb = &ctx->shaderbuf[t];
805 emit_ssbo_sizes(ctx, v, ring, sb);
806 }
807
808 if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_IMAGE)) {
809 struct fd_shaderimg_stateobj *si = &ctx->shaderimg[t];
810 emit_image_dims(ctx, v, ring, si);
811 }
812 }
813
814 void
815 ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
816 struct fd_context *ctx, const struct pipe_draw_info *info)
817 {
818 debug_assert(v->type == SHADER_VERTEX);
819
820 emit_common_consts(v, ring, ctx, PIPE_SHADER_VERTEX);
821
822 /* emit driver params every time: */
823 /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
824 if (info) {
825 uint32_t offset = v->constbase.driver_param;
826 if (v->constlen > offset) {
827 uint32_t vertex_params[IR3_DP_VS_COUNT] = {
828 [IR3_DP_VTXID_BASE] = info->index_size ?
829 info->index_bias : info->start,
830 [IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
831 };
832 /* if no user-clip-planes, we don't need to emit the
833 * entire thing:
834 */
835 uint32_t vertex_params_size = 4;
836
837 if (v->key.ucp_enables) {
838 struct pipe_clip_state *ucp = &ctx->ucp;
839 unsigned pos = IR3_DP_UCP0_X;
840 for (unsigned i = 0; pos <= IR3_DP_UCP7_W; i++) {
841 for (unsigned j = 0; j < 4; j++) {
842 vertex_params[pos] = fui(ucp->ucp[i][j]);
843 pos++;
844 }
845 }
846 vertex_params_size = ARRAY_SIZE(vertex_params);
847 }
848
849 fd_wfi(ctx->batch, ring);
850
851 bool needs_vtxid_base =
852 ir3_find_sysval_regid(v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) != regid(63, 0);
853
854 /* for indirect draw, we need to copy VTXID_BASE from
855 * indirect-draw parameters buffer.. which is annoying
856 * and means we can't easily emit these consts in cmd
857 * stream so need to copy them to bo.
858 */
859 if (info->indirect && needs_vtxid_base) {
860 struct pipe_draw_indirect_info *indirect = info->indirect;
861 struct pipe_resource *vertex_params_rsc =
862 pipe_buffer_create(&ctx->screen->base,
863 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM,
864 vertex_params_size * 4);
865 unsigned src_off = info->indirect->offset;;
866 void *ptr;
867
868 ptr = fd_bo_map(fd_resource(vertex_params_rsc)->bo);
869 memcpy(ptr, vertex_params, vertex_params_size * 4);
870
871 if (info->index_size) {
872 /* indexed draw, index_bias is 4th field: */
873 src_off += 3 * 4;
874 } else {
875 /* non-indexed draw, start is 3rd field: */
876 src_off += 2 * 4;
877 }
878
879 /* copy index_bias or start from draw params: */
880 ctx->mem_to_mem(ring, vertex_params_rsc, 0,
881 indirect->buffer, src_off, 1);
882
883 ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
884 vertex_params_size, NULL, vertex_params_rsc);
885
886 pipe_resource_reference(&vertex_params_rsc, NULL);
887 } else {
888 ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
889 vertex_params_size, vertex_params, NULL);
890 }
891
892 /* if needed, emit stream-out buffer addresses: */
893 if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
894 emit_tfbos(ctx, v, ring);
895 }
896 }
897 }
898 }
899
900 void
901 ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
902 struct fd_context *ctx)
903 {
904 debug_assert(v->type == SHADER_FRAGMENT);
905
906 emit_common_consts(v, ring, ctx, PIPE_SHADER_FRAGMENT);
907 }
908
909 /* emit compute-shader consts: */
910 void
911 ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
912 struct fd_context *ctx, const struct pipe_grid_info *info)
913 {
914 debug_assert(v->type == SHADER_COMPUTE);
915
916 emit_common_consts(v, ring, ctx, PIPE_SHADER_COMPUTE);
917
918 /* emit compute-shader driver-params: */
919 uint32_t offset = v->constbase.driver_param;
920 if (v->constlen > offset) {
921 fd_wfi(ctx->batch, ring);
922
923 if (info->indirect) {
924 struct pipe_resource *indirect = NULL;
925 unsigned indirect_offset;
926
927 /* This is a bit awkward, but CP_LOAD_STATE.EXT_SRC_ADDR needs
928 * to be aligned more strongly than 4 bytes. So in this case
929 * we need a temporary buffer to copy NumWorkGroups.xyz to.
930 *
931 * TODO if previous compute job is writing to info->indirect,
932 * we might need a WFI.. but since we currently flush for each
933 * compute job, we are probably ok for now.
934 */
935 if (info->indirect_offset & 0xf) {
936 indirect = pipe_buffer_create(&ctx->screen->base,
937 PIPE_BIND_COMMAND_ARGS_BUFFER, PIPE_USAGE_STREAM,
938 0x1000);
939 indirect_offset = 0;
940
941 ctx->mem_to_mem(ring, indirect, 0, info->indirect,
942 info->indirect_offset, 3);
943 } else {
944 pipe_resource_reference(&indirect, info->indirect);
945 indirect_offset = info->indirect_offset;
946 }
947
948 ctx->emit_const(ring, SHADER_COMPUTE, offset * 4,
949 indirect_offset, 4, NULL, indirect);
950
951 pipe_resource_reference(&indirect, NULL);
952 } else {
953 uint32_t compute_params[IR3_DP_CS_COUNT] = {
954 [IR3_DP_NUM_WORK_GROUPS_X] = info->grid[0],
955 [IR3_DP_NUM_WORK_GROUPS_Y] = info->grid[1],
956 [IR3_DP_NUM_WORK_GROUPS_Z] = info->grid[2],
957 [IR3_DP_LOCAL_GROUP_SIZE_X] = info->block[0],
958 [IR3_DP_LOCAL_GROUP_SIZE_Y] = info->block[1],
959 [IR3_DP_LOCAL_GROUP_SIZE_Z] = info->block[2],
960 };
961
962 ctx->emit_const(ring, SHADER_COMPUTE, offset * 4, 0,
963 ARRAY_SIZE(compute_params), compute_params, NULL);
964 }
965 }
966 }