src/gallium/drivers/freedreno/ir3/ir3_shader.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34 #include "tgsi/tgsi_dump.h"
  35 #include "tgsi/tgsi_parse.h"
  36
  37 #include "freedreno_context.h"
  38 #include "freedreno_util.h"
  39
  40 #include "ir3_shader.h"
  41 #include "ir3_compiler.h"
  42 #include "ir3_nir.h"
  43
  44 static void
  45 delete_variant(struct ir3_shader_variant *v)
  46 {
  47         if (v->ir)
  48                 ir3_destroy(v->ir);
  49         if (v->bo)
  50                 fd_bo_del(v->bo);
  51         free(v);
  52 }
  53
  54 /* for vertex shader, the inputs are loaded into registers before the shader
  55  * is executed, so max_regs from the shader instructions might not properly
  56  * reflect the # of registers actually used, especially in case passthrough
  57  * varyings.
  58  *
  59  * Likewise, for fragment shader, we can have some regs which are passed
  60  * input values but never touched by the resulting shader (ie. as result
  61  * of dead code elimination or simply because we don't know how to turn
  62  * the reg off.
  63  */
  64 static void
  65 fixup_regfootprint(struct ir3_shader_variant *v)
  66 {
  67         if (v->type == SHADER_VERTEX) {
  68                 unsigned i;
  69                 for (i = 0; i < v->inputs_count; i++) {
  70                         /* skip frag inputs fetch via bary.f since their reg's are
  71                          * not written by gpu before shader starts (and in fact the
  72                          * regid's might not even be valid)
  73                          */
  74                         if (v->inputs[i].bary)
  75                                 continue;
  76
  77                         if (v->inputs[i].compmask) {
  78                                 int32_t regid = (v->inputs[i].regid + 3) >> 2;
  79                                 v->info.max_reg = MAX2(v->info.max_reg, regid);
  80                         }
  81                 }
  82                 for (i = 0; i < v->outputs_count; i++) {
  83                         int32_t regid = (v->outputs[i].regid + 3) >> 2;
  84                         v->info.max_reg = MAX2(v->info.max_reg, regid);
  85                 }
  86         } else if (v->type == SHADER_FRAGMENT) {
  87                 /* NOTE: not sure how to turn pos_regid off..  but this could
  88                  * be, for example, r1.x while max reg used by the shader is
  89                  * r0.*, in which case we need to fixup the reg footprint:
  90                  */
  91                 v->info.max_reg = MAX2(v->info.max_reg, v->pos_regid >> 2);
  92                 if (v->frag_coord)
  93                         debug_assert(v->info.max_reg >= 0); /* hard coded r0.x */
  94                 if (v->frag_face)
  95                         debug_assert(v->info.max_half_reg >= 0); /* hr0.x */
  96         }
  97 }
  98
  99 /* wrapper for ir3_assemble() which does some info fixup based on
 100  * shader state.  Non-static since used by ir3_cmdline too.
 101  */
 102 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 103 {
 104         void *bin;
 105
 106         bin = ir3_assemble(v->ir, &v->info, gpu_id);
 107         if (!bin)
 108                 return NULL;
 109
 110         if (gpu_id >= 400) {
 111                 v->instrlen = v->info.sizedwords / (2 * 16);
 112         } else {
 113                 v->instrlen = v->info.sizedwords / (2 * 4);
 114         }
 115
 116         /* NOTE: if relative addressing is used, we set constlen in
 117          * the compiler (to worst-case value) since we don't know in
 118          * the assembler what the max addr reg value can be:
 119          */
 120         v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
 121
 122         fixup_regfootprint(v);
 123
 124         return bin;
 125 }
 126
 127 static void
 128 assemble_variant(struct ir3_shader_variant *v)
 129 {
 130         struct ir3_compiler *compiler = v->shader->compiler;
 131         uint32_t gpu_id = compiler->gpu_id;
 132         uint32_t sz, *bin;
 133
 134         bin = ir3_shader_assemble(v, gpu_id);
 135         sz = v->info.sizedwords * 4;
 136
 137         v->bo = fd_bo_new(compiler->dev, sz,
 138                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 139                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 140
 141         memcpy(fd_bo_map(v->bo), bin, sz);
 142
 143         if (fd_mesa_debug & FD_DBG_DISASM) {
 144                 struct ir3_shader_key key = v->key;
 145                 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
 146                         key.binning_pass, key.color_two_side, key.half_precision);
 147                 ir3_shader_disasm(v, bin);
 148         }
 149
 150         free(bin);
 151
 152         /* no need to keep the ir around beyond this point: */
 153         ir3_destroy(v->ir);
 154         v->ir = NULL;
 155 }
 156
 157 static void
 158 dump_shader_info(struct ir3_shader_variant *v, struct pipe_debug_callback *debug)
 159 {
 160         if (!unlikely(fd_mesa_debug & FD_DBG_SHADERDB))
 161                 return;
 162
 163         pipe_debug_message(debug, SHADER_INFO, "\n"
 164                         "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n"
 165                         "SHADER-DB: %s prog %d/%d: %u half, %u full\n"
 166                         "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n",
 167                         ir3_shader_stage(v->shader),
 168                         v->shader->id, v->id,
 169                         v->info.instrs_count,
 170                         v->info.sizedwords,
 171                         ir3_shader_stage(v->shader),
 172                         v->shader->id, v->id,
 173                         v->info.max_half_reg + 1,
 174                         v->info.max_reg + 1,
 175                         ir3_shader_stage(v->shader),
 176                         v->shader->id, v->id,
 177                         v->info.max_const + 1,
 178                         v->constlen);
 179 }
 180
 181 static struct ir3_shader_variant *
 182 create_variant(struct ir3_shader *shader, struct ir3_shader_key key)
 183 {
 184         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 185         int ret;
 186
 187         if (!v)
 188                 return NULL;
 189
 190         v->id = ++shader->variant_count;
 191         v->shader = shader;
 192         v->key = key;
 193         v->type = shader->type;
 194
 195         ret = ir3_compile_shader_nir(shader->compiler, v);
 196         if (ret) {
 197                 debug_error("compile failed!");
 198                 goto fail;
 199         }
 200
 201         assemble_variant(v);
 202         if (!v->bo) {
 203                 debug_error("assemble failed!");
 204                 goto fail;
 205         }
 206
 207         return v;
 208
 209 fail:
 210         delete_variant(v);
 211         return NULL;
 212 }
 213
 214 struct ir3_shader_variant *
 215 ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key,
 216                 struct pipe_debug_callback *debug)
 217 {
 218         struct ir3_shader_variant *v;
 219
 220         /* some shader key values only apply to vertex or frag shader,
 221          * so normalize the key to avoid constructing multiple identical
 222          * variants:
 223          */
 224         switch (shader->type) {
 225         case SHADER_FRAGMENT:
 226         case SHADER_COMPUTE:
 227                 key.binning_pass = false;
 228                 if (key.has_per_samp) {
 229                         key.vsaturate_s = 0;
 230                         key.vsaturate_t = 0;
 231                         key.vsaturate_r = 0;
 232                         key.vastc_srgb = 0;
 233                 }
 234                 break;
 235         case SHADER_VERTEX:
 236                 key.color_two_side = false;
 237                 key.half_precision = false;
 238                 key.rasterflat = false;
 239                 if (key.has_per_samp) {
 240                         key.fsaturate_s = 0;
 241                         key.fsaturate_t = 0;
 242                         key.fsaturate_r = 0;
 243                         key.fastc_srgb = 0;
 244                 }
 245                 break;
 246         }
 247
 248         for (v = shader->variants; v; v = v->next)
 249                 if (ir3_shader_key_equal(&key, &v->key))
 250                         return v;
 251
 252         /* compile new variant if it doesn't exist already: */
 253         v = create_variant(shader, key);
 254         if (v) {
 255                 v->next = shader->variants;
 256                 shader->variants = v;
 257                 dump_shader_info(v, debug);
 258         }
 259
 260         return v;
 261 }
 262
 263
 264 void
 265 ir3_shader_destroy(struct ir3_shader *shader)
 266 {
 267         struct ir3_shader_variant *v, *t;
 268         for (v = shader->variants; v; ) {
 269                 t = v;
 270                 v = v->next;
 271                 delete_variant(t);
 272         }
 273         ralloc_free(shader->nir);
 274         free(shader);
 275 }
 276
 277 struct ir3_shader *
 278 ir3_shader_create(struct ir3_compiler *compiler,
 279                 const struct pipe_shader_state *cso, enum shader_t type,
 280                 struct pipe_debug_callback *debug)
 281 {
 282         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 283         shader->compiler = compiler;
 284         shader->id = ++shader->compiler->shader_count;
 285         shader->type = type;
 286
 287         nir_shader *nir;
 288         if (cso->type == PIPE_SHADER_IR_NIR) {
 289                 /* we take ownership of the reference: */
 290                 nir = cso->ir.nir;
 291         } else {
 292                 if (fd_mesa_debug & FD_DBG_DISASM) {
 293                         DBG("dump tgsi: type=%d", shader->type);
 294                         tgsi_dump(cso->tokens, 0);
 295                 }
 296                 nir = ir3_tgsi_to_nir(cso->tokens);
 297                 shader->from_tgsi = true;
 298         }
 299         /* do first pass optimization, ignoring the key: */
 300         shader->nir = ir3_optimize_nir(shader, nir, NULL);
 301         if (fd_mesa_debug & FD_DBG_DISASM) {
 302                 DBG("dump nir%d: type=%d", shader->id, shader->type);
 303                 nir_print_shader(shader->nir, stdout);
 304         }
 305
 306         shader->stream_output = cso->stream_output;
 307         if (fd_mesa_debug & FD_DBG_SHADERDB) {
 308                 /* if shader-db run, create a standard variant immediately
 309                  * (as otherwise nothing will trigger the shader to be
 310                  * actually compiled)
 311                  */
 312                 static struct ir3_shader_key key;
 313                 memset(&key, 0, sizeof(key));
 314                 ir3_shader_variant(shader, key, debug);
 315         }
 316         return shader;
 317 }
 318
 319 static void dump_reg(const char *name, uint32_t r)
 320 {
 321         if (r != regid(63,0))
 322                 debug_printf("; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
 323 }
 324
 325 static void dump_output(struct ir3_shader_variant *so,
 326                 unsigned slot, const char *name)
 327 {
 328         uint32_t regid;
 329         regid = ir3_find_output_regid(so, slot);
 330         dump_reg(name, regid);
 331 }
 332
 333 void
 334 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
 335 {
 336         struct ir3 *ir = so->ir;
 337         struct ir3_register *reg;
 338         const char *type = ir3_shader_stage(so->shader);
 339         uint8_t regid;
 340         unsigned i;
 341
 342         for (i = 0; i < ir->ninputs; i++) {
 343                 if (!ir->inputs[i]) {
 344                         debug_printf("; in%d unused\n", i);
 345                         continue;
 346                 }
 347                 reg = ir->inputs[i]->regs[0];
 348                 regid = reg->num;
 349                 debug_printf("@in(%sr%d.%c)\tin%d\n",
 350                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 351                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 352         }
 353
 354         for (i = 0; i < ir->noutputs; i++) {
 355                 if (!ir->outputs[i]) {
 356                         debug_printf("; out%d unused\n", i);
 357                         continue;
 358                 }
 359                 /* kill shows up as a virtual output.. skip it! */
 360                 if (is_kill(ir->outputs[i]))
 361                         continue;
 362                 reg = ir->outputs[i]->regs[0];
 363                 regid = reg->num;
 364                 debug_printf("@out(%sr%d.%c)\tout%d\n",
 365                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 366                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 367         }
 368
 369         for (i = 0; i < so->immediates_count; i++) {
 370                 debug_printf("@const(c%d.x)\t", so->first_immediate + i);
 371                 debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 372                                 so->immediates[i].val[0],
 373                                 so->immediates[i].val[1],
 374                                 so->immediates[i].val[2],
 375                                 so->immediates[i].val[3]);
 376         }
 377
 378         disasm_a3xx(bin, so->info.sizedwords, 0, so->type);
 379
 380         switch (so->type) {
 381         case SHADER_VERTEX:
 382                 debug_printf("; %s: outputs:", type);
 383                 for (i = 0; i < so->outputs_count; i++) {
 384                         uint8_t regid = so->outputs[i].regid;
 385                         debug_printf(" r%d.%c (%s)",
 386                                         (regid >> 2), "xyzw"[regid & 0x3],
 387                                         gl_varying_slot_name(so->outputs[i].slot));
 388                 }
 389                 debug_printf("\n");
 390                 debug_printf("; %s: inputs:", type);
 391                 for (i = 0; i < so->inputs_count; i++) {
 392                         uint8_t regid = so->inputs[i].regid;
 393                         debug_printf(" r%d.%c (cm=%x,il=%u,b=%u)",
 394                                         (regid >> 2), "xyzw"[regid & 0x3],
 395                                         so->inputs[i].compmask,
 396                                         so->inputs[i].inloc,
 397                                         so->inputs[i].bary);
 398                 }
 399                 debug_printf("\n");
 400                 break;
 401         case SHADER_FRAGMENT:
 402                 debug_printf("; %s: outputs:", type);
 403                 for (i = 0; i < so->outputs_count; i++) {
 404                         uint8_t regid = so->outputs[i].regid;
 405                         debug_printf(" r%d.%c (%s)",
 406                                         (regid >> 2), "xyzw"[regid & 0x3],
 407                                         gl_frag_result_name(so->outputs[i].slot));
 408                 }
 409                 debug_printf("\n");
 410                 debug_printf("; %s: inputs:", type);
 411                 for (i = 0; i < so->inputs_count; i++) {
 412                         uint8_t regid = so->inputs[i].regid;
 413                         debug_printf(" r%d.%c (%s,cm=%x,il=%u,b=%u)",
 414                                         (regid >> 2), "xyzw"[regid & 0x3],
 415                                         gl_varying_slot_name(so->inputs[i].slot),
 416                                         so->inputs[i].compmask,
 417                                         so->inputs[i].inloc,
 418                                         so->inputs[i].bary);
 419                 }
 420                 debug_printf("\n");
 421                 break;
 422         case SHADER_COMPUTE:
 423                 break;
 424         }
 425
 426         /* print generic shader info: */
 427         debug_printf("; %s prog %d/%d: %u instructions, %d half, %d full\n",
 428                         type, so->shader->id, so->id,
 429                         so->info.instrs_count,
 430                         so->info.max_half_reg + 1,
 431                         so->info.max_reg + 1);
 432
 433         debug_printf("; %d const, %u constlen\n",
 434                         so->info.max_const + 1,
 435                         so->constlen);
 436
 437         /* print shader type specific info: */
 438         switch (so->type) {
 439         case SHADER_VERTEX:
 440                 dump_output(so, VARYING_SLOT_POS, "pos");
 441                 dump_output(so, VARYING_SLOT_PSIZ, "psize");
 442                 break;
 443         case SHADER_FRAGMENT:
 444                 dump_reg("pos (bary)", so->pos_regid);
 445                 dump_output(so, FRAG_RESULT_DEPTH, "posz");
 446                 if (so->color0_mrt) {
 447                         dump_output(so, FRAG_RESULT_COLOR, "color");
 448                 } else {
 449                         dump_output(so, FRAG_RESULT_DATA0, "data0");
 450                         dump_output(so, FRAG_RESULT_DATA1, "data1");
 451                         dump_output(so, FRAG_RESULT_DATA2, "data2");
 452                         dump_output(so, FRAG_RESULT_DATA3, "data3");
 453                         dump_output(so, FRAG_RESULT_DATA4, "data4");
 454                         dump_output(so, FRAG_RESULT_DATA5, "data5");
 455                         dump_output(so, FRAG_RESULT_DATA6, "data6");
 456                         dump_output(so, FRAG_RESULT_DATA7, "data7");
 457                 }
 458                 /* these two are hard-coded since we don't know how to
 459                  * program them to anything but all 0's...
 460                  */
 461                 if (so->frag_coord)
 462                         debug_printf("; fragcoord: r0.x\n");
 463                 if (so->frag_face)
 464                         debug_printf("; fragface: hr0.x\n");
 465                 break;
 466         case SHADER_COMPUTE:
 467                 break;
 468         }
 469
 470         debug_printf("\n");
 471 }
 472
 473 /* This has to reach into the fd_context a bit more than the rest of
 474  * ir3, but it needs to be aligned with the compiler, so both agree
 475  * on which const regs hold what.  And the logic is identical between
 476  * a3xx/a4xx, the only difference is small details in the actual
 477  * CP_LOAD_STATE packets (which is handled inside the generation
 478  * specific ctx->emit_const(_bo)() fxns)
 479  */
 480
 481 #include "freedreno_resource.h"
 482
 483 static void
 484 emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
 485                 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 486 {
 487         const unsigned index = 0;     /* user consts are index 0 */
 488         /* TODO save/restore dirty_mask for binning pass instead: */
 489         uint32_t dirty_mask = constbuf->enabled_mask;
 490
 491         if (dirty_mask & (1 << index)) {
 492                 struct pipe_constant_buffer *cb = &constbuf->cb[index];
 493                 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
 494
 495                 /* in particular, with binning shader we may end up with
 496                  * unused consts, ie. we could end up w/ constlen that is
 497                  * smaller than first_driver_param.  In that case truncate
 498                  * the user consts early to avoid HLSQ lockup caused by
 499                  * writing too many consts
 500                  */
 501                 uint32_t max_const = MIN2(v->first_driver_param, v->constlen);
 502
 503                 // I expect that size should be a multiple of vec4's:
 504                 assert(size == align(size, 4));
 505
 506                 /* and even if the start of the const buffer is before
 507                  * first_immediate, the end may not be:
 508                  */
 509                 size = MIN2(size, 4 * max_const);
 510
 511                 if (size > 0) {
 512                         fd_wfi(ctx->batch, ring);
 513                         ctx->emit_const(ring, v->type, 0,
 514                                         cb->buffer_offset, size,
 515                                         cb->user_buffer, cb->buffer);
 516                         constbuf->dirty_mask &= ~(1 << index);
 517                 }
 518         }
 519 }
 520
 521 static void
 522 emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
 523                 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 524 {
 525         uint32_t offset = v->first_driver_param + IR3_UBOS_OFF;
 526         if (v->constlen > offset) {
 527                 uint32_t params = MIN2(4, v->constlen - offset) * 4;
 528                 uint32_t offsets[params];
 529                 struct pipe_resource *prscs[params];
 530
 531                 for (uint32_t i = 0; i < params; i++) {
 532                         const uint32_t index = i + 1;   /* UBOs start at index 1 */
 533                         struct pipe_constant_buffer *cb = &constbuf->cb[index];
 534                         assert(!cb->user_buffer);
 535
 536                         if ((constbuf->enabled_mask & (1 << index)) && cb->buffer) {
 537                                 offsets[i] = cb->buffer_offset;
 538                                 prscs[i] = cb->buffer;
 539                         } else {
 540                                 offsets[i] = 0;
 541                                 prscs[i] = NULL;
 542                         }
 543                 }
 544
 545                 fd_wfi(ctx->batch, ring);
 546                 ctx->emit_const_bo(ring, v->type, false, offset * 4, params, prscs, offsets);
 547         }
 548 }
 549
 550 static void
 551 emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v,
 552                 struct fd_ringbuffer *ring)
 553 {
 554         int size = v->immediates_count;
 555         uint32_t base = v->first_immediate;
 556
 557         /* truncate size to avoid writing constants that shader
 558          * does not use:
 559          */
 560         size = MIN2(size + base, v->constlen) - base;
 561
 562         /* convert out of vec4: */
 563         base *= 4;
 564         size *= 4;
 565
 566         if (size > 0) {
 567                 fd_wfi(ctx->batch, ring);
 568                 ctx->emit_const(ring, v->type, base,
 569                         0, size, v->immediates[0].val, NULL);
 570         }
 571 }
 572
 573 /* emit stream-out buffers: */
 574 static void
 575 emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
 576                 struct fd_ringbuffer *ring)
 577 {
 578         /* streamout addresses after driver-params: */
 579         uint32_t offset = v->first_driver_param + IR3_TFBOS_OFF;
 580         if (v->constlen > offset) {
 581                 struct fd_streamout_stateobj *so = &ctx->streamout;
 582                 struct pipe_stream_output_info *info = &v->shader->stream_output;
 583                 uint32_t params = 4;
 584                 uint32_t offsets[params];
 585                 struct pipe_resource *prscs[params];
 586
 587                 for (uint32_t i = 0; i < params; i++) {
 588                         struct pipe_stream_output_target *target = so->targets[i];
 589
 590                         if (target) {
 591                                 offsets[i] = (so->offsets[i] * info->stride[i] * 4) +
 592                                                 target->buffer_offset;
 593                                 prscs[i] = target->buffer;
 594                         } else {
 595                                 offsets[i] = 0;
 596                                 prscs[i] = NULL;
 597                         }
 598                 }
 599
 600                 fd_wfi(ctx->batch, ring);
 601                 ctx->emit_const_bo(ring, v->type, true, offset * 4, params, prscs, offsets);
 602         }
 603 }
 604
 605 static uint32_t
 606 max_tf_vtx(struct fd_context *ctx, const struct ir3_shader_variant *v)
 607 {
 608         struct fd_streamout_stateobj *so = &ctx->streamout;
 609         struct pipe_stream_output_info *info = &v->shader->stream_output;
 610         uint32_t maxvtxcnt = 0x7fffffff;
 611
 612         if (v->key.binning_pass)
 613                 return 0;
 614         if (v->shader->stream_output.num_outputs == 0)
 615                 return 0;
 616         if (so->num_targets == 0)
 617                 return 0;
 618
 619         /* offset to write to is:
 620          *
 621          *   total_vtxcnt = vtxcnt + offsets[i]
 622          *   offset = total_vtxcnt * stride[i]
 623          *
 624          *   offset =   vtxcnt * stride[i]       ; calculated in shader
 625          *            + offsets[i] * stride[i]   ; calculated at emit_tfbos()
 626          *
 627          * assuming for each vtx, each target buffer will have data written
 628          * up to 'offset + stride[i]', that leaves maxvtxcnt as:
 629          *
 630          *   buffer_size = (maxvtxcnt * stride[i]) + stride[i]
 631          *   maxvtxcnt   = (buffer_size - stride[i]) / stride[i]
 632          *
 633          * but shader is actually doing a less-than (rather than less-than-
 634          * equal) check, so we can drop the -stride[i].
 635          *
 636          * TODO is assumption about `offset + stride[i]` legit?
 637          */
 638         for (unsigned i = 0; i < so->num_targets; i++) {
 639                 struct pipe_stream_output_target *target = so->targets[i];
 640                 unsigned stride = info->stride[i] * 4;   /* convert dwords->bytes */
 641                 if (target) {
 642                         uint32_t max = target->buffer_size / stride;
 643                         maxvtxcnt = MIN2(maxvtxcnt, max);
 644                 }
 645         }
 646
 647         return maxvtxcnt;
 648 }
 649
 650 void
 651 ir3_emit_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 652                 struct fd_context *ctx, const struct pipe_draw_info *info, uint32_t dirty)
 653 {
 654         if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) {
 655                 struct fd_constbuf_stateobj *constbuf;
 656                 bool shader_dirty;
 657
 658                 if (v->type == SHADER_VERTEX) {
 659                         constbuf = &ctx->constbuf[PIPE_SHADER_VERTEX];
 660                         shader_dirty = !!(dirty & FD_SHADER_DIRTY_VP);
 661                 } else if (v->type == SHADER_FRAGMENT) {
 662                         constbuf = &ctx->constbuf[PIPE_SHADER_FRAGMENT];
 663                         shader_dirty = !!(dirty & FD_SHADER_DIRTY_FP);
 664                 } else {
 665                         unreachable("bad shader type");
 666                         return;
 667                 }
 668
 669                 emit_user_consts(ctx, v, ring, constbuf);
 670                 emit_ubos(ctx, v, ring, constbuf);
 671                 if (shader_dirty)
 672                         emit_immediates(ctx, v, ring);
 673         }
 674
 675         /* emit driver params every time: */
 676         /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
 677         if (info && (v->type == SHADER_VERTEX)) {
 678                 uint32_t offset = v->first_driver_param + IR3_DRIVER_PARAM_OFF;
 679                 if (v->constlen >= offset) {
 680                         uint32_t vertex_params[IR3_DP_COUNT] = {
 681                                 [IR3_DP_VTXID_BASE] = info->indexed ?
 682                                                 info->index_bias : info->start,
 683                                 [IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
 684                         };
 685                         /* if no user-clip-planes, we don't need to emit the
 686                          * entire thing:
 687                          */
 688                         uint32_t vertex_params_size = 4;
 689
 690                         if (v->key.ucp_enables) {
 691                                 struct pipe_clip_state *ucp = &ctx->ucp;
 692                                 unsigned pos = IR3_DP_UCP0_X;
 693                                 for (unsigned i = 0; pos <= IR3_DP_UCP7_W; i++) {
 694                                         for (unsigned j = 0; j < 4; j++) {
 695                                                 vertex_params[pos] = fui(ucp->ucp[i][j]);
 696                                                 pos++;
 697                                         }
 698                                 }
 699                                 vertex_params_size = ARRAY_SIZE(vertex_params);
 700                         }
 701
 702                         fd_wfi(ctx->batch, ring);
 703                         ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
 704                                         vertex_params_size, vertex_params, NULL);
 705
 706                         /* if needed, emit stream-out buffer addresses: */
 707                         if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
 708                                 emit_tfbos(ctx, v, ring);
 709                         }
 710                 }
 711         }
 712 }