1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
37 #include "freedreno_context.h"
38 #include "freedreno_util.h"
40 #include "ir3_shader.h"
41 #include "ir3_compiler.h"
45 delete_variant(struct ir3_shader_variant
*v
)
54 /* for vertex shader, the inputs are loaded into registers before the shader
55 * is executed, so max_regs from the shader instructions might not properly
56 * reflect the # of registers actually used, especially in case passthrough
59 * Likewise, for fragment shader, we can have some regs which are passed
60 * input values but never touched by the resulting shader (ie. as result
61 * of dead code elimination or simply because we don't know how to turn
65 fixup_regfootprint(struct ir3_shader_variant
*v
)
67 if (v
->type
== SHADER_VERTEX
) {
69 for (i
= 0; i
< v
->inputs_count
; i
++) {
70 /* skip frag inputs fetch via bary.f since their reg's are
71 * not written by gpu before shader starts (and in fact the
72 * regid's might not even be valid)
74 if (v
->inputs
[i
].bary
)
77 if (v
->inputs
[i
].compmask
) {
78 int32_t regid
= (v
->inputs
[i
].regid
+ 3) >> 2;
79 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
);
82 for (i
= 0; i
< v
->outputs_count
; i
++) {
83 int32_t regid
= (v
->outputs
[i
].regid
+ 3) >> 2;
84 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
);
86 } else if (v
->type
== SHADER_FRAGMENT
) {
87 /* NOTE: not sure how to turn pos_regid off.. but this could
88 * be, for example, r1.x while max reg used by the shader is
89 * r0.*, in which case we need to fixup the reg footprint:
91 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, v
->pos_regid
>> 2);
93 debug_assert(v
->info
.max_reg
>= 0); /* hard coded r0.x */
95 debug_assert(v
->info
.max_half_reg
>= 0); /* hr0.x */
99 /* wrapper for ir3_assemble() which does some info fixup based on
100 * shader state. Non-static since used by ir3_cmdline too.
102 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
)
106 bin
= ir3_assemble(v
->ir
, &v
->info
, gpu_id
);
111 v
->instrlen
= v
->info
.sizedwords
/ (2 * 16);
113 v
->instrlen
= v
->info
.sizedwords
/ (2 * 4);
116 /* NOTE: if relative addressing is used, we set constlen in
117 * the compiler (to worst-case value) since we don't know in
118 * the assembler what the max addr reg value can be:
120 v
->constlen
= MIN2(255, MAX2(v
->constlen
, v
->info
.max_const
+ 1));
122 fixup_regfootprint(v
);
128 assemble_variant(struct ir3_shader_variant
*v
)
130 struct ir3_compiler
*compiler
= v
->shader
->compiler
;
131 uint32_t gpu_id
= compiler
->gpu_id
;
134 bin
= ir3_shader_assemble(v
, gpu_id
);
135 sz
= v
->info
.sizedwords
* 4;
137 v
->bo
= fd_bo_new(compiler
->dev
, sz
,
138 DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
139 DRM_FREEDRENO_GEM_TYPE_KMEM
);
141 memcpy(fd_bo_map(v
->bo
), bin
, sz
);
143 if (fd_mesa_debug
& FD_DBG_DISASM
) {
144 struct ir3_shader_key key
= v
->key
;
145 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v
->type
,
146 key
.binning_pass
, key
.color_two_side
, key
.half_precision
);
147 ir3_shader_disasm(v
, bin
);
150 if (fd_mesa_debug
& FD_DBG_SHADERDB
) {
151 /* print generic shader info: */
152 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n",
153 ir3_shader_stage(v
->shader
),
154 v
->shader
->id
, v
->id
,
155 v
->info
.instrs_count
,
157 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %u half, %u full\n",
158 ir3_shader_stage(v
->shader
),
159 v
->shader
->id
, v
->id
,
160 v
->info
.max_half_reg
+ 1,
161 v
->info
.max_reg
+ 1);
162 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n",
163 ir3_shader_stage(v
->shader
),
164 v
->shader
->id
, v
->id
,
165 v
->info
.max_const
+ 1,
171 /* no need to keep the ir around beyond this point: */
176 static struct ir3_shader_variant
*
177 create_variant(struct ir3_shader
*shader
, struct ir3_shader_key key
)
179 struct ir3_shader_variant
*v
= CALLOC_STRUCT(ir3_shader_variant
);
185 v
->id
= ++shader
->variant_count
;
188 v
->type
= shader
->type
;
190 ret
= ir3_compile_shader_nir(shader
->compiler
, v
);
192 debug_error("compile failed!");
198 debug_error("assemble failed!");
209 struct ir3_shader_variant
*
210 ir3_shader_variant(struct ir3_shader
*shader
, struct ir3_shader_key key
)
212 struct ir3_shader_variant
*v
;
214 /* some shader key values only apply to vertex or frag shader,
215 * so normalize the key to avoid constructing multiple identical
218 switch (shader
->type
) {
219 case SHADER_FRAGMENT
:
221 key
.binning_pass
= false;
222 if (key
.has_per_samp
) {
229 key
.color_two_side
= false;
230 key
.half_precision
= false;
231 key
.rasterflat
= false;
232 if (key
.has_per_samp
) {
240 for (v
= shader
->variants
; v
; v
= v
->next
)
241 if (ir3_shader_key_equal(&key
, &v
->key
))
244 /* compile new variant if it doesn't exist already: */
245 v
= create_variant(shader
, key
);
247 v
->next
= shader
->variants
;
248 shader
->variants
= v
;
256 ir3_shader_destroy(struct ir3_shader
*shader
)
258 struct ir3_shader_variant
*v
, *t
;
259 for (v
= shader
->variants
; v
; ) {
264 ralloc_free(shader
->nir
);
269 ir3_shader_create(struct ir3_compiler
*compiler
,
270 const struct pipe_shader_state
*cso
,
273 struct ir3_shader
*shader
= CALLOC_STRUCT(ir3_shader
);
274 shader
->compiler
= compiler
;
275 shader
->id
= ++shader
->compiler
->shader_count
;
277 if (fd_mesa_debug
& FD_DBG_DISASM
) {
278 DBG("dump tgsi: type=%d", shader
->type
);
279 tgsi_dump(cso
->tokens
, 0);
281 nir_shader
*nir
= ir3_tgsi_to_nir(cso
->tokens
);
282 /* do first pass optimization, ignoring the key: */
283 shader
->nir
= ir3_optimize_nir(shader
, nir
, NULL
);
284 if (fd_mesa_debug
& FD_DBG_DISASM
) {
285 DBG("dump nir%d: type=%d", shader
->id
, shader
->type
);
286 nir_print_shader(shader
->nir
, stdout
);
288 shader
->stream_output
= cso
->stream_output
;
289 if (fd_mesa_debug
& FD_DBG_SHADERDB
) {
290 /* if shader-db run, create a standard variant immediately
291 * (as otherwise nothing will trigger the shader to be
294 static struct ir3_shader_key key
= {0};
295 ir3_shader_variant(shader
, key
);
300 static void dump_reg(const char *name
, uint32_t r
)
302 if (r
!= regid(63,0))
303 debug_printf("; %s: r%d.%c\n", name
, r
>> 2, "xyzw"[r
& 0x3]);
306 static void dump_output(struct ir3_shader_variant
*so
,
307 unsigned slot
, const char *name
)
310 regid
= ir3_find_output_regid(so
, slot
);
311 dump_reg(name
, regid
);
315 ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
)
317 struct ir3
*ir
= so
->ir
;
318 struct ir3_register
*reg
;
319 const char *type
= ir3_shader_stage(so
->shader
);
323 for (i
= 0; i
< ir
->ninputs
; i
++) {
324 if (!ir
->inputs
[i
]) {
325 debug_printf("; in%d unused\n", i
);
328 reg
= ir
->inputs
[i
]->regs
[0];
330 debug_printf("@in(%sr%d.%c)\tin%d\n",
331 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
332 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
335 for (i
= 0; i
< ir
->noutputs
; i
++) {
336 if (!ir
->outputs
[i
]) {
337 debug_printf("; out%d unused\n", i
);
340 /* kill shows up as a virtual output.. skip it! */
341 if (is_kill(ir
->outputs
[i
]))
343 reg
= ir
->outputs
[i
]->regs
[0];
345 debug_printf("@out(%sr%d.%c)\tout%d\n",
346 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
347 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
350 for (i
= 0; i
< so
->immediates_count
; i
++) {
351 debug_printf("@const(c%d.x)\t", so
->first_immediate
+ i
);
352 debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
353 so
->immediates
[i
].val
[0],
354 so
->immediates
[i
].val
[1],
355 so
->immediates
[i
].val
[2],
356 so
->immediates
[i
].val
[3]);
359 disasm_a3xx(bin
, so
->info
.sizedwords
, 0, so
->type
);
363 debug_printf("; %s: outputs:", type
);
364 for (i
= 0; i
< so
->outputs_count
; i
++) {
365 uint8_t regid
= so
->outputs
[i
].regid
;
366 debug_printf(" r%d.%c (%s)",
367 (regid
>> 2), "xyzw"[regid
& 0x3],
368 gl_varying_slot_name(so
->outputs
[i
].slot
));
371 debug_printf("; %s: inputs:", type
);
372 for (i
= 0; i
< so
->inputs_count
; i
++) {
373 uint8_t regid
= so
->inputs
[i
].regid
;
374 debug_printf(" r%d.%c (cm=%x,il=%u,b=%u)",
375 (regid
>> 2), "xyzw"[regid
& 0x3],
376 so
->inputs
[i
].compmask
,
382 case SHADER_FRAGMENT
:
383 debug_printf("; %s: outputs:", type
);
384 for (i
= 0; i
< so
->outputs_count
; i
++) {
385 uint8_t regid
= so
->outputs
[i
].regid
;
386 debug_printf(" r%d.%c (%s)",
387 (regid
>> 2), "xyzw"[regid
& 0x3],
388 gl_frag_result_name(so
->outputs
[i
].slot
));
391 debug_printf("; %s: inputs:", type
);
392 for (i
= 0; i
< so
->inputs_count
; i
++) {
393 uint8_t regid
= so
->inputs
[i
].regid
;
394 debug_printf(" r%d.%c (%s,cm=%x,il=%u,b=%u)",
395 (regid
>> 2), "xyzw"[regid
& 0x3],
396 gl_varying_slot_name(so
->inputs
[i
].slot
),
397 so
->inputs
[i
].compmask
,
407 /* print generic shader info: */
408 debug_printf("; %s prog %d/%d: %u instructions, %d half, %d full\n",
409 type
, so
->shader
->id
, so
->id
,
410 so
->info
.instrs_count
,
411 so
->info
.max_half_reg
+ 1,
412 so
->info
.max_reg
+ 1);
414 debug_printf("; %d const, %u constlen\n",
415 so
->info
.max_const
+ 1,
418 /* print shader type specific info: */
421 dump_output(so
, VARYING_SLOT_POS
, "pos");
422 dump_output(so
, VARYING_SLOT_PSIZ
, "psize");
424 case SHADER_FRAGMENT
:
425 dump_reg("pos (bary)", so
->pos_regid
);
426 dump_output(so
, FRAG_RESULT_DEPTH
, "posz");
427 if (so
->color0_mrt
) {
428 dump_output(so
, FRAG_RESULT_COLOR
, "color");
430 dump_output(so
, FRAG_RESULT_DATA0
, "data0");
431 dump_output(so
, FRAG_RESULT_DATA1
, "data1");
432 dump_output(so
, FRAG_RESULT_DATA2
, "data2");
433 dump_output(so
, FRAG_RESULT_DATA3
, "data3");
434 dump_output(so
, FRAG_RESULT_DATA4
, "data4");
435 dump_output(so
, FRAG_RESULT_DATA5
, "data5");
436 dump_output(so
, FRAG_RESULT_DATA6
, "data6");
437 dump_output(so
, FRAG_RESULT_DATA7
, "data7");
439 /* these two are hard-coded since we don't know how to
440 * program them to anything but all 0's...
443 debug_printf("; fragcoord: r0.x\n");
445 debug_printf("; fragface: hr0.x\n");
454 /* This has to reach into the fd_context a bit more than the rest of
455 * ir3, but it needs to be aligned with the compiler, so both agree
456 * on which const regs hold what. And the logic is identical between
457 * a3xx/a4xx, the only difference is small details in the actual
458 * CP_LOAD_STATE packets (which is handled inside the generation
459 * specific ctx->emit_const(_bo)() fxns)
462 #include "freedreno_resource.h"
465 emit_user_consts(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
466 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
468 const unsigned index
= 0; /* user consts are index 0 */
469 /* TODO save/restore dirty_mask for binning pass instead: */
470 uint32_t dirty_mask
= constbuf
->enabled_mask
;
472 if (dirty_mask
& (1 << index
)) {
473 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
474 unsigned size
= align(cb
->buffer_size
, 4) / 4; /* size in dwords */
476 /* in particular, with binning shader we may end up with
477 * unused consts, ie. we could end up w/ constlen that is
478 * smaller than first_driver_param. In that case truncate
479 * the user consts early to avoid HLSQ lockup caused by
480 * writing too many consts
482 uint32_t max_const
= MIN2(v
->first_driver_param
, v
->constlen
);
484 // I expect that size should be a multiple of vec4's:
485 assert(size
== align(size
, 4));
487 /* and even if the start of the const buffer is before
488 * first_immediate, the end may not be:
490 size
= MIN2(size
, 4 * max_const
);
494 ctx
->emit_const(ring
, v
->type
, 0,
495 cb
->buffer_offset
, size
,
496 cb
->user_buffer
, cb
->buffer
);
497 constbuf
->dirty_mask
&= ~(1 << index
);
503 emit_ubos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
504 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
506 uint32_t offset
= v
->first_driver_param
+ IR3_UBOS_OFF
;
507 if (v
->constlen
> offset
) {
508 uint32_t params
= MIN2(4, v
->constlen
- offset
) * 4;
509 uint32_t offsets
[params
];
510 struct fd_bo
*bos
[params
];
512 for (uint32_t i
= 0; i
< params
; i
++) {
513 const uint32_t index
= i
+ 1; /* UBOs start at index 1 */
514 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
515 assert(!cb
->user_buffer
);
517 if ((constbuf
->enabled_mask
& (1 << index
)) && cb
->buffer
) {
518 offsets
[i
] = cb
->buffer_offset
;
519 bos
[i
] = fd_resource(cb
->buffer
)->bo
;
527 ctx
->emit_const_bo(ring
, v
->type
, false, offset
* 4, params
, bos
, offsets
);
532 emit_immediates(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
533 struct fd_ringbuffer
*ring
)
535 int size
= v
->immediates_count
;
536 uint32_t base
= v
->first_immediate
;
538 /* truncate size to avoid writing constants that shader
541 size
= MIN2(size
+ base
, v
->constlen
) - base
;
543 /* convert out of vec4: */
549 ctx
->emit_const(ring
, v
->type
, base
,
550 0, size
, v
->immediates
[0].val
, NULL
);
554 /* emit stream-out buffers: */
556 emit_tfbos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
557 struct fd_ringbuffer
*ring
)
559 /* streamout addresses after driver-params: */
560 uint32_t offset
= v
->first_driver_param
+ IR3_TFBOS_OFF
;
561 if (v
->constlen
> offset
) {
562 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
563 struct pipe_stream_output_info
*info
= &v
->shader
->stream_output
;
565 uint32_t offsets
[params
];
566 struct fd_bo
*bos
[params
];
568 for (uint32_t i
= 0; i
< params
; i
++) {
569 struct pipe_stream_output_target
*target
= so
->targets
[i
];
572 offsets
[i
] = (so
->offsets
[i
] * info
->stride
[i
] * 4) +
573 target
->buffer_offset
;
574 bos
[i
] = fd_resource(target
->buffer
)->bo
;
582 ctx
->emit_const_bo(ring
, v
->type
, true, offset
* 4, params
, bos
, offsets
);
587 max_tf_vtx(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
)
589 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
590 struct pipe_stream_output_info
*info
= &v
->shader
->stream_output
;
591 uint32_t maxvtxcnt
= 0x7fffffff;
593 if (v
->key
.binning_pass
)
595 if (v
->shader
->stream_output
.num_outputs
== 0)
597 if (so
->num_targets
== 0)
600 /* offset to write to is:
602 * total_vtxcnt = vtxcnt + offsets[i]
603 * offset = total_vtxcnt * stride[i]
605 * offset = vtxcnt * stride[i] ; calculated in shader
606 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
608 * assuming for each vtx, each target buffer will have data written
609 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
611 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
612 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
614 * but shader is actually doing a less-than (rather than less-than-
615 * equal) check, so we can drop the -stride[i].
617 * TODO is assumption about `offset + stride[i]` legit?
619 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
620 struct pipe_stream_output_target
*target
= so
->targets
[i
];
621 unsigned stride
= info
->stride
[i
] * 4; /* convert dwords->bytes */
623 uint32_t max
= target
->buffer_size
/ stride
;
624 maxvtxcnt
= MIN2(maxvtxcnt
, max
);
632 ir3_emit_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
633 struct fd_context
*ctx
, const struct pipe_draw_info
*info
, uint32_t dirty
)
635 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_CONSTBUF
)) {
636 struct fd_constbuf_stateobj
*constbuf
;
639 if (v
->type
== SHADER_VERTEX
) {
640 constbuf
= &ctx
->constbuf
[PIPE_SHADER_VERTEX
];
641 shader_dirty
= !!(ctx
->prog
.dirty
& FD_SHADER_DIRTY_VP
);
642 } else if (v
->type
== SHADER_FRAGMENT
) {
643 constbuf
= &ctx
->constbuf
[PIPE_SHADER_FRAGMENT
];
644 shader_dirty
= !!(ctx
->prog
.dirty
& FD_SHADER_DIRTY_FP
);
646 unreachable("bad shader type");
650 emit_user_consts(ctx
, v
, ring
, constbuf
);
651 emit_ubos(ctx
, v
, ring
, constbuf
);
653 emit_immediates(ctx
, v
, ring
);
656 /* emit driver params every time: */
657 /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
658 if (info
&& (v
->type
== SHADER_VERTEX
)) {
659 uint32_t offset
= v
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
660 if (v
->constlen
>= offset
) {
661 uint32_t vertex_params
[IR3_DP_COUNT
] = {
662 [IR3_DP_VTXID_BASE
] = info
->indexed
?
663 info
->index_bias
: info
->start
,
664 [IR3_DP_VTXCNT_MAX
] = max_tf_vtx(ctx
, v
),
666 /* if no user-clip-planes, we don't need to emit the
669 uint32_t vertex_params_size
= 4;
671 if (v
->key
.ucp_enables
) {
672 struct pipe_clip_state
*ucp
= &ctx
->ucp
;
673 unsigned pos
= IR3_DP_UCP0_X
;
674 for (unsigned i
= 0; pos
<= IR3_DP_UCP7_W
; i
++) {
675 for (unsigned j
= 0; j
< 4; j
++) {
676 vertex_params
[pos
] = fui(ucp
->ucp
[i
][j
]);
680 vertex_params_size
= ARRAY_SIZE(vertex_params
);
684 ctx
->emit_const(ring
, SHADER_VERTEX
, offset
* 4, 0,
685 vertex_params_size
, vertex_params
, NULL
);
687 /* if needed, emit stream-out buffer addresses: */
688 if (vertex_params
[IR3_DP_VTXCNT_MAX
] > 0) {
689 emit_tfbos(ctx
, v
, ring
);