src/gallium/drivers/freedreno/ir3/ir3_shader.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34 #include "tgsi/tgsi_dump.h"
  35 #include "tgsi/tgsi_parse.h"
  36
  37 #include "freedreno_context.h"
  38 #include "freedreno_util.h"
  39
  40 #include "ir3_shader.h"
  41 #include "ir3_compiler.h"
  42
  43
  44 static void
  45 delete_variant(struct ir3_shader_variant *v)
  46 {
  47         if (v->ir)
  48                 ir3_destroy(v->ir);
  49         if (v->bo)
  50                 fd_bo_del(v->bo);
  51         free(v);
  52 }
  53
  54 /* for vertex shader, the inputs are loaded into registers before the shader
  55  * is executed, so max_regs from the shader instructions might not properly
  56  * reflect the # of registers actually used, especially in case passthrough
  57  * varyings.
  58  *
  59  * Likewise, for fragment shader, we can have some regs which are passed
  60  * input values but never touched by the resulting shader (ie. as result
  61  * of dead code elimination or simply because we don't know how to turn
  62  * the reg off.
  63  */
  64 static void
  65 fixup_regfootprint(struct ir3_shader_variant *v)
  66 {
  67         if (v->type == SHADER_VERTEX) {
  68                 unsigned i;
  69                 for (i = 0; i < v->inputs_count; i++) {
  70                         /* skip frag inputs fetch via bary.f since their reg's are
  71                          * not written by gpu before shader starts (and in fact the
  72                          * regid's might not even be valid)
  73                          */
  74                         if (v->inputs[i].bary)
  75                                 continue;
  76
  77                         if (v->inputs[i].compmask) {
  78                                 int32_t regid = (v->inputs[i].regid + 3) >> 2;
  79                                 v->info.max_reg = MAX2(v->info.max_reg, regid);
  80                         }
  81                 }
  82                 for (i = 0; i < v->outputs_count; i++) {
  83                         int32_t regid = (v->outputs[i].regid + 3) >> 2;
  84                         v->info.max_reg = MAX2(v->info.max_reg, regid);
  85                 }
  86         } else if (v->type == SHADER_FRAGMENT) {
  87                 /* NOTE: not sure how to turn pos_regid off..  but this could
  88                  * be, for example, r1.x while max reg used by the shader is
  89                  * r0.*, in which case we need to fixup the reg footprint:
  90                  */
  91                 v->info.max_reg = MAX2(v->info.max_reg, v->pos_regid >> 2);
  92                 if (v->frag_coord)
  93                         debug_assert(v->info.max_reg >= 0); /* hard coded r0.x */
  94                 if (v->frag_face)
  95                         debug_assert(v->info.max_half_reg >= 0); /* hr0.x */
  96         }
  97 }
  98
  99 /* wrapper for ir3_assemble() which does some info fixup based on
 100  * shader state.  Non-static since used by ir3_cmdline too.
 101  */
 102 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 103 {
 104         void *bin;
 105
 106         bin = ir3_assemble(v->ir, &v->info, gpu_id);
 107         if (!bin)
 108                 return NULL;
 109
 110         if (gpu_id >= 400) {
 111                 v->instrlen = v->info.sizedwords / (2 * 16);
 112         } else {
 113                 v->instrlen = v->info.sizedwords / (2 * 4);
 114         }
 115
 116         /* NOTE: if relative addressing is used, we set constlen in
 117          * the compiler (to worst-case value) since we don't know in
 118          * the assembler what the max addr reg value can be:
 119          */
 120         v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
 121
 122         fixup_regfootprint(v);
 123
 124         return bin;
 125 }
 126
 127 static void
 128 assemble_variant(struct ir3_shader_variant *v)
 129 {
 130         struct fd_context *ctx = fd_context(v->shader->pctx);
 131         uint32_t gpu_id = v->shader->compiler->gpu_id;
 132         uint32_t sz, *bin;
 133
 134         bin = ir3_shader_assemble(v, gpu_id);
 135         sz = v->info.sizedwords * 4;
 136
 137         v->bo = fd_bo_new(ctx->dev, sz,
 138                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 139                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 140
 141         memcpy(fd_bo_map(v->bo), bin, sz);
 142
 143         free(bin);
 144
 145         /* no need to keep the ir around beyond this point: */
 146         ir3_destroy(v->ir);
 147         v->ir = NULL;
 148 }
 149
 150 static struct ir3_shader_variant *
 151 create_variant(struct ir3_shader *shader, struct ir3_shader_key key)
 152 {
 153         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 154         const struct tgsi_token *tokens = shader->tokens;
 155         int ret;
 156
 157         if (!v)
 158                 return NULL;
 159
 160         v->shader = shader;
 161         v->key = key;
 162         v->type = shader->type;
 163
 164         if (fd_mesa_debug & FD_DBG_DISASM) {
 165                 DBG("dump tgsi: type=%d, k={bp=%u,cts=%u,hp=%u}", shader->type,
 166                         key.binning_pass, key.color_two_side, key.half_precision);
 167                 tgsi_dump(tokens, 0);
 168         }
 169
 170         ret = ir3_compile_shader_nir(shader->compiler, v, tokens, key);
 171         if (ret) {
 172                 debug_error("compile failed!");
 173                 goto fail;
 174         }
 175
 176         assemble_variant(v);
 177         if (!v->bo) {
 178                 debug_error("assemble failed!");
 179                 goto fail;
 180         }
 181
 182         if (fd_mesa_debug & FD_DBG_DISASM) {
 183                 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
 184                         key.binning_pass, key.color_two_side, key.half_precision);
 185                 disasm_a3xx(fd_bo_map(v->bo), v->info.sizedwords, 0, v->type);
 186         }
 187
 188         return v;
 189
 190 fail:
 191         delete_variant(v);
 192         return NULL;
 193 }
 194
 195 struct ir3_shader_variant *
 196 ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key)
 197 {
 198         struct ir3_shader_variant *v;
 199
 200         /* some shader key values only apply to vertex or frag shader,
 201          * so normalize the key to avoid constructing multiple identical
 202          * variants:
 203          */
 204         switch (shader->type) {
 205         case SHADER_FRAGMENT:
 206         case SHADER_COMPUTE:
 207                 key.binning_pass = false;
 208                 if (key.has_per_samp) {
 209                         key.vsaturate_s = 0;
 210                         key.vsaturate_t = 0;
 211                         key.vsaturate_r = 0;
 212                 }
 213                 break;
 214         case SHADER_VERTEX:
 215                 key.color_two_side = false;
 216                 key.half_precision = false;
 217                 key.rasterflat = false;
 218                 if (key.has_per_samp) {
 219                         key.fsaturate_s = 0;
 220                         key.fsaturate_t = 0;
 221                         key.fsaturate_r = 0;
 222                 }
 223                 break;
 224         }
 225
 226         for (v = shader->variants; v; v = v->next)
 227                 if (ir3_shader_key_equal(&key, &v->key))
 228                         return v;
 229
 230         /* compile new variant if it doesn't exist already: */
 231         v = create_variant(shader, key);
 232         if (v) {
 233                 v->next = shader->variants;
 234                 shader->variants = v;
 235         }
 236
 237         return v;
 238 }
 239
 240
 241 void
 242 ir3_shader_destroy(struct ir3_shader *shader)
 243 {
 244         struct ir3_shader_variant *v, *t;
 245         for (v = shader->variants; v; ) {
 246                 t = v;
 247                 v = v->next;
 248                 delete_variant(t);
 249         }
 250         free((void *)shader->tokens);
 251         free(shader);
 252 }
 253
 254 struct ir3_shader *
 255 ir3_shader_create(struct pipe_context *pctx, const struct tgsi_token *tokens,
 256                 enum shader_t type)
 257 {
 258         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 259         shader->compiler = fd_context(pctx)->screen->compiler;
 260         shader->pctx = pctx;
 261         shader->type = type;
 262         shader->tokens = tgsi_dup_tokens(tokens);
 263         return shader;
 264 }