src/gallium/drivers/freedreno/ir3/ir3_shader.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34 #include "tgsi/tgsi_dump.h"
  35 #include "tgsi/tgsi_parse.h"
  36
  37 #include "freedreno_context.h"
  38 #include "freedreno_util.h"
  39
  40 #include "ir3_shader.h"
  41 #include "ir3_compiler.h"
  42
  43
  44 static void
  45 delete_variant(struct ir3_shader_variant *v)
  46 {
  47         if (v->ir)
  48                 ir3_destroy(v->ir);
  49         if (v->bo)
  50                 fd_bo_del(v->bo);
  51         free(v);
  52 }
  53
  54 /* for vertex shader, the inputs are loaded into registers before the shader
  55  * is executed, so max_regs from the shader instructions might not properly
  56  * reflect the # of registers actually used, especially in case passthrough
  57  * varyings.
  58  *
  59  * Likewise, for fragment shader, we can have some regs which are passed
  60  * input values but never touched by the resulting shader (ie. as result
  61  * of dead code elimination or simply because we don't know how to turn
  62  * the reg off.
  63  */
  64 static void
  65 fixup_regfootprint(struct ir3_shader_variant *v)
  66 {
  67         if (v->type == SHADER_VERTEX) {
  68                 unsigned i;
  69                 for (i = 0; i < v->inputs_count; i++) {
  70                         /* skip frag inputs fetch via bary.f since their reg's are
  71                          * not written by gpu before shader starts (and in fact the
  72                          * regid's might not even be valid)
  73                          */
  74                         if (v->inputs[i].bary)
  75                                 continue;
  76
  77                         if (v->inputs[i].compmask) {
  78                                 int32_t regid = (v->inputs[i].regid + 3) >> 2;
  79                                 v->info.max_reg = MAX2(v->info.max_reg, regid);
  80                         }
  81                 }
  82                 for (i = 0; i < v->outputs_count; i++) {
  83                         int32_t regid = (v->outputs[i].regid + 3) >> 2;
  84                         v->info.max_reg = MAX2(v->info.max_reg, regid);
  85                 }
  86         } else if (v->type == SHADER_FRAGMENT) {
  87                 /* NOTE: not sure how to turn pos_regid off..  but this could
  88                  * be, for example, r1.x while max reg used by the shader is
  89                  * r0.*, in which case we need to fixup the reg footprint:
  90                  */
  91                 v->info.max_reg = MAX2(v->info.max_reg, v->pos_regid >> 2);
  92                 if (v->frag_coord)
  93                         debug_assert(v->info.max_reg >= 0); /* hard coded r0.x */
  94                 if (v->frag_face)
  95                         debug_assert(v->info.max_half_reg >= 0); /* hr0.x */
  96         }
  97 }
  98
  99 /* wrapper for ir3_assemble() which does some info fixup based on
 100  * shader state.  Non-static since used by ir3_cmdline too.
 101  */
 102 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 103 {
 104         void *bin;
 105
 106         bin = ir3_assemble(v->ir, &v->info, gpu_id);
 107         if (!bin)
 108                 return NULL;
 109
 110         if (gpu_id >= 400) {
 111                 v->instrlen = v->info.sizedwords / (2 * 16);
 112         } else {
 113                 v->instrlen = v->info.sizedwords / (2 * 4);
 114         }
 115
 116         /* NOTE: if relative addressing is used, we set constlen in
 117          * the compiler (to worst-case value) since we don't know in
 118          * the assembler what the max addr reg value can be:
 119          */
 120         v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
 121
 122         fixup_regfootprint(v);
 123
 124         return bin;
 125 }
 126
 127 static void
 128 assemble_variant(struct ir3_shader_variant *v)
 129 {
 130         struct fd_context *ctx = fd_context(v->shader->pctx);
 131         uint32_t gpu_id = v->shader->compiler->gpu_id;
 132         uint32_t sz, *bin;
 133
 134         bin = ir3_shader_assemble(v, gpu_id);
 135         sz = v->info.sizedwords * 4;
 136
 137         v->bo = fd_bo_new(ctx->dev, sz,
 138                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 139                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 140
 141         memcpy(fd_bo_map(v->bo), bin, sz);
 142
 143         if (fd_mesa_debug & FD_DBG_DISASM) {
 144                 struct ir3_shader_key key = v->key;
 145                 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
 146                         key.binning_pass, key.color_two_side, key.half_precision);
 147                 ir3_shader_disasm(v, bin);
 148         }
 149
 150         if (fd_mesa_debug & FD_DBG_SHADERDB) {
 151                 /* print generic shader info: */
 152                 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n",
 153                                 ir3_shader_stage(v->shader),
 154                                 v->shader->id, v->id,
 155                                 v->info.instrs_count,
 156                                 v->info.sizedwords);
 157                 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u half, %u full\n",
 158                                 ir3_shader_stage(v->shader),
 159                                 v->shader->id, v->id,
 160                                 v->info.max_half_reg + 1,
 161                                 v->info.max_reg + 1);
 162                 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n",
 163                                 ir3_shader_stage(v->shader),
 164                                 v->shader->id, v->id,
 165                                 v->info.max_const + 1,
 166                                 v->constlen);
 167         }
 168
 169         free(bin);
 170
 171         /* no need to keep the ir around beyond this point: */
 172         ir3_destroy(v->ir);
 173         v->ir = NULL;
 174 }
 175
 176 static struct ir3_shader_variant *
 177 create_variant(struct ir3_shader *shader, struct ir3_shader_key key)
 178 {
 179         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 180         const struct tgsi_token *tokens = shader->tokens;
 181         int ret;
 182
 183         if (!v)
 184                 return NULL;
 185
 186         v->id = ++shader->variant_count;
 187         v->shader = shader;
 188         v->key = key;
 189         v->type = shader->type;
 190
 191         if (fd_mesa_debug & FD_DBG_DISASM) {
 192                 DBG("dump tgsi: type=%d, k={bp=%u,cts=%u,hp=%u}", shader->type,
 193                         key.binning_pass, key.color_two_side, key.half_precision);
 194                 tgsi_dump(tokens, 0);
 195         }
 196
 197         ret = ir3_compile_shader_nir(shader->compiler, v, tokens, key);
 198         if (ret) {
 199                 debug_error("compile failed!");
 200                 goto fail;
 201         }
 202
 203         assemble_variant(v);
 204         if (!v->bo) {
 205                 debug_error("assemble failed!");
 206                 goto fail;
 207         }
 208
 209         return v;
 210
 211 fail:
 212         delete_variant(v);
 213         return NULL;
 214 }
 215
 216 struct ir3_shader_variant *
 217 ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key)
 218 {
 219         struct ir3_shader_variant *v;
 220
 221         /* some shader key values only apply to vertex or frag shader,
 222          * so normalize the key to avoid constructing multiple identical
 223          * variants:
 224          */
 225         switch (shader->type) {
 226         case SHADER_FRAGMENT:
 227         case SHADER_COMPUTE:
 228                 key.binning_pass = false;
 229                 if (key.has_per_samp) {
 230                         key.vsaturate_s = 0;
 231                         key.vsaturate_t = 0;
 232                         key.vsaturate_r = 0;
 233                 }
 234                 break;
 235         case SHADER_VERTEX:
 236                 key.color_two_side = false;
 237                 key.half_precision = false;
 238                 key.rasterflat = false;
 239                 if (key.has_per_samp) {
 240                         key.fsaturate_s = 0;
 241                         key.fsaturate_t = 0;
 242                         key.fsaturate_r = 0;
 243                 }
 244                 break;
 245         }
 246
 247         for (v = shader->variants; v; v = v->next)
 248                 if (ir3_shader_key_equal(&key, &v->key))
 249                         return v;
 250
 251         /* compile new variant if it doesn't exist already: */
 252         v = create_variant(shader, key);
 253         if (v) {
 254                 v->next = shader->variants;
 255                 shader->variants = v;
 256         }
 257
 258         return v;
 259 }
 260
 261
 262 void
 263 ir3_shader_destroy(struct ir3_shader *shader)
 264 {
 265         struct ir3_shader_variant *v, *t;
 266         for (v = shader->variants; v; ) {
 267                 t = v;
 268                 v = v->next;
 269                 delete_variant(t);
 270         }
 271         free((void *)shader->tokens);
 272         free(shader);
 273 }
 274
 275 struct ir3_shader *
 276 ir3_shader_create(struct pipe_context *pctx, const struct tgsi_token *tokens,
 277                 enum shader_t type)
 278 {
 279         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 280         shader->compiler = fd_context(pctx)->screen->compiler;
 281         shader->id = ++shader->compiler->shader_count;
 282         shader->pctx = pctx;
 283         shader->type = type;
 284         shader->tokens = tgsi_dup_tokens(tokens);
 285         if (fd_mesa_debug & FD_DBG_SHADERDB) {
 286                 /* if shader-db run, create a standard variant immediately
 287                  * (as otherwise nothing will trigger the shader to be
 288                  * actually compiled)
 289                  */
 290                 static struct ir3_shader_key key = {};
 291                 ir3_shader_variant(shader, key);
 292         }
 293         return shader;
 294 }
 295
 296 static void dump_reg(const char *name, uint32_t r)
 297 {
 298         if (r != regid(63,0))
 299                 debug_printf("; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
 300 }
 301
 302 static void dump_semantic(struct ir3_shader_variant *so,
 303                 unsigned sem, const char *name)
 304 {
 305         uint32_t regid;
 306         regid = ir3_find_output_regid(so, ir3_semantic_name(sem, 0));
 307         dump_reg(name, regid);
 308 }
 309
 310 void
 311 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
 312 {
 313         struct ir3 *ir = so->ir;
 314         struct ir3_register *reg;
 315         const char *type = ir3_shader_stage(so->shader);
 316         uint8_t regid;
 317         unsigned i;
 318
 319         for (i = 0; i < ir->ninputs; i++) {
 320                 if (!ir->inputs[i]) {
 321                         debug_printf("; in%d unused\n", i);
 322                         continue;
 323                 }
 324                 reg = ir->inputs[i]->regs[0];
 325                 regid = reg->num;
 326                 debug_printf("@in(%sr%d.%c)\tin%d\n",
 327                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 328                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 329         }
 330
 331         for (i = 0; i < ir->noutputs; i++) {
 332                 if (!ir->outputs[i]) {
 333                         debug_printf("; out%d unused\n", i);
 334                         continue;
 335                 }
 336                 /* kill shows up as a virtual output.. skip it! */
 337                 if (is_kill(ir->outputs[i]))
 338                         continue;
 339                 reg = ir->outputs[i]->regs[0];
 340                 regid = reg->num;
 341                 debug_printf("@out(%sr%d.%c)\tout%d\n",
 342                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 343                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 344         }
 345
 346         for (i = 0; i < so->immediates_count; i++) {
 347                 debug_printf("@const(c%d.x)\t", so->first_immediate + i);
 348                 debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 349                                 so->immediates[i].val[0],
 350                                 so->immediates[i].val[1],
 351                                 so->immediates[i].val[2],
 352                                 so->immediates[i].val[3]);
 353         }
 354
 355         disasm_a3xx(bin, so->info.sizedwords, 0, so->type);
 356
 357         debug_printf("; %s: outputs:", type);
 358         for (i = 0; i < so->outputs_count; i++) {
 359                 uint8_t regid = so->outputs[i].regid;
 360                 ir3_semantic sem = so->outputs[i].semantic;
 361                 debug_printf(" r%d.%c (%u:%u)",
 362                                 (regid >> 2), "xyzw"[regid & 0x3],
 363                                 sem2name(sem), sem2idx(sem));
 364         }
 365         debug_printf("\n");
 366         debug_printf("; %s: inputs:", type);
 367         for (i = 0; i < so->inputs_count; i++) {
 368                 uint8_t regid = so->inputs[i].regid;
 369                 ir3_semantic sem = so->inputs[i].semantic;
 370                 debug_printf(" r%d.%c (%u:%u,cm=%x,il=%u,b=%u)",
 371                                 (regid >> 2), "xyzw"[regid & 0x3],
 372                                 sem2name(sem), sem2idx(sem),
 373                                 so->inputs[i].compmask,
 374                                 so->inputs[i].inloc,
 375                                 so->inputs[i].bary);
 376         }
 377         debug_printf("\n");
 378
 379         /* print generic shader info: */
 380         debug_printf("; %s prog %d/%d: %u instructions, %d half, %d full\n",
 381                         type, so->shader->id, so->id,
 382                         so->info.instrs_count,
 383                         so->info.max_half_reg + 1,
 384                         so->info.max_reg + 1);
 385
 386         debug_printf("; %d const, %u constlen\n",
 387                         so->info.max_const + 1,
 388                         so->constlen);
 389
 390         /* print shader type specific info: */
 391         switch (so->type) {
 392         case SHADER_VERTEX:
 393                 dump_semantic(so, TGSI_SEMANTIC_POSITION, "pos");
 394                 dump_semantic(so, TGSI_SEMANTIC_PSIZE, "psize");
 395                 break;
 396         case SHADER_FRAGMENT:
 397                 dump_reg("pos (bary)", so->pos_regid);
 398                 dump_semantic(so, TGSI_SEMANTIC_POSITION, "posz");
 399                 dump_semantic(so, TGSI_SEMANTIC_COLOR, "color");
 400                 /* these two are hard-coded since we don't know how to
 401                  * program them to anything but all 0's...
 402                  */
 403                 if (so->frag_coord)
 404                         debug_printf("; fragcoord: r0.x\n");
 405                 if (so->frag_face)
 406                         debug_printf("; fragface: hr0.x\n");
 407                 break;
 408         case SHADER_COMPUTE:
 409                 break;
 410         }
 411
 412         debug_printf("\n");
 413 }