freedreno/a4xx: lower srgb in shader for astc textures
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_shader.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
36
37 #include "freedreno_context.h"
38 #include "freedreno_util.h"
39
40 #include "ir3_shader.h"
41 #include "ir3_compiler.h"
42 #include "ir3_nir.h"
43
44 static void
45 delete_variant(struct ir3_shader_variant *v)
46 {
47 if (v->ir)
48 ir3_destroy(v->ir);
49 if (v->bo)
50 fd_bo_del(v->bo);
51 free(v);
52 }
53
54 /* for vertex shader, the inputs are loaded into registers before the shader
55 * is executed, so max_regs from the shader instructions might not properly
56 * reflect the # of registers actually used, especially in case passthrough
57 * varyings.
58 *
59 * Likewise, for fragment shader, we can have some regs which are passed
60 * input values but never touched by the resulting shader (ie. as result
61 * of dead code elimination or simply because we don't know how to turn
62 * the reg off.
63 */
64 static void
65 fixup_regfootprint(struct ir3_shader_variant *v)
66 {
67 if (v->type == SHADER_VERTEX) {
68 unsigned i;
69 for (i = 0; i < v->inputs_count; i++) {
70 /* skip frag inputs fetch via bary.f since their reg's are
71 * not written by gpu before shader starts (and in fact the
72 * regid's might not even be valid)
73 */
74 if (v->inputs[i].bary)
75 continue;
76
77 if (v->inputs[i].compmask) {
78 int32_t regid = (v->inputs[i].regid + 3) >> 2;
79 v->info.max_reg = MAX2(v->info.max_reg, regid);
80 }
81 }
82 for (i = 0; i < v->outputs_count; i++) {
83 int32_t regid = (v->outputs[i].regid + 3) >> 2;
84 v->info.max_reg = MAX2(v->info.max_reg, regid);
85 }
86 } else if (v->type == SHADER_FRAGMENT) {
87 /* NOTE: not sure how to turn pos_regid off.. but this could
88 * be, for example, r1.x while max reg used by the shader is
89 * r0.*, in which case we need to fixup the reg footprint:
90 */
91 v->info.max_reg = MAX2(v->info.max_reg, v->pos_regid >> 2);
92 if (v->frag_coord)
93 debug_assert(v->info.max_reg >= 0); /* hard coded r0.x */
94 if (v->frag_face)
95 debug_assert(v->info.max_half_reg >= 0); /* hr0.x */
96 }
97 }
98
99 /* wrapper for ir3_assemble() which does some info fixup based on
100 * shader state. Non-static since used by ir3_cmdline too.
101 */
102 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
103 {
104 void *bin;
105
106 bin = ir3_assemble(v->ir, &v->info, gpu_id);
107 if (!bin)
108 return NULL;
109
110 if (gpu_id >= 400) {
111 v->instrlen = v->info.sizedwords / (2 * 16);
112 } else {
113 v->instrlen = v->info.sizedwords / (2 * 4);
114 }
115
116 /* NOTE: if relative addressing is used, we set constlen in
117 * the compiler (to worst-case value) since we don't know in
118 * the assembler what the max addr reg value can be:
119 */
120 v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
121
122 fixup_regfootprint(v);
123
124 return bin;
125 }
126
127 static void
128 assemble_variant(struct ir3_shader_variant *v)
129 {
130 struct ir3_compiler *compiler = v->shader->compiler;
131 uint32_t gpu_id = compiler->gpu_id;
132 uint32_t sz, *bin;
133
134 bin = ir3_shader_assemble(v, gpu_id);
135 sz = v->info.sizedwords * 4;
136
137 v->bo = fd_bo_new(compiler->dev, sz,
138 DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
139 DRM_FREEDRENO_GEM_TYPE_KMEM);
140
141 memcpy(fd_bo_map(v->bo), bin, sz);
142
143 if (fd_mesa_debug & FD_DBG_DISASM) {
144 struct ir3_shader_key key = v->key;
145 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
146 key.binning_pass, key.color_two_side, key.half_precision);
147 ir3_shader_disasm(v, bin);
148 }
149
150 if (fd_mesa_debug & FD_DBG_SHADERDB) {
151 /* print generic shader info: */
152 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n",
153 ir3_shader_stage(v->shader),
154 v->shader->id, v->id,
155 v->info.instrs_count,
156 v->info.sizedwords);
157 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u half, %u full\n",
158 ir3_shader_stage(v->shader),
159 v->shader->id, v->id,
160 v->info.max_half_reg + 1,
161 v->info.max_reg + 1);
162 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n",
163 ir3_shader_stage(v->shader),
164 v->shader->id, v->id,
165 v->info.max_const + 1,
166 v->constlen);
167 }
168
169 free(bin);
170
171 /* no need to keep the ir around beyond this point: */
172 ir3_destroy(v->ir);
173 v->ir = NULL;
174 }
175
176 static struct ir3_shader_variant *
177 create_variant(struct ir3_shader *shader, struct ir3_shader_key key)
178 {
179 struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
180 int ret;
181
182 if (!v)
183 return NULL;
184
185 v->id = ++shader->variant_count;
186 v->shader = shader;
187 v->key = key;
188 v->type = shader->type;
189
190 ret = ir3_compile_shader_nir(shader->compiler, v);
191 if (ret) {
192 debug_error("compile failed!");
193 goto fail;
194 }
195
196 assemble_variant(v);
197 if (!v->bo) {
198 debug_error("assemble failed!");
199 goto fail;
200 }
201
202 return v;
203
204 fail:
205 delete_variant(v);
206 return NULL;
207 }
208
209 struct ir3_shader_variant *
210 ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key)
211 {
212 struct ir3_shader_variant *v;
213
214 /* some shader key values only apply to vertex or frag shader,
215 * so normalize the key to avoid constructing multiple identical
216 * variants:
217 */
218 switch (shader->type) {
219 case SHADER_FRAGMENT:
220 case SHADER_COMPUTE:
221 key.binning_pass = false;
222 if (key.has_per_samp) {
223 key.vsaturate_s = 0;
224 key.vsaturate_t = 0;
225 key.vsaturate_r = 0;
226 key.vlower_srgb = 0;
227 }
228 break;
229 case SHADER_VERTEX:
230 key.color_two_side = false;
231 key.half_precision = false;
232 key.rasterflat = false;
233 if (key.has_per_samp) {
234 key.fsaturate_s = 0;
235 key.fsaturate_t = 0;
236 key.fsaturate_r = 0;
237 key.flower_srgb = 0;
238 }
239 break;
240 }
241
242 for (v = shader->variants; v; v = v->next)
243 if (ir3_shader_key_equal(&key, &v->key))
244 return v;
245
246 /* compile new variant if it doesn't exist already: */
247 v = create_variant(shader, key);
248 if (v) {
249 v->next = shader->variants;
250 shader->variants = v;
251 }
252
253 return v;
254 }
255
256
257 void
258 ir3_shader_destroy(struct ir3_shader *shader)
259 {
260 struct ir3_shader_variant *v, *t;
261 for (v = shader->variants; v; ) {
262 t = v;
263 v = v->next;
264 delete_variant(t);
265 }
266 ralloc_free(shader->nir);
267 free(shader);
268 }
269
270 struct ir3_shader *
271 ir3_shader_create(struct ir3_compiler *compiler,
272 const struct pipe_shader_state *cso,
273 enum shader_t type)
274 {
275 struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
276 shader->compiler = compiler;
277 shader->id = ++shader->compiler->shader_count;
278 shader->type = type;
279 if (fd_mesa_debug & FD_DBG_DISASM) {
280 DBG("dump tgsi: type=%d", shader->type);
281 tgsi_dump(cso->tokens, 0);
282 }
283 nir_shader *nir = ir3_tgsi_to_nir(cso->tokens);
284 /* do first pass optimization, ignoring the key: */
285 shader->nir = ir3_optimize_nir(shader, nir, NULL);
286 if (fd_mesa_debug & FD_DBG_DISASM) {
287 DBG("dump nir%d: type=%d", shader->id, shader->type);
288 nir_print_shader(shader->nir, stdout);
289 }
290 shader->stream_output = cso->stream_output;
291 if (fd_mesa_debug & FD_DBG_SHADERDB) {
292 /* if shader-db run, create a standard variant immediately
293 * (as otherwise nothing will trigger the shader to be
294 * actually compiled)
295 */
296 static struct ir3_shader_key key = {0};
297 ir3_shader_variant(shader, key);
298 }
299 return shader;
300 }
301
302 static void dump_reg(const char *name, uint32_t r)
303 {
304 if (r != regid(63,0))
305 debug_printf("; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
306 }
307
308 static void dump_output(struct ir3_shader_variant *so,
309 unsigned slot, const char *name)
310 {
311 uint32_t regid;
312 regid = ir3_find_output_regid(so, slot);
313 dump_reg(name, regid);
314 }
315
316 void
317 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
318 {
319 struct ir3 *ir = so->ir;
320 struct ir3_register *reg;
321 const char *type = ir3_shader_stage(so->shader);
322 uint8_t regid;
323 unsigned i;
324
325 for (i = 0; i < ir->ninputs; i++) {
326 if (!ir->inputs[i]) {
327 debug_printf("; in%d unused\n", i);
328 continue;
329 }
330 reg = ir->inputs[i]->regs[0];
331 regid = reg->num;
332 debug_printf("@in(%sr%d.%c)\tin%d\n",
333 (reg->flags & IR3_REG_HALF) ? "h" : "",
334 (regid >> 2), "xyzw"[regid & 0x3], i);
335 }
336
337 for (i = 0; i < ir->noutputs; i++) {
338 if (!ir->outputs[i]) {
339 debug_printf("; out%d unused\n", i);
340 continue;
341 }
342 /* kill shows up as a virtual output.. skip it! */
343 if (is_kill(ir->outputs[i]))
344 continue;
345 reg = ir->outputs[i]->regs[0];
346 regid = reg->num;
347 debug_printf("@out(%sr%d.%c)\tout%d\n",
348 (reg->flags & IR3_REG_HALF) ? "h" : "",
349 (regid >> 2), "xyzw"[regid & 0x3], i);
350 }
351
352 for (i = 0; i < so->immediates_count; i++) {
353 debug_printf("@const(c%d.x)\t", so->first_immediate + i);
354 debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
355 so->immediates[i].val[0],
356 so->immediates[i].val[1],
357 so->immediates[i].val[2],
358 so->immediates[i].val[3]);
359 }
360
361 disasm_a3xx(bin, so->info.sizedwords, 0, so->type);
362
363 switch (so->type) {
364 case SHADER_VERTEX:
365 debug_printf("; %s: outputs:", type);
366 for (i = 0; i < so->outputs_count; i++) {
367 uint8_t regid = so->outputs[i].regid;
368 debug_printf(" r%d.%c (%s)",
369 (regid >> 2), "xyzw"[regid & 0x3],
370 gl_varying_slot_name(so->outputs[i].slot));
371 }
372 debug_printf("\n");
373 debug_printf("; %s: inputs:", type);
374 for (i = 0; i < so->inputs_count; i++) {
375 uint8_t regid = so->inputs[i].regid;
376 debug_printf(" r%d.%c (cm=%x,il=%u,b=%u)",
377 (regid >> 2), "xyzw"[regid & 0x3],
378 so->inputs[i].compmask,
379 so->inputs[i].inloc,
380 so->inputs[i].bary);
381 }
382 debug_printf("\n");
383 break;
384 case SHADER_FRAGMENT:
385 debug_printf("; %s: outputs:", type);
386 for (i = 0; i < so->outputs_count; i++) {
387 uint8_t regid = so->outputs[i].regid;
388 debug_printf(" r%d.%c (%s)",
389 (regid >> 2), "xyzw"[regid & 0x3],
390 gl_frag_result_name(so->outputs[i].slot));
391 }
392 debug_printf("\n");
393 debug_printf("; %s: inputs:", type);
394 for (i = 0; i < so->inputs_count; i++) {
395 uint8_t regid = so->inputs[i].regid;
396 debug_printf(" r%d.%c (%s,cm=%x,il=%u,b=%u)",
397 (regid >> 2), "xyzw"[regid & 0x3],
398 gl_varying_slot_name(so->inputs[i].slot),
399 so->inputs[i].compmask,
400 so->inputs[i].inloc,
401 so->inputs[i].bary);
402 }
403 debug_printf("\n");
404 break;
405 case SHADER_COMPUTE:
406 break;
407 }
408
409 /* print generic shader info: */
410 debug_printf("; %s prog %d/%d: %u instructions, %d half, %d full\n",
411 type, so->shader->id, so->id,
412 so->info.instrs_count,
413 so->info.max_half_reg + 1,
414 so->info.max_reg + 1);
415
416 debug_printf("; %d const, %u constlen\n",
417 so->info.max_const + 1,
418 so->constlen);
419
420 /* print shader type specific info: */
421 switch (so->type) {
422 case SHADER_VERTEX:
423 dump_output(so, VARYING_SLOT_POS, "pos");
424 dump_output(so, VARYING_SLOT_PSIZ, "psize");
425 break;
426 case SHADER_FRAGMENT:
427 dump_reg("pos (bary)", so->pos_regid);
428 dump_output(so, FRAG_RESULT_DEPTH, "posz");
429 if (so->color0_mrt) {
430 dump_output(so, FRAG_RESULT_COLOR, "color");
431 } else {
432 dump_output(so, FRAG_RESULT_DATA0, "data0");
433 dump_output(so, FRAG_RESULT_DATA1, "data1");
434 dump_output(so, FRAG_RESULT_DATA2, "data2");
435 dump_output(so, FRAG_RESULT_DATA3, "data3");
436 dump_output(so, FRAG_RESULT_DATA4, "data4");
437 dump_output(so, FRAG_RESULT_DATA5, "data5");
438 dump_output(so, FRAG_RESULT_DATA6, "data6");
439 dump_output(so, FRAG_RESULT_DATA7, "data7");
440 }
441 /* these two are hard-coded since we don't know how to
442 * program them to anything but all 0's...
443 */
444 if (so->frag_coord)
445 debug_printf("; fragcoord: r0.x\n");
446 if (so->frag_face)
447 debug_printf("; fragface: hr0.x\n");
448 break;
449 case SHADER_COMPUTE:
450 break;
451 }
452
453 debug_printf("\n");
454 }
455
456 /* This has to reach into the fd_context a bit more than the rest of
457 * ir3, but it needs to be aligned with the compiler, so both agree
458 * on which const regs hold what. And the logic is identical between
459 * a3xx/a4xx, the only difference is small details in the actual
460 * CP_LOAD_STATE packets (which is handled inside the generation
461 * specific ctx->emit_const(_bo)() fxns)
462 */
463
464 #include "freedreno_resource.h"
465
466 static void
467 emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
468 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
469 {
470 const unsigned index = 0; /* user consts are index 0 */
471 /* TODO save/restore dirty_mask for binning pass instead: */
472 uint32_t dirty_mask = constbuf->enabled_mask;
473
474 if (dirty_mask & (1 << index)) {
475 struct pipe_constant_buffer *cb = &constbuf->cb[index];
476 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
477
478 /* in particular, with binning shader we may end up with
479 * unused consts, ie. we could end up w/ constlen that is
480 * smaller than first_driver_param. In that case truncate
481 * the user consts early to avoid HLSQ lockup caused by
482 * writing too many consts
483 */
484 uint32_t max_const = MIN2(v->first_driver_param, v->constlen);
485
486 // I expect that size should be a multiple of vec4's:
487 assert(size == align(size, 4));
488
489 /* and even if the start of the const buffer is before
490 * first_immediate, the end may not be:
491 */
492 size = MIN2(size, 4 * max_const);
493
494 if (size > 0) {
495 fd_wfi(ctx, ring);
496 ctx->emit_const(ring, v->type, 0,
497 cb->buffer_offset, size,
498 cb->user_buffer, cb->buffer);
499 constbuf->dirty_mask &= ~(1 << index);
500 }
501 }
502 }
503
504 static void
505 emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
506 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
507 {
508 uint32_t offset = v->first_driver_param + IR3_UBOS_OFF;
509 if (v->constlen > offset) {
510 uint32_t params = MIN2(4, v->constlen - offset) * 4;
511 uint32_t offsets[params];
512 struct fd_bo *bos[params];
513
514 for (uint32_t i = 0; i < params; i++) {
515 const uint32_t index = i + 1; /* UBOs start at index 1 */
516 struct pipe_constant_buffer *cb = &constbuf->cb[index];
517 assert(!cb->user_buffer);
518
519 if ((constbuf->enabled_mask & (1 << index)) && cb->buffer) {
520 offsets[i] = cb->buffer_offset;
521 bos[i] = fd_resource(cb->buffer)->bo;
522 } else {
523 offsets[i] = 0;
524 bos[i] = NULL;
525 }
526 }
527
528 fd_wfi(ctx, ring);
529 ctx->emit_const_bo(ring, v->type, false, offset * 4, params, bos, offsets);
530 }
531 }
532
533 static void
534 emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v,
535 struct fd_ringbuffer *ring)
536 {
537 int size = v->immediates_count;
538 uint32_t base = v->first_immediate;
539
540 /* truncate size to avoid writing constants that shader
541 * does not use:
542 */
543 size = MIN2(size + base, v->constlen) - base;
544
545 /* convert out of vec4: */
546 base *= 4;
547 size *= 4;
548
549 if (size > 0) {
550 fd_wfi(ctx, ring);
551 ctx->emit_const(ring, v->type, base,
552 0, size, v->immediates[0].val, NULL);
553 }
554 }
555
556 /* emit stream-out buffers: */
557 static void
558 emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
559 struct fd_ringbuffer *ring)
560 {
561 /* streamout addresses after driver-params: */
562 uint32_t offset = v->first_driver_param + IR3_TFBOS_OFF;
563 if (v->constlen > offset) {
564 struct fd_streamout_stateobj *so = &ctx->streamout;
565 struct pipe_stream_output_info *info = &v->shader->stream_output;
566 uint32_t params = 4;
567 uint32_t offsets[params];
568 struct fd_bo *bos[params];
569
570 for (uint32_t i = 0; i < params; i++) {
571 struct pipe_stream_output_target *target = so->targets[i];
572
573 if (target) {
574 offsets[i] = (so->offsets[i] * info->stride[i] * 4) +
575 target->buffer_offset;
576 bos[i] = fd_resource(target->buffer)->bo;
577 } else {
578 offsets[i] = 0;
579 bos[i] = NULL;
580 }
581 }
582
583 fd_wfi(ctx, ring);
584 ctx->emit_const_bo(ring, v->type, true, offset * 4, params, bos, offsets);
585 }
586 }
587
588 static uint32_t
589 max_tf_vtx(struct fd_context *ctx, const struct ir3_shader_variant *v)
590 {
591 struct fd_streamout_stateobj *so = &ctx->streamout;
592 struct pipe_stream_output_info *info = &v->shader->stream_output;
593 uint32_t maxvtxcnt = 0x7fffffff;
594
595 if (v->key.binning_pass)
596 return 0;
597 if (v->shader->stream_output.num_outputs == 0)
598 return 0;
599 if (so->num_targets == 0)
600 return 0;
601
602 /* offset to write to is:
603 *
604 * total_vtxcnt = vtxcnt + offsets[i]
605 * offset = total_vtxcnt * stride[i]
606 *
607 * offset = vtxcnt * stride[i] ; calculated in shader
608 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
609 *
610 * assuming for each vtx, each target buffer will have data written
611 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
612 *
613 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
614 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
615 *
616 * but shader is actually doing a less-than (rather than less-than-
617 * equal) check, so we can drop the -stride[i].
618 *
619 * TODO is assumption about `offset + stride[i]` legit?
620 */
621 for (unsigned i = 0; i < so->num_targets; i++) {
622 struct pipe_stream_output_target *target = so->targets[i];
623 unsigned stride = info->stride[i] * 4; /* convert dwords->bytes */
624 if (target) {
625 uint32_t max = target->buffer_size / stride;
626 maxvtxcnt = MIN2(maxvtxcnt, max);
627 }
628 }
629
630 return maxvtxcnt;
631 }
632
633 void
634 ir3_emit_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
635 struct fd_context *ctx, const struct pipe_draw_info *info, uint32_t dirty)
636 {
637 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) {
638 struct fd_constbuf_stateobj *constbuf;
639 bool shader_dirty;
640
641 if (v->type == SHADER_VERTEX) {
642 constbuf = &ctx->constbuf[PIPE_SHADER_VERTEX];
643 shader_dirty = !!(ctx->prog.dirty & FD_SHADER_DIRTY_VP);
644 } else if (v->type == SHADER_FRAGMENT) {
645 constbuf = &ctx->constbuf[PIPE_SHADER_FRAGMENT];
646 shader_dirty = !!(ctx->prog.dirty & FD_SHADER_DIRTY_FP);
647 } else {
648 unreachable("bad shader type");
649 return;
650 }
651
652 emit_user_consts(ctx, v, ring, constbuf);
653 emit_ubos(ctx, v, ring, constbuf);
654 if (shader_dirty)
655 emit_immediates(ctx, v, ring);
656 }
657
658 /* emit driver params every time: */
659 /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
660 if (info && (v->type == SHADER_VERTEX)) {
661 uint32_t offset = v->first_driver_param + IR3_DRIVER_PARAM_OFF;
662 if (v->constlen >= offset) {
663 uint32_t vertex_params[IR3_DP_COUNT] = {
664 [IR3_DP_VTXID_BASE] = info->indexed ?
665 info->index_bias : info->start,
666 [IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
667 };
668 /* if no user-clip-planes, we don't need to emit the
669 * entire thing:
670 */
671 uint32_t vertex_params_size = 4;
672
673 if (v->key.ucp_enables) {
674 struct pipe_clip_state *ucp = &ctx->ucp;
675 unsigned pos = IR3_DP_UCP0_X;
676 for (unsigned i = 0; pos <= IR3_DP_UCP7_W; i++) {
677 for (unsigned j = 0; j < 4; j++) {
678 vertex_params[pos] = fui(ucp->ucp[i][j]);
679 pos++;
680 }
681 }
682 vertex_params_size = ARRAY_SIZE(vertex_params);
683 }
684
685 fd_wfi(ctx, ring);
686 ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
687 vertex_params_size, vertex_params, NULL);
688
689 /* if needed, emit stream-out buffer addresses: */
690 if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
691 emit_tfbos(ctx, v, ring);
692 }
693 }
694 }
695 }