src/gallium/drivers/freedreno/ir3/ir3_shader.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34 #include "tgsi/tgsi_dump.h"
  35 #include "tgsi/tgsi_parse.h"
  36
  37 #include "freedreno_context.h"
  38 #include "freedreno_util.h"
  39
  40 #include "ir3_shader.h"
  41 #include "ir3_compiler.h"
  42
  43
  44 static void
  45 delete_variant(struct ir3_shader_variant *v)
  46 {
  47         if (v->ir)
  48                 ir3_destroy(v->ir);
  49         if (v->bo)
  50                 fd_bo_del(v->bo);
  51         free(v);
  52 }
  53
  54 /* for vertex shader, the inputs are loaded into registers before the shader
  55  * is executed, so max_regs from the shader instructions might not properly
  56  * reflect the # of registers actually used, especially in case passthrough
  57  * varyings.
  58  *
  59  * Likewise, for fragment shader, we can have some regs which are passed
  60  * input values but never touched by the resulting shader (ie. as result
  61  * of dead code elimination or simply because we don't know how to turn
  62  * the reg off.
  63  */
  64 static void
  65 fixup_regfootprint(struct ir3_shader_variant *v)
  66 {
  67         if (v->type == SHADER_VERTEX) {
  68                 unsigned i;
  69                 for (i = 0; i < v->inputs_count; i++) {
  70                         /* skip frag inputs fetch via bary.f since their reg's are
  71                          * not written by gpu before shader starts (and in fact the
  72                          * regid's might not even be valid)
  73                          */
  74                         if (v->inputs[i].bary)
  75                                 continue;
  76
  77                         if (v->inputs[i].compmask) {
  78                                 int32_t regid = (v->inputs[i].regid + 3) >> 2;
  79                                 v->info.max_reg = MAX2(v->info.max_reg, regid);
  80                         }
  81                 }
  82                 for (i = 0; i < v->outputs_count; i++) {
  83                         int32_t regid = (v->outputs[i].regid + 3) >> 2;
  84                         v->info.max_reg = MAX2(v->info.max_reg, regid);
  85                 }
  86         } else if (v->type == SHADER_FRAGMENT) {
  87                 /* NOTE: not sure how to turn pos_regid off..  but this could
  88                  * be, for example, r1.x while max reg used by the shader is
  89                  * r0.*, in which case we need to fixup the reg footprint:
  90                  */
  91                 v->info.max_reg = MAX2(v->info.max_reg, v->pos_regid >> 2);
  92                 if (v->frag_coord)
  93                         debug_assert(v->info.max_reg >= 0); /* hard coded r0.x */
  94                 if (v->frag_face)
  95                         debug_assert(v->info.max_half_reg >= 0); /* hr0.x */
  96         }
  97 }
  98
  99 /* wrapper for ir3_assemble() which does some info fixup based on
 100  * shader state.  Non-static since used by ir3_cmdline too.
 101  */
 102 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 103 {
 104         void *bin;
 105
 106         bin = ir3_assemble(v->ir, &v->info, gpu_id);
 107         if (!bin)
 108                 return NULL;
 109
 110         if (gpu_id >= 400) {
 111                 v->instrlen = v->info.sizedwords / (2 * 16);
 112         } else {
 113                 v->instrlen = v->info.sizedwords / (2 * 4);
 114         }
 115
 116         /* NOTE: if relative addressing is used, we set constlen in
 117          * the compiler (to worst-case value) since we don't know in
 118          * the assembler what the max addr reg value can be:
 119          */
 120         v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
 121
 122         fixup_regfootprint(v);
 123
 124         return bin;
 125 }
 126
 127 static void
 128 assemble_variant(struct ir3_shader_variant *v)
 129 {
 130         struct fd_context *ctx = fd_context(v->shader->pctx);
 131         uint32_t gpu_id = v->shader->compiler->gpu_id;
 132         uint32_t sz, *bin;
 133
 134         bin = ir3_shader_assemble(v, gpu_id);
 135         sz = v->info.sizedwords * 4;
 136
 137         v->bo = fd_bo_new(ctx->dev, sz,
 138                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 139                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 140
 141         memcpy(fd_bo_map(v->bo), bin, sz);
 142
 143         if (fd_mesa_debug & FD_DBG_DISASM) {
 144                 struct ir3_shader_key key = v->key;
 145                 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
 146                         key.binning_pass, key.color_two_side, key.half_precision);
 147                 ir3_shader_disasm(v, bin);
 148         }
 149
 150         if (fd_mesa_debug & FD_DBG_SHADERDB) {
 151                 /* print generic shader info: */
 152                 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n",
 153                                 ir3_shader_stage(v->shader),
 154                                 v->shader->id, v->id,
 155                                 v->info.instrs_count,
 156                                 v->info.sizedwords);
 157                 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u half, %u full\n",
 158                                 ir3_shader_stage(v->shader),
 159                                 v->shader->id, v->id,
 160                                 v->info.max_half_reg + 1,
 161                                 v->info.max_reg + 1);
 162                 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n",
 163                                 ir3_shader_stage(v->shader),
 164                                 v->shader->id, v->id,
 165                                 v->info.max_const + 1,
 166                                 v->constlen);
 167         }
 168
 169         free(bin);
 170
 171         /* no need to keep the ir around beyond this point: */
 172         ir3_destroy(v->ir);
 173         v->ir = NULL;
 174 }
 175
 176 static struct ir3_shader_variant *
 177 create_variant(struct ir3_shader *shader, struct ir3_shader_key key)
 178 {
 179         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 180         int ret;
 181
 182         if (!v)
 183                 return NULL;
 184
 185         v->id = ++shader->variant_count;
 186         v->shader = shader;
 187         v->key = key;
 188         v->type = shader->type;
 189
 190         if (fd_mesa_debug & FD_DBG_DISASM) {
 191                 DBG("dump tgsi: type=%d, k={bp=%u,cts=%u,hp=%u}", shader->type,
 192                         key.binning_pass, key.color_two_side, key.half_precision);
 193                 tgsi_dump(shader->tokens, 0);
 194         }
 195
 196         ret = ir3_compile_shader_nir(shader->compiler, v);
 197         if (ret) {
 198                 debug_error("compile failed!");
 199                 goto fail;
 200         }
 201
 202         assemble_variant(v);
 203         if (!v->bo) {
 204                 debug_error("assemble failed!");
 205                 goto fail;
 206         }
 207
 208         return v;
 209
 210 fail:
 211         delete_variant(v);
 212         return NULL;
 213 }
 214
 215 struct ir3_shader_variant *
 216 ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key)
 217 {
 218         struct ir3_shader_variant *v;
 219
 220         /* some shader key values only apply to vertex or frag shader,
 221          * so normalize the key to avoid constructing multiple identical
 222          * variants:
 223          */
 224         switch (shader->type) {
 225         case SHADER_FRAGMENT:
 226         case SHADER_COMPUTE:
 227                 key.binning_pass = false;
 228                 if (key.has_per_samp) {
 229                         key.vsaturate_s = 0;
 230                         key.vsaturate_t = 0;
 231                         key.vsaturate_r = 0;
 232                 }
 233                 break;
 234         case SHADER_VERTEX:
 235                 key.color_two_side = false;
 236                 key.half_precision = false;
 237                 key.rasterflat = false;
 238                 if (key.has_per_samp) {
 239                         key.fsaturate_s = 0;
 240                         key.fsaturate_t = 0;
 241                         key.fsaturate_r = 0;
 242                 }
 243                 break;
 244         }
 245
 246         for (v = shader->variants; v; v = v->next)
 247                 if (ir3_shader_key_equal(&key, &v->key))
 248                         return v;
 249
 250         /* compile new variant if it doesn't exist already: */
 251         v = create_variant(shader, key);
 252         if (v) {
 253                 v->next = shader->variants;
 254                 shader->variants = v;
 255         }
 256
 257         return v;
 258 }
 259
 260
 261 void
 262 ir3_shader_destroy(struct ir3_shader *shader)
 263 {
 264         struct ir3_shader_variant *v, *t;
 265         for (v = shader->variants; v; ) {
 266                 t = v;
 267                 v = v->next;
 268                 delete_variant(t);
 269         }
 270         free((void *)shader->tokens);
 271         free(shader);
 272 }
 273
 274 struct ir3_shader *
 275 ir3_shader_create(struct pipe_context *pctx,
 276                 const struct pipe_shader_state *cso,
 277                 enum shader_t type)
 278 {
 279         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 280         shader->compiler = fd_context(pctx)->screen->compiler;
 281         shader->id = ++shader->compiler->shader_count;
 282         shader->pctx = pctx;
 283         shader->type = type;
 284         shader->tokens = tgsi_dup_tokens(cso->tokens);
 285         shader->stream_output = cso->stream_output;
 286         if (fd_mesa_debug & FD_DBG_SHADERDB) {
 287                 /* if shader-db run, create a standard variant immediately
 288                  * (as otherwise nothing will trigger the shader to be
 289                  * actually compiled)
 290                  */
 291                 static struct ir3_shader_key key = {};
 292                 ir3_shader_variant(shader, key);
 293         }
 294         return shader;
 295 }
 296
 297 static void dump_reg(const char *name, uint32_t r)
 298 {
 299         if (r != regid(63,0))
 300                 debug_printf("; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
 301 }
 302
 303 static void dump_output(struct ir3_shader_variant *so,
 304                 unsigned slot, const char *name)
 305 {
 306         uint32_t regid;
 307         regid = ir3_find_output_regid(so, slot);
 308         dump_reg(name, regid);
 309 }
 310
 311 void
 312 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
 313 {
 314         struct ir3 *ir = so->ir;
 315         struct ir3_register *reg;
 316         const char *type = ir3_shader_stage(so->shader);
 317         uint8_t regid;
 318         unsigned i;
 319
 320         for (i = 0; i < ir->ninputs; i++) {
 321                 if (!ir->inputs[i]) {
 322                         debug_printf("; in%d unused\n", i);
 323                         continue;
 324                 }
 325                 reg = ir->inputs[i]->regs[0];
 326                 regid = reg->num;
 327                 debug_printf("@in(%sr%d.%c)\tin%d\n",
 328                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 329                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 330         }
 331
 332         for (i = 0; i < ir->noutputs; i++) {
 333                 if (!ir->outputs[i]) {
 334                         debug_printf("; out%d unused\n", i);
 335                         continue;
 336                 }
 337                 /* kill shows up as a virtual output.. skip it! */
 338                 if (is_kill(ir->outputs[i]))
 339                         continue;
 340                 reg = ir->outputs[i]->regs[0];
 341                 regid = reg->num;
 342                 debug_printf("@out(%sr%d.%c)\tout%d\n",
 343                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 344                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 345         }
 346
 347         for (i = 0; i < so->immediates_count; i++) {
 348                 debug_printf("@const(c%d.x)\t", so->first_immediate + i);
 349                 debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 350                                 so->immediates[i].val[0],
 351                                 so->immediates[i].val[1],
 352                                 so->immediates[i].val[2],
 353                                 so->immediates[i].val[3]);
 354         }
 355
 356         disasm_a3xx(bin, so->info.sizedwords, 0, so->type);
 357
 358         switch (so->type) {
 359         case SHADER_VERTEX:
 360                 debug_printf("; %s: outputs:", type);
 361                 for (i = 0; i < so->outputs_count; i++) {
 362                         uint8_t regid = so->outputs[i].regid;
 363                         debug_printf(" r%d.%c (%s)",
 364                                         (regid >> 2), "xyzw"[regid & 0x3],
 365                                         gl_varying_slot_name(so->outputs[i].slot));
 366                 }
 367                 debug_printf("\n");
 368                 debug_printf("; %s: inputs:", type);
 369                 for (i = 0; i < so->inputs_count; i++) {
 370                         uint8_t regid = so->inputs[i].regid;
 371                         debug_printf(" r%d.%c (cm=%x,il=%u,b=%u)",
 372                                         (regid >> 2), "xyzw"[regid & 0x3],
 373                                         so->inputs[i].compmask,
 374                                         so->inputs[i].inloc,
 375                                         so->inputs[i].bary);
 376                 }
 377                 debug_printf("\n");
 378                 break;
 379         case SHADER_FRAGMENT:
 380                 debug_printf("; %s: outputs:", type);
 381                 for (i = 0; i < so->outputs_count; i++) {
 382                         uint8_t regid = so->outputs[i].regid;
 383                         debug_printf(" r%d.%c (%s)",
 384                                         (regid >> 2), "xyzw"[regid & 0x3],
 385                                         gl_frag_result_name(so->outputs[i].slot));
 386                 }
 387                 debug_printf("\n");
 388                 debug_printf("; %s: inputs:", type);
 389                 for (i = 0; i < so->inputs_count; i++) {
 390                         uint8_t regid = so->inputs[i].regid;
 391                         debug_printf(" r%d.%c (%s,cm=%x,il=%u,b=%u)",
 392                                         (regid >> 2), "xyzw"[regid & 0x3],
 393                                         gl_varying_slot_name(so->inputs[i].slot),
 394                                         so->inputs[i].compmask,
 395                                         so->inputs[i].inloc,
 396                                         so->inputs[i].bary);
 397                 }
 398                 debug_printf("\n");
 399                 break;
 400         case SHADER_COMPUTE:
 401                 break;
 402         }
 403
 404         /* print generic shader info: */
 405         debug_printf("; %s prog %d/%d: %u instructions, %d half, %d full\n",
 406                         type, so->shader->id, so->id,
 407                         so->info.instrs_count,
 408                         so->info.max_half_reg + 1,
 409                         so->info.max_reg + 1);
 410
 411         debug_printf("; %d const, %u constlen\n",
 412                         so->info.max_const + 1,
 413                         so->constlen);
 414
 415         /* print shader type specific info: */
 416         switch (so->type) {
 417         case SHADER_VERTEX:
 418                 dump_output(so, VARYING_SLOT_POS, "pos");
 419                 dump_output(so, VARYING_SLOT_PSIZ, "psize");
 420                 break;
 421         case SHADER_FRAGMENT:
 422                 dump_reg("pos (bary)", so->pos_regid);
 423                 dump_output(so, FRAG_RESULT_DEPTH, "posz");
 424                 if (so->color0_mrt) {
 425                         dump_output(so, FRAG_RESULT_COLOR, "color");
 426                 } else {
 427                         dump_output(so, FRAG_RESULT_DATA0, "data0");
 428                         dump_output(so, FRAG_RESULT_DATA1, "data1");
 429                         dump_output(so, FRAG_RESULT_DATA2, "data2");
 430                         dump_output(so, FRAG_RESULT_DATA3, "data3");
 431                         dump_output(so, FRAG_RESULT_DATA4, "data4");
 432                         dump_output(so, FRAG_RESULT_DATA5, "data5");
 433                         dump_output(so, FRAG_RESULT_DATA6, "data6");
 434                         dump_output(so, FRAG_RESULT_DATA7, "data7");
 435                 }
 436                 /* these two are hard-coded since we don't know how to
 437                  * program them to anything but all 0's...
 438                  */
 439                 if (so->frag_coord)
 440                         debug_printf("; fragcoord: r0.x\n");
 441                 if (so->frag_face)
 442                         debug_printf("; fragface: hr0.x\n");
 443                 break;
 444         case SHADER_COMPUTE:
 445                 break;
 446         }
 447
 448         debug_printf("\n");
 449 }
 450
 451 /* This has to reach into the fd_context a bit more than the rest of
 452  * ir3, but it needs to be aligned with the compiler, so both agree
 453  * on which const regs hold what.  And the logic is identical between
 454  * a3xx/a4xx, the only difference is small details in the actual
 455  * CP_LOAD_STATE packets (which is handled inside the generation
 456  * specific ctx->emit_const(_bo)() fxns)
 457  */
 458
 459 #include "freedreno_resource.h"
 460
 461 static void
 462 emit_user_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 463                 struct fd_constbuf_stateobj *constbuf)
 464 {
 465         struct fd_context *ctx = fd_context(v->shader->pctx);
 466         const unsigned index = 0;     /* user consts are index 0 */
 467         /* TODO save/restore dirty_mask for binning pass instead: */
 468         uint32_t dirty_mask = constbuf->enabled_mask;
 469
 470         if (dirty_mask & (1 << index)) {
 471                 struct pipe_constant_buffer *cb = &constbuf->cb[index];
 472                 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
 473
 474                 /* in particular, with binning shader we may end up with
 475                  * unused consts, ie. we could end up w/ constlen that is
 476                  * smaller than first_driver_param.  In that case truncate
 477                  * the user consts early to avoid HLSQ lockup caused by
 478                  * writing too many consts
 479                  */
 480                 uint32_t max_const = MIN2(v->first_driver_param, v->constlen);
 481
 482                 // I expect that size should be a multiple of vec4's:
 483                 assert(size == align(size, 4));
 484
 485                 /* and even if the start of the const buffer is before
 486                  * first_immediate, the end may not be:
 487                  */
 488                 size = MIN2(size, 4 * max_const);
 489
 490                 if (size > 0) {
 491                         fd_wfi(ctx, ring);
 492                         ctx->emit_const(ring, v->type, 0,
 493                                         cb->buffer_offset, size,
 494                                         cb->user_buffer, cb->buffer);
 495                         constbuf->dirty_mask &= ~(1 << index);
 496                 }
 497         }
 498 }
 499
 500 static void
 501 emit_ubos(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 502                 struct fd_constbuf_stateobj *constbuf)
 503 {
 504         uint32_t offset = v->first_driver_param + IR3_UBOS_OFF;
 505         if (v->constlen > offset) {
 506                 struct fd_context *ctx = fd_context(v->shader->pctx);
 507                 uint32_t params = MIN2(4, v->constlen - offset) * 4;
 508                 uint32_t offsets[params];
 509                 struct fd_bo *bos[params];
 510
 511                 for (uint32_t i = 0; i < params; i++) {
 512                         const uint32_t index = i + 1;   /* UBOs start at index 1 */
 513                         struct pipe_constant_buffer *cb = &constbuf->cb[index];
 514                         assert(!cb->user_buffer);
 515
 516                         if ((constbuf->enabled_mask & (1 << index)) && cb->buffer) {
 517                                 offsets[i] = cb->buffer_offset;
 518                                 bos[i] = fd_resource(cb->buffer)->bo;
 519                         } else {
 520                                 offsets[i] = 0;
 521                                 bos[i] = NULL;
 522                         }
 523                 }
 524
 525                 fd_wfi(ctx, ring);
 526                 ctx->emit_const_bo(ring, v->type, false, offset * 4, params, bos, offsets);
 527         }
 528 }
 529
 530 static void
 531 emit_immediates(struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
 532 {
 533         struct fd_context *ctx = fd_context(v->shader->pctx);
 534         int size = v->immediates_count;
 535         uint32_t base = v->first_immediate;
 536
 537         /* truncate size to avoid writing constants that shader
 538          * does not use:
 539          */
 540         size = MIN2(size + base, v->constlen) - base;
 541
 542         /* convert out of vec4: */
 543         base *= 4;
 544         size *= 4;
 545
 546         if (size > 0) {
 547                 fd_wfi(ctx, ring);
 548                 ctx->emit_const(ring, v->type, base,
 549                         0, size, v->immediates[0].val, NULL);
 550         }
 551 }
 552
 553 /* emit stream-out buffers: */
 554 static void
 555 emit_tfbos(struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
 556 {
 557         /* streamout addresses after driver-params: */
 558         uint32_t offset = v->first_driver_param + IR3_TFBOS_OFF;
 559         if (v->constlen > offset) {
 560                 struct fd_context *ctx = fd_context(v->shader->pctx);
 561                 struct fd_streamout_stateobj *so = &ctx->streamout;
 562                 struct pipe_stream_output_info *info = &v->shader->stream_output;
 563                 uint32_t params = 4;
 564                 uint32_t offsets[params];
 565                 struct fd_bo *bos[params];
 566
 567                 for (uint32_t i = 0; i < params; i++) {
 568                         struct pipe_stream_output_target *target = so->targets[i];
 569
 570                         if (target) {
 571                                 offsets[i] = (so->offsets[i] * info->stride[i] * 4) +
 572                                                 target->buffer_offset;
 573                                 bos[i] = fd_resource(target->buffer)->bo;
 574                         } else {
 575                                 offsets[i] = 0;
 576                                 bos[i] = NULL;
 577                         }
 578                 }
 579
 580                 fd_wfi(ctx, ring);
 581                 ctx->emit_const_bo(ring, v->type, true, offset * 4, params, bos, offsets);
 582         }
 583 }
 584
 585 static uint32_t
 586 max_tf_vtx(struct ir3_shader_variant *v)
 587 {
 588         struct fd_context *ctx = fd_context(v->shader->pctx);
 589         struct fd_streamout_stateobj *so = &ctx->streamout;
 590         struct pipe_stream_output_info *info = &v->shader->stream_output;
 591         uint32_t maxvtxcnt = 0x7fffffff;
 592
 593         if (v->key.binning_pass)
 594                 return 0;
 595         if (v->shader->stream_output.num_outputs == 0)
 596                 return 0;
 597         if (so->num_targets == 0)
 598                 return 0;
 599
 600         /* offset to write to is:
 601          *
 602          *   total_vtxcnt = vtxcnt + offsets[i]
 603          *   offset = total_vtxcnt * stride[i]
 604          *
 605          *   offset =   vtxcnt * stride[i]       ; calculated in shader
 606          *            + offsets[i] * stride[i]   ; calculated at emit_tfbos()
 607          *
 608          * assuming for each vtx, each target buffer will have data written
 609          * up to 'offset + stride[i]', that leaves maxvtxcnt as:
 610          *
 611          *   buffer_size = (maxvtxcnt * stride[i]) + stride[i]
 612          *   maxvtxcnt   = (buffer_size - stride[i]) / stride[i]
 613          *
 614          * but shader is actually doing a less-than (rather than less-than-
 615          * equal) check, so we can drop the -stride[i].
 616          *
 617          * TODO is assumption about `offset + stride[i]` legit?
 618          */
 619         for (unsigned i = 0; i < so->num_targets; i++) {
 620                 struct pipe_stream_output_target *target = so->targets[i];
 621                 unsigned stride = info->stride[i] * 4;   /* convert dwords->bytes */
 622                 if (target) {
 623                         uint32_t max = target->buffer_size / stride;
 624                         maxvtxcnt = MIN2(maxvtxcnt, max);
 625                 }
 626         }
 627
 628         return maxvtxcnt;
 629 }
 630
 631 void
 632 ir3_emit_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 633                 const struct pipe_draw_info *info, uint32_t dirty)
 634 {
 635         struct fd_context *ctx = fd_context(v->shader->pctx);
 636
 637         if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) {
 638                 struct fd_constbuf_stateobj *constbuf;
 639                 bool shader_dirty;
 640
 641                 if (v->type == SHADER_VERTEX) {
 642                         constbuf = &ctx->constbuf[PIPE_SHADER_VERTEX];
 643                         shader_dirty = !!(ctx->prog.dirty & FD_SHADER_DIRTY_VP);
 644                 } else if (v->type == SHADER_FRAGMENT) {
 645                         constbuf = &ctx->constbuf[PIPE_SHADER_FRAGMENT];
 646                         shader_dirty = !!(ctx->prog.dirty & FD_SHADER_DIRTY_FP);
 647                 } else {
 648                         unreachable("bad shader type");
 649                         return;
 650                 }
 651
 652                 emit_user_consts(v, ring, constbuf);
 653                 emit_ubos(v, ring, constbuf);
 654                 if (shader_dirty)
 655                         emit_immediates(v, ring);
 656         }
 657
 658         /* emit driver params every time: */
 659         /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
 660         if (info && (v->type == SHADER_VERTEX)) {
 661                 uint32_t offset = v->first_driver_param + IR3_DRIVER_PARAM_OFF;
 662                 if (v->constlen >= offset) {
 663                         uint32_t vertex_params[IR3_DP_COUNT] = {
 664                                 [IR3_DP_VTXID_BASE] = info->indexed ?
 665                                                 info->index_bias : info->start,
 666                                 [IR3_DP_VTXCNT_MAX] = max_tf_vtx(v),
 667                         };
 668                         /* if no user-clip-planes, we don't need to emit the
 669                          * entire thing:
 670                          */
 671                         uint32_t vertex_params_size = 4;
 672
 673                         if (v->key.ucp_enables) {
 674                                 struct pipe_clip_state *ucp = &ctx->ucp;
 675                                 unsigned pos = IR3_DP_UCP0_X;
 676                                 for (unsigned i = 0; pos <= IR3_DP_UCP7_W; i++) {
 677                                         for (unsigned j = 0; j < 4; j++) {
 678                                                 vertex_params[pos] = fui(ucp->ucp[i][j]);
 679                                                 pos++;
 680                                         }
 681                                 }
 682                                 vertex_params_size = ARRAY_SIZE(vertex_params);
 683                         }
 684
 685                         fd_wfi(ctx, ring);
 686                         ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
 687                                         vertex_params_size, vertex_params, NULL);
 688
 689                         /* if needed, emit stream-out buffer addresses: */
 690                         if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
 691                                 emit_tfbos(v, ring);
 692                         }
 693                 }
 694         }
 695 }