1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
37 #include "freedreno_context.h"
38 #include "freedreno_util.h"
40 #include "ir3_shader.h"
41 #include "ir3_compiler.h"
45 delete_variant(struct ir3_shader_variant
*v
)
54 /* for vertex shader, the inputs are loaded into registers before the shader
55 * is executed, so max_regs from the shader instructions might not properly
56 * reflect the # of registers actually used, especially in case passthrough
59 * Likewise, for fragment shader, we can have some regs which are passed
60 * input values but never touched by the resulting shader (ie. as result
61 * of dead code elimination or simply because we don't know how to turn
65 fixup_regfootprint(struct ir3_shader_variant
*v
)
67 if (v
->type
== SHADER_VERTEX
) {
69 for (i
= 0; i
< v
->inputs_count
; i
++) {
70 /* skip frag inputs fetch via bary.f since their reg's are
71 * not written by gpu before shader starts (and in fact the
72 * regid's might not even be valid)
74 if (v
->inputs
[i
].bary
)
77 if (v
->inputs
[i
].compmask
) {
78 int32_t regid
= (v
->inputs
[i
].regid
+ 3) >> 2;
79 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
);
82 for (i
= 0; i
< v
->outputs_count
; i
++) {
83 int32_t regid
= (v
->outputs
[i
].regid
+ 3) >> 2;
84 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
);
86 } else if (v
->type
== SHADER_FRAGMENT
) {
87 /* NOTE: not sure how to turn pos_regid off.. but this could
88 * be, for example, r1.x while max reg used by the shader is
89 * r0.*, in which case we need to fixup the reg footprint:
91 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, v
->pos_regid
>> 2);
93 debug_assert(v
->info
.max_reg
>= 0); /* hard coded r0.x */
95 debug_assert(v
->info
.max_half_reg
>= 0); /* hr0.x */
99 /* wrapper for ir3_assemble() which does some info fixup based on
100 * shader state. Non-static since used by ir3_cmdline too.
102 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
)
106 bin
= ir3_assemble(v
->ir
, &v
->info
, gpu_id
);
111 v
->instrlen
= v
->info
.sizedwords
/ (2 * 16);
113 v
->instrlen
= v
->info
.sizedwords
/ (2 * 4);
116 /* NOTE: if relative addressing is used, we set constlen in
117 * the compiler (to worst-case value) since we don't know in
118 * the assembler what the max addr reg value can be:
120 v
->constlen
= MIN2(255, MAX2(v
->constlen
, v
->info
.max_const
+ 1));
122 fixup_regfootprint(v
);
128 assemble_variant(struct ir3_shader_variant
*v
)
130 struct ir3_compiler
*compiler
= v
->shader
->compiler
;
131 uint32_t gpu_id
= compiler
->gpu_id
;
134 bin
= ir3_shader_assemble(v
, gpu_id
);
135 sz
= v
->info
.sizedwords
* 4;
137 v
->bo
= fd_bo_new(compiler
->dev
, sz
,
138 DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
139 DRM_FREEDRENO_GEM_TYPE_KMEM
);
141 memcpy(fd_bo_map(v
->bo
), bin
, sz
);
143 if (fd_mesa_debug
& FD_DBG_DISASM
) {
144 struct ir3_shader_key key
= v
->key
;
145 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v
->type
,
146 key
.binning_pass
, key
.color_two_side
, key
.half_precision
);
147 ir3_shader_disasm(v
, bin
);
152 /* no need to keep the ir around beyond this point: */
158 dump_shader_info(struct ir3_shader_variant
*v
, struct pipe_debug_callback
*debug
)
160 if (!unlikely(fd_mesa_debug
& FD_DBG_SHADERDB
))
163 pipe_debug_message(debug
, SHADER_INFO
, "\n"
164 "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n"
165 "SHADER-DB: %s prog %d/%d: %u half, %u full\n"
166 "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n",
167 ir3_shader_stage(v
->shader
),
168 v
->shader
->id
, v
->id
,
169 v
->info
.instrs_count
,
171 ir3_shader_stage(v
->shader
),
172 v
->shader
->id
, v
->id
,
173 v
->info
.max_half_reg
+ 1,
175 ir3_shader_stage(v
->shader
),
176 v
->shader
->id
, v
->id
,
177 v
->info
.max_const
+ 1,
181 static struct ir3_shader_variant
*
182 create_variant(struct ir3_shader
*shader
, struct ir3_shader_key key
)
184 struct ir3_shader_variant
*v
= CALLOC_STRUCT(ir3_shader_variant
);
190 v
->id
= ++shader
->variant_count
;
193 v
->type
= shader
->type
;
195 ret
= ir3_compile_shader_nir(shader
->compiler
, v
);
197 debug_error("compile failed!");
203 debug_error("assemble failed!");
214 struct ir3_shader_variant
*
215 ir3_shader_variant(struct ir3_shader
*shader
, struct ir3_shader_key key
,
216 struct pipe_debug_callback
*debug
)
218 struct ir3_shader_variant
*v
;
220 /* some shader key values only apply to vertex or frag shader,
221 * so normalize the key to avoid constructing multiple identical
224 switch (shader
->type
) {
225 case SHADER_FRAGMENT
:
227 key
.binning_pass
= false;
228 if (key
.has_per_samp
) {
236 key
.color_two_side
= false;
237 key
.half_precision
= false;
238 key
.rasterflat
= false;
239 if (key
.has_per_samp
) {
248 for (v
= shader
->variants
; v
; v
= v
->next
)
249 if (ir3_shader_key_equal(&key
, &v
->key
))
252 /* compile new variant if it doesn't exist already: */
253 v
= create_variant(shader
, key
);
255 v
->next
= shader
->variants
;
256 shader
->variants
= v
;
257 dump_shader_info(v
, debug
);
265 ir3_shader_destroy(struct ir3_shader
*shader
)
267 struct ir3_shader_variant
*v
, *t
;
268 for (v
= shader
->variants
; v
; ) {
273 ralloc_free(shader
->nir
);
278 ir3_shader_create(struct ir3_compiler
*compiler
,
279 const struct pipe_shader_state
*cso
, enum shader_t type
,
280 struct pipe_debug_callback
*debug
)
282 struct ir3_shader
*shader
= CALLOC_STRUCT(ir3_shader
);
283 shader
->compiler
= compiler
;
284 shader
->id
= ++shader
->compiler
->shader_count
;
288 if (cso
->type
== PIPE_SHADER_IR_NIR
) {
289 /* we take ownership of the reference: */
292 if (fd_mesa_debug
& FD_DBG_DISASM
) {
293 DBG("dump tgsi: type=%d", shader
->type
);
294 tgsi_dump(cso
->tokens
, 0);
296 nir
= ir3_tgsi_to_nir(cso
->tokens
);
297 shader
->from_tgsi
= true;
299 /* do first pass optimization, ignoring the key: */
300 shader
->nir
= ir3_optimize_nir(shader
, nir
, NULL
);
301 if (fd_mesa_debug
& FD_DBG_DISASM
) {
302 DBG("dump nir%d: type=%d", shader
->id
, shader
->type
);
303 nir_print_shader(shader
->nir
, stdout
);
306 shader
->stream_output
= cso
->stream_output
;
307 if (fd_mesa_debug
& FD_DBG_SHADERDB
) {
308 /* if shader-db run, create a standard variant immediately
309 * (as otherwise nothing will trigger the shader to be
312 static struct ir3_shader_key key
= {{0}};
313 ir3_shader_variant(shader
, key
, debug
);
318 static void dump_reg(const char *name
, uint32_t r
)
320 if (r
!= regid(63,0))
321 debug_printf("; %s: r%d.%c\n", name
, r
>> 2, "xyzw"[r
& 0x3]);
324 static void dump_output(struct ir3_shader_variant
*so
,
325 unsigned slot
, const char *name
)
328 regid
= ir3_find_output_regid(so
, slot
);
329 dump_reg(name
, regid
);
333 ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
)
335 struct ir3
*ir
= so
->ir
;
336 struct ir3_register
*reg
;
337 const char *type
= ir3_shader_stage(so
->shader
);
341 for (i
= 0; i
< ir
->ninputs
; i
++) {
342 if (!ir
->inputs
[i
]) {
343 debug_printf("; in%d unused\n", i
);
346 reg
= ir
->inputs
[i
]->regs
[0];
348 debug_printf("@in(%sr%d.%c)\tin%d\n",
349 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
350 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
353 for (i
= 0; i
< ir
->noutputs
; i
++) {
354 if (!ir
->outputs
[i
]) {
355 debug_printf("; out%d unused\n", i
);
358 /* kill shows up as a virtual output.. skip it! */
359 if (is_kill(ir
->outputs
[i
]))
361 reg
= ir
->outputs
[i
]->regs
[0];
363 debug_printf("@out(%sr%d.%c)\tout%d\n",
364 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
365 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
368 for (i
= 0; i
< so
->immediates_count
; i
++) {
369 debug_printf("@const(c%d.x)\t", so
->first_immediate
+ i
);
370 debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
371 so
->immediates
[i
].val
[0],
372 so
->immediates
[i
].val
[1],
373 so
->immediates
[i
].val
[2],
374 so
->immediates
[i
].val
[3]);
377 disasm_a3xx(bin
, so
->info
.sizedwords
, 0, so
->type
);
381 debug_printf("; %s: outputs:", type
);
382 for (i
= 0; i
< so
->outputs_count
; i
++) {
383 uint8_t regid
= so
->outputs
[i
].regid
;
384 debug_printf(" r%d.%c (%s)",
385 (regid
>> 2), "xyzw"[regid
& 0x3],
386 gl_varying_slot_name(so
->outputs
[i
].slot
));
389 debug_printf("; %s: inputs:", type
);
390 for (i
= 0; i
< so
->inputs_count
; i
++) {
391 uint8_t regid
= so
->inputs
[i
].regid
;
392 debug_printf(" r%d.%c (cm=%x,il=%u,b=%u)",
393 (regid
>> 2), "xyzw"[regid
& 0x3],
394 so
->inputs
[i
].compmask
,
400 case SHADER_FRAGMENT
:
401 debug_printf("; %s: outputs:", type
);
402 for (i
= 0; i
< so
->outputs_count
; i
++) {
403 uint8_t regid
= so
->outputs
[i
].regid
;
404 debug_printf(" r%d.%c (%s)",
405 (regid
>> 2), "xyzw"[regid
& 0x3],
406 gl_frag_result_name(so
->outputs
[i
].slot
));
409 debug_printf("; %s: inputs:", type
);
410 for (i
= 0; i
< so
->inputs_count
; i
++) {
411 uint8_t regid
= so
->inputs
[i
].regid
;
412 debug_printf(" r%d.%c (%s,cm=%x,il=%u,b=%u)",
413 (regid
>> 2), "xyzw"[regid
& 0x3],
414 gl_varying_slot_name(so
->inputs
[i
].slot
),
415 so
->inputs
[i
].compmask
,
425 /* print generic shader info: */
426 debug_printf("; %s prog %d/%d: %u instructions, %d half, %d full\n",
427 type
, so
->shader
->id
, so
->id
,
428 so
->info
.instrs_count
,
429 so
->info
.max_half_reg
+ 1,
430 so
->info
.max_reg
+ 1);
432 debug_printf("; %d const, %u constlen\n",
433 so
->info
.max_const
+ 1,
436 /* print shader type specific info: */
439 dump_output(so
, VARYING_SLOT_POS
, "pos");
440 dump_output(so
, VARYING_SLOT_PSIZ
, "psize");
442 case SHADER_FRAGMENT
:
443 dump_reg("pos (bary)", so
->pos_regid
);
444 dump_output(so
, FRAG_RESULT_DEPTH
, "posz");
445 if (so
->color0_mrt
) {
446 dump_output(so
, FRAG_RESULT_COLOR
, "color");
448 dump_output(so
, FRAG_RESULT_DATA0
, "data0");
449 dump_output(so
, FRAG_RESULT_DATA1
, "data1");
450 dump_output(so
, FRAG_RESULT_DATA2
, "data2");
451 dump_output(so
, FRAG_RESULT_DATA3
, "data3");
452 dump_output(so
, FRAG_RESULT_DATA4
, "data4");
453 dump_output(so
, FRAG_RESULT_DATA5
, "data5");
454 dump_output(so
, FRAG_RESULT_DATA6
, "data6");
455 dump_output(so
, FRAG_RESULT_DATA7
, "data7");
457 /* these two are hard-coded since we don't know how to
458 * program them to anything but all 0's...
461 debug_printf("; fragcoord: r0.x\n");
463 debug_printf("; fragface: hr0.x\n");
472 /* This has to reach into the fd_context a bit more than the rest of
473 * ir3, but it needs to be aligned with the compiler, so both agree
474 * on which const regs hold what. And the logic is identical between
475 * a3xx/a4xx, the only difference is small details in the actual
476 * CP_LOAD_STATE packets (which is handled inside the generation
477 * specific ctx->emit_const(_bo)() fxns)
480 #include "freedreno_resource.h"
483 emit_user_consts(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
484 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
486 const unsigned index
= 0; /* user consts are index 0 */
487 /* TODO save/restore dirty_mask for binning pass instead: */
488 uint32_t dirty_mask
= constbuf
->enabled_mask
;
490 if (dirty_mask
& (1 << index
)) {
491 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
492 unsigned size
= align(cb
->buffer_size
, 4) / 4; /* size in dwords */
494 /* in particular, with binning shader we may end up with
495 * unused consts, ie. we could end up w/ constlen that is
496 * smaller than first_driver_param. In that case truncate
497 * the user consts early to avoid HLSQ lockup caused by
498 * writing too many consts
500 uint32_t max_const
= MIN2(v
->first_driver_param
, v
->constlen
);
502 // I expect that size should be a multiple of vec4's:
503 assert(size
== align(size
, 4));
505 /* and even if the start of the const buffer is before
506 * first_immediate, the end may not be:
508 size
= MIN2(size
, 4 * max_const
);
512 ctx
->emit_const(ring
, v
->type
, 0,
513 cb
->buffer_offset
, size
,
514 cb
->user_buffer
, cb
->buffer
);
515 constbuf
->dirty_mask
&= ~(1 << index
);
521 emit_ubos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
522 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
524 uint32_t offset
= v
->first_driver_param
+ IR3_UBOS_OFF
;
525 if (v
->constlen
> offset
) {
526 uint32_t params
= MIN2(4, v
->constlen
- offset
) * 4;
527 uint32_t offsets
[params
];
528 struct pipe_resource
*prscs
[params
];
530 for (uint32_t i
= 0; i
< params
; i
++) {
531 const uint32_t index
= i
+ 1; /* UBOs start at index 1 */
532 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
533 assert(!cb
->user_buffer
);
535 if ((constbuf
->enabled_mask
& (1 << index
)) && cb
->buffer
) {
536 offsets
[i
] = cb
->buffer_offset
;
537 prscs
[i
] = cb
->buffer
;
545 ctx
->emit_const_bo(ring
, v
->type
, false, offset
* 4, params
, prscs
, offsets
);
550 emit_immediates(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
551 struct fd_ringbuffer
*ring
)
553 int size
= v
->immediates_count
;
554 uint32_t base
= v
->first_immediate
;
556 /* truncate size to avoid writing constants that shader
559 size
= MIN2(size
+ base
, v
->constlen
) - base
;
561 /* convert out of vec4: */
567 ctx
->emit_const(ring
, v
->type
, base
,
568 0, size
, v
->immediates
[0].val
, NULL
);
572 /* emit stream-out buffers: */
574 emit_tfbos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
575 struct fd_ringbuffer
*ring
)
577 /* streamout addresses after driver-params: */
578 uint32_t offset
= v
->first_driver_param
+ IR3_TFBOS_OFF
;
579 if (v
->constlen
> offset
) {
580 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
581 struct pipe_stream_output_info
*info
= &v
->shader
->stream_output
;
583 uint32_t offsets
[params
];
584 struct pipe_resource
*prscs
[params
];
586 for (uint32_t i
= 0; i
< params
; i
++) {
587 struct pipe_stream_output_target
*target
= so
->targets
[i
];
590 offsets
[i
] = (so
->offsets
[i
] * info
->stride
[i
] * 4) +
591 target
->buffer_offset
;
592 prscs
[i
] = target
->buffer
;
600 ctx
->emit_const_bo(ring
, v
->type
, true, offset
* 4, params
, prscs
, offsets
);
605 max_tf_vtx(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
)
607 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
608 struct pipe_stream_output_info
*info
= &v
->shader
->stream_output
;
609 uint32_t maxvtxcnt
= 0x7fffffff;
611 if (v
->key
.binning_pass
)
613 if (v
->shader
->stream_output
.num_outputs
== 0)
615 if (so
->num_targets
== 0)
618 /* offset to write to is:
620 * total_vtxcnt = vtxcnt + offsets[i]
621 * offset = total_vtxcnt * stride[i]
623 * offset = vtxcnt * stride[i] ; calculated in shader
624 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
626 * assuming for each vtx, each target buffer will have data written
627 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
629 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
630 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
632 * but shader is actually doing a less-than (rather than less-than-
633 * equal) check, so we can drop the -stride[i].
635 * TODO is assumption about `offset + stride[i]` legit?
637 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
638 struct pipe_stream_output_target
*target
= so
->targets
[i
];
639 unsigned stride
= info
->stride
[i
] * 4; /* convert dwords->bytes */
641 uint32_t max
= target
->buffer_size
/ stride
;
642 maxvtxcnt
= MIN2(maxvtxcnt
, max
);
650 ir3_emit_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
651 struct fd_context
*ctx
, const struct pipe_draw_info
*info
, uint32_t dirty
)
653 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_CONSTBUF
)) {
654 struct fd_constbuf_stateobj
*constbuf
;
657 if (v
->type
== SHADER_VERTEX
) {
658 constbuf
= &ctx
->constbuf
[PIPE_SHADER_VERTEX
];
659 shader_dirty
= !!(dirty
& FD_SHADER_DIRTY_VP
);
660 } else if (v
->type
== SHADER_FRAGMENT
) {
661 constbuf
= &ctx
->constbuf
[PIPE_SHADER_FRAGMENT
];
662 shader_dirty
= !!(dirty
& FD_SHADER_DIRTY_FP
);
664 unreachable("bad shader type");
668 emit_user_consts(ctx
, v
, ring
, constbuf
);
669 emit_ubos(ctx
, v
, ring
, constbuf
);
671 emit_immediates(ctx
, v
, ring
);
674 /* emit driver params every time: */
675 /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
676 if (info
&& (v
->type
== SHADER_VERTEX
)) {
677 uint32_t offset
= v
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
678 if (v
->constlen
>= offset
) {
679 uint32_t vertex_params
[IR3_DP_COUNT
] = {
680 [IR3_DP_VTXID_BASE
] = info
->indexed
?
681 info
->index_bias
: info
->start
,
682 [IR3_DP_VTXCNT_MAX
] = max_tf_vtx(ctx
, v
),
684 /* if no user-clip-planes, we don't need to emit the
687 uint32_t vertex_params_size
= 4;
689 if (v
->key
.ucp_enables
) {
690 struct pipe_clip_state
*ucp
= &ctx
->ucp
;
691 unsigned pos
= IR3_DP_UCP0_X
;
692 for (unsigned i
= 0; pos
<= IR3_DP_UCP7_W
; i
++) {
693 for (unsigned j
= 0; j
< 4; j
++) {
694 vertex_params
[pos
] = fui(ucp
->ucp
[i
][j
]);
698 vertex_params_size
= ARRAY_SIZE(vertex_params
);
702 ctx
->emit_const(ring
, SHADER_VERTEX
, offset
* 4, 0,
703 vertex_params_size
, vertex_params
, NULL
);
705 /* if needed, emit stream-out buffer addresses: */
706 if (vertex_params
[IR3_DP_VTXCNT_MAX
] > 0) {
707 emit_tfbos(ctx
, v
, ring
);