2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_state.h"
31 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
39 /* driver param indices: */
40 enum ir3_driver_param
{
41 /* compute shader driver params: */
42 IR3_DP_NUM_WORK_GROUPS_X
= 0,
43 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
44 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
45 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
46 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
47 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
48 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
49 * glDispatchComputeIndirect() needs to load these from
50 * the info->indirect buffer. Keep that in mind when/if
51 * adding any addition CS driver params.
53 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
55 /* vertex shader driver params: */
56 IR3_DP_VTXID_BASE
= 0,
57 IR3_DP_VTXCNT_MAX
= 1,
58 /* user-clip-plane components, up to 8x vec4's: */
62 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
66 * For consts needed to pass internal values to shader which may or may not
67 * be required, rather than allocating worst-case const space, we scan the
68 * shader and allocate consts as-needed:
70 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
73 * + Image dimensions: needed to calculate pixel offset, but only for
74 * images that have a image_store intrinsic
76 struct ir3_driver_const_layout
{
78 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
79 uint32_t count
; /* number of consts allocated */
80 /* one const allocated per SSBO which has get_buffer_size,
81 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
84 uint32_t off
[PIPE_MAX_SHADER_BUFFERS
];
88 uint32_t mask
; /* bitmask of images that have image_store */
89 uint32_t count
; /* number of consts allocated */
90 /* three const allocated per image which has image_store:
91 * + cpp (bytes per pixel)
93 * + array_pitch (z pitch)
95 uint32_t off
[PIPE_MAX_SHADER_IMAGES
];
99 /* Configuration key used to identify a shader variant.. different
100 * shader variants can be used to implement features not supported
101 * in hw (two sided color), binning-pass vertex shader, etc.
103 struct ir3_shader_key
{
107 * Combined Vertex/Fragment shader parameters:
109 unsigned ucp_enables
: 8;
111 /* do we need to check {v,f}saturate_{s,t,r}? */
112 unsigned has_per_samp
: 1;
115 * Vertex shader variant parameters:
117 unsigned vclamp_color
: 1;
120 * Fragment shader variant parameters:
122 unsigned color_two_side
: 1;
123 unsigned half_precision
: 1;
124 /* used when shader needs to handle flat varyings (a4xx)
125 * for front/back color inputs to frag shader:
127 unsigned rasterflat
: 1;
128 unsigned fclamp_color
: 1;
133 /* bitmask of sampler which needs coords clamped for vertex
136 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
138 /* bitmask of sampler which needs coords clamped for frag
141 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
143 /* bitmask of ms shifts */
144 uint32_t vsamples
, fsamples
;
146 /* bitmask of samplers which need astc srgb workaround: */
147 uint16_t vastc_srgb
, fastc_srgb
;
151 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
153 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
154 if (a
->has_per_samp
|| b
->has_per_samp
)
155 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
156 return a
->global
== b
->global
;
159 /* will the two keys produce different lowering for a fragment shader? */
161 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
163 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
164 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
165 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
166 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
167 (last_key
->fsamples
!= key
->fsamples
) ||
168 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
172 if (last_key
->fclamp_color
!= key
->fclamp_color
)
175 if (last_key
->color_two_side
!= key
->color_two_side
)
178 if (last_key
->half_precision
!= key
->half_precision
)
181 if (last_key
->rasterflat
!= key
->rasterflat
)
184 if (last_key
->ucp_enables
!= key
->ucp_enables
)
190 /* will the two keys produce different lowering for a vertex shader? */
192 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
194 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
195 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
196 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
197 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
198 (last_key
->vsamples
!= key
->vsamples
) ||
199 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
203 if (last_key
->vclamp_color
!= key
->vclamp_color
)
206 if (last_key
->ucp_enables
!= key
->ucp_enables
)
212 struct ir3_shader_variant
{
215 /* variant id (for debug) */
218 struct ir3_shader_key key
;
220 /* vertex shaders can have an extra version for hwbinning pass,
221 * which is pointed to by so->binning:
224 struct ir3_shader_variant
*binning
;
226 struct ir3_driver_const_layout const_layout
;
227 struct ir3_info info
;
230 /* the instructions length is in units of instruction groups
231 * (4 instructions for a3xx, 16 instructions for a4xx.. each
232 * instruction is 2 dwords):
236 /* the constants length is in units of vec4's, and is the sum of
237 * the uniforms and the built-in compiler constants
241 /* number of uniforms (in vec4), not including built-in compiler
244 unsigned num_uniforms
;
249 * + Let the frag shader determine the position/compmask for the
250 * varyings, since it is the place where we know if the varying
251 * is actually used, and if so, which components are used. So
252 * what the hw calls "outloc" is taken from the "inloc" of the
254 * + From the vert shader, we only need the output regid
257 bool frag_coord
, frag_face
, color0_mrt
;
259 /* NOTE: for input/outputs, slot is:
260 * gl_vert_attrib - for VS inputs
261 * gl_varying_slot - for VS output / FS input
262 * gl_frag_result - for FS output
265 /* varyings/outputs: */
266 unsigned outputs_count
;
270 } outputs
[16 + 2]; /* +POSITION +PSIZE */
271 bool writes_pos
, writes_psize
;
273 /* attributes (VS) / varyings (FS):
274 * Note that sysval's should come *after* normal inputs.
276 unsigned inputs_count
;
282 /* location of input (ie. offset passed to bary.f, etc). This
283 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
284 * have the OUTLOCn value offset by 8, presumably to account
285 * for gl_Position/gl_PointSize)
288 /* vertex shader specific: */
289 bool sysval
: 1; /* slot is a gl_system_value */
290 /* fragment shader specific: */
291 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
292 bool rasterflat
: 1; /* special handling for emit->rasterflat */
293 enum glsl_interp_mode interpolate
;
294 } inputs
[16 + 2]; /* +POSITION +FACE */
296 /* sum of input components (scalar). For frag shaders, it only counts
297 * the varying inputs:
301 /* For frag shaders, the total number of inputs (not scalar,
302 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
306 /* number of samplers/textures (which are currently 1:1): */
309 /* do we have one or more SSBO instructions: */
312 /* do we have kill instructions: */
315 /* Layout of constant registers, each section (in vec4). Pointer size
316 * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
317 * UBO and stream-out consts.
320 /* user const start at zero */
322 /* NOTE that a3xx might need a section for SSBO addresses too */
325 unsigned driver_param
;
330 unsigned immediates_count
;
331 unsigned immediates_size
;
336 /* for astc srgb workaround, the number/base of additional
337 * alpha tex states we need, and index of original tex states
340 unsigned base
, count
;
341 unsigned orig_idx
[16];
344 /* shader variants form a linked list: */
345 struct ir3_shader_variant
*next
;
347 /* replicated here to avoid passing extra ptrs everywhere: */
348 gl_shader_stage type
;
349 struct ir3_shader
*shader
;
353 gl_shader_stage type
;
355 /* shader id (for debug): */
357 uint32_t variant_count
;
359 /* so we know when we can disable TGSI related hacks: */
362 struct ir3_compiler
*compiler
;
364 struct nir_shader
*nir
;
365 struct pipe_stream_output_info stream_output
;
367 struct ir3_shader_variant
*variants
;
370 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
372 struct ir3_shader
* ir3_shader_create(struct ir3_compiler
*compiler
,
373 const struct pipe_shader_state
*cso
, gl_shader_stage type
,
374 struct pipe_debug_callback
*debug
);
376 ir3_shader_create_compute(struct ir3_compiler
*compiler
,
377 const struct pipe_compute_state
*cso
,
378 struct pipe_debug_callback
*debug
);
379 void ir3_shader_destroy(struct ir3_shader
*shader
);
380 struct ir3_shader_variant
* ir3_shader_variant(struct ir3_shader
*shader
,
381 struct ir3_shader_key key
, bool binning_pass
,
382 struct pipe_debug_callback
*debug
);
383 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
384 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
386 struct fd_ringbuffer
;
388 void ir3_emit_vs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
389 struct fd_context
*ctx
, const struct pipe_draw_info
*info
);
390 void ir3_emit_fs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
391 struct fd_context
*ctx
);
392 void ir3_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
393 struct fd_context
*ctx
, const struct pipe_grid_info
*info
);
396 ir3_glsl_type_size(const struct glsl_type
*type
);
398 static inline const char *
399 ir3_shader_stage(struct ir3_shader
*shader
)
401 switch (shader
->type
) {
402 case MESA_SHADER_VERTEX
: return "VERT";
403 case MESA_SHADER_FRAGMENT
: return "FRAG";
404 case MESA_SHADER_COMPUTE
: return "CL";
406 unreachable("invalid type");
415 #include "pipe/p_shader_tokens.h"
418 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
422 for (j
= 0; j
< so
->outputs_count
; j
++)
423 if (so
->outputs
[j
].slot
== slot
)
426 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
427 * in the vertex shader.. but the fragment shader doesn't know this
428 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
429 * at link time if there is no matching OUT.BCOLOR[n], we must map
430 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
431 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
433 if (slot
== VARYING_SLOT_BFC0
) {
434 slot
= VARYING_SLOT_COL0
;
435 } else if (slot
== VARYING_SLOT_BFC1
) {
436 slot
= VARYING_SLOT_COL1
;
437 } else if (slot
== VARYING_SLOT_COL0
) {
438 slot
= VARYING_SLOT_BFC0
;
439 } else if (slot
== VARYING_SLOT_COL1
) {
440 slot
= VARYING_SLOT_BFC1
;
445 for (j
= 0; j
< so
->outputs_count
; j
++)
446 if (so
->outputs
[j
].slot
== slot
)
455 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
457 while (++i
< so
->inputs_count
)
458 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
463 struct ir3_shader_linkage
{
474 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid
, uint8_t compmask
, uint8_t loc
)
478 debug_assert(i
< ARRAY_SIZE(l
->var
));
480 l
->var
[i
].regid
= regid
;
481 l
->var
[i
].compmask
= compmask
;
483 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
487 ir3_link_shaders(struct ir3_shader_linkage
*l
,
488 const struct ir3_shader_variant
*vs
,
489 const struct ir3_shader_variant
*fs
)
493 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
494 j
= ir3_next_varying(fs
, j
);
496 if (j
>= fs
->inputs_count
)
499 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
502 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
504 ir3_link_add(l
, vs
->outputs
[k
].regid
,
505 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
509 static inline uint32_t
510 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
513 for (j
= 0; j
< so
->outputs_count
; j
++)
514 if (so
->outputs
[j
].slot
== slot
)
515 return so
->outputs
[j
].regid
;
519 static inline uint32_t
520 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
523 for (j
= 0; j
< so
->inputs_count
; j
++)
524 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
525 return so
->inputs
[j
].regid
;
529 /* calculate register footprint in terms of half-regs (ie. one full
530 * reg counts as two half-regs).
532 static inline uint32_t
533 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
535 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
538 #endif /* IR3_SHADER_H_ */